blob: 09db24929a353d55a5b5c2036e183bee4e692322 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
TODO
change parser to use <> syntax (and update all tests)
think about on-reset
make instances always male, flip the bundles on declaration
write out FIFO example pass
write out diff mem examples and how we will support it
instances can be bulk connected -> change := semantics to:
F := M -> F := M (legal)
M := F -> M := F (legal)
M := M -> (illegal)
F := F -> (illegal)
B := B -> F := M (legal)
F := U -> F := M (legal)
M := U -> M := F (legal)
U := M -> F := M (legal)
U := F -> M := F (legal)
U := U -> U := U (legal)
Address this in gender inference pass, when see M := F, replace with F := M
What if Instances were Male always? And its type is the flipped version of module??
talk to palmer/patrick about how writing passes is going to be supported
Write lowering step for primops
Figure out how widths propogate for all updated primops (Adam)
Add bit-reduce-and etc to primops (Jonathan)
Write pass to rename identifiers (alpha-transform) (Adam)
Add partial bulk connect (Scott, Stephen)
Add FIFOs to the IR (Palmer)
Registers/Memories only have data and enable fields, which can be written/read from. These are set by the front-end. This will probably have to wait (Palmer)
Multi-streams for print statements (Jack)
Consider def female node. (Patrick)
Think about supporting memories (Scott)
Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed)
Update spec
add new field for sequential or combinational
add assertions
cannot connect directly to a mem (loc can never contain a mem)
Future questions to address in spec:
Introduction – motivation, and intended usage
Philosophical justifications for all constructs
More introduction for types, e.g. what is a ground type?
What is a statement? What is an expression? What is a memory? Difference between vector type and memory? What are accessors for?
Why would I ever write an empty statement? Mainly for use by compiler/passes
What is a structural element? Duplication?
Subtracting two unsigned numbers… Should talk to a math guy to figure it out
What are shift left and shift right operations? HW doesn’t have these concepts. Need justification.
What is lowered form? What is it for?
Checks:
Subfields are only on bundles, before type inference
after adding dynamic assertions, insert bounds check with accessor expansion
all things only assigned to once
Tests:
Error if declare anything other than module in circuit
Error if incorrectly assign stuff, like use = instead of :=
Error: Node not parsed for stmts
Male node:
defnode n = e
==>
wire n
n := e
Female node:
defnode n = e
==>
wire n
e := n
Front-end needs to guarantee unique names per module.
FIRRTL rule: No name can be a prefix of any other name.
|
