; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
;CHECK: Done!

circuit BundleWire : 
  module BundleWire : 
    input in : {x : UInt<32>, y : UInt<32>}
    output outs : {x : UInt<32>, y : UInt<32>}[4]
    
    wire coords : {x : UInt<32>, y : UInt<32>}[4]
    coords[0] := in
    outs[0] := coords[0]
    coords[1] := in
    outs[1] := coords[1]
    coords[2] := in
    outs[2] := coords[2]
    coords[3] := in
    outs[3] := coords[3]