// See LICENSE for license details. package firrtlTests import firrtl.RenameMap import firrtl.annotations.{ CircuitName, ModuleName, ComponentName } class RenameMapSpec extends FirrtlFlatSpec { val cir = CircuitName("Top") val modA = ModuleName("A", cir) val modB = ModuleName("B", cir) val foo = ComponentName("foo", modA) val bar = ComponentName("bar", modA) val fizz = ComponentName("fizz", modA) val fooB = ComponentName("foo", modB) val barB = ComponentName("bar", modB) behavior of "RenameMap" it should "return None if it does not rename something" in { val renames = RenameMap() renames.get(modA) should be (None) renames.get(foo) should be (None) } it should "return a Seq of renamed things if it does rename something" in { val renames = RenameMap() renames.rename(foo, bar) renames.get(foo) should be (Some(Seq(bar))) } it should "allow something to be renamed to multiple things" in { val renames = RenameMap() renames.rename(foo, bar) renames.rename(foo, fizz) renames.get(foo) should be (Some(Seq(bar, fizz))) } it should "allow something to be renamed to nothing (ie. deleted)" in { val renames = RenameMap() renames.rename(foo, Seq()) renames.get(foo) should be (Some(Seq())) } it should "return None if something is renamed to itself" in { val renames = RenameMap() renames.rename(foo, foo) renames.get(foo) should be (None) } it should "allow components to change module" in { val renames = RenameMap() renames.rename(foo, fooB) renames.get(foo) should be (Some(Seq(fooB))) } it should "rename components if their module is renamed" in { val renames = RenameMap() renames.rename(modA, modB) renames.get(foo) should be (Some(Seq(fooB))) renames.get(bar) should be (Some(Seq(barB))) } it should "rename renamed components if the module of the target component is renamed" in { val renames = RenameMap() renames.rename(modA, modB) renames.rename(foo, bar) renames.get(foo) should be (Some(Seq(barB))) } }