defpackage firrtl/compiler :
  import core
  import verse
  import firrtl/passes
  import firrtl/errors
  import firrtl/flo
  import firrtl/verilog
  import firrtl/ir2
  import firrtl/ir-utils

public defstruct StandardFlo <: Compiler :
   file: String with: (as-method => true)
public defmethod passes (c:StandardFlo) -> List<Pass> :
   to-list $ [
      CheckHighForm()
      ;; TempElimination()
      ToWorkingIR()
      MakeExplicitReset()
      ResolveKinds()
      CheckKinds()
      InferTypes()
      CheckTypes()
      ResolveGenders()
      CheckGenders()
      ExpandAccessors()
      LowerToGround()
      ExpandIndexedConnects()
      ExpandWhens()
      InferWidths()
      Pad()
      Inline()
      SplitExp()
      ToRealIR()
      Flo(file(c))
   ]

public defstruct StandardVerilog <: Compiler :
   file: String with: (as-method => true)
public defmethod passes (c:StandardVerilog) -> List<Pass> :
   to-list $ [
      CheckHighForm()
      ;; TempElimination()
      ToWorkingIR()
      MakeExplicitReset()
      ResolveKinds()
      CheckKinds()
      InferTypes()
      CheckTypes()
      ResolveGenders()
      CheckGenders()
      ExpandAccessors()
      LowerToGround()
      ExpandIndexedConnects()
      ExpandWhens()
      InferWidths()
      ;Inline()
      SplitExp()
      ToRealIR()
      Verilog(file(c))
   ]

;============= DRIVER ======================================
public defn run-passes (c:Circuit,comp:Compiler) : 
   run-passes(c,passes(comp))
public defn run-passes (c:Circuit,ls:List<Pass>) :
   var c*:Circuit = c
   println("Compiling!")
   if PRINT-CIRCUITS : println("Original Circuit")
   if PRINT-CIRCUITS : print(c)
   for p in ls do : 
      if PRINT-CIRCUITS : println(name(p))
      c* = pass(p)(c*)
      if PRINT-CIRCUITS : print(c*)
      if PRINT-CIRCUITS : println-all(["Finished " name(p) "\n"])
   println("Done!")