/src/main/scala/firrtl/passes/

• ../
• CInferMDir.scala
• CheckChirrtl.scala
• CheckFlows.scala
• CheckHighForm.scala
• CheckInitialization.scala
• CheckTypes.scala
• CheckWidths.scala
• CommonSubexpressionElimination.scala
• ConvertFixedToSInt.scala
• ExpandConnects.scala
• ExpandWhens.scala
• InferBinaryPoints.scala
• InferTypes.scala
• InferWidths.scala
• Inline.scala
• LegalizeConnects.scala
• LowerTypes.scala
• PadWidths.scala
• Pass.scala
• PullMuxes.scala
• RemoveAccesses.scala
• RemoveCHIRRTL.scala
• RemoveEmpty.scala
• RemoveIntervals.scala
• RemoveValidIf.scala
• ReplaceAccesses.scala
• ResolveFlows.scala
• ResolveKinds.scala
• SplitExpressions.scala
• ToWorkingIR.scala
• TrimIntervals.scala
• Uniquify.scala
• VerilogModulusCleanup.scala
• VerilogPrep.scala
• ZeroLengthVecs.scala
• ZeroWidth.scala
• clocklist
• memlib
• wiring