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package firrtl

import com.typesafe.scalalogging.LazyLogging
import java.io.Writer

import Utils._
import firrtl.passes._


// ===========================================
//                 Annotations
// -------------------------------------------
case class AnnotationException(message: String) extends Exception(message)
trait Named { def name: String }
case class ModuleName(name: String) extends Named
case class ComponentName(name: String, module: ModuleName) extends Named

// - Associated with an arbitrary serializable annotation
trait Annotation {
   def serialize: String
}

// - Used to identify which annotation is consumed by which pass
trait CircuitAnnotationKind
case object UnknownCAKind extends CircuitAnnotationKind

// - A collection of annotations on a given circuit
// - Call update to keep annotations synced with circuit after
//    a transformation modifies module or component names
trait CircuitAnnotation {
   def kind: CircuitAnnotationKind
   def update (renames: RenameMap): CircuitAnnotation
}

// - A class that contains a map from old name to modified names
// - Generated by transformations that modify names
trait RenameMap { def map: Map[Named, Seq[Named]] }
case class BasicRenameMap(map: Map[Named,Seq[Named]]) extends RenameMap


// ===========================================
//                 Transforms
// -------------------------------------------

case class TransformResult (
   circuit: Circuit,
   renames: Option[RenameMap] = None,
   annotation: Option[CircuitAnnotation] = None)

// - Transforms a circuit
// - Can consume multiple CircuitAnnotation's
trait Transform {
   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult
}

// ===========================================
//                 Compilers
// -------------------------------------------

case class CompilerResult (circuit: Circuit, annotations: Seq[CircuitAnnotation])

// - A sequence of transformations
// - Call compile to executes each transformation in sequence onto
//    a given circuit.
trait Compiler extends LazyLogging {
   def transforms(w: Writer): Seq[Transform]
   def compile(circuit: Circuit, annotations: Seq[CircuitAnnotation], writer: Writer): CompilerResult = {
      transforms(writer).foldLeft(CompilerResult(circuit,annotations))((in: CompilerResult, xform: Transform) => {
         val result = xform.execute(in.circuit,in.annotations)
         val in_remapped = result.renames match {
            case Some(renames) => in.annotations.map(_.update(renames))
            case None => in.annotations
         }
         val full_annotations = in_remapped ++ result.annotation
         CompilerResult(result.circuit,full_annotations)
      })
   }
}