circuit module extmodule input output defname parameter skip is invalid inst of wire node UInt SInt Fixed Analog Clock Reset AsyncReset when else attach add sub mul div rem lt leq gt geq eq neq pad asUInt asSInt asClock shl shr dshl dshr cvt neg not and or xor andr orr xorr cat bits head tail asFixedPoint bpshl bpshr bpset mux validif stop printf assert assume cover