circuit Top : module HTIF : input clock : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1], mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.scr.resp.ready := UInt<1>("h00") io.scr.req.bits.data := UInt<1>("h00") io.scr.req.bits.addr := UInt<1>("h00") io.scr.req.bits.rw := UInt<1>("h00") io.scr.req.valid := UInt<1>("h00") io.mem.grant.ready := UInt<1>("h00") io.mem.acquire.bits.union := UInt<1>("h00") io.mem.acquire.bits.a_type := UInt<1>("h00") io.mem.acquire.bits.is_builtin_type := UInt<1>("h00") io.mem.acquire.bits.data := UInt<1>("h00") io.mem.acquire.bits.addr_beat := UInt<1>("h00") io.mem.acquire.bits.client_xact_id := UInt<1>("h00") io.mem.acquire.bits.addr_block := UInt<1>("h00") io.mem.acquire.valid := UInt<1>("h00") io.cpu[0].ipi_rep.bits := UInt<1>("h00") io.cpu[0].ipi_rep.valid := UInt<1>("h00") io.cpu[0].ipi_req.ready := UInt<1>("h00") io.cpu[0].pcr.resp.ready := UInt<1>("h00") io.cpu[0].pcr.req.bits.data := UInt<1>("h00") io.cpu[0].pcr.req.bits.addr := UInt<1>("h00") io.cpu[0].pcr.req.bits.rw := UInt<1>("h00") io.cpu[0].pcr.req.valid := UInt<1>("h00") io.cpu[0].id := UInt<1>("h00") io.cpu[0].reset := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.out.bits := UInt<1>("h00") io.host.out.valid := UInt<1>("h00") io.host.in.ready := UInt<1>("h00") io.host.clk_edge := UInt<1>("h00") io.host.clk := UInt<1>("h00") io.host.debug_stats_pcr := io.cpu[0].debug_stats_pcr reg rx_count : UInt<15>, clock, reset onreset rx_count := UInt<15>("h00") reg rx_shifter : UInt<64>, clock, reset node T_934 = bits(rx_shifter, 63, 16) node rx_shifter_in = cat(io.host.in.bits, T_934) node next_cmd = bits(rx_shifter_in, 3, 0) reg cmd : UInt, clock, reset reg size : UInt, clock, reset reg pos : UInt, clock, reset reg seqno : UInt, clock, reset reg addr : UInt, clock, reset node T_947 = and(io.host.in.valid, io.host.in.ready) when T_947 : rx_shifter := rx_shifter_in node T_949 = addw(rx_count, UInt<1>("h01")) rx_count := T_949 node T_951 = eq(rx_count, UInt<2>("h03")) when T_951 : cmd := next_cmd node T_952 = bits(rx_shifter_in, 15, 4) size := T_952 node T_953 = bits(rx_shifter_in, 15, 7) pos := T_953 node T_954 = bits(rx_shifter_in, 23, 16) seqno := T_954 node T_955 = bits(rx_shifter_in, 63, 24) addr := T_955 skip skip node rx_word_count = shr(rx_count, 2) node T_957 = bits(rx_count, 1, 0) node T_958 = not(T_957) node T_960 = eq(T_958, UInt<1>("h00")) node rx_word_done = and(io.host.in.valid, T_960) cmem packet_ram : UInt<64>[8], clock node T_965 = and(rx_word_done, io.host.in.ready) when T_965 : node T_966 = bits(rx_word_count, 2, 0) node T_968 = subw(T_966, UInt<1>("h01")) infer accessor T_969 = packet_ram[T_968] T_969 := rx_shifter_in skip node pcr_addr = bits(addr, 11, 0) node pcr_coreid = bits(addr, 21, 20) infer accessor pcr_wdata = packet_ram[UInt<1>("h00")] node T_981 = bits(size, 2, 0) node T_983 = neq(T_981, UInt<1>("h00")) node T_984 = bits(addr, 2, 0) node T_986 = neq(T_984, UInt<1>("h00")) node bad_mem_packet = or(T_983, T_986) node T_988 = eq(cmd, UInt<1>("h00")) node T_989 = eq(cmd, UInt<1>("h01")) node T_990 = or(T_988, T_989) node T_991 = eq(cmd, UInt<2>("h02")) node T_992 = eq(cmd, UInt<2>("h03")) node T_993 = or(T_991, T_992) node T_995 = neq(size, UInt<1>("h01")) node T_997 = mux(T_993, T_995, UInt<1>("h01")) node nack = mux(T_990, bad_mem_packet, T_997) reg tx_count : UInt<15>, clock, reset onreset tx_count := UInt<15>("h00") node tx_subword_count = bits(tx_count, 1, 0) node tx_word_count = bits(tx_count, 14, 2) node T_1003 = bits(tx_word_count, 2, 0) node packet_ram_raddr = subw(T_1003, UInt<1>("h01")) node T_1006 = and(io.host.out.valid, io.host.out.ready) when T_1006 : node T_1008 = addw(tx_count, UInt<1>("h01")) tx_count := T_1008 skip node T_1010 = eq(rx_word_count, UInt<1>("h00")) node T_1011 = neq(next_cmd, UInt<1>("h01")) node T_1012 = neq(next_cmd, UInt<2>("h03")) node T_1013 = and(T_1011, T_1012) node T_1014 = eq(rx_word_count, size) node T_1015 = bits(rx_word_count, 2, 0) node T_1017 = eq(T_1015, UInt<1>("h00")) node T_1018 = or(T_1014, T_1017) node T_1019 = mux(T_1010, T_1013, T_1018) node rx_done = and(rx_word_done, T_1019) node T_1022 = eq(nack, UInt<1>("h00")) node T_1023 = eq(cmd, UInt<1>("h00")) node T_1024 = eq(cmd, UInt<2>("h02")) node T_1025 = or(T_1023, T_1024) node T_1026 = eq(cmd, UInt<2>("h03")) node T_1027 = or(T_1025, T_1026) node T_1028 = and(T_1022, T_1027) node tx_size = mux(T_1028, size, UInt<1>("h00")) node T_1031 = not(tx_subword_count) node T_1033 = eq(T_1031, UInt<1>("h00")) node T_1034 = and(io.host.out.ready, T_1033) node T_1035 = eq(tx_word_count, tx_size) node T_1037 = gt(tx_word_count, UInt<1>("h00")) node T_1038 = not(packet_ram_raddr) node T_1040 = eq(T_1038, UInt<1>("h00")) node T_1041 = and(T_1037, T_1040) node T_1042 = or(T_1035, T_1041) node tx_done = and(T_1034, T_1042) reg state : UInt, clock, reset onreset state := UInt<1>("h00") node T_1054 = eq(state, UInt<3>("h04")) node T_1055 = and(T_1054, io.mem.acquire.ready) node T_1056 = eq(state, UInt<3>("h05")) node T_1057 = and(T_1056, io.mem.grant.valid) node T_1058 = or(T_1055, T_1057) reg cnt : UInt<2>, clock, reset onreset cnt := UInt<2>("h00") when T_1058 : node T_1062 = eq(cnt, UInt<2>("h03")) node T_1064 = and(UInt<1>("h00"), T_1062) node T_1067 = addw(cnt, UInt<1>("h01")) node T_1068 = mux(T_1064, UInt<1>("h00"), T_1067) cnt := T_1068 skip node cnt_done = and(T_1058, T_1062) node T_1071 = eq(rx_word_count, UInt<1>("h00")) node rx_cmd = mux(T_1071, next_cmd, cmd) node T_1073 = eq(state, UInt<1>("h00")) node T_1074 = and(T_1073, rx_done) when T_1074 : node T_1075 = eq(rx_cmd, UInt<1>("h00")) node T_1076 = eq(rx_cmd, UInt<1>("h01")) node T_1077 = eq(rx_cmd, UInt<2>("h02")) node T_1078 = eq(rx_cmd, UInt<2>("h03")) node T_1079 = or(T_1077, T_1078) node T_1080 = mux(T_1079, UInt<1>("h01"), UInt<3>("h07")) node T_1081 = mux(T_1076, UInt<3>("h04"), T_1080) node T_1082 = mux(T_1075, UInt<2>("h03"), T_1081) state := T_1082 skip node T_1083 = eq(state, UInt<3>("h04")) when T_1083 : when cnt_done : state := UInt<3>("h06") skip skip node T_1084 = eq(state, UInt<2>("h03")) when T_1084 : when io.mem.acquire.ready : state := UInt<3>("h05") skip skip node T_1085 = eq(state, UInt<3>("h06")) node T_1086 = and(T_1085, io.mem.grant.valid) when T_1086 : node T_1087 = eq(cmd, UInt<1>("h00")) node T_1089 = eq(pos, UInt<1>("h01")) node T_1090 = or(T_1087, T_1089) node T_1091 = mux(T_1090, UInt<3>("h07"), UInt<1>("h00")) state := T_1091 node T_1093 = subw(pos, UInt<1>("h01")) pos := T_1093 node T_1095 = addw(addr, UInt<4>("h08")) addr := T_1095 skip node T_1096 = eq(state, UInt<3>("h05")) node T_1097 = and(T_1096, cnt_done) when T_1097 : node T_1098 = eq(cmd, UInt<1>("h00")) node T_1100 = eq(pos, UInt<1>("h01")) node T_1101 = or(T_1098, T_1100) node T_1102 = mux(T_1101, UInt<3>("h07"), UInt<1>("h00")) state := T_1102 node T_1104 = subw(pos, UInt<1>("h01")) pos := T_1104 node T_1106 = addw(addr, UInt<4>("h08")) addr := T_1106 skip node T_1107 = eq(state, UInt<3>("h07")) node T_1108 = and(T_1107, tx_done) when T_1108 : node T_1109 = eq(tx_word_count, tx_size) when T_1109 : rx_count := UInt<1>("h00") tx_count := UInt<1>("h00") skip node T_1112 = eq(cmd, UInt<1>("h00")) node T_1114 = neq(pos, UInt<1>("h00")) node T_1115 = and(T_1112, T_1114) node T_1116 = mux(T_1115, UInt<2>("h03"), UInt<1>("h00")) state := T_1116 skip node T_1118 = eq(state, UInt<3>("h05")) node T_1119 = and(T_1118, io.mem.grant.valid) when T_1119 : node T_1120 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00")) infer accessor T_1121 = packet_ram[T_1120] node T_1122 = bits(io.mem.grant.bits.data, 63, 0) T_1121 := T_1122 skip node T_1123 = cat(cnt, UInt<1>("h00")) infer accessor T_1124 = packet_ram[T_1123] node T_1126 = eq(state, UInt<3>("h05")) node T_1127 = and(T_1126, io.mem.grant.valid) when T_1127 : node T_1128 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01")) infer accessor T_1129 = packet_ram[T_1128] node T_1130 = bits(io.mem.grant.bits.data, 127, 64) T_1129 := T_1130 skip node T_1131 = cat(cnt, UInt<1>("h01")) infer accessor T_1132 = packet_ram[T_1131] node mem_req_data = cat(T_1132, T_1124) node init_addr = shr(addr, 3) node T_1135 = eq(state, UInt<2>("h03")) node T_1136 = eq(state, UInt<3>("h04")) node T_1137 = or(T_1135, T_1136) io.mem.acquire.valid := T_1137 node T_1138 = eq(cmd, UInt<1>("h01")) node T_1175 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1176 = cat(T_1175, UInt<1>("h01")) wire T_1208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1208.union := UInt<1>("h00") T_1208.a_type := UInt<1>("h00") T_1208.is_builtin_type := UInt<1>("h00") T_1208.data := UInt<1>("h00") T_1208.addr_beat := UInt<1>("h00") T_1208.client_xact_id := UInt<1>("h00") T_1208.addr_block := UInt<1>("h00") T_1208.is_builtin_type := UInt<1>("h01") T_1208.a_type := UInt<3>("h03") T_1208.client_xact_id := UInt<1>("h00") T_1208.addr_block := init_addr T_1208.addr_beat := cnt T_1208.data := mem_req_data T_1208.union := T_1176 node T_1250 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1251 = cat(UInt<3>("h07"), T_1250) wire T_1285 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1285.union := UInt<1>("h00") T_1285.a_type := UInt<1>("h00") T_1285.is_builtin_type := UInt<1>("h00") T_1285.data := UInt<1>("h00") T_1285.addr_beat := UInt<1>("h00") T_1285.client_xact_id := UInt<1>("h00") T_1285.addr_block := UInt<1>("h00") T_1285.is_builtin_type := UInt<1>("h01") T_1285.a_type := UInt<3>("h01") T_1285.client_xact_id := UInt<1>("h00") T_1285.addr_block := init_addr T_1285.addr_beat := UInt<1>("h00") T_1285.data := UInt<1>("h00") T_1285.union := T_1251 wire T_1354 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1354 <> T_1285 when T_1138 : T_1354 <> T_1208 skip io.mem.acquire.bits <> T_1354 io.mem.grant.ready := UInt<1>("h01") reg pcrReadData : UInt<64>, clock, reset reg T_1389 : UInt<1>, clock, reset onreset T_1389 := UInt<1>("h01") reg T_1391 : UInt<1>, clock, reset onreset T_1391 := UInt<1>("h00") node T_1393 = eq(pcr_coreid, UInt<1>("h00")) node T_1394 = eq(state, UInt<1>("h01")) node T_1395 = and(T_1394, T_1393) node T_1397 = neq(pcr_addr, UInt<11>("h0782")) node T_1398 = and(T_1395, T_1397) io.cpu[0].pcr.req.valid := T_1398 node T_1399 = eq(cmd, UInt<2>("h03")) io.cpu[0].pcr.req.bits.rw := T_1399 io.cpu[0].pcr.req.bits.addr := pcr_addr io.cpu[0].pcr.req.bits.data := pcr_wdata io.cpu[0].reset := T_1389 when io.cpu[0].ipi_rep.ready : T_1391 := UInt<1>("h00") skip io.cpu[0].ipi_rep.valid := T_1391 io.cpu[0].ipi_req.ready := UInt<1>("h01") node T_1403 = eq(io.cpu[0].ipi_req.bits, UInt<1>("h00")) node T_1404 = and(io.cpu[0].ipi_req.valid, T_1403) when T_1404 : T_1391 := UInt<1>("h01") skip node T_1406 = and(io.cpu[0].pcr.req.ready, io.cpu[0].pcr.req.valid) when T_1406 : state := UInt<2>("h02") skip node T_1407 = eq(state, UInt<1>("h01")) node T_1408 = and(T_1407, T_1393) node T_1410 = eq(pcr_addr, UInt<11>("h0782")) node T_1411 = and(T_1408, T_1410) when T_1411 : node T_1412 = eq(cmd, UInt<2>("h03")) when T_1412 : node T_1413 = bit(pcr_wdata, 0) T_1389 := T_1413 skip pcrReadData := T_1389 state := UInt<3>("h07") skip io.cpu[0].pcr.resp.ready := UInt<1>("h01") node T_1415 = eq(state, UInt<2>("h02")) node T_1416 = and(T_1415, io.cpu[0].pcr.resp.valid) when T_1416 : pcrReadData := io.cpu[0].pcr.resp.bits state := UInt<3>("h07") skip node T_1417 = eq(state, UInt<1>("h01")) node T_1418 = not(pcr_coreid) node T_1420 = eq(T_1418, UInt<1>("h00")) node T_1421 = and(T_1417, T_1420) io.scr.req.valid := T_1421 node T_1422 = bits(addr, 5, 0) io.scr.req.bits.addr := T_1422 io.scr.req.bits.data := pcr_wdata node T_1423 = eq(cmd, UInt<2>("h03")) io.scr.req.bits.rw := T_1423 io.scr.resp.ready := UInt<1>("h01") node T_1425 = and(io.scr.req.ready, io.scr.req.valid) when T_1425 : state := UInt<2>("h02") skip node T_1426 = eq(state, UInt<2>("h02")) node T_1427 = and(T_1426, io.scr.resp.valid) when T_1427 : pcrReadData := io.scr.resp.bits state := UInt<3>("h07") skip node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) node T_1431 = cat(addr, seqno) node T_1432 = cat(tx_size, tx_cmd_ext) node tx_header = cat(T_1431, T_1432) node T_1435 = eq(tx_word_count, UInt<1>("h00")) node T_1436 = eq(cmd, UInt<2>("h02")) node T_1437 = eq(cmd, UInt<2>("h03")) node T_1438 = or(T_1436, T_1437) infer accessor T_1439 = packet_ram[packet_ram_raddr] node T_1440 = mux(T_1438, pcrReadData, T_1439) node tx_data = mux(T_1435, tx_header, T_1440) node T_1442 = eq(state, UInt<1>("h00")) io.host.in.ready := T_1442 node T_1443 = eq(state, UInt<3>("h07")) io.host.out.valid := T_1443 node T_1444 = bits(tx_count, 1, 0) node T_1446 = cat(T_1444, UInt<4>("h00")) node T_1447 = dshr(tx_data, T_1446) io.host.out.bits := T_1447 module ClientTileLinkIOWrapper : input clock : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} io.out.release.bits.voluntary := UInt<1>("h00") io.out.release.bits.r_type := UInt<1>("h00") io.out.release.bits.data := UInt<1>("h00") io.out.release.bits.addr_beat := UInt<1>("h00") io.out.release.bits.client_xact_id := UInt<1>("h00") io.out.release.bits.addr_block := UInt<1>("h00") io.out.release.valid := UInt<1>("h00") io.out.probe.ready := UInt<1>("h00") io.out.grant.ready := UInt<1>("h00") io.out.acquire.bits.union := UInt<1>("h00") io.out.acquire.bits.a_type := UInt<1>("h00") io.out.acquire.bits.is_builtin_type := UInt<1>("h00") io.out.acquire.bits.data := UInt<1>("h00") io.out.acquire.bits.addr_beat := UInt<1>("h00") io.out.acquire.bits.client_xact_id := UInt<1>("h00") io.out.acquire.bits.addr_block := UInt<1>("h00") io.out.acquire.valid := UInt<1>("h00") io.in.grant.bits.g_type := UInt<1>("h00") io.in.grant.bits.is_builtin_type := UInt<1>("h00") io.in.grant.bits.manager_xact_id := UInt<1>("h00") io.in.grant.bits.client_xact_id := UInt<1>("h00") io.in.grant.bits.data := UInt<1>("h00") io.in.grant.bits.addr_beat := UInt<1>("h00") io.in.grant.valid := UInt<1>("h00") io.in.acquire.ready := UInt<1>("h00") io.out.acquire <> io.in.acquire io.in.grant <> io.out.grant io.out.probe.ready := UInt<1>("h01") io.out.release.valid := UInt<1>("h00") module FinishQueue : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.dst := UInt<1>("h00") io.deq.bits.fin.manager_xact_id := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem T_463 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2], clock reg T_465 : UInt<1>, clock, reset onreset T_465 := UInt<1>("h00") reg T_467 : UInt<1>, clock, reset onreset T_467 := UInt<1>("h00") reg T_469 : UInt<1>, clock, reset onreset T_469 := UInt<1>("h00") node T_470 = eq(T_465, T_467) node T_472 = eq(T_469, UInt<1>("h00")) node T_473 = and(T_470, T_472) node T_474 = and(T_470, T_469) node T_476 = and(UInt<1>("h00"), T_473) node T_477 = and(T_476, io.deq.ready) node T_478 = and(io.enq.ready, io.enq.valid) node T_480 = eq(T_477, UInt<1>("h00")) node T_481 = and(T_478, T_480) node T_482 = and(io.deq.ready, io.deq.valid) node T_484 = eq(T_477, UInt<1>("h00")) node T_485 = and(T_482, T_484) when T_481 : infer accessor T_486 = T_463[T_465] T_486 <> io.enq.bits node T_537 = eq(T_465, UInt<1>("h01")) node T_539 = and(UInt<1>("h00"), T_537) node T_542 = addw(T_465, UInt<1>("h01")) node T_543 = mux(T_539, UInt<1>("h00"), T_542) T_465 := T_543 skip when T_485 : node T_545 = eq(T_467, UInt<1>("h01")) node T_547 = and(UInt<1>("h00"), T_545) node T_550 = addw(T_467, UInt<1>("h01")) node T_551 = mux(T_547, UInt<1>("h00"), T_550) T_467 := T_551 skip node T_552 = neq(T_481, T_485) when T_552 : T_469 := T_481 skip node T_554 = eq(T_473, UInt<1>("h00")) node T_556 = and(UInt<1>("h00"), io.enq.valid) node T_557 = or(T_554, T_556) io.deq.valid := T_557 node T_559 = eq(T_474, UInt<1>("h00")) node T_561 = and(UInt<1>("h00"), io.deq.ready) node T_562 = or(T_559, T_561) io.enq.ready := T_562 infer accessor T_563 = T_463[T_467] wire T_663 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>} T_663 <> T_563 when T_476 : T_663 <> io.enq.bits skip io.deq.bits <> T_663 node T_713 = subw(T_465, T_467) node T_714 = and(T_469, T_470) node T_715 = cat(T_714, T_713) io.count := T_715 module FinishUnit : input clock : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready := UInt<1>("h00") io.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.finish.bits.header.dst := UInt<1>("h00") io.finish.bits.header.src := UInt<1>("h00") io.finish.valid := UInt<1>("h00") io.refill.bits.g_type := UInt<1>("h00") io.refill.bits.is_builtin_type := UInt<1>("h00") io.refill.bits.manager_xact_id := UInt<1>("h00") io.refill.bits.client_xact_id := UInt<1>("h00") io.refill.bits.data := UInt<1>("h00") io.refill.bits.addr_beat := UInt<1>("h00") io.refill.valid := UInt<1>("h00") io.grant.ready := UInt<1>("h00") node T_442 = and(io.grant.ready, io.grant.valid) wire T_447 : UInt<3>[1] T_447[0] := UInt<3>("h05") node T_450 = eq(T_447[0], io.grant.bits.payload.g_type) node T_452 = or(UInt<1>("h00"), T_450) wire T_454 : UInt<1>[2] T_454[0] := UInt<1>("h00") T_454[1] := UInt<1>("h01") node T_458 = eq(T_454[0], io.grant.bits.payload.g_type) node T_459 = eq(T_454[1], io.grant.bits.payload.g_type) node T_461 = or(UInt<1>("h00"), T_458) node T_462 = or(T_461, T_459) node T_463 = mux(io.grant.bits.payload.is_builtin_type, T_452, T_462) node T_464 = and(UInt<1>("h01"), T_463) node T_465 = and(T_442, T_464) reg T_467 : UInt<2>, clock, reset onreset T_467 := UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 := T_475 skip node T_476 = and(T_465, T_469) node T_477 = mux(T_464, T_467, UInt<1>("h00")) node T_478 = mux(T_464, T_476, T_442) inst T_529 of FinishQueue T_529.io.deq.ready := UInt<1>("h00") T_529.io.enq.bits.dst := UInt<1>("h00") T_529.io.enq.bits.fin.manager_xact_id := UInt<1>("h00") T_529.io.enq.valid := UInt<1>("h00") T_529.clock := clock T_529.reset := reset node T_534 = and(io.grant.ready, io.grant.valid) node T_537 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_539 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_540 = and(io.grant.bits.payload.is_builtin_type, T_539) node T_542 = eq(T_540, UInt<1>("h00")) node T_543 = and(T_537, T_542) node T_544 = and(T_534, T_543) wire T_548 : UInt<3>[1] T_548[0] := UInt<3>("h05") node T_551 = eq(T_548[0], io.grant.bits.payload.g_type) node T_553 = or(UInt<1>("h00"), T_551) wire T_555 : UInt<1>[2] T_555[0] := UInt<1>("h00") T_555[1] := UInt<1>("h01") node T_559 = eq(T_555[0], io.grant.bits.payload.g_type) node T_560 = eq(T_555[1], io.grant.bits.payload.g_type) node T_562 = or(UInt<1>("h00"), T_559) node T_563 = or(T_562, T_560) node T_564 = mux(io.grant.bits.payload.is_builtin_type, T_553, T_563) node T_565 = and(UInt<1>("h01"), T_564) node T_567 = eq(T_565, UInt<1>("h00")) node T_568 = or(T_567, T_478) node T_569 = and(T_544, T_568) T_529.io.enq.valid := T_569 wire T_595 : {manager_xact_id : UInt<4>} T_595.manager_xact_id := UInt<1>("h00") T_595.manager_xact_id := io.grant.bits.payload.manager_xact_id T_529.io.enq.bits.fin <> T_595 T_529.io.enq.bits.dst := io.grant.bits.header.src io.finish.bits.header.src := UInt<1>("h00") io.finish.bits.header.dst := T_529.io.deq.bits.dst io.finish.bits.payload <> T_529.io.deq.bits.fin io.finish.valid := T_529.io.deq.valid T_529.io.deq.ready := io.finish.ready io.refill.valid := io.grant.valid io.refill.bits <> io.grant.bits.payload node T_624 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_626 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_627 = and(io.grant.bits.payload.is_builtin_type, T_626) node T_629 = eq(T_627, UInt<1>("h00")) node T_630 = and(T_624, T_629) node T_632 = eq(T_630, UInt<1>("h00")) node T_633 = or(T_529.io.enq.ready, T_632) node T_634 = and(T_633, io.refill.ready) io.grant.ready := T_634 io.ready := T_529.io.enq.ready module ClientTileLinkNetworkPort : input clock : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.network.release.bits.payload.voluntary := UInt<1>("h00") io.network.release.bits.payload.r_type := UInt<1>("h00") io.network.release.bits.payload.data := UInt<1>("h00") io.network.release.bits.payload.addr_beat := UInt<1>("h00") io.network.release.bits.payload.client_xact_id := UInt<1>("h00") io.network.release.bits.payload.addr_block := UInt<1>("h00") io.network.release.bits.header.dst := UInt<1>("h00") io.network.release.bits.header.src := UInt<1>("h00") io.network.release.valid := UInt<1>("h00") io.network.probe.ready := UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.network.finish.bits.header.dst := UInt<1>("h00") io.network.finish.bits.header.src := UInt<1>("h00") io.network.finish.valid := UInt<1>("h00") io.network.grant.ready := UInt<1>("h00") io.network.acquire.bits.payload.union := UInt<1>("h00") io.network.acquire.bits.payload.a_type := UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") io.network.acquire.bits.payload.data := UInt<1>("h00") io.network.acquire.bits.payload.addr_beat := UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") io.network.acquire.bits.payload.addr_block := UInt<1>("h00") io.network.acquire.bits.header.dst := UInt<1>("h00") io.network.acquire.bits.header.src := UInt<1>("h00") io.network.acquire.valid := UInt<1>("h00") io.client.release.ready := UInt<1>("h00") io.client.probe.bits.p_type := UInt<1>("h00") io.client.probe.bits.addr_block := UInt<1>("h00") io.client.probe.valid := UInt<1>("h00") io.client.grant.bits.g_type := UInt<1>("h00") io.client.grant.bits.is_builtin_type := UInt<1>("h00") io.client.grant.bits.manager_xact_id := UInt<1>("h00") io.client.grant.bits.client_xact_id := UInt<1>("h00") io.client.grant.bits.data := UInt<1>("h00") io.client.grant.bits.addr_beat := UInt<1>("h00") io.client.grant.valid := UInt<1>("h00") io.client.acquire.ready := UInt<1>("h00") inst finisher of FinishUnit finisher.io.finish.ready := UInt<1>("h00") finisher.io.refill.ready := UInt<1>("h00") finisher.io.grant.bits.payload.g_type := UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type := UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.data := UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat := UInt<1>("h00") finisher.io.grant.bits.header.dst := UInt<1>("h00") finisher.io.grant.bits.header.src := UInt<1>("h00") finisher.io.grant.valid := UInt<1>("h00") finisher.clock := clock finisher.reset := reset finisher.io.grant <> io.network.grant io.network.finish <> finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} acq_with_header.bits.payload.union := UInt<1>("h00") acq_with_header.bits.payload.a_type := UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") acq_with_header.bits.payload.data := UInt<1>("h00") acq_with_header.bits.payload.addr_beat := UInt<1>("h00") acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") acq_with_header.bits.payload.addr_block := UInt<1>("h00") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.bits.header.src := UInt<1>("h00") acq_with_header.valid := UInt<1>("h00") acq_with_header.ready := UInt<1>("h00") acq_with_header.bits.payload <> io.client.acquire.bits acq_with_header.bits.header.src := UInt<1>("h00") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.valid := io.client.acquire.valid io.client.acquire.ready := acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} rel_with_header.bits.payload.voluntary := UInt<1>("h00") rel_with_header.bits.payload.r_type := UInt<1>("h00") rel_with_header.bits.payload.data := UInt<1>("h00") rel_with_header.bits.payload.addr_beat := UInt<1>("h00") rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") rel_with_header.bits.payload.addr_block := UInt<1>("h00") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.bits.header.src := UInt<1>("h00") rel_with_header.valid := UInt<1>("h00") rel_with_header.ready := UInt<1>("h00") rel_with_header.bits.payload <> io.client.release.bits rel_with_header.bits.header.src := UInt<1>("h00") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.valid := io.client.release.valid io.client.release.ready := rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type := UInt<1>("h00") prb_without_header.bits.addr_block := UInt<1>("h00") prb_without_header.valid := UInt<1>("h00") prb_without_header.ready := UInt<1>("h00") prb_without_header.valid := io.network.probe.valid prb_without_header.bits <> io.network.probe.bits.payload io.network.probe.ready := prb_without_header.ready io.network.acquire.bits <> acq_with_header.bits node T_2346 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid := T_2346 node T_2347 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready := T_2347 io.network.release <> rel_with_header io.client.probe <> prb_without_header io.client.grant <> finisher.io.refill module Queue : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.payload.union := UInt<1>("h00") io.deq.bits.payload.a_type := UInt<1>("h00") io.deq.bits.payload.is_builtin_type := UInt<1>("h00") io.deq.bits.payload.data := UInt<1>("h00") io.deq.bits.payload.addr_beat := UInt<1>("h00") io.deq.bits.payload.client_xact_id := UInt<1>("h00") io.deq.bits.payload.addr_block := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2], clock reg T_332 : UInt<1>, clock, reset onreset T_332 := UInt<1>("h00") reg T_334 : UInt<1>, clock, reset onreset T_334 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_332, T_334) node T_339 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_339) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_345 = and(io.enq.ready, io.enq.valid) node T_347 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_345, T_347) node T_349 = and(io.deq.ready, io.deq.valid) node T_351 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_349, T_351) when do_enq : infer accessor T_353 = ram[T_332] T_353 <> io.enq.bits node T_389 = eq(T_332, UInt<1>("h01")) node T_391 = and(UInt<1>("h00"), T_389) node T_394 = addw(T_332, UInt<1>("h01")) node T_395 = mux(T_391, UInt<1>("h00"), T_394) T_332 := T_395 skip when do_deq : node T_397 = eq(T_334, UInt<1>("h01")) node T_399 = and(UInt<1>("h00"), T_397) node T_402 = addw(T_334, UInt<1>("h01")) node T_403 = mux(T_399, UInt<1>("h00"), T_402) T_334 := T_403 skip node T_404 = neq(do_enq, do_deq) when T_404 : maybe_full := do_enq skip node T_406 = eq(empty, UInt<1>("h00")) node T_408 = and(UInt<1>("h00"), io.enq.valid) node T_409 = or(T_406, T_408) io.deq.valid := T_409 node T_411 = eq(full, UInt<1>("h00")) node T_413 = and(UInt<1>("h00"), io.deq.ready) node T_414 = or(T_411, T_413) io.enq.ready := T_414 infer accessor T_415 = ram[T_334] wire T_485 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} T_485 <> T_415 when maybe_flow : T_485 <> io.enq.bits skip io.deq.bits <> T_485 node ptr_diff = subw(T_332, T_334) node T_521 = and(maybe_full, ptr_match) node T_522 = cat(T_521, ptr_diff) io.count := T_522 module Queue_2 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.payload.p_type := UInt<1>("h00") io.deq.bits.payload.addr_block := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2], clock reg T_287 : UInt<1>, clock, reset onreset T_287 := UInt<1>("h00") reg T_289 : UInt<1>, clock, reset onreset T_289 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_287, T_289) node T_294 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_294) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_300 = and(io.enq.ready, io.enq.valid) node T_302 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_300, T_302) node T_304 = and(io.deq.ready, io.deq.valid) node T_306 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_304, T_306) when do_enq : infer accessor T_308 = ram[T_287] T_308 <> io.enq.bits node T_339 = eq(T_287, UInt<1>("h01")) node T_341 = and(UInt<1>("h00"), T_339) node T_344 = addw(T_287, UInt<1>("h01")) node T_345 = mux(T_341, UInt<1>("h00"), T_344) T_287 := T_345 skip when do_deq : node T_347 = eq(T_289, UInt<1>("h01")) node T_349 = and(UInt<1>("h00"), T_347) node T_352 = addw(T_289, UInt<1>("h01")) node T_353 = mux(T_349, UInt<1>("h00"), T_352) T_289 := T_353 skip node T_354 = neq(do_enq, do_deq) when T_354 : maybe_full := do_enq skip node T_356 = eq(empty, UInt<1>("h00")) node T_358 = and(UInt<1>("h00"), io.enq.valid) node T_359 = or(T_356, T_358) io.deq.valid := T_359 node T_361 = eq(full, UInt<1>("h00")) node T_363 = and(UInt<1>("h00"), io.deq.ready) node T_364 = or(T_361, T_363) io.enq.ready := T_364 infer accessor T_365 = ram[T_289] wire T_425 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}} T_425 <> T_365 when maybe_flow : T_425 <> io.enq.bits skip io.deq.bits <> T_425 node ptr_diff = subw(T_287, T_289) node T_456 = and(maybe_full, ptr_match) node T_457 = cat(T_456, ptr_diff) io.count := T_457 module Queue_3 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.payload.voluntary := UInt<1>("h00") io.deq.bits.payload.r_type := UInt<1>("h00") io.deq.bits.payload.data := UInt<1>("h00") io.deq.bits.payload.addr_beat := UInt<1>("h00") io.deq.bits.payload.client_xact_id := UInt<1>("h00") io.deq.bits.payload.addr_block := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2], clock reg T_323 : UInt<1>, clock, reset onreset T_323 := UInt<1>("h00") reg T_325 : UInt<1>, clock, reset onreset T_325 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_323, T_325) node T_330 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_330) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_336 = and(io.enq.ready, io.enq.valid) node T_338 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_336, T_338) node T_340 = and(io.deq.ready, io.deq.valid) node T_342 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_340, T_342) when do_enq : infer accessor T_344 = ram[T_323] T_344 <> io.enq.bits node T_379 = eq(T_323, UInt<1>("h01")) node T_381 = and(UInt<1>("h00"), T_379) node T_384 = addw(T_323, UInt<1>("h01")) node T_385 = mux(T_381, UInt<1>("h00"), T_384) T_323 := T_385 skip when do_deq : node T_387 = eq(T_325, UInt<1>("h01")) node T_389 = and(UInt<1>("h00"), T_387) node T_392 = addw(T_325, UInt<1>("h01")) node T_393 = mux(T_389, UInt<1>("h00"), T_392) T_325 := T_393 skip node T_394 = neq(do_enq, do_deq) when T_394 : maybe_full := do_enq skip node T_396 = eq(empty, UInt<1>("h00")) node T_398 = and(UInt<1>("h00"), io.enq.valid) node T_399 = or(T_396, T_398) io.deq.valid := T_399 node T_401 = eq(full, UInt<1>("h00")) node T_403 = and(UInt<1>("h00"), io.deq.ready) node T_404 = or(T_401, T_403) io.enq.ready := T_404 infer accessor T_405 = ram[T_325] wire T_473 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} T_473 <> T_405 when maybe_flow : T_473 <> io.enq.bits skip io.deq.bits <> T_473 node ptr_diff = subw(T_323, T_325) node T_508 = and(maybe_full, ptr_match) node T_509 = cat(T_508, ptr_diff) io.count := T_509 module Queue_4 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.payload.g_type := UInt<1>("h00") io.deq.bits.payload.is_builtin_type := UInt<1>("h00") io.deq.bits.payload.manager_xact_id := UInt<1>("h00") io.deq.bits.payload.client_xact_id := UInt<1>("h00") io.deq.bits.payload.data := UInt<1>("h00") io.deq.bits.payload.addr_beat := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2], clock reg T_323 : UInt<1>, clock, reset onreset T_323 := UInt<1>("h00") reg T_325 : UInt<1>, clock, reset onreset T_325 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_323, T_325) node T_330 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_330) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_336 = and(io.enq.ready, io.enq.valid) node T_338 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_336, T_338) node T_340 = and(io.deq.ready, io.deq.valid) node T_342 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_340, T_342) when do_enq : infer accessor T_344 = ram[T_323] T_344 <> io.enq.bits node T_379 = eq(T_323, UInt<1>("h01")) node T_381 = and(UInt<1>("h00"), T_379) node T_384 = addw(T_323, UInt<1>("h01")) node T_385 = mux(T_381, UInt<1>("h00"), T_384) T_323 := T_385 skip when do_deq : node T_387 = eq(T_325, UInt<1>("h01")) node T_389 = and(UInt<1>("h00"), T_387) node T_392 = addw(T_325, UInt<1>("h01")) node T_393 = mux(T_389, UInt<1>("h00"), T_392) T_325 := T_393 skip node T_394 = neq(do_enq, do_deq) when T_394 : maybe_full := do_enq skip node T_396 = eq(empty, UInt<1>("h00")) node T_398 = and(UInt<1>("h00"), io.enq.valid) node T_399 = or(T_396, T_398) io.deq.valid := T_399 node T_401 = eq(full, UInt<1>("h00")) node T_403 = and(UInt<1>("h00"), io.deq.ready) node T_404 = or(T_401, T_403) io.enq.ready := T_404 infer accessor T_405 = ram[T_325] wire T_473 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} T_473 <> T_405 when maybe_flow : T_473 <> io.enq.bits skip io.deq.bits <> T_473 node ptr_diff = subw(T_323, T_325) node T_508 = and(maybe_full, ptr_match) node T_509 = cat(T_508, ptr_diff) io.count := T_509 module Queue_5 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.payload.manager_xact_id := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2], clock reg T_278 : UInt<1>, clock, reset onreset T_278 := UInt<1>("h00") reg T_280 : UInt<1>, clock, reset onreset T_280 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_278, T_280) node T_285 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_285) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_291 = and(io.enq.ready, io.enq.valid) node T_293 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_291, T_293) node T_295 = and(io.deq.ready, io.deq.valid) node T_297 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_295, T_297) when do_enq : infer accessor T_299 = ram[T_278] T_299 <> io.enq.bits node T_329 = eq(T_278, UInt<1>("h01")) node T_331 = and(UInt<1>("h00"), T_329) node T_334 = addw(T_278, UInt<1>("h01")) node T_335 = mux(T_331, UInt<1>("h00"), T_334) T_278 := T_335 skip when do_deq : node T_337 = eq(T_280, UInt<1>("h01")) node T_339 = and(UInt<1>("h00"), T_337) node T_342 = addw(T_280, UInt<1>("h01")) node T_343 = mux(T_339, UInt<1>("h00"), T_342) T_280 := T_343 skip node T_344 = neq(do_enq, do_deq) when T_344 : maybe_full := do_enq skip node T_346 = eq(empty, UInt<1>("h00")) node T_348 = and(UInt<1>("h00"), io.enq.valid) node T_349 = or(T_346, T_348) io.deq.valid := T_349 node T_351 = eq(full, UInt<1>("h00")) node T_353 = and(UInt<1>("h00"), io.deq.ready) node T_354 = or(T_351, T_353) io.enq.ready := T_354 infer accessor T_355 = ram[T_280] wire T_413 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}} T_413 <> T_355 when maybe_flow : T_413 <> io.enq.bits skip io.deq.bits <> T_413 node ptr_diff = subw(T_278, T_280) node T_443 = and(maybe_full, ptr_match) node T_444 = cat(T_443, ptr_diff) io.count := T_444 module TileLinkEnqueuer : input clock : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.manager.release.bits.payload.voluntary := UInt<1>("h00") io.manager.release.bits.payload.r_type := UInt<1>("h00") io.manager.release.bits.payload.data := UInt<1>("h00") io.manager.release.bits.payload.addr_beat := UInt<1>("h00") io.manager.release.bits.payload.client_xact_id := UInt<1>("h00") io.manager.release.bits.payload.addr_block := UInt<1>("h00") io.manager.release.bits.header.dst := UInt<1>("h00") io.manager.release.bits.header.src := UInt<1>("h00") io.manager.release.valid := UInt<1>("h00") io.manager.probe.ready := UInt<1>("h00") io.manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.manager.finish.bits.header.dst := UInt<1>("h00") io.manager.finish.bits.header.src := UInt<1>("h00") io.manager.finish.valid := UInt<1>("h00") io.manager.grant.ready := UInt<1>("h00") io.manager.acquire.bits.payload.union := UInt<1>("h00") io.manager.acquire.bits.payload.a_type := UInt<1>("h00") io.manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") io.manager.acquire.bits.payload.data := UInt<1>("h00") io.manager.acquire.bits.payload.addr_beat := UInt<1>("h00") io.manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") io.manager.acquire.bits.payload.addr_block := UInt<1>("h00") io.manager.acquire.bits.header.dst := UInt<1>("h00") io.manager.acquire.bits.header.src := UInt<1>("h00") io.manager.acquire.valid := UInt<1>("h00") io.client.release.ready := UInt<1>("h00") io.client.probe.bits.payload.p_type := UInt<1>("h00") io.client.probe.bits.payload.addr_block := UInt<1>("h00") io.client.probe.bits.header.dst := UInt<1>("h00") io.client.probe.bits.header.src := UInt<1>("h00") io.client.probe.valid := UInt<1>("h00") io.client.finish.ready := UInt<1>("h00") io.client.grant.bits.payload.g_type := UInt<1>("h00") io.client.grant.bits.payload.is_builtin_type := UInt<1>("h00") io.client.grant.bits.payload.manager_xact_id := UInt<1>("h00") io.client.grant.bits.payload.client_xact_id := UInt<1>("h00") io.client.grant.bits.payload.data := UInt<1>("h00") io.client.grant.bits.payload.addr_beat := UInt<1>("h00") io.client.grant.bits.header.dst := UInt<1>("h00") io.client.grant.bits.header.src := UInt<1>("h00") io.client.grant.valid := UInt<1>("h00") io.client.acquire.ready := UInt<1>("h00") inst T_2442 of Queue T_2442.io.deq.ready := UInt<1>("h00") T_2442.io.enq.bits.payload.union := UInt<1>("h00") T_2442.io.enq.bits.payload.a_type := UInt<1>("h00") T_2442.io.enq.bits.payload.is_builtin_type := UInt<1>("h00") T_2442.io.enq.bits.payload.data := UInt<1>("h00") T_2442.io.enq.bits.payload.addr_beat := UInt<1>("h00") T_2442.io.enq.bits.payload.client_xact_id := UInt<1>("h00") T_2442.io.enq.bits.payload.addr_block := UInt<1>("h00") T_2442.io.enq.bits.header.dst := UInt<1>("h00") T_2442.io.enq.bits.header.src := UInt<1>("h00") T_2442.io.enq.valid := UInt<1>("h00") T_2442.clock := clock T_2442.reset := reset T_2442.io.enq.valid := io.client.acquire.valid T_2442.io.enq.bits <> io.client.acquire.bits io.client.acquire.ready := T_2442.io.enq.ready io.manager.acquire <> T_2442.io.deq inst T_2484 of Queue_2 T_2484.io.deq.ready := UInt<1>("h00") T_2484.io.enq.bits.payload.p_type := UInt<1>("h00") T_2484.io.enq.bits.payload.addr_block := UInt<1>("h00") T_2484.io.enq.bits.header.dst := UInt<1>("h00") T_2484.io.enq.bits.header.src := UInt<1>("h00") T_2484.io.enq.valid := UInt<1>("h00") T_2484.clock := clock T_2484.reset := reset T_2484.io.enq.valid := io.manager.probe.valid T_2484.io.enq.bits <> io.manager.probe.bits io.manager.probe.ready := T_2484.io.enq.ready io.client.probe <> T_2484.io.deq inst T_2525 of Queue_3 T_2525.io.deq.ready := UInt<1>("h00") T_2525.io.enq.bits.payload.voluntary := UInt<1>("h00") T_2525.io.enq.bits.payload.r_type := UInt<1>("h00") T_2525.io.enq.bits.payload.data := UInt<1>("h00") T_2525.io.enq.bits.payload.addr_beat := UInt<1>("h00") T_2525.io.enq.bits.payload.client_xact_id := UInt<1>("h00") T_2525.io.enq.bits.payload.addr_block := UInt<1>("h00") T_2525.io.enq.bits.header.dst := UInt<1>("h00") T_2525.io.enq.bits.header.src := UInt<1>("h00") T_2525.io.enq.valid := UInt<1>("h00") T_2525.clock := clock T_2525.reset := reset T_2525.io.enq.valid := io.client.release.valid T_2525.io.enq.bits <> io.client.release.bits io.client.release.ready := T_2525.io.enq.ready io.manager.release <> T_2525.io.deq inst T_2570 of Queue_4 T_2570.io.deq.ready := UInt<1>("h00") T_2570.io.enq.bits.payload.g_type := UInt<1>("h00") T_2570.io.enq.bits.payload.is_builtin_type := UInt<1>("h00") T_2570.io.enq.bits.payload.manager_xact_id := UInt<1>("h00") T_2570.io.enq.bits.payload.client_xact_id := UInt<1>("h00") T_2570.io.enq.bits.payload.data := UInt<1>("h00") T_2570.io.enq.bits.payload.addr_beat := UInt<1>("h00") T_2570.io.enq.bits.header.dst := UInt<1>("h00") T_2570.io.enq.bits.header.src := UInt<1>("h00") T_2570.io.enq.valid := UInt<1>("h00") T_2570.clock := clock T_2570.reset := reset T_2570.io.enq.valid := io.manager.grant.valid T_2570.io.enq.bits <> io.manager.grant.bits io.manager.grant.ready := T_2570.io.enq.ready io.client.grant <> T_2570.io.deq inst T_2610 of Queue_5 T_2610.io.deq.ready := UInt<1>("h00") T_2610.io.enq.bits.payload.manager_xact_id := UInt<1>("h00") T_2610.io.enq.bits.header.dst := UInt<1>("h00") T_2610.io.enq.bits.header.src := UInt<1>("h00") T_2610.io.enq.valid := UInt<1>("h00") T_2610.clock := clock T_2610.reset := reset T_2610.io.enq.valid := io.client.finish.valid T_2610.io.enq.bits <> io.client.finish.bits io.client.finish.ready := T_2610.io.enq.ready io.manager.finish <> T_2610.io.deq module FinishUnit_7 : input clock : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready := UInt<1>("h00") io.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.finish.bits.header.dst := UInt<1>("h00") io.finish.bits.header.src := UInt<1>("h00") io.finish.valid := UInt<1>("h00") io.refill.bits.g_type := UInt<1>("h00") io.refill.bits.is_builtin_type := UInt<1>("h00") io.refill.bits.manager_xact_id := UInt<1>("h00") io.refill.bits.client_xact_id := UInt<1>("h00") io.refill.bits.data := UInt<1>("h00") io.refill.bits.addr_beat := UInt<1>("h00") io.refill.valid := UInt<1>("h00") io.grant.ready := UInt<1>("h00") node T_442 = and(io.grant.ready, io.grant.valid) wire T_447 : UInt<3>[1] T_447[0] := UInt<3>("h05") node T_450 = eq(T_447[0], io.grant.bits.payload.g_type) node T_452 = or(UInt<1>("h00"), T_450) wire T_454 : UInt<1>[2] T_454[0] := UInt<1>("h00") T_454[1] := UInt<1>("h01") node T_458 = eq(T_454[0], io.grant.bits.payload.g_type) node T_459 = eq(T_454[1], io.grant.bits.payload.g_type) node T_461 = or(UInt<1>("h00"), T_458) node T_462 = or(T_461, T_459) node T_463 = mux(io.grant.bits.payload.is_builtin_type, T_452, T_462) node T_464 = and(UInt<1>("h01"), T_463) node T_465 = and(T_442, T_464) reg T_467 : UInt<2>, clock, reset onreset T_467 := UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 := T_475 skip node T_476 = and(T_465, T_469) node T_477 = mux(T_464, T_467, UInt<1>("h00")) node T_478 = mux(T_464, T_476, T_442) inst T_529 of FinishQueue T_529.io.deq.ready := UInt<1>("h00") T_529.io.enq.bits.dst := UInt<1>("h00") T_529.io.enq.bits.fin.manager_xact_id := UInt<1>("h00") T_529.io.enq.valid := UInt<1>("h00") T_529.clock := clock T_529.reset := reset node T_534 = and(io.grant.ready, io.grant.valid) node T_537 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_539 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_540 = and(io.grant.bits.payload.is_builtin_type, T_539) node T_542 = eq(T_540, UInt<1>("h00")) node T_543 = and(T_537, T_542) node T_544 = and(T_534, T_543) wire T_548 : UInt<3>[1] T_548[0] := UInt<3>("h05") node T_551 = eq(T_548[0], io.grant.bits.payload.g_type) node T_553 = or(UInt<1>("h00"), T_551) wire T_555 : UInt<1>[2] T_555[0] := UInt<1>("h00") T_555[1] := UInt<1>("h01") node T_559 = eq(T_555[0], io.grant.bits.payload.g_type) node T_560 = eq(T_555[1], io.grant.bits.payload.g_type) node T_562 = or(UInt<1>("h00"), T_559) node T_563 = or(T_562, T_560) node T_564 = mux(io.grant.bits.payload.is_builtin_type, T_553, T_563) node T_565 = and(UInt<1>("h01"), T_564) node T_567 = eq(T_565, UInt<1>("h00")) node T_568 = or(T_567, T_478) node T_569 = and(T_544, T_568) T_529.io.enq.valid := T_569 wire T_595 : {manager_xact_id : UInt<4>} T_595.manager_xact_id := UInt<1>("h00") T_595.manager_xact_id := io.grant.bits.payload.manager_xact_id T_529.io.enq.bits.fin <> T_595 T_529.io.enq.bits.dst := io.grant.bits.header.src io.finish.bits.header.src := UInt<1>("h01") io.finish.bits.header.dst := T_529.io.deq.bits.dst io.finish.bits.payload <> T_529.io.deq.bits.fin io.finish.valid := T_529.io.deq.valid T_529.io.deq.ready := io.finish.ready io.refill.valid := io.grant.valid io.refill.bits <> io.grant.bits.payload node T_624 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_626 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_627 = and(io.grant.bits.payload.is_builtin_type, T_626) node T_629 = eq(T_627, UInt<1>("h00")) node T_630 = and(T_624, T_629) node T_632 = eq(T_630, UInt<1>("h00")) node T_633 = or(T_529.io.enq.ready, T_632) node T_634 = and(T_633, io.refill.ready) io.grant.ready := T_634 io.ready := T_529.io.enq.ready module ClientTileLinkNetworkPort_6 : input clock : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.network.release.bits.payload.voluntary := UInt<1>("h00") io.network.release.bits.payload.r_type := UInt<1>("h00") io.network.release.bits.payload.data := UInt<1>("h00") io.network.release.bits.payload.addr_beat := UInt<1>("h00") io.network.release.bits.payload.client_xact_id := UInt<1>("h00") io.network.release.bits.payload.addr_block := UInt<1>("h00") io.network.release.bits.header.dst := UInt<1>("h00") io.network.release.bits.header.src := UInt<1>("h00") io.network.release.valid := UInt<1>("h00") io.network.probe.ready := UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.network.finish.bits.header.dst := UInt<1>("h00") io.network.finish.bits.header.src := UInt<1>("h00") io.network.finish.valid := UInt<1>("h00") io.network.grant.ready := UInt<1>("h00") io.network.acquire.bits.payload.union := UInt<1>("h00") io.network.acquire.bits.payload.a_type := UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") io.network.acquire.bits.payload.data := UInt<1>("h00") io.network.acquire.bits.payload.addr_beat := UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") io.network.acquire.bits.payload.addr_block := UInt<1>("h00") io.network.acquire.bits.header.dst := UInt<1>("h00") io.network.acquire.bits.header.src := UInt<1>("h00") io.network.acquire.valid := UInt<1>("h00") io.client.release.ready := UInt<1>("h00") io.client.probe.bits.p_type := UInt<1>("h00") io.client.probe.bits.addr_block := UInt<1>("h00") io.client.probe.valid := UInt<1>("h00") io.client.grant.bits.g_type := UInt<1>("h00") io.client.grant.bits.is_builtin_type := UInt<1>("h00") io.client.grant.bits.manager_xact_id := UInt<1>("h00") io.client.grant.bits.client_xact_id := UInt<1>("h00") io.client.grant.bits.data := UInt<1>("h00") io.client.grant.bits.addr_beat := UInt<1>("h00") io.client.grant.valid := UInt<1>("h00") io.client.acquire.ready := UInt<1>("h00") inst finisher of FinishUnit_7 finisher.io.finish.ready := UInt<1>("h00") finisher.io.refill.ready := UInt<1>("h00") finisher.io.grant.bits.payload.g_type := UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type := UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.data := UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat := UInt<1>("h00") finisher.io.grant.bits.header.dst := UInt<1>("h00") finisher.io.grant.bits.header.src := UInt<1>("h00") finisher.io.grant.valid := UInt<1>("h00") finisher.clock := clock finisher.reset := reset finisher.io.grant <> io.network.grant io.network.finish <> finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} acq_with_header.bits.payload.union := UInt<1>("h00") acq_with_header.bits.payload.a_type := UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") acq_with_header.bits.payload.data := UInt<1>("h00") acq_with_header.bits.payload.addr_beat := UInt<1>("h00") acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") acq_with_header.bits.payload.addr_block := UInt<1>("h00") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.bits.header.src := UInt<1>("h00") acq_with_header.valid := UInt<1>("h00") acq_with_header.ready := UInt<1>("h00") acq_with_header.bits.payload <> io.client.acquire.bits acq_with_header.bits.header.src := UInt<1>("h01") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.valid := io.client.acquire.valid io.client.acquire.ready := acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} rel_with_header.bits.payload.voluntary := UInt<1>("h00") rel_with_header.bits.payload.r_type := UInt<1>("h00") rel_with_header.bits.payload.data := UInt<1>("h00") rel_with_header.bits.payload.addr_beat := UInt<1>("h00") rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") rel_with_header.bits.payload.addr_block := UInt<1>("h00") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.bits.header.src := UInt<1>("h00") rel_with_header.valid := UInt<1>("h00") rel_with_header.ready := UInt<1>("h00") rel_with_header.bits.payload <> io.client.release.bits rel_with_header.bits.header.src := UInt<1>("h01") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.valid := io.client.release.valid io.client.release.ready := rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type := UInt<1>("h00") prb_without_header.bits.addr_block := UInt<1>("h00") prb_without_header.valid := UInt<1>("h00") prb_without_header.ready := UInt<1>("h00") prb_without_header.valid := io.network.probe.valid prb_without_header.bits <> io.network.probe.bits.payload io.network.probe.ready := prb_without_header.ready io.network.acquire.bits <> acq_with_header.bits node T_2346 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid := T_2346 node T_2347 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready := T_2347 io.network.release <> rel_with_header io.client.probe <> prb_without_header io.client.grant <> finisher.io.refill module FinishUnit_16 : input clock : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready := UInt<1>("h00") io.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.finish.bits.header.dst := UInt<1>("h00") io.finish.bits.header.src := UInt<1>("h00") io.finish.valid := UInt<1>("h00") io.refill.bits.g_type := UInt<1>("h00") io.refill.bits.is_builtin_type := UInt<1>("h00") io.refill.bits.manager_xact_id := UInt<1>("h00") io.refill.bits.client_xact_id := UInt<1>("h00") io.refill.bits.data := UInt<1>("h00") io.refill.bits.addr_beat := UInt<1>("h00") io.refill.valid := UInt<1>("h00") io.grant.ready := UInt<1>("h00") node T_442 = and(io.grant.ready, io.grant.valid) wire T_447 : UInt<3>[1] T_447[0] := UInt<3>("h05") node T_450 = eq(T_447[0], io.grant.bits.payload.g_type) node T_452 = or(UInt<1>("h00"), T_450) wire T_454 : UInt<1>[2] T_454[0] := UInt<1>("h00") T_454[1] := UInt<1>("h01") node T_458 = eq(T_454[0], io.grant.bits.payload.g_type) node T_459 = eq(T_454[1], io.grant.bits.payload.g_type) node T_461 = or(UInt<1>("h00"), T_458) node T_462 = or(T_461, T_459) node T_463 = mux(io.grant.bits.payload.is_builtin_type, T_452, T_462) node T_464 = and(UInt<1>("h01"), T_463) node T_465 = and(T_442, T_464) reg T_467 : UInt<2>, clock, reset onreset T_467 := UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 := T_475 skip node T_476 = and(T_465, T_469) node T_477 = mux(T_464, T_467, UInt<1>("h00")) node T_478 = mux(T_464, T_476, T_442) inst T_529 of FinishQueue T_529.io.deq.ready := UInt<1>("h00") T_529.io.enq.bits.dst := UInt<1>("h00") T_529.io.enq.bits.fin.manager_xact_id := UInt<1>("h00") T_529.io.enq.valid := UInt<1>("h00") T_529.clock := clock T_529.reset := reset node T_534 = and(io.grant.ready, io.grant.valid) node T_537 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_539 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_540 = and(io.grant.bits.payload.is_builtin_type, T_539) node T_542 = eq(T_540, UInt<1>("h00")) node T_543 = and(T_537, T_542) node T_544 = and(T_534, T_543) wire T_548 : UInt<3>[1] T_548[0] := UInt<3>("h05") node T_551 = eq(T_548[0], io.grant.bits.payload.g_type) node T_553 = or(UInt<1>("h00"), T_551) wire T_555 : UInt<1>[2] T_555[0] := UInt<1>("h00") T_555[1] := UInt<1>("h01") node T_559 = eq(T_555[0], io.grant.bits.payload.g_type) node T_560 = eq(T_555[1], io.grant.bits.payload.g_type) node T_562 = or(UInt<1>("h00"), T_559) node T_563 = or(T_562, T_560) node T_564 = mux(io.grant.bits.payload.is_builtin_type, T_553, T_563) node T_565 = and(UInt<1>("h01"), T_564) node T_567 = eq(T_565, UInt<1>("h00")) node T_568 = or(T_567, T_478) node T_569 = and(T_544, T_568) T_529.io.enq.valid := T_569 wire T_595 : {manager_xact_id : UInt<4>} T_595.manager_xact_id := UInt<1>("h00") T_595.manager_xact_id := io.grant.bits.payload.manager_xact_id T_529.io.enq.bits.fin <> T_595 T_529.io.enq.bits.dst := io.grant.bits.header.src io.finish.bits.header.src := UInt<2>("h02") io.finish.bits.header.dst := T_529.io.deq.bits.dst io.finish.bits.payload <> T_529.io.deq.bits.fin io.finish.valid := T_529.io.deq.valid T_529.io.deq.ready := io.finish.ready io.refill.valid := io.grant.valid io.refill.bits <> io.grant.bits.payload node T_624 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_626 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_627 = and(io.grant.bits.payload.is_builtin_type, T_626) node T_629 = eq(T_627, UInt<1>("h00")) node T_630 = and(T_624, T_629) node T_632 = eq(T_630, UInt<1>("h00")) node T_633 = or(T_529.io.enq.ready, T_632) node T_634 = and(T_633, io.refill.ready) io.grant.ready := T_634 io.ready := T_529.io.enq.ready module ClientTileLinkNetworkPort_15 : input clock : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.network.release.bits.payload.voluntary := UInt<1>("h00") io.network.release.bits.payload.r_type := UInt<1>("h00") io.network.release.bits.payload.data := UInt<1>("h00") io.network.release.bits.payload.addr_beat := UInt<1>("h00") io.network.release.bits.payload.client_xact_id := UInt<1>("h00") io.network.release.bits.payload.addr_block := UInt<1>("h00") io.network.release.bits.header.dst := UInt<1>("h00") io.network.release.bits.header.src := UInt<1>("h00") io.network.release.valid := UInt<1>("h00") io.network.probe.ready := UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.network.finish.bits.header.dst := UInt<1>("h00") io.network.finish.bits.header.src := UInt<1>("h00") io.network.finish.valid := UInt<1>("h00") io.network.grant.ready := UInt<1>("h00") io.network.acquire.bits.payload.union := UInt<1>("h00") io.network.acquire.bits.payload.a_type := UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") io.network.acquire.bits.payload.data := UInt<1>("h00") io.network.acquire.bits.payload.addr_beat := UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") io.network.acquire.bits.payload.addr_block := UInt<1>("h00") io.network.acquire.bits.header.dst := UInt<1>("h00") io.network.acquire.bits.header.src := UInt<1>("h00") io.network.acquire.valid := UInt<1>("h00") io.client.release.ready := UInt<1>("h00") io.client.probe.bits.p_type := UInt<1>("h00") io.client.probe.bits.addr_block := UInt<1>("h00") io.client.probe.valid := UInt<1>("h00") io.client.grant.bits.g_type := UInt<1>("h00") io.client.grant.bits.is_builtin_type := UInt<1>("h00") io.client.grant.bits.manager_xact_id := UInt<1>("h00") io.client.grant.bits.client_xact_id := UInt<1>("h00") io.client.grant.bits.data := UInt<1>("h00") io.client.grant.bits.addr_beat := UInt<1>("h00") io.client.grant.valid := UInt<1>("h00") io.client.acquire.ready := UInt<1>("h00") inst finisher of FinishUnit_16 finisher.io.finish.ready := UInt<1>("h00") finisher.io.refill.ready := UInt<1>("h00") finisher.io.grant.bits.payload.g_type := UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type := UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id := UInt<1>("h00") finisher.io.grant.bits.payload.data := UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat := UInt<1>("h00") finisher.io.grant.bits.header.dst := UInt<1>("h00") finisher.io.grant.bits.header.src := UInt<1>("h00") finisher.io.grant.valid := UInt<1>("h00") finisher.clock := clock finisher.reset := reset finisher.io.grant <> io.network.grant io.network.finish <> finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} acq_with_header.bits.payload.union := UInt<1>("h00") acq_with_header.bits.payload.a_type := UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") acq_with_header.bits.payload.data := UInt<1>("h00") acq_with_header.bits.payload.addr_beat := UInt<1>("h00") acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") acq_with_header.bits.payload.addr_block := UInt<1>("h00") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.bits.header.src := UInt<1>("h00") acq_with_header.valid := UInt<1>("h00") acq_with_header.ready := UInt<1>("h00") acq_with_header.bits.payload <> io.client.acquire.bits acq_with_header.bits.header.src := UInt<2>("h02") acq_with_header.bits.header.dst := UInt<1>("h00") acq_with_header.valid := io.client.acquire.valid io.client.acquire.ready := acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} rel_with_header.bits.payload.voluntary := UInt<1>("h00") rel_with_header.bits.payload.r_type := UInt<1>("h00") rel_with_header.bits.payload.data := UInt<1>("h00") rel_with_header.bits.payload.addr_beat := UInt<1>("h00") rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") rel_with_header.bits.payload.addr_block := UInt<1>("h00") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.bits.header.src := UInt<1>("h00") rel_with_header.valid := UInt<1>("h00") rel_with_header.ready := UInt<1>("h00") rel_with_header.bits.payload <> io.client.release.bits rel_with_header.bits.header.src := UInt<2>("h02") rel_with_header.bits.header.dst := UInt<1>("h00") rel_with_header.valid := io.client.release.valid io.client.release.ready := rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type := UInt<1>("h00") prb_without_header.bits.addr_block := UInt<1>("h00") prb_without_header.valid := UInt<1>("h00") prb_without_header.ready := UInt<1>("h00") prb_without_header.valid := io.network.probe.valid prb_without_header.bits <> io.network.probe.bits.payload io.network.probe.ready := prb_without_header.ready io.network.acquire.bits <> acq_with_header.bits node T_2346 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid := T_2346 node T_2347 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready := T_2347 io.network.release <> rel_with_header io.client.probe <> prb_without_header io.client.grant <> finisher.io.refill module ManagerTileLinkNetworkPort : input clock : Clock input reset : UInt<1> output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.network.release.ready := UInt<1>("h00") io.network.probe.bits.payload.p_type := UInt<1>("h00") io.network.probe.bits.payload.addr_block := UInt<1>("h00") io.network.probe.bits.header.dst := UInt<1>("h00") io.network.probe.bits.header.src := UInt<1>("h00") io.network.probe.valid := UInt<1>("h00") io.network.finish.ready := UInt<1>("h00") io.network.grant.bits.payload.g_type := UInt<1>("h00") io.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") io.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") io.network.grant.bits.payload.client_xact_id := UInt<1>("h00") io.network.grant.bits.payload.data := UInt<1>("h00") io.network.grant.bits.payload.addr_beat := UInt<1>("h00") io.network.grant.bits.header.dst := UInt<1>("h00") io.network.grant.bits.header.src := UInt<1>("h00") io.network.grant.valid := UInt<1>("h00") io.network.acquire.ready := UInt<1>("h00") io.manager.release.bits.client_id := UInt<1>("h00") io.manager.release.bits.voluntary := UInt<1>("h00") io.manager.release.bits.r_type := UInt<1>("h00") io.manager.release.bits.data := UInt<1>("h00") io.manager.release.bits.addr_beat := UInt<1>("h00") io.manager.release.bits.client_xact_id := UInt<1>("h00") io.manager.release.bits.addr_block := UInt<1>("h00") io.manager.release.valid := UInt<1>("h00") io.manager.probe.ready := UInt<1>("h00") io.manager.finish.bits.manager_xact_id := UInt<1>("h00") io.manager.finish.valid := UInt<1>("h00") io.manager.grant.ready := UInt<1>("h00") io.manager.acquire.bits.client_id := UInt<1>("h00") io.manager.acquire.bits.union := UInt<1>("h00") io.manager.acquire.bits.a_type := UInt<1>("h00") io.manager.acquire.bits.is_builtin_type := UInt<1>("h00") io.manager.acquire.bits.data := UInt<1>("h00") io.manager.acquire.bits.addr_beat := UInt<1>("h00") io.manager.acquire.bits.client_xact_id := UInt<1>("h00") io.manager.acquire.bits.addr_block := UInt<1>("h00") io.manager.acquire.valid := UInt<1>("h00") wire T_3061 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}} T_3061.bits.payload.client_id := UInt<1>("h00") T_3061.bits.payload.g_type := UInt<1>("h00") T_3061.bits.payload.is_builtin_type := UInt<1>("h00") T_3061.bits.payload.manager_xact_id := UInt<1>("h00") T_3061.bits.payload.client_xact_id := UInt<1>("h00") T_3061.bits.payload.data := UInt<1>("h00") T_3061.bits.payload.addr_beat := UInt<1>("h00") T_3061.bits.header.dst := UInt<1>("h00") T_3061.bits.header.src := UInt<1>("h00") T_3061.valid := UInt<1>("h00") T_3061.ready := UInt<1>("h00") T_3061.bits.payload <> io.manager.grant.bits T_3061.bits.header.src := UInt<1>("h00") T_3061.bits.header.dst := io.manager.grant.bits.client_id T_3061.valid := io.manager.grant.valid io.manager.grant.ready := T_3061.ready io.network.grant <> T_3061 wire T_3242 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} T_3242.bits.payload.client_id := UInt<1>("h00") T_3242.bits.payload.p_type := UInt<1>("h00") T_3242.bits.payload.addr_block := UInt<1>("h00") T_3242.bits.header.dst := UInt<1>("h00") T_3242.bits.header.src := UInt<1>("h00") T_3242.valid := UInt<1>("h00") T_3242.ready := UInt<1>("h00") T_3242.bits.payload <> io.manager.probe.bits T_3242.bits.header.src := UInt<1>("h00") T_3242.bits.header.dst := io.manager.probe.bits.client_id T_3242.valid := io.manager.probe.valid io.manager.probe.ready := T_3242.ready io.network.probe <> T_3242 io.manager.acquire.bits.client_id := io.network.acquire.bits.header.src wire T_3380 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} T_3380.bits.union := UInt<1>("h00") T_3380.bits.a_type := UInt<1>("h00") T_3380.bits.is_builtin_type := UInt<1>("h00") T_3380.bits.data := UInt<1>("h00") T_3380.bits.addr_beat := UInt<1>("h00") T_3380.bits.client_xact_id := UInt<1>("h00") T_3380.bits.addr_block := UInt<1>("h00") T_3380.valid := UInt<1>("h00") T_3380.ready := UInt<1>("h00") T_3380.valid := io.network.acquire.valid T_3380.bits <> io.network.acquire.bits.payload io.network.acquire.ready := T_3380.ready io.manager.acquire <> T_3380 io.manager.release.bits.client_id := io.network.release.bits.header.src wire T_3517 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} T_3517.bits.voluntary := UInt<1>("h00") T_3517.bits.r_type := UInt<1>("h00") T_3517.bits.data := UInt<1>("h00") T_3517.bits.addr_beat := UInt<1>("h00") T_3517.bits.client_xact_id := UInt<1>("h00") T_3517.bits.addr_block := UInt<1>("h00") T_3517.valid := UInt<1>("h00") T_3517.ready := UInt<1>("h00") T_3517.valid := io.network.release.valid T_3517.bits <> io.network.release.bits.payload io.network.release.ready := T_3517.ready io.manager.release <> T_3517 wire T_3641 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} T_3641.bits.manager_xact_id := UInt<1>("h00") T_3641.valid := UInt<1>("h00") T_3641.ready := UInt<1>("h00") T_3641.valid := io.network.finish.valid T_3641.bits <> io.network.finish.bits.payload io.network.finish.ready := T_3641.ready io.manager.finish <> T_3641 module Queue_25 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, count : UInt<1>} io.count := UInt<1>("h00") io.deq.bits.payload.voluntary := UInt<1>("h00") io.deq.bits.payload.r_type := UInt<1>("h00") io.deq.bits.payload.data := UInt<1>("h00") io.deq.bits.payload.addr_beat := UInt<1>("h00") io.deq.bits.payload.client_xact_id := UInt<1>("h00") io.deq.bits.payload.addr_block := UInt<1>("h00") io.deq.bits.header.dst := UInt<1>("h00") io.deq.bits.header.src := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[1], clock reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_328 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_328) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_334 = and(io.enq.ready, io.enq.valid) node T_336 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_334, T_336) node T_338 = and(io.deq.ready, io.deq.valid) node T_340 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_338, T_340) when do_enq : infer accessor T_342 = ram[UInt<1>("h00")] T_342 <> io.enq.bits skip when do_deq : skip node T_378 = neq(do_enq, do_deq) when T_378 : maybe_full := do_enq skip node T_380 = eq(empty, UInt<1>("h00")) node T_382 = and(UInt<1>("h00"), io.enq.valid) node T_383 = or(T_380, T_382) io.deq.valid := T_383 node T_385 = eq(full, UInt<1>("h00")) node T_387 = and(UInt<1>("h00"), io.deq.ready) node T_388 = or(T_385, T_387) io.enq.ready := T_388 infer accessor T_389 = ram[UInt<1>("h00")] wire T_457 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} T_457 <> T_389 when maybe_flow : T_457 <> io.enq.bits skip io.deq.bits <> T_457 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_492 = and(maybe_full, ptr_match) node T_493 = cat(T_492, ptr_diff) io.count := T_493 module TileLinkEnqueuer_24 : input clock : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}} io.manager.release.bits.payload.voluntary := UInt<1>("h00") io.manager.release.bits.payload.r_type := UInt<1>("h00") io.manager.release.bits.payload.data := UInt<1>("h00") io.manager.release.bits.payload.addr_beat := UInt<1>("h00") io.manager.release.bits.payload.client_xact_id := UInt<1>("h00") io.manager.release.bits.payload.addr_block := UInt<1>("h00") io.manager.release.bits.header.dst := UInt<1>("h00") io.manager.release.bits.header.src := UInt<1>("h00") io.manager.release.valid := UInt<1>("h00") io.manager.probe.ready := UInt<1>("h00") io.manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") io.manager.finish.bits.header.dst := UInt<1>("h00") io.manager.finish.bits.header.src := UInt<1>("h00") io.manager.finish.valid := UInt<1>("h00") io.manager.grant.ready := UInt<1>("h00") io.manager.acquire.bits.payload.union := UInt<1>("h00") io.manager.acquire.bits.payload.a_type := UInt<1>("h00") io.manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") io.manager.acquire.bits.payload.data := UInt<1>("h00") io.manager.acquire.bits.payload.addr_beat := UInt<1>("h00") io.manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") io.manager.acquire.bits.payload.addr_block := UInt<1>("h00") io.manager.acquire.bits.header.dst := UInt<1>("h00") io.manager.acquire.bits.header.src := UInt<1>("h00") io.manager.acquire.valid := UInt<1>("h00") io.client.release.ready := UInt<1>("h00") io.client.probe.bits.payload.p_type := UInt<1>("h00") io.client.probe.bits.payload.addr_block := UInt<1>("h00") io.client.probe.bits.header.dst := UInt<1>("h00") io.client.probe.bits.header.src := UInt<1>("h00") io.client.probe.valid := UInt<1>("h00") io.client.finish.ready := UInt<1>("h00") io.client.grant.bits.payload.g_type := UInt<1>("h00") io.client.grant.bits.payload.is_builtin_type := UInt<1>("h00") io.client.grant.bits.payload.manager_xact_id := UInt<1>("h00") io.client.grant.bits.payload.client_xact_id := UInt<1>("h00") io.client.grant.bits.payload.data := UInt<1>("h00") io.client.grant.bits.payload.addr_beat := UInt<1>("h00") io.client.grant.bits.header.dst := UInt<1>("h00") io.client.grant.bits.header.src := UInt<1>("h00") io.client.grant.valid := UInt<1>("h00") io.client.acquire.ready := UInt<1>("h00") io.manager.acquire <> io.client.acquire io.client.probe <> io.manager.probe inst T_2441 of Queue_25 T_2441.io.deq.ready := UInt<1>("h00") T_2441.io.enq.bits.payload.voluntary := UInt<1>("h00") T_2441.io.enq.bits.payload.r_type := UInt<1>("h00") T_2441.io.enq.bits.payload.data := UInt<1>("h00") T_2441.io.enq.bits.payload.addr_beat := UInt<1>("h00") T_2441.io.enq.bits.payload.client_xact_id := UInt<1>("h00") T_2441.io.enq.bits.payload.addr_block := UInt<1>("h00") T_2441.io.enq.bits.header.dst := UInt<1>("h00") T_2441.io.enq.bits.header.src := UInt<1>("h00") T_2441.io.enq.valid := UInt<1>("h00") T_2441.clock := clock T_2441.reset := reset T_2441.io.enq.valid := io.client.release.valid T_2441.io.enq.bits <> io.client.release.bits io.client.release.ready := T_2441.io.enq.ready io.manager.release <> T_2441.io.deq io.client.grant <> io.manager.grant io.manager.finish <> io.client.finish module LockingRRArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.payload.union := UInt<1>("h00") io.out.bits.payload.a_type := UInt<1>("h00") io.out.bits.payload.is_builtin_type := UInt<1>("h00") io.out.bits.payload.data := UInt<1>("h00") io.out.bits.payload.addr_beat := UInt<1>("h00") io.out.bits.payload.client_xact_id := UInt<1>("h00") io.out.bits.payload.addr_block := UInt<1>("h00") io.out.bits.header.dst := UInt<1>("h00") io.out.bits.header.src := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") reg T_956 : UInt<1>, clock, reset onreset T_956 := UInt<1>("h00") reg T_958 : UInt, clock, reset onreset T_958 := UInt<2>("h02") wire T_960 : UInt<2> T_960 := UInt<1>("h00") infer accessor T_962 = io.in[T_960] io.out.valid := T_962.valid infer accessor T_1035 = io.in[T_960] io.out.bits <> T_1035.bits io.chosen := T_960 infer accessor T_1108 = io.in[T_960] T_1108.ready := UInt<1>("h00") reg last_grant : UInt<2>, clock, reset onreset last_grant := UInt<2>("h00") node T_1185 = gt(UInt<1>("h00"), last_grant) node T_1186 = and(io.in[0].valid, T_1185) node T_1188 = gt(UInt<1>("h01"), last_grant) node T_1189 = and(io.in[1].valid, T_1188) node T_1191 = gt(UInt<2>("h02"), last_grant) node T_1192 = and(io.in[2].valid, T_1191) node T_1195 = or(UInt<1>("h00"), T_1186) node T_1197 = eq(T_1195, UInt<1>("h00")) node T_1199 = or(UInt<1>("h00"), T_1186) node T_1200 = or(T_1199, T_1189) node T_1202 = eq(T_1200, UInt<1>("h00")) node T_1204 = or(UInt<1>("h00"), T_1186) node T_1205 = or(T_1204, T_1189) node T_1206 = or(T_1205, T_1192) node T_1208 = eq(T_1206, UInt<1>("h00")) node T_1210 = or(UInt<1>("h00"), T_1186) node T_1211 = or(T_1210, T_1189) node T_1212 = or(T_1211, T_1192) node T_1213 = or(T_1212, io.in[0].valid) node T_1215 = eq(T_1213, UInt<1>("h00")) node T_1217 = or(UInt<1>("h00"), T_1186) node T_1218 = or(T_1217, T_1189) node T_1219 = or(T_1218, T_1192) node T_1220 = or(T_1219, io.in[0].valid) node T_1221 = or(T_1220, io.in[1].valid) node T_1223 = eq(T_1221, UInt<1>("h00")) node T_1225 = gt(UInt<1>("h00"), last_grant) node T_1226 = and(UInt<1>("h01"), T_1225) node T_1227 = or(T_1226, T_1208) node T_1229 = gt(UInt<1>("h01"), last_grant) node T_1230 = and(T_1197, T_1229) node T_1231 = or(T_1230, T_1215) node T_1233 = gt(UInt<2>("h02"), last_grant) node T_1234 = and(T_1202, T_1233) node T_1235 = or(T_1234, T_1223) node T_1237 = eq(T_958, UInt<1>("h00")) node T_1238 = mux(T_956, T_1237, T_1227) node T_1239 = and(T_1238, io.out.ready) io.in[0].ready := T_1239 node T_1241 = eq(T_958, UInt<1>("h01")) node T_1242 = mux(T_956, T_1241, T_1231) node T_1243 = and(T_1242, io.out.ready) io.in[1].ready := T_1243 node T_1245 = eq(T_958, UInt<2>("h02")) node T_1246 = mux(T_956, T_1245, T_1235) node T_1247 = and(T_1246, io.out.ready) io.in[2].ready := T_1247 reg T_1249 : UInt<2>, clock, reset onreset T_1249 := UInt<2>("h00") node T_1251 = addw(T_1249, UInt<1>("h01")) node T_1252 = and(io.out.ready, io.out.valid) when T_1252 : node T_1254 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type) wire T_1257 : UInt<3>[1] T_1257[0] := UInt<3>("h03") node T_1260 = eq(T_1257[0], io.out.bits.payload.a_type) node T_1262 = or(UInt<1>("h00"), T_1260) node T_1263 = and(T_1254, T_1262) when T_1263 : T_1249 := T_1251 node T_1265 = eq(T_956, UInt<1>("h00")) when T_1265 : T_956 := UInt<1>("h01") node T_1267 = and(io.in[0].ready, io.in[0].valid) node T_1268 = and(io.in[1].ready, io.in[1].valid) node T_1269 = and(io.in[2].ready, io.in[2].valid) wire T_1271 : UInt<1>[3] T_1271[0] := T_1267 T_1271[1] := T_1268 T_1271[2] := T_1269 node T_1279 = mux(T_1271[1], UInt<1>("h01"), UInt<2>("h02")) node T_1280 = mux(T_1271[0], UInt<1>("h00"), T_1279) T_958 := T_1280 skip skip node T_1282 = eq(T_1251, UInt<1>("h00")) when T_1282 : T_956 := UInt<1>("h00") skip skip node T_1286 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_1288 = mux(io.in[0].valid, UInt<1>("h00"), T_1286) node T_1290 = gt(UInt<2>("h02"), last_grant) node T_1291 = and(io.in[2].valid, T_1290) node T_1293 = mux(T_1291, UInt<2>("h02"), T_1288) node T_1295 = gt(UInt<1>("h01"), last_grant) node T_1296 = and(io.in[1].valid, T_1295) node choose = mux(T_1296, UInt<1>("h01"), T_1293) node T_1299 = mux(T_956, T_958, choose) T_960 := T_1299 node T_1300 = and(io.out.ready, io.out.valid) when T_1300 : last_grant := T_960 skip module LockingRRArbiter_26 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.payload.voluntary := UInt<1>("h00") io.out.bits.payload.r_type := UInt<1>("h00") io.out.bits.payload.data := UInt<1>("h00") io.out.bits.payload.addr_beat := UInt<1>("h00") io.out.bits.payload.client_xact_id := UInt<1>("h00") io.out.bits.payload.addr_block := UInt<1>("h00") io.out.bits.header.dst := UInt<1>("h00") io.out.bits.header.src := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") reg T_930 : UInt<1>, clock, reset onreset T_930 := UInt<1>("h00") reg T_932 : UInt, clock, reset onreset T_932 := UInt<2>("h02") wire T_934 : UInt<2> T_934 := UInt<1>("h00") infer accessor T_936 = io.in[T_934] io.out.valid := T_936.valid infer accessor T_1007 = io.in[T_934] io.out.bits <> T_1007.bits io.chosen := T_934 infer accessor T_1078 = io.in[T_934] T_1078.ready := UInt<1>("h00") reg last_grant : UInt<2>, clock, reset onreset last_grant := UInt<2>("h00") node T_1153 = gt(UInt<1>("h00"), last_grant) node T_1154 = and(io.in[0].valid, T_1153) node T_1156 = gt(UInt<1>("h01"), last_grant) node T_1157 = and(io.in[1].valid, T_1156) node T_1159 = gt(UInt<2>("h02"), last_grant) node T_1160 = and(io.in[2].valid, T_1159) node T_1163 = or(UInt<1>("h00"), T_1154) node T_1165 = eq(T_1163, UInt<1>("h00")) node T_1167 = or(UInt<1>("h00"), T_1154) node T_1168 = or(T_1167, T_1157) node T_1170 = eq(T_1168, UInt<1>("h00")) node T_1172 = or(UInt<1>("h00"), T_1154) node T_1173 = or(T_1172, T_1157) node T_1174 = or(T_1173, T_1160) node T_1176 = eq(T_1174, UInt<1>("h00")) node T_1178 = or(UInt<1>("h00"), T_1154) node T_1179 = or(T_1178, T_1157) node T_1180 = or(T_1179, T_1160) node T_1181 = or(T_1180, io.in[0].valid) node T_1183 = eq(T_1181, UInt<1>("h00")) node T_1185 = or(UInt<1>("h00"), T_1154) node T_1186 = or(T_1185, T_1157) node T_1187 = or(T_1186, T_1160) node T_1188 = or(T_1187, io.in[0].valid) node T_1189 = or(T_1188, io.in[1].valid) node T_1191 = eq(T_1189, UInt<1>("h00")) node T_1193 = gt(UInt<1>("h00"), last_grant) node T_1194 = and(UInt<1>("h01"), T_1193) node T_1195 = or(T_1194, T_1176) node T_1197 = gt(UInt<1>("h01"), last_grant) node T_1198 = and(T_1165, T_1197) node T_1199 = or(T_1198, T_1183) node T_1201 = gt(UInt<2>("h02"), last_grant) node T_1202 = and(T_1170, T_1201) node T_1203 = or(T_1202, T_1191) node T_1205 = eq(T_932, UInt<1>("h00")) node T_1206 = mux(T_930, T_1205, T_1195) node T_1207 = and(T_1206, io.out.ready) io.in[0].ready := T_1207 node T_1209 = eq(T_932, UInt<1>("h01")) node T_1210 = mux(T_930, T_1209, T_1199) node T_1211 = and(T_1210, io.out.ready) io.in[1].ready := T_1211 node T_1213 = eq(T_932, UInt<2>("h02")) node T_1214 = mux(T_930, T_1213, T_1203) node T_1215 = and(T_1214, io.out.ready) io.in[2].ready := T_1215 reg T_1217 : UInt<2>, clock, reset onreset T_1217 := UInt<2>("h00") node T_1219 = addw(T_1217, UInt<1>("h01")) node T_1220 = and(io.out.ready, io.out.valid) when T_1220 : wire T_1223 : UInt<2>[3] T_1223[0] := UInt<1>("h00") T_1223[1] := UInt<1>("h01") T_1223[2] := UInt<2>("h02") node T_1228 = eq(T_1223[0], io.out.bits.payload.r_type) node T_1229 = eq(T_1223[1], io.out.bits.payload.r_type) node T_1230 = eq(T_1223[2], io.out.bits.payload.r_type) node T_1232 = or(UInt<1>("h00"), T_1228) node T_1233 = or(T_1232, T_1229) node T_1234 = or(T_1233, T_1230) node T_1235 = and(UInt<1>("h01"), T_1234) when T_1235 : T_1217 := T_1219 node T_1237 = eq(T_930, UInt<1>("h00")) when T_1237 : T_930 := UInt<1>("h01") node T_1239 = and(io.in[0].ready, io.in[0].valid) node T_1240 = and(io.in[1].ready, io.in[1].valid) node T_1241 = and(io.in[2].ready, io.in[2].valid) wire T_1243 : UInt<1>[3] T_1243[0] := T_1239 T_1243[1] := T_1240 T_1243[2] := T_1241 node T_1251 = mux(T_1243[1], UInt<1>("h01"), UInt<2>("h02")) node T_1252 = mux(T_1243[0], UInt<1>("h00"), T_1251) T_932 := T_1252 skip skip node T_1254 = eq(T_1219, UInt<1>("h00")) when T_1254 : T_930 := UInt<1>("h00") skip skip node T_1258 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_1260 = mux(io.in[0].valid, UInt<1>("h00"), T_1258) node T_1262 = gt(UInt<2>("h02"), last_grant) node T_1263 = and(io.in[2].valid, T_1262) node T_1265 = mux(T_1263, UInt<2>("h02"), T_1260) node T_1267 = gt(UInt<1>("h01"), last_grant) node T_1268 = and(io.in[1].valid, T_1267) node choose = mux(T_1268, UInt<1>("h01"), T_1265) node T_1271 = mux(T_930, T_932, choose) T_934 := T_1271 node T_1272 = and(io.out.ready, io.out.valid) when T_1272 : last_grant := T_934 skip module RRArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.payload.manager_xact_id := UInt<1>("h00") io.out.bits.header.dst := UInt<1>("h00") io.out.bits.header.src := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") wire T_802 : UInt<2> T_802 := UInt<1>("h00") infer accessor T_804 = io.in[T_802] io.out.valid := T_804.valid infer accessor T_865 = io.in[T_802] io.out.bits <> T_865.bits io.chosen := T_802 infer accessor T_926 = io.in[T_802] T_926.ready := UInt<1>("h00") reg T_990 : UInt<2>, clock, reset onreset T_990 := UInt<2>("h00") node T_991 = gt(UInt<1>("h00"), T_990) node T_992 = and(io.in[0].valid, T_991) node T_994 = gt(UInt<1>("h01"), T_990) node T_995 = and(io.in[1].valid, T_994) node T_997 = gt(UInt<2>("h02"), T_990) node T_998 = and(io.in[2].valid, T_997) node T_1001 = or(UInt<1>("h00"), T_992) node T_1003 = eq(T_1001, UInt<1>("h00")) node T_1005 = or(UInt<1>("h00"), T_992) node T_1006 = or(T_1005, T_995) node T_1008 = eq(T_1006, UInt<1>("h00")) node T_1010 = or(UInt<1>("h00"), T_992) node T_1011 = or(T_1010, T_995) node T_1012 = or(T_1011, T_998) node T_1014 = eq(T_1012, UInt<1>("h00")) node T_1016 = or(UInt<1>("h00"), T_992) node T_1017 = or(T_1016, T_995) node T_1018 = or(T_1017, T_998) node T_1019 = or(T_1018, io.in[0].valid) node T_1021 = eq(T_1019, UInt<1>("h00")) node T_1023 = or(UInt<1>("h00"), T_992) node T_1024 = or(T_1023, T_995) node T_1025 = or(T_1024, T_998) node T_1026 = or(T_1025, io.in[0].valid) node T_1027 = or(T_1026, io.in[1].valid) node T_1029 = eq(T_1027, UInt<1>("h00")) node T_1031 = gt(UInt<1>("h00"), T_990) node T_1032 = and(UInt<1>("h01"), T_1031) node T_1033 = or(T_1032, T_1014) node T_1035 = gt(UInt<1>("h01"), T_990) node T_1036 = and(T_1003, T_1035) node T_1037 = or(T_1036, T_1021) node T_1039 = gt(UInt<2>("h02"), T_990) node T_1040 = and(T_1008, T_1039) node T_1041 = or(T_1040, T_1029) node T_1043 = eq(UInt<2>("h02"), UInt<1>("h00")) node T_1044 = mux(UInt<1>("h00"), T_1043, T_1033) node T_1045 = and(T_1044, io.out.ready) io.in[0].ready := T_1045 node T_1047 = eq(UInt<2>("h02"), UInt<1>("h01")) node T_1048 = mux(UInt<1>("h00"), T_1047, T_1037) node T_1049 = and(T_1048, io.out.ready) io.in[1].ready := T_1049 node T_1051 = eq(UInt<2>("h02"), UInt<2>("h02")) node T_1052 = mux(UInt<1>("h00"), T_1051, T_1041) node T_1053 = and(T_1052, io.out.ready) io.in[2].ready := T_1053 node T_1056 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_1058 = mux(io.in[0].valid, UInt<1>("h00"), T_1056) node T_1060 = gt(UInt<2>("h02"), T_990) node T_1061 = and(io.in[2].valid, T_1060) node T_1063 = mux(T_1061, UInt<2>("h02"), T_1058) node T_1065 = gt(UInt<1>("h01"), T_990) node T_1066 = and(io.in[1].valid, T_1065) node T_1068 = mux(T_1066, UInt<1>("h01"), T_1063) node T_1069 = mux(UInt<1>("h00"), UInt<2>("h02"), T_1068) T_802 := T_1069 node T_1070 = and(io.out.ready, io.out.valid) when T_1070 : T_990 := T_802 skip module RocketChipTileLinkArbiter : input clock : Clock input reset : UInt<1> output io : {flip clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}[1]} io.managers[0].release.bits.client_id := UInt<1>("h00") io.managers[0].release.bits.voluntary := UInt<1>("h00") io.managers[0].release.bits.r_type := UInt<1>("h00") io.managers[0].release.bits.data := UInt<1>("h00") io.managers[0].release.bits.addr_beat := UInt<1>("h00") io.managers[0].release.bits.client_xact_id := UInt<1>("h00") io.managers[0].release.bits.addr_block := UInt<1>("h00") io.managers[0].release.valid := UInt<1>("h00") io.managers[0].probe.ready := UInt<1>("h00") io.managers[0].finish.bits.manager_xact_id := UInt<1>("h00") io.managers[0].finish.valid := UInt<1>("h00") io.managers[0].grant.ready := UInt<1>("h00") io.managers[0].acquire.bits.client_id := UInt<1>("h00") io.managers[0].acquire.bits.union := UInt<1>("h00") io.managers[0].acquire.bits.a_type := UInt<1>("h00") io.managers[0].acquire.bits.is_builtin_type := UInt<1>("h00") io.managers[0].acquire.bits.data := UInt<1>("h00") io.managers[0].acquire.bits.addr_beat := UInt<1>("h00") io.managers[0].acquire.bits.client_xact_id := UInt<1>("h00") io.managers[0].acquire.bits.addr_block := UInt<1>("h00") io.managers[0].acquire.valid := UInt<1>("h00") io.clients[0].release.ready := UInt<1>("h00") io.clients[0].probe.bits.p_type := UInt<1>("h00") io.clients[0].probe.bits.addr_block := UInt<1>("h00") io.clients[0].probe.valid := UInt<1>("h00") io.clients[0].grant.bits.g_type := UInt<1>("h00") io.clients[0].grant.bits.is_builtin_type := UInt<1>("h00") io.clients[0].grant.bits.manager_xact_id := UInt<1>("h00") io.clients[0].grant.bits.client_xact_id := UInt<1>("h00") io.clients[0].grant.bits.data := UInt<1>("h00") io.clients[0].grant.bits.addr_beat := UInt<1>("h00") io.clients[0].grant.valid := UInt<1>("h00") io.clients[0].acquire.ready := UInt<1>("h00") io.clients[1].release.ready := UInt<1>("h00") io.clients[1].probe.bits.p_type := UInt<1>("h00") io.clients[1].probe.bits.addr_block := UInt<1>("h00") io.clients[1].probe.valid := UInt<1>("h00") io.clients[1].grant.bits.g_type := UInt<1>("h00") io.clients[1].grant.bits.is_builtin_type := UInt<1>("h00") io.clients[1].grant.bits.manager_xact_id := UInt<1>("h00") io.clients[1].grant.bits.client_xact_id := UInt<1>("h00") io.clients[1].grant.bits.data := UInt<1>("h00") io.clients[1].grant.bits.addr_beat := UInt<1>("h00") io.clients[1].grant.valid := UInt<1>("h00") io.clients[1].acquire.ready := UInt<1>("h00") io.clients[2].release.ready := UInt<1>("h00") io.clients[2].probe.bits.p_type := UInt<1>("h00") io.clients[2].probe.bits.addr_block := UInt<1>("h00") io.clients[2].probe.valid := UInt<1>("h00") io.clients[2].grant.bits.g_type := UInt<1>("h00") io.clients[2].grant.bits.is_builtin_type := UInt<1>("h00") io.clients[2].grant.bits.manager_xact_id := UInt<1>("h00") io.clients[2].grant.bits.client_xact_id := UInt<1>("h00") io.clients[2].grant.bits.data := UInt<1>("h00") io.clients[2].grant.bits.addr_beat := UInt<1>("h00") io.clients[2].grant.valid := UInt<1>("h00") io.clients[2].acquire.ready := UInt<1>("h00") inst T_11386 of ClientTileLinkNetworkPort T_11386.io.network.release.ready := UInt<1>("h00") T_11386.io.network.probe.bits.payload.p_type := UInt<1>("h00") T_11386.io.network.probe.bits.payload.addr_block := UInt<1>("h00") T_11386.io.network.probe.bits.header.dst := UInt<1>("h00") T_11386.io.network.probe.bits.header.src := UInt<1>("h00") T_11386.io.network.probe.valid := UInt<1>("h00") T_11386.io.network.finish.ready := UInt<1>("h00") T_11386.io.network.grant.bits.payload.g_type := UInt<1>("h00") T_11386.io.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11386.io.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11386.io.network.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11386.io.network.grant.bits.payload.data := UInt<1>("h00") T_11386.io.network.grant.bits.payload.addr_beat := UInt<1>("h00") T_11386.io.network.grant.bits.header.dst := UInt<1>("h00") T_11386.io.network.grant.bits.header.src := UInt<1>("h00") T_11386.io.network.grant.valid := UInt<1>("h00") T_11386.io.network.acquire.ready := UInt<1>("h00") T_11386.io.client.release.bits.voluntary := UInt<1>("h00") T_11386.io.client.release.bits.r_type := UInt<1>("h00") T_11386.io.client.release.bits.data := UInt<1>("h00") T_11386.io.client.release.bits.addr_beat := UInt<1>("h00") T_11386.io.client.release.bits.client_xact_id := UInt<1>("h00") T_11386.io.client.release.bits.addr_block := UInt<1>("h00") T_11386.io.client.release.valid := UInt<1>("h00") T_11386.io.client.probe.ready := UInt<1>("h00") T_11386.io.client.grant.ready := UInt<1>("h00") T_11386.io.client.acquire.bits.union := UInt<1>("h00") T_11386.io.client.acquire.bits.a_type := UInt<1>("h00") T_11386.io.client.acquire.bits.is_builtin_type := UInt<1>("h00") T_11386.io.client.acquire.bits.data := UInt<1>("h00") T_11386.io.client.acquire.bits.addr_beat := UInt<1>("h00") T_11386.io.client.acquire.bits.client_xact_id := UInt<1>("h00") T_11386.io.client.acquire.bits.addr_block := UInt<1>("h00") T_11386.io.client.acquire.valid := UInt<1>("h00") T_11386.clock := clock T_11386.reset := reset inst T_11421 of TileLinkEnqueuer T_11421.io.manager.release.ready := UInt<1>("h00") T_11421.io.manager.probe.bits.payload.p_type := UInt<1>("h00") T_11421.io.manager.probe.bits.payload.addr_block := UInt<1>("h00") T_11421.io.manager.probe.bits.header.dst := UInt<1>("h00") T_11421.io.manager.probe.bits.header.src := UInt<1>("h00") T_11421.io.manager.probe.valid := UInt<1>("h00") T_11421.io.manager.finish.ready := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.g_type := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.data := UInt<1>("h00") T_11421.io.manager.grant.bits.payload.addr_beat := UInt<1>("h00") T_11421.io.manager.grant.bits.header.dst := UInt<1>("h00") T_11421.io.manager.grant.bits.header.src := UInt<1>("h00") T_11421.io.manager.grant.valid := UInt<1>("h00") T_11421.io.manager.acquire.ready := UInt<1>("h00") T_11421.io.client.release.bits.payload.voluntary := UInt<1>("h00") T_11421.io.client.release.bits.payload.r_type := UInt<1>("h00") T_11421.io.client.release.bits.payload.data := UInt<1>("h00") T_11421.io.client.release.bits.payload.addr_beat := UInt<1>("h00") T_11421.io.client.release.bits.payload.client_xact_id := UInt<1>("h00") T_11421.io.client.release.bits.payload.addr_block := UInt<1>("h00") T_11421.io.client.release.bits.header.dst := UInt<1>("h00") T_11421.io.client.release.bits.header.src := UInt<1>("h00") T_11421.io.client.release.valid := UInt<1>("h00") T_11421.io.client.probe.ready := UInt<1>("h00") T_11421.io.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") T_11421.io.client.finish.bits.header.dst := UInt<1>("h00") T_11421.io.client.finish.bits.header.src := UInt<1>("h00") T_11421.io.client.finish.valid := UInt<1>("h00") T_11421.io.client.grant.ready := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.union := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.a_type := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.data := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.addr_beat := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") T_11421.io.client.acquire.bits.payload.addr_block := UInt<1>("h00") T_11421.io.client.acquire.bits.header.dst := UInt<1>("h00") T_11421.io.client.acquire.bits.header.src := UInt<1>("h00") T_11421.io.client.acquire.valid := UInt<1>("h00") T_11421.clock := clock T_11421.reset := reset T_11386.io.client <> io.clients[0] T_11421.io.client <> T_11386.io.network inst T_11464 of ClientTileLinkNetworkPort_6 T_11464.io.network.release.ready := UInt<1>("h00") T_11464.io.network.probe.bits.payload.p_type := UInt<1>("h00") T_11464.io.network.probe.bits.payload.addr_block := UInt<1>("h00") T_11464.io.network.probe.bits.header.dst := UInt<1>("h00") T_11464.io.network.probe.bits.header.src := UInt<1>("h00") T_11464.io.network.probe.valid := UInt<1>("h00") T_11464.io.network.finish.ready := UInt<1>("h00") T_11464.io.network.grant.bits.payload.g_type := UInt<1>("h00") T_11464.io.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11464.io.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11464.io.network.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11464.io.network.grant.bits.payload.data := UInt<1>("h00") T_11464.io.network.grant.bits.payload.addr_beat := UInt<1>("h00") T_11464.io.network.grant.bits.header.dst := UInt<1>("h00") T_11464.io.network.grant.bits.header.src := UInt<1>("h00") T_11464.io.network.grant.valid := UInt<1>("h00") T_11464.io.network.acquire.ready := UInt<1>("h00") T_11464.io.client.release.bits.voluntary := UInt<1>("h00") T_11464.io.client.release.bits.r_type := UInt<1>("h00") T_11464.io.client.release.bits.data := UInt<1>("h00") T_11464.io.client.release.bits.addr_beat := UInt<1>("h00") T_11464.io.client.release.bits.client_xact_id := UInt<1>("h00") T_11464.io.client.release.bits.addr_block := UInt<1>("h00") T_11464.io.client.release.valid := UInt<1>("h00") T_11464.io.client.probe.ready := UInt<1>("h00") T_11464.io.client.grant.ready := UInt<1>("h00") T_11464.io.client.acquire.bits.union := UInt<1>("h00") T_11464.io.client.acquire.bits.a_type := UInt<1>("h00") T_11464.io.client.acquire.bits.is_builtin_type := UInt<1>("h00") T_11464.io.client.acquire.bits.data := UInt<1>("h00") T_11464.io.client.acquire.bits.addr_beat := UInt<1>("h00") T_11464.io.client.acquire.bits.client_xact_id := UInt<1>("h00") T_11464.io.client.acquire.bits.addr_block := UInt<1>("h00") T_11464.io.client.acquire.valid := UInt<1>("h00") T_11464.clock := clock T_11464.reset := reset inst T_11499 of TileLinkEnqueuer T_11499.io.manager.release.ready := UInt<1>("h00") T_11499.io.manager.probe.bits.payload.p_type := UInt<1>("h00") T_11499.io.manager.probe.bits.payload.addr_block := UInt<1>("h00") T_11499.io.manager.probe.bits.header.dst := UInt<1>("h00") T_11499.io.manager.probe.bits.header.src := UInt<1>("h00") T_11499.io.manager.probe.valid := UInt<1>("h00") T_11499.io.manager.finish.ready := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.g_type := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.data := UInt<1>("h00") T_11499.io.manager.grant.bits.payload.addr_beat := UInt<1>("h00") T_11499.io.manager.grant.bits.header.dst := UInt<1>("h00") T_11499.io.manager.grant.bits.header.src := UInt<1>("h00") T_11499.io.manager.grant.valid := UInt<1>("h00") T_11499.io.manager.acquire.ready := UInt<1>("h00") T_11499.io.client.release.bits.payload.voluntary := UInt<1>("h00") T_11499.io.client.release.bits.payload.r_type := UInt<1>("h00") T_11499.io.client.release.bits.payload.data := UInt<1>("h00") T_11499.io.client.release.bits.payload.addr_beat := UInt<1>("h00") T_11499.io.client.release.bits.payload.client_xact_id := UInt<1>("h00") T_11499.io.client.release.bits.payload.addr_block := UInt<1>("h00") T_11499.io.client.release.bits.header.dst := UInt<1>("h00") T_11499.io.client.release.bits.header.src := UInt<1>("h00") T_11499.io.client.release.valid := UInt<1>("h00") T_11499.io.client.probe.ready := UInt<1>("h00") T_11499.io.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") T_11499.io.client.finish.bits.header.dst := UInt<1>("h00") T_11499.io.client.finish.bits.header.src := UInt<1>("h00") T_11499.io.client.finish.valid := UInt<1>("h00") T_11499.io.client.grant.ready := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.union := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.a_type := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.data := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.addr_beat := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") T_11499.io.client.acquire.bits.payload.addr_block := UInt<1>("h00") T_11499.io.client.acquire.bits.header.dst := UInt<1>("h00") T_11499.io.client.acquire.bits.header.src := UInt<1>("h00") T_11499.io.client.acquire.valid := UInt<1>("h00") T_11499.clock := clock T_11499.reset := reset T_11464.io.client <> io.clients[1] T_11499.io.client <> T_11464.io.network inst T_11542 of ClientTileLinkNetworkPort_15 T_11542.io.network.release.ready := UInt<1>("h00") T_11542.io.network.probe.bits.payload.p_type := UInt<1>("h00") T_11542.io.network.probe.bits.payload.addr_block := UInt<1>("h00") T_11542.io.network.probe.bits.header.dst := UInt<1>("h00") T_11542.io.network.probe.bits.header.src := UInt<1>("h00") T_11542.io.network.probe.valid := UInt<1>("h00") T_11542.io.network.finish.ready := UInt<1>("h00") T_11542.io.network.grant.bits.payload.g_type := UInt<1>("h00") T_11542.io.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11542.io.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11542.io.network.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11542.io.network.grant.bits.payload.data := UInt<1>("h00") T_11542.io.network.grant.bits.payload.addr_beat := UInt<1>("h00") T_11542.io.network.grant.bits.header.dst := UInt<1>("h00") T_11542.io.network.grant.bits.header.src := UInt<1>("h00") T_11542.io.network.grant.valid := UInt<1>("h00") T_11542.io.network.acquire.ready := UInt<1>("h00") T_11542.io.client.release.bits.voluntary := UInt<1>("h00") T_11542.io.client.release.bits.r_type := UInt<1>("h00") T_11542.io.client.release.bits.data := UInt<1>("h00") T_11542.io.client.release.bits.addr_beat := UInt<1>("h00") T_11542.io.client.release.bits.client_xact_id := UInt<1>("h00") T_11542.io.client.release.bits.addr_block := UInt<1>("h00") T_11542.io.client.release.valid := UInt<1>("h00") T_11542.io.client.probe.ready := UInt<1>("h00") T_11542.io.client.grant.ready := UInt<1>("h00") T_11542.io.client.acquire.bits.union := UInt<1>("h00") T_11542.io.client.acquire.bits.a_type := UInt<1>("h00") T_11542.io.client.acquire.bits.is_builtin_type := UInt<1>("h00") T_11542.io.client.acquire.bits.data := UInt<1>("h00") T_11542.io.client.acquire.bits.addr_beat := UInt<1>("h00") T_11542.io.client.acquire.bits.client_xact_id := UInt<1>("h00") T_11542.io.client.acquire.bits.addr_block := UInt<1>("h00") T_11542.io.client.acquire.valid := UInt<1>("h00") T_11542.clock := clock T_11542.reset := reset inst T_11577 of TileLinkEnqueuer T_11577.io.manager.release.ready := UInt<1>("h00") T_11577.io.manager.probe.bits.payload.p_type := UInt<1>("h00") T_11577.io.manager.probe.bits.payload.addr_block := UInt<1>("h00") T_11577.io.manager.probe.bits.header.dst := UInt<1>("h00") T_11577.io.manager.probe.bits.header.src := UInt<1>("h00") T_11577.io.manager.probe.valid := UInt<1>("h00") T_11577.io.manager.finish.ready := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.g_type := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.data := UInt<1>("h00") T_11577.io.manager.grant.bits.payload.addr_beat := UInt<1>("h00") T_11577.io.manager.grant.bits.header.dst := UInt<1>("h00") T_11577.io.manager.grant.bits.header.src := UInt<1>("h00") T_11577.io.manager.grant.valid := UInt<1>("h00") T_11577.io.manager.acquire.ready := UInt<1>("h00") T_11577.io.client.release.bits.payload.voluntary := UInt<1>("h00") T_11577.io.client.release.bits.payload.r_type := UInt<1>("h00") T_11577.io.client.release.bits.payload.data := UInt<1>("h00") T_11577.io.client.release.bits.payload.addr_beat := UInt<1>("h00") T_11577.io.client.release.bits.payload.client_xact_id := UInt<1>("h00") T_11577.io.client.release.bits.payload.addr_block := UInt<1>("h00") T_11577.io.client.release.bits.header.dst := UInt<1>("h00") T_11577.io.client.release.bits.header.src := UInt<1>("h00") T_11577.io.client.release.valid := UInt<1>("h00") T_11577.io.client.probe.ready := UInt<1>("h00") T_11577.io.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") T_11577.io.client.finish.bits.header.dst := UInt<1>("h00") T_11577.io.client.finish.bits.header.src := UInt<1>("h00") T_11577.io.client.finish.valid := UInt<1>("h00") T_11577.io.client.grant.ready := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.union := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.a_type := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.data := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.addr_beat := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") T_11577.io.client.acquire.bits.payload.addr_block := UInt<1>("h00") T_11577.io.client.acquire.bits.header.dst := UInt<1>("h00") T_11577.io.client.acquire.bits.header.src := UInt<1>("h00") T_11577.io.client.acquire.valid := UInt<1>("h00") T_11577.clock := clock T_11577.reset := reset T_11542.io.client <> io.clients[2] T_11577.io.client <> T_11542.io.network inst T_11620 of ManagerTileLinkNetworkPort T_11620.io.network.release.bits.payload.voluntary := UInt<1>("h00") T_11620.io.network.release.bits.payload.r_type := UInt<1>("h00") T_11620.io.network.release.bits.payload.data := UInt<1>("h00") T_11620.io.network.release.bits.payload.addr_beat := UInt<1>("h00") T_11620.io.network.release.bits.payload.client_xact_id := UInt<1>("h00") T_11620.io.network.release.bits.payload.addr_block := UInt<1>("h00") T_11620.io.network.release.bits.header.dst := UInt<1>("h00") T_11620.io.network.release.bits.header.src := UInt<1>("h00") T_11620.io.network.release.valid := UInt<1>("h00") T_11620.io.network.probe.ready := UInt<1>("h00") T_11620.io.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") T_11620.io.network.finish.bits.header.dst := UInt<1>("h00") T_11620.io.network.finish.bits.header.src := UInt<1>("h00") T_11620.io.network.finish.valid := UInt<1>("h00") T_11620.io.network.grant.ready := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.union := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.a_type := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.data := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.addr_beat := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") T_11620.io.network.acquire.bits.payload.addr_block := UInt<1>("h00") T_11620.io.network.acquire.bits.header.dst := UInt<1>("h00") T_11620.io.network.acquire.bits.header.src := UInt<1>("h00") T_11620.io.network.acquire.valid := UInt<1>("h00") T_11620.io.manager.release.ready := UInt<1>("h00") T_11620.io.manager.probe.bits.client_id := UInt<1>("h00") T_11620.io.manager.probe.bits.p_type := UInt<1>("h00") T_11620.io.manager.probe.bits.addr_block := UInt<1>("h00") T_11620.io.manager.probe.valid := UInt<1>("h00") T_11620.io.manager.finish.ready := UInt<1>("h00") T_11620.io.manager.grant.bits.client_id := UInt<1>("h00") T_11620.io.manager.grant.bits.g_type := UInt<1>("h00") T_11620.io.manager.grant.bits.is_builtin_type := UInt<1>("h00") T_11620.io.manager.grant.bits.manager_xact_id := UInt<1>("h00") T_11620.io.manager.grant.bits.client_xact_id := UInt<1>("h00") T_11620.io.manager.grant.bits.data := UInt<1>("h00") T_11620.io.manager.grant.bits.addr_beat := UInt<1>("h00") T_11620.io.manager.grant.valid := UInt<1>("h00") T_11620.io.manager.acquire.ready := UInt<1>("h00") T_11620.clock := clock T_11620.reset := reset inst T_11661 of TileLinkEnqueuer_24 T_11661.io.manager.release.ready := UInt<1>("h00") T_11661.io.manager.probe.bits.payload.p_type := UInt<1>("h00") T_11661.io.manager.probe.bits.payload.addr_block := UInt<1>("h00") T_11661.io.manager.probe.bits.header.dst := UInt<1>("h00") T_11661.io.manager.probe.bits.header.src := UInt<1>("h00") T_11661.io.manager.probe.valid := UInt<1>("h00") T_11661.io.manager.finish.ready := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.g_type := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.data := UInt<1>("h00") T_11661.io.manager.grant.bits.payload.addr_beat := UInt<1>("h00") T_11661.io.manager.grant.bits.header.dst := UInt<1>("h00") T_11661.io.manager.grant.bits.header.src := UInt<1>("h00") T_11661.io.manager.grant.valid := UInt<1>("h00") T_11661.io.manager.acquire.ready := UInt<1>("h00") T_11661.io.client.release.bits.payload.voluntary := UInt<1>("h00") T_11661.io.client.release.bits.payload.r_type := UInt<1>("h00") T_11661.io.client.release.bits.payload.data := UInt<1>("h00") T_11661.io.client.release.bits.payload.addr_beat := UInt<1>("h00") T_11661.io.client.release.bits.payload.client_xact_id := UInt<1>("h00") T_11661.io.client.release.bits.payload.addr_block := UInt<1>("h00") T_11661.io.client.release.bits.header.dst := UInt<1>("h00") T_11661.io.client.release.bits.header.src := UInt<1>("h00") T_11661.io.client.release.valid := UInt<1>("h00") T_11661.io.client.probe.ready := UInt<1>("h00") T_11661.io.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") T_11661.io.client.finish.bits.header.dst := UInt<1>("h00") T_11661.io.client.finish.bits.header.src := UInt<1>("h00") T_11661.io.client.finish.valid := UInt<1>("h00") T_11661.io.client.grant.ready := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.union := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.a_type := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.data := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.addr_beat := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") T_11661.io.client.acquire.bits.payload.addr_block := UInt<1>("h00") T_11661.io.client.acquire.bits.header.dst := UInt<1>("h00") T_11661.io.client.acquire.bits.header.src := UInt<1>("h00") T_11661.io.client.acquire.valid := UInt<1>("h00") T_11661.clock := clock T_11661.reset := reset T_11620.io.manager <> io.managers[0] T_11620.io.network <> T_11661.io.manager inst T_11704 of LockingRRArbiter T_11704.io.out.ready := UInt<1>("h00") T_11704.io.in[0].bits.payload.union := UInt<1>("h00") T_11704.io.in[0].bits.payload.a_type := UInt<1>("h00") T_11704.io.in[0].bits.payload.is_builtin_type := UInt<1>("h00") T_11704.io.in[0].bits.payload.data := UInt<1>("h00") T_11704.io.in[0].bits.payload.addr_beat := UInt<1>("h00") T_11704.io.in[0].bits.payload.client_xact_id := UInt<1>("h00") T_11704.io.in[0].bits.payload.addr_block := UInt<1>("h00") T_11704.io.in[0].bits.header.dst := UInt<1>("h00") T_11704.io.in[0].bits.header.src := UInt<1>("h00") T_11704.io.in[0].valid := UInt<1>("h00") T_11704.io.in[1].bits.payload.union := UInt<1>("h00") T_11704.io.in[1].bits.payload.a_type := UInt<1>("h00") T_11704.io.in[1].bits.payload.is_builtin_type := UInt<1>("h00") T_11704.io.in[1].bits.payload.data := UInt<1>("h00") T_11704.io.in[1].bits.payload.addr_beat := UInt<1>("h00") T_11704.io.in[1].bits.payload.client_xact_id := UInt<1>("h00") T_11704.io.in[1].bits.payload.addr_block := UInt<1>("h00") T_11704.io.in[1].bits.header.dst := UInt<1>("h00") T_11704.io.in[1].bits.header.src := UInt<1>("h00") T_11704.io.in[1].valid := UInt<1>("h00") T_11704.io.in[2].bits.payload.union := UInt<1>("h00") T_11704.io.in[2].bits.payload.a_type := UInt<1>("h00") T_11704.io.in[2].bits.payload.is_builtin_type := UInt<1>("h00") T_11704.io.in[2].bits.payload.data := UInt<1>("h00") T_11704.io.in[2].bits.payload.addr_beat := UInt<1>("h00") T_11704.io.in[2].bits.payload.client_xact_id := UInt<1>("h00") T_11704.io.in[2].bits.payload.addr_block := UInt<1>("h00") T_11704.io.in[2].bits.header.dst := UInt<1>("h00") T_11704.io.in[2].bits.header.src := UInt<1>("h00") T_11704.io.in[2].valid := UInt<1>("h00") T_11704.clock := clock T_11704.reset := reset T_11704.io.in[0].valid := T_11421.io.manager.acquire.valid T_11704.io.in[0].bits <> T_11421.io.manager.acquire.bits T_11704.io.in[0].bits.payload.client_xact_id := T_11421.io.manager.acquire.bits.payload.client_xact_id T_11421.io.manager.acquire.ready := T_11704.io.in[0].ready T_11704.io.in[1].valid := T_11499.io.manager.acquire.valid T_11704.io.in[1].bits <> T_11499.io.manager.acquire.bits T_11704.io.in[1].bits.payload.client_xact_id := T_11499.io.manager.acquire.bits.payload.client_xact_id T_11499.io.manager.acquire.ready := T_11704.io.in[1].ready T_11704.io.in[2].valid := T_11577.io.manager.acquire.valid T_11704.io.in[2].bits <> T_11577.io.manager.acquire.bits T_11704.io.in[2].bits.payload.client_xact_id := T_11577.io.manager.acquire.bits.payload.client_xact_id T_11577.io.manager.acquire.ready := T_11704.io.in[2].ready T_11661.io.client.acquire <> T_11704.io.out inst T_11736 of LockingRRArbiter_26 T_11736.io.out.ready := UInt<1>("h00") T_11736.io.in[0].bits.payload.voluntary := UInt<1>("h00") T_11736.io.in[0].bits.payload.r_type := UInt<1>("h00") T_11736.io.in[0].bits.payload.data := UInt<1>("h00") T_11736.io.in[0].bits.payload.addr_beat := UInt<1>("h00") T_11736.io.in[0].bits.payload.client_xact_id := UInt<1>("h00") T_11736.io.in[0].bits.payload.addr_block := UInt<1>("h00") T_11736.io.in[0].bits.header.dst := UInt<1>("h00") T_11736.io.in[0].bits.header.src := UInt<1>("h00") T_11736.io.in[0].valid := UInt<1>("h00") T_11736.io.in[1].bits.payload.voluntary := UInt<1>("h00") T_11736.io.in[1].bits.payload.r_type := UInt<1>("h00") T_11736.io.in[1].bits.payload.data := UInt<1>("h00") T_11736.io.in[1].bits.payload.addr_beat := UInt<1>("h00") T_11736.io.in[1].bits.payload.client_xact_id := UInt<1>("h00") T_11736.io.in[1].bits.payload.addr_block := UInt<1>("h00") T_11736.io.in[1].bits.header.dst := UInt<1>("h00") T_11736.io.in[1].bits.header.src := UInt<1>("h00") T_11736.io.in[1].valid := UInt<1>("h00") T_11736.io.in[2].bits.payload.voluntary := UInt<1>("h00") T_11736.io.in[2].bits.payload.r_type := UInt<1>("h00") T_11736.io.in[2].bits.payload.data := UInt<1>("h00") T_11736.io.in[2].bits.payload.addr_beat := UInt<1>("h00") T_11736.io.in[2].bits.payload.client_xact_id := UInt<1>("h00") T_11736.io.in[2].bits.payload.addr_block := UInt<1>("h00") T_11736.io.in[2].bits.header.dst := UInt<1>("h00") T_11736.io.in[2].bits.header.src := UInt<1>("h00") T_11736.io.in[2].valid := UInt<1>("h00") T_11736.clock := clock T_11736.reset := reset T_11736.io.in[0].valid := T_11421.io.manager.release.valid T_11736.io.in[0].bits <> T_11421.io.manager.release.bits T_11736.io.in[0].bits.payload.client_xact_id := T_11421.io.manager.release.bits.payload.client_xact_id T_11421.io.manager.release.ready := T_11736.io.in[0].ready T_11736.io.in[1].valid := T_11499.io.manager.release.valid T_11736.io.in[1].bits <> T_11499.io.manager.release.bits T_11736.io.in[1].bits.payload.client_xact_id := T_11499.io.manager.release.bits.payload.client_xact_id T_11499.io.manager.release.ready := T_11736.io.in[1].ready T_11736.io.in[2].valid := T_11577.io.manager.release.valid T_11736.io.in[2].bits <> T_11577.io.manager.release.bits T_11736.io.in[2].bits.payload.client_xact_id := T_11577.io.manager.release.bits.payload.client_xact_id T_11577.io.manager.release.ready := T_11736.io.in[2].ready T_11661.io.client.release <> T_11736.io.out inst T_11765 of RRArbiter T_11765.io.out.ready := UInt<1>("h00") T_11765.io.in[0].bits.payload.manager_xact_id := UInt<1>("h00") T_11765.io.in[0].bits.header.dst := UInt<1>("h00") T_11765.io.in[0].bits.header.src := UInt<1>("h00") T_11765.io.in[0].valid := UInt<1>("h00") T_11765.io.in[1].bits.payload.manager_xact_id := UInt<1>("h00") T_11765.io.in[1].bits.header.dst := UInt<1>("h00") T_11765.io.in[1].bits.header.src := UInt<1>("h00") T_11765.io.in[1].valid := UInt<1>("h00") T_11765.io.in[2].bits.payload.manager_xact_id := UInt<1>("h00") T_11765.io.in[2].bits.header.dst := UInt<1>("h00") T_11765.io.in[2].bits.header.src := UInt<1>("h00") T_11765.io.in[2].valid := UInt<1>("h00") T_11765.clock := clock T_11765.reset := reset T_11765.io.in[0] <> T_11421.io.manager.finish T_11765.io.in[1] <> T_11499.io.manager.finish T_11765.io.in[2] <> T_11577.io.manager.finish T_11661.io.client.finish <> T_11765.io.out T_11661.io.client.probe.ready := UInt<1>("h00") T_11421.io.manager.probe.valid := UInt<1>("h00") node T_11782 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h00")) when T_11782 : T_11421.io.manager.probe.valid := T_11661.io.client.probe.valid T_11661.io.client.probe.ready := T_11421.io.manager.probe.ready skip T_11421.io.manager.probe.bits <> T_11661.io.client.probe.bits T_11499.io.manager.probe.valid := UInt<1>("h00") node T_11785 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h01")) when T_11785 : T_11499.io.manager.probe.valid := T_11661.io.client.probe.valid T_11661.io.client.probe.ready := T_11499.io.manager.probe.ready skip T_11499.io.manager.probe.bits <> T_11661.io.client.probe.bits T_11577.io.manager.probe.valid := UInt<1>("h00") node T_11788 = eq(T_11661.io.client.probe.bits.header.dst, UInt<2>("h02")) when T_11788 : T_11577.io.manager.probe.valid := T_11661.io.client.probe.valid T_11661.io.client.probe.ready := T_11577.io.manager.probe.ready skip T_11577.io.manager.probe.bits <> T_11661.io.client.probe.bits T_11661.io.client.grant.ready := UInt<1>("h00") T_11421.io.manager.grant.valid := UInt<1>("h00") node T_11792 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h00")) when T_11792 : T_11421.io.manager.grant.valid := T_11661.io.client.grant.valid T_11661.io.client.grant.ready := T_11421.io.manager.grant.ready skip T_11421.io.manager.grant.bits <> T_11661.io.client.grant.bits T_11499.io.manager.grant.valid := UInt<1>("h00") node T_11795 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h01")) when T_11795 : T_11499.io.manager.grant.valid := T_11661.io.client.grant.valid T_11661.io.client.grant.ready := T_11499.io.manager.grant.ready skip T_11499.io.manager.grant.bits <> T_11661.io.client.grant.bits T_11577.io.manager.grant.valid := UInt<1>("h00") node T_11798 = eq(T_11661.io.client.grant.bits.header.dst, UInt<2>("h02")) when T_11798 : T_11577.io.manager.grant.valid := T_11661.io.client.grant.valid T_11661.io.client.grant.ready := T_11577.io.manager.grant.ready skip T_11577.io.manager.grant.bits <> T_11661.io.client.grant.bits module BroadcastVoluntaryReleaseTracker : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") reg collect_irel_data : UInt<1>, clock, reset onreset collect_irel_data := UInt<1>("h00") reg irel_data_valid : UInt<4>, clock, reset onreset irel_data_valid := UInt<4>("h00") node T_1091 = and(io.inner.release.ready, io.inner.release.valid) wire T_1095 : UInt<2>[3] T_1095[0] := UInt<1>("h00") T_1095[1] := UInt<1>("h01") T_1095[2] := UInt<2>("h02") node T_1100 = eq(T_1095[0], io.inner.release.bits.r_type) node T_1101 = eq(T_1095[1], io.inner.release.bits.r_type) node T_1102 = eq(T_1095[2], io.inner.release.bits.r_type) node T_1104 = or(UInt<1>("h00"), T_1100) node T_1105 = or(T_1104, T_1101) node T_1106 = or(T_1105, T_1102) node T_1107 = and(UInt<1>("h01"), T_1106) node T_1108 = and(T_1091, T_1107) reg T_1110 : UInt<2>, clock, reset onreset T_1110 := UInt<2>("h00") when T_1108 : node T_1112 = eq(T_1110, UInt<2>("h03")) node T_1114 = and(UInt<1>("h00"), T_1112) node T_1117 = addw(T_1110, UInt<1>("h01")) node T_1118 = mux(T_1114, UInt<1>("h00"), T_1117) T_1110 := T_1118 skip node T_1119 = and(T_1108, T_1112) node T_1120 = mux(T_1107, T_1110, UInt<1>("h00")) node irel_data_done = mux(T_1107, T_1119, T_1091) node T_1123 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1125 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1128 : UInt<3>[1] T_1128[0] := UInt<3>("h03") node T_1131 = eq(T_1128[0], io.outer.acquire.bits.a_type) node T_1133 = or(UInt<1>("h00"), T_1131) node T_1134 = and(T_1125, T_1133) node T_1135 = and(T_1123, T_1134) reg T_1137 : UInt<2>, clock, reset onreset T_1137 := UInt<2>("h00") when T_1135 : node T_1139 = eq(T_1137, UInt<2>("h03")) node T_1141 = and(UInt<1>("h00"), T_1139) node T_1144 = addw(T_1137, UInt<1>("h01")) node T_1145 = mux(T_1141, UInt<1>("h00"), T_1144) T_1137 := T_1145 skip node T_1146 = and(T_1135, T_1139) node oacq_data_cnt = mux(T_1134, T_1137, UInt<1>("h00")) node oacq_data_done = mux(T_1134, T_1146, T_1123) io.has_acquire_conflict := UInt<1>("h00") io.has_release_match := io.inner.release.bits.voluntary io.has_acquire_match := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") wire T_1194 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1194.client_id := UInt<1>("h00") T_1194.g_type := UInt<1>("h00") T_1194.is_builtin_type := UInt<1>("h00") T_1194.manager_xact_id := UInt<1>("h00") T_1194.client_xact_id := UInt<1>("h00") T_1194.data := UInt<1>("h00") T_1194.addr_beat := UInt<1>("h00") T_1194.client_id := xact.client_id T_1194.is_builtin_type := UInt<1>("h01") T_1194.g_type := UInt<3>("h00") T_1194.client_xact_id := xact.client_xact_id T_1194.manager_xact_id := UInt<1>("h00") T_1194.addr_beat := UInt<1>("h00") T_1194.data := UInt<1>("h00") io.inner.grant.bits <> T_1194 infer accessor T_1233 = data_buffer[oacq_data_cnt] node T_1266 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1267 = cat(T_1266, UInt<1>("h01")) wire T_1296 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1296.union := UInt<1>("h00") T_1296.a_type := UInt<1>("h00") T_1296.is_builtin_type := UInt<1>("h00") T_1296.data := UInt<1>("h00") T_1296.addr_beat := UInt<1>("h00") T_1296.client_xact_id := UInt<1>("h00") T_1296.addr_block := UInt<1>("h00") T_1296.is_builtin_type := UInt<1>("h01") T_1296.a_type := UInt<3>("h03") T_1296.client_xact_id := UInt<1>("h00") T_1296.addr_block := xact.addr_block T_1296.addr_beat := oacq_data_cnt T_1296.data := T_1233 T_1296.union := T_1267 io.outer.acquire.bits <> T_1296 when collect_irel_data : io.inner.release.ready := UInt<1>("h01") when io.inner.release.valid : infer accessor T_1332 = data_buffer[io.inner.release.bits.addr_beat] T_1332 := io.inner.release.bits.data node T_1335 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) node T_1336 = or(irel_data_valid, T_1335) node T_1337 = not(irel_data_valid) node T_1338 = or(T_1337, T_1335) node T_1339 = not(T_1338) node T_1340 = mux(UInt<1>("h01"), T_1336, T_1339) irel_data_valid := T_1340 skip when irel_data_done : collect_irel_data := UInt<1>("h00") skip skip node T_1342 = eq(UInt<1>("h00"), state) when T_1342 : io.inner.release.ready := UInt<1>("h01") when io.inner.release.valid : xact <> io.inner.release.bits infer accessor T_1345 = data_buffer[UInt<1>("h00")] T_1345 := io.inner.release.bits.data wire T_1348 : UInt<2>[3] T_1348[0] := UInt<1>("h00") T_1348[1] := UInt<1>("h01") T_1348[2] := UInt<2>("h02") node T_1353 = eq(T_1348[0], io.inner.release.bits.r_type) node T_1354 = eq(T_1348[1], io.inner.release.bits.r_type) node T_1355 = eq(T_1348[2], io.inner.release.bits.r_type) node T_1357 = or(UInt<1>("h00"), T_1353) node T_1358 = or(T_1357, T_1354) node T_1359 = or(T_1358, T_1355) node T_1360 = and(UInt<1>("h01"), T_1359) collect_irel_data := T_1360 wire T_1362 : UInt<2>[3] T_1362[0] := UInt<1>("h00") T_1362[1] := UInt<1>("h01") T_1362[2] := UInt<2>("h02") node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) node T_1371 = or(UInt<1>("h00"), T_1367) node T_1372 = or(T_1371, T_1368) node T_1373 = or(T_1372, T_1369) node T_1374 = dshl(T_1373, io.inner.release.bits.addr_beat) irel_data_valid := T_1374 wire T_1376 : UInt<2>[3] T_1376[0] := UInt<1>("h00") T_1376[1] := UInt<1>("h01") T_1376[2] := UInt<2>("h02") node T_1381 = eq(T_1376[0], io.inner.release.bits.r_type) node T_1382 = eq(T_1376[1], io.inner.release.bits.r_type) node T_1383 = eq(T_1376[2], io.inner.release.bits.r_type) node T_1385 = or(UInt<1>("h00"), T_1381) node T_1386 = or(T_1385, T_1382) node T_1387 = or(T_1386, T_1383) node T_1390 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1391 = mux(T_1390, UInt<2>("h03"), UInt<1>("h00")) node T_1392 = mux(T_1387, UInt<1>("h01"), T_1391) state := T_1392 skip skip node T_1393 = eq(UInt<1>("h01"), state) when T_1393 : node T_1395 = eq(collect_irel_data, UInt<1>("h00")) node T_1396 = dshr(irel_data_valid, oacq_data_cnt) node T_1397 = bit(T_1396, 0) node T_1398 = or(T_1395, T_1397) io.outer.acquire.valid := T_1398 when oacq_data_done : state := UInt<2>("h02") skip skip node T_1399 = eq(UInt<2>("h02"), state) when T_1399 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid node T_1400 = and(io.inner.grant.ready, io.inner.grant.valid) when T_1400 : node T_1403 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1405 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1406 = and(io.inner.grant.bits.is_builtin_type, T_1405) node T_1408 = eq(T_1406, UInt<1>("h00")) node T_1409 = and(T_1403, T_1408) node T_1410 = mux(T_1409, UInt<2>("h03"), UInt<1>("h00")) state := T_1410 skip skip node T_1411 = eq(UInt<2>("h03"), state) when T_1411 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<1>("h01") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<1>("h01") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<1>("h01") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<1>("h01") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<1>("h01") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<1>("h01") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<1>("h01") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_27 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<2>("h02") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<2>("h02") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<2>("h02") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<2>("h02") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<2>("h02") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<2>("h02") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<2>("h02") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_28 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<2>("h03") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<2>("h03") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<2>("h03") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<2>("h03") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<2>("h03") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<2>("h03") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<2>("h03") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_29 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<3>("h04") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<3>("h04") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<3>("h04") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<3>("h04") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<3>("h04") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<3>("h04") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<3>("h04") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_30 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<3>("h05") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<3>("h05") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<3>("h05") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<3>("h05") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<3>("h05") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<3>("h05") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<3>("h05") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_31 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<3>("h06") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<3>("h06") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<3>("h06") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<3>("h06") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<3>("h06") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<3>("h06") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<3>("h06") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module BroadcastAcquireTracker_32 : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match := UInt<1>("h00") io.has_acquire_match := UInt<1>("h00") io.has_acquire_conflict := UInt<1>("h00") io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}, clock, reset reg data_buffer : UInt<4>[4], clock, reset wire coh : {sharers : UInt<1>} coh.sharers := UInt<1>("h00") coh.sharers := UInt<1>("h00") node T_1092 = neq(state, UInt<1>("h00")) node T_1093 = and(T_1092, xact.is_builtin_type) wire T_1097 : UInt<3>[2] T_1097[0] := UInt<3>("h04") T_1097[1] := UInt<3>("h05") node T_1101 = eq(T_1097[0], xact.a_type) node T_1102 = eq(T_1097[1], xact.a_type) node T_1104 = or(UInt<1>("h00"), T_1101) node T_1105 = or(T_1104, T_1102) node T_1106 = and(T_1093, T_1105) node T_1108 = eq(T_1106, UInt<1>("h00")) reg release_count : UInt<1>, clock, reset onreset release_count := UInt<1>("h00") reg pending_probes : UInt<1>, clock, reset onreset pending_probes := UInt<1>("h00") node T_1113 = bit(pending_probes, 0) wire T_1115 : UInt<1>[1] T_1115[0] := T_1113 node T_1120 = asUInt(asSInt(UInt<1>("h01"))) node T_1123 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_1124 = or(T_1120, T_1123) node T_1125 = not(T_1120) node T_1126 = or(T_1125, T_1123) node T_1127 = not(T_1126) node mask_self = mux(UInt<1>("h00"), T_1124, T_1127) node T_1129 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_1129) reg collect_iacq_data : UInt<1>, clock, reset onreset collect_iacq_data := UInt<1>("h00") reg iacq_data_valid : UInt<4>, clock, reset onreset iacq_data_valid := UInt<4>("h00") node T_1135 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1138 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1141 : UInt<3>[1] T_1141[0] := UInt<3>("h03") node T_1144 = eq(T_1141[0], io.inner.acquire.bits.a_type) node T_1146 = or(UInt<1>("h00"), T_1144) node T_1147 = and(T_1138, T_1146) node T_1148 = and(T_1135, T_1147) reg T_1150 : UInt<2>, clock, reset onreset T_1150 := UInt<2>("h00") when T_1148 : node T_1152 = eq(T_1150, UInt<2>("h03")) node T_1154 = and(UInt<1>("h00"), T_1152) node T_1157 = addw(T_1150, UInt<1>("h01")) node T_1158 = mux(T_1154, UInt<1>("h00"), T_1157) T_1150 := T_1158 skip node T_1159 = and(T_1148, T_1152) node T_1160 = mux(T_1147, T_1150, UInt<1>("h00")) node iacq_data_done = mux(T_1147, T_1159, T_1135) node T_1162 = and(io.inner.release.ready, io.inner.release.valid) wire T_1166 : UInt<2>[3] T_1166[0] := UInt<1>("h00") T_1166[1] := UInt<1>("h01") T_1166[2] := UInt<2>("h02") node T_1171 = eq(T_1166[0], io.inner.release.bits.r_type) node T_1172 = eq(T_1166[1], io.inner.release.bits.r_type) node T_1173 = eq(T_1166[2], io.inner.release.bits.r_type) node T_1175 = or(UInt<1>("h00"), T_1171) node T_1176 = or(T_1175, T_1172) node T_1177 = or(T_1176, T_1173) node T_1178 = and(UInt<1>("h01"), T_1177) node T_1179 = and(T_1162, T_1178) reg T_1181 : UInt<2>, clock, reset onreset T_1181 := UInt<2>("h00") when T_1179 : node T_1183 = eq(T_1181, UInt<2>("h03")) node T_1185 = and(UInt<1>("h00"), T_1183) node T_1188 = addw(T_1181, UInt<1>("h01")) node T_1189 = mux(T_1185, UInt<1>("h00"), T_1188) T_1181 := T_1189 skip node T_1190 = and(T_1179, T_1183) node T_1191 = mux(T_1178, T_1181, UInt<1>("h00")) node irel_data_done = mux(T_1178, T_1190, T_1162) node T_1194 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_1198 : UInt<3>[1] T_1198[0] := UInt<3>("h05") node T_1201 = eq(T_1198[0], io.inner.grant.bits.g_type) node T_1203 = or(UInt<1>("h00"), T_1201) wire T_1205 : UInt<1>[2] T_1205[0] := UInt<1>("h00") T_1205[1] := UInt<1>("h01") node T_1209 = eq(T_1205[0], io.inner.grant.bits.g_type) node T_1210 = eq(T_1205[1], io.inner.grant.bits.g_type) node T_1212 = or(UInt<1>("h00"), T_1209) node T_1213 = or(T_1212, T_1210) node T_1214 = mux(io.inner.grant.bits.is_builtin_type, T_1203, T_1213) node T_1215 = and(UInt<1>("h01"), T_1214) node T_1216 = and(T_1194, T_1215) reg T_1218 : UInt<2>, clock, reset onreset T_1218 := UInt<2>("h00") when T_1216 : node T_1220 = eq(T_1218, UInt<2>("h03")) node T_1222 = and(UInt<1>("h00"), T_1220) node T_1225 = addw(T_1218, UInt<1>("h01")) node T_1226 = mux(T_1222, UInt<1>("h00"), T_1225) T_1218 := T_1226 skip node T_1227 = and(T_1216, T_1220) node ignt_data_cnt = mux(T_1215, T_1218, UInt<1>("h00")) node ignt_data_done = mux(T_1215, T_1227, T_1194) node T_1231 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_1233 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_1236 : UInt<3>[1] T_1236[0] := UInt<3>("h03") node T_1239 = eq(T_1236[0], io.outer.acquire.bits.a_type) node T_1241 = or(UInt<1>("h00"), T_1239) node T_1242 = and(T_1233, T_1241) node T_1243 = and(T_1231, T_1242) reg T_1245 : UInt<2>, clock, reset onreset T_1245 := UInt<2>("h00") when T_1243 : node T_1247 = eq(T_1245, UInt<2>("h03")) node T_1249 = and(UInt<1>("h00"), T_1247) node T_1252 = addw(T_1245, UInt<1>("h01")) node T_1253 = mux(T_1249, UInt<1>("h00"), T_1252) T_1245 := T_1253 skip node T_1254 = and(T_1243, T_1247) node oacq_data_cnt = mux(T_1242, T_1245, UInt<1>("h00")) node oacq_data_done = mux(T_1242, T_1254, T_1231) node T_1257 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_1262 : UInt<3>[1] T_1262[0] := UInt<3>("h05") node T_1265 = eq(T_1262[0], io.outer.grant.bits.g_type) node T_1267 = or(UInt<1>("h00"), T_1265) wire T_1269 : UInt<1>[1] T_1269[0] := UInt<1>("h00") node T_1272 = eq(T_1269[0], io.outer.grant.bits.g_type) node T_1274 = or(UInt<1>("h00"), T_1272) node T_1275 = mux(io.outer.grant.bits.is_builtin_type, T_1267, T_1274) node T_1276 = and(UInt<1>("h01"), T_1275) node T_1277 = and(T_1257, T_1276) reg T_1279 : UInt<2>, clock, reset onreset T_1279 := UInt<2>("h00") when T_1277 : node T_1281 = eq(T_1279, UInt<2>("h03")) node T_1283 = and(UInt<1>("h00"), T_1281) node T_1286 = addw(T_1279, UInt<1>("h01")) node T_1287 = mux(T_1283, UInt<1>("h00"), T_1286) T_1279 := T_1287 skip node T_1288 = and(T_1277, T_1281) node T_1289 = mux(T_1276, T_1279, UInt<1>("h00")) node ognt_data_done = mux(T_1276, T_1288, T_1257) reg pending_ognt_ack : UInt<1>, clock, reset onreset pending_ognt_ack := UInt<1>("h00") wire T_1297 : UInt<3>[3] T_1297[0] := UInt<3>("h02") T_1297[1] := UInt<3>("h03") T_1297[2] := UInt<3>("h04") node T_1302 = eq(T_1297[0], xact.a_type) node T_1303 = eq(T_1297[1], xact.a_type) node T_1304 = eq(T_1297[2], xact.a_type) node T_1306 = or(UInt<1>("h00"), T_1302) node T_1307 = or(T_1306, T_1303) node T_1308 = or(T_1307, T_1304) node pending_outer_write = and(xact.is_builtin_type, T_1308) wire T_1314 : UInt<3>[3] T_1314[0] := UInt<3>("h02") T_1314[1] := UInt<3>("h03") T_1314[2] := UInt<3>("h04") node T_1319 = eq(T_1314[0], io.inner.acquire.bits.a_type) node T_1320 = eq(T_1314[1], io.inner.acquire.bits.a_type) node T_1321 = eq(T_1314[2], io.inner.acquire.bits.a_type) node T_1323 = or(UInt<1>("h00"), T_1319) node T_1324 = or(T_1323, T_1320) node T_1325 = or(T_1324, T_1321) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_1325) wire T_1330 : UInt<3>[2] T_1330[0] := UInt<3>("h05") T_1330[1] := UInt<3>("h04") node T_1334 = eq(T_1330[0], io.inner.grant.bits.g_type) node T_1335 = eq(T_1330[1], io.inner.grant.bits.g_type) node T_1337 = or(UInt<1>("h00"), T_1334) node T_1338 = or(T_1337, T_1335) wire T_1340 : UInt<1>[2] T_1340[0] := UInt<1>("h00") T_1340[1] := UInt<1>("h01") node T_1344 = eq(T_1340[0], io.inner.grant.bits.g_type) node T_1345 = eq(T_1340[1], io.inner.grant.bits.g_type) node T_1347 = or(UInt<1>("h00"), T_1344) node T_1348 = or(T_1347, T_1345) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_1338, T_1348) node T_1366 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_1367 = mux(T_1366, UInt<3>("h01"), UInt<3>("h03")) node T_1368 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_1369 = mux(T_1368, UInt<3>("h04"), T_1367) node T_1370 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_1371 = mux(T_1370, UInt<3>("h03"), T_1369) node T_1372 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_1373 = mux(T_1372, UInt<3>("h03"), T_1371) node T_1374 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_1375 = mux(T_1374, UInt<3>("h05"), T_1373) node T_1376 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) node T_1378 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_1381 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1382 = mux(T_1381, UInt<1>("h00"), UInt<1>("h01")) node T_1383 = mux(T_1378, T_1382, UInt<1>("h01")) node T_1384 = mux(io.inner.acquire.bits.is_builtin_type, T_1377, T_1383) wire T_1416 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_1416.client_id := UInt<1>("h00") T_1416.g_type := UInt<1>("h00") T_1416.is_builtin_type := UInt<1>("h00") T_1416.manager_xact_id := UInt<1>("h00") T_1416.client_xact_id := UInt<1>("h00") T_1416.data := UInt<1>("h00") T_1416.addr_beat := UInt<1>("h00") T_1416.client_id := io.inner.acquire.bits.client_id T_1416.is_builtin_type := io.inner.acquire.bits.is_builtin_type T_1416.g_type := T_1384 T_1416.client_xact_id := io.inner.acquire.bits.client_xact_id T_1416.manager_xact_id := UInt<3>("h07") T_1416.addr_beat := UInt<1>("h00") T_1416.data := UInt<1>("h00") wire T_1457 : UInt<3>[2] T_1457[0] := UInt<3>("h05") T_1457[1] := UInt<3>("h04") node T_1461 = eq(T_1457[0], T_1416.g_type) node T_1462 = eq(T_1457[1], T_1416.g_type) node T_1464 = or(UInt<1>("h00"), T_1461) node T_1465 = or(T_1464, T_1462) wire T_1467 : UInt<1>[2] T_1467[0] := UInt<1>("h00") T_1467[1] := UInt<1>("h01") node T_1471 = eq(T_1467[0], T_1416.g_type) node T_1472 = eq(T_1467[1], T_1416.g_type) node T_1474 = or(UInt<1>("h00"), T_1471) node T_1475 = or(T_1474, T_1472) node pending_outer_read_ = mux(T_1416.is_builtin_type, T_1465, T_1475) wire T_1481 : UInt<3>[3] T_1481[0] := UInt<3>("h02") T_1481[1] := UInt<3>("h00") T_1481[2] := UInt<3>("h04") node T_1486 = eq(T_1481[0], xact.a_type) node T_1487 = eq(T_1481[1], xact.a_type) node T_1488 = eq(T_1481[2], xact.a_type) node T_1490 = or(UInt<1>("h00"), T_1486) node T_1491 = or(T_1490, T_1487) node T_1492 = or(T_1491, T_1488) node subblock_type = and(xact.is_builtin_type, T_1492) node T_1494 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1495 = neq(state, UInt<1>("h00")) node T_1496 = and(T_1494, T_1495) node T_1498 = eq(collect_iacq_data, UInt<1>("h00")) node T_1499 = and(T_1496, T_1498) io.has_acquire_conflict := T_1499 node T_1500 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_1501 = and(T_1500, collect_iacq_data) io.has_acquire_match := T_1501 node T_1502 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_1504 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_1505 = and(T_1502, T_1504) node T_1506 = eq(state, UInt<1>("h01")) node T_1507 = and(T_1505, T_1506) io.has_release_match := T_1507 node T_1544 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1545 = cat(T_1544, UInt<1>("h01")) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_probe.union := UInt<1>("h00") oacq_probe.a_type := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h00") oacq_probe.data := UInt<1>("h00") oacq_probe.addr_beat := UInt<1>("h00") oacq_probe.client_xact_id := UInt<1>("h00") oacq_probe.addr_block := UInt<1>("h00") oacq_probe.is_builtin_type := UInt<1>("h01") oacq_probe.a_type := UInt<3>("h03") oacq_probe.client_xact_id := UInt<3>("h07") oacq_probe.addr_block := io.inner.release.bits.addr_block oacq_probe.addr_beat := io.inner.release.bits.addr_beat oacq_probe.data := io.inner.release.bits.data oacq_probe.union := T_1545 node T_1617 = eq(xact.a_type, UInt<3>("h04")) node T_1618 = and(xact.is_builtin_type, T_1617) node T_1619 = bits(xact.union, 12, 9) node T_1620 = bits(T_1619, 3, 3) node T_1622 = dshl(UInt<1>("h01"), T_1620) node T_1623 = bit(T_1622, 0) node T_1624 = bit(T_1622, 1) wire T_1626 : UInt<1>[2] T_1626[0] := T_1623 T_1626[1] := T_1624 node T_1631 = subw(UInt<8>("h00"), T_1626[0]) node T_1633 = subw(UInt<8>("h00"), T_1626[1]) wire T_1635 : UInt<8>[2] T_1635[0] := T_1631 T_1635[1] := T_1633 node T_1639 = cat(T_1635[1], T_1635[0]) node T_1641 = eq(xact.a_type, UInt<3>("h03")) node T_1642 = and(xact.is_builtin_type, T_1641) node T_1644 = eq(xact.a_type, UInt<3>("h02")) node T_1645 = and(xact.is_builtin_type, T_1644) node T_1646 = or(T_1642, T_1645) node T_1647 = bits(xact.union, 16, 1) node T_1649 = mux(T_1646, T_1647, UInt<16>("h00")) node T_1650 = mux(T_1618, T_1639, T_1649) node T_1654 = cat(T_1650, UInt<1>("h01")) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_beat.union := UInt<1>("h00") oacq_write_beat.a_type := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h00") oacq_write_beat.data := UInt<1>("h00") oacq_write_beat.addr_beat := UInt<1>("h00") oacq_write_beat.client_xact_id := UInt<1>("h00") oacq_write_beat.addr_block := UInt<1>("h00") oacq_write_beat.is_builtin_type := UInt<1>("h01") oacq_write_beat.a_type := UInt<3>("h02") oacq_write_beat.client_xact_id := UInt<3>("h07") oacq_write_beat.addr_block := xact.addr_block oacq_write_beat.addr_beat := xact.addr_beat oacq_write_beat.data := data_buffer[0] oacq_write_beat.union := T_1654 infer accessor T_1725 = data_buffer[oacq_data_cnt] node T_1761 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1762 = cat(T_1761, UInt<1>("h01")) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_write_block.union := UInt<1>("h00") oacq_write_block.a_type := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h00") oacq_write_block.data := UInt<1>("h00") oacq_write_block.addr_beat := UInt<1>("h00") oacq_write_block.client_xact_id := UInt<1>("h00") oacq_write_block.addr_block := UInt<1>("h00") oacq_write_block.is_builtin_type := UInt<1>("h01") oacq_write_block.a_type := UInt<3>("h03") oacq_write_block.client_xact_id := UInt<3>("h07") oacq_write_block.addr_block := xact.addr_block oacq_write_block.addr_beat := oacq_data_cnt oacq_write_block.data := T_1725 oacq_write_block.union := T_1762 node T_1833 = bits(xact.union, 12, 9) node T_1834 = bits(xact.union, 8, 6) node T_1838 = cat(T_1833, T_1834) node T_1839 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1840 = cat(T_1838, T_1839) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_beat.union := UInt<1>("h00") oacq_read_beat.a_type := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h00") oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.addr_beat := UInt<1>("h00") oacq_read_beat.client_xact_id := UInt<1>("h00") oacq_read_beat.addr_block := UInt<1>("h00") oacq_read_beat.is_builtin_type := UInt<1>("h01") oacq_read_beat.a_type := UInt<3>("h00") oacq_read_beat.client_xact_id := UInt<3>("h07") oacq_read_beat.addr_block := xact.addr_block oacq_read_beat.addr_beat := xact.addr_beat oacq_read_beat.data := UInt<1>("h00") oacq_read_beat.union := T_1840 node T_1915 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1916 = cat(UInt<3>("h07"), T_1915) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} oacq_read_block.union := UInt<1>("h00") oacq_read_block.a_type := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.client_xact_id := UInt<1>("h00") oacq_read_block.addr_block := UInt<1>("h00") oacq_read_block.is_builtin_type := UInt<1>("h01") oacq_read_block.a_type := UInt<3>("h01") oacq_read_block.client_xact_id := UInt<3>("h07") oacq_read_block.addr_block := xact.addr_block oacq_read_block.addr_beat := UInt<1>("h00") oacq_read_block.data := UInt<1>("h00") oacq_read_block.union := T_1916 io.outer.acquire.valid := UInt<1>("h00") node T_1989 = eq(state, UInt<1>("h01")) node T_1990 = eq(state, UInt<2>("h03")) wire T_2022 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2022 <> oacq_write_block when subblock_type : T_2022 <> oacq_write_beat skip wire T_2084 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2084 <> oacq_read_block when subblock_type : T_2084 <> oacq_read_beat skip wire T_2146 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2146 <> T_2084 when T_1990 : T_2146 <> T_2022 skip wire T_2208 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_2208 <> T_2146 when T_1989 : T_2208 <> oacq_probe skip io.outer.acquire.bits <> T_2208 io.outer.grant.ready := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") node T_2246 = eq(UInt<3>("h04"), xact.a_type) node T_2247 = mux(T_2246, UInt<1>("h00"), UInt<2>("h02")) node T_2248 = eq(UInt<3>("h02"), xact.a_type) node T_2249 = mux(T_2248, UInt<1>("h00"), T_2247) node T_2250 = eq(UInt<3>("h00"), xact.a_type) node T_2251 = mux(T_2250, UInt<2>("h02"), T_2249) node T_2252 = eq(UInt<3>("h03"), xact.a_type) node T_2253 = mux(T_2252, UInt<1>("h00"), T_2251) node T_2254 = eq(UInt<3>("h01"), xact.a_type) node T_2255 = mux(T_2254, UInt<2>("h02"), T_2253) node T_2256 = eq(UInt<1>("h01"), xact.a_type) node T_2257 = mux(T_2256, UInt<1>("h00"), UInt<2>("h02")) node T_2258 = eq(UInt<1>("h00"), xact.a_type) node T_2259 = mux(T_2258, UInt<1>("h01"), T_2257) node T_2260 = mux(xact.is_builtin_type, T_2255, T_2259) wire T_2288 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_2288.client_id := UInt<1>("h00") T_2288.p_type := UInt<1>("h00") T_2288.addr_block := UInt<1>("h00") T_2288.client_id := UInt<1>("h00") T_2288.p_type := T_2260 T_2288.addr_block := xact.addr_block io.inner.probe.bits <> T_2288 io.inner.grant.valid := UInt<1>("h00") node T_2335 = eq(UInt<3>("h05"), xact.a_type) node T_2336 = mux(T_2335, UInt<3>("h01"), UInt<3>("h03")) node T_2337 = eq(UInt<3>("h04"), xact.a_type) node T_2338 = mux(T_2337, UInt<3>("h04"), T_2336) node T_2339 = eq(UInt<3>("h03"), xact.a_type) node T_2340 = mux(T_2339, UInt<3>("h03"), T_2338) node T_2341 = eq(UInt<3>("h02"), xact.a_type) node T_2342 = mux(T_2341, UInt<3>("h03"), T_2340) node T_2343 = eq(UInt<3>("h01"), xact.a_type) node T_2344 = mux(T_2343, UInt<3>("h05"), T_2342) node T_2345 = eq(UInt<3>("h00"), xact.a_type) node T_2346 = mux(T_2345, UInt<3>("h04"), T_2344) node T_2347 = eq(xact.a_type, UInt<1>("h00")) node T_2350 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2351 = mux(T_2350, UInt<1>("h00"), UInt<1>("h01")) node T_2352 = mux(T_2347, T_2351, UInt<1>("h01")) node T_2353 = mux(xact.is_builtin_type, T_2346, T_2352) wire T_2385 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} T_2385.client_id := UInt<1>("h00") T_2385.g_type := UInt<1>("h00") T_2385.is_builtin_type := UInt<1>("h00") T_2385.manager_xact_id := UInt<1>("h00") T_2385.client_xact_id := UInt<1>("h00") T_2385.data := UInt<1>("h00") T_2385.addr_beat := UInt<1>("h00") T_2385.client_id := xact.client_id T_2385.is_builtin_type := xact.is_builtin_type T_2385.g_type := T_2353 T_2385.client_xact_id := xact.client_xact_id T_2385.manager_xact_id := UInt<3>("h07") T_2385.addr_beat := UInt<1>("h00") T_2385.data := UInt<1>("h00") io.inner.grant.bits <> T_2385 io.inner.acquire.ready := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") node T_2426 = neq(state, UInt<1>("h00")) node T_2427 = and(T_2426, collect_iacq_data) node T_2428 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2429 = and(T_2427, T_2428) node T_2430 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_2431 = and(T_2429, T_2430) node T_2433 = eq(T_2431, UInt<1>("h00")) node T_2434 = neq(state, UInt<1>("h00")) node T_2435 = and(T_2434, collect_iacq_data) node T_2436 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2437 = and(T_2435, T_2436) node T_2438 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_2439 = and(T_2437, T_2438) node T_2441 = eq(T_2439, UInt<1>("h00")) node T_2442 = eq(state, UInt<1>("h00")) node T_2443 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_2444 = and(T_2442, T_2443) node T_2446 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_2447 = and(T_2444, T_2446) node T_2449 = eq(T_2447, UInt<1>("h00")) when collect_iacq_data : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : infer accessor T_2451 = data_buffer[io.inner.acquire.bits.addr_beat] T_2451 := io.inner.acquire.bits.data node T_2454 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_2455 = or(iacq_data_valid, T_2454) node T_2456 = not(iacq_data_valid) node T_2457 = or(T_2456, T_2454) node T_2458 = not(T_2457) node T_2459 = mux(UInt<1>("h01"), T_2455, T_2458) iacq_data_valid := T_2459 skip when iacq_data_done : collect_iacq_data := UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready := UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack := UInt<1>("h00") skip skip node T_2463 = eq(UInt<1>("h00"), state) when T_2463 : io.inner.acquire.ready := UInt<1>("h01") when io.inner.acquire.valid : xact <> io.inner.acquire.bits infer accessor T_2466 = data_buffer[UInt<1>("h00")] T_2466 := io.inner.acquire.bits.data node T_2468 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_2471 : UInt<3>[1] T_2471[0] := UInt<3>("h03") node T_2474 = eq(T_2471[0], io.inner.acquire.bits.a_type) node T_2476 = or(UInt<1>("h00"), T_2474) node T_2477 = and(T_2468, T_2476) collect_iacq_data := T_2477 wire T_2482 : UInt<3>[3] T_2482[0] := UInt<3>("h02") T_2482[1] := UInt<3>("h03") T_2482[2] := UInt<3>("h04") node T_2487 = eq(T_2482[0], io.inner.acquire.bits.a_type) node T_2488 = eq(T_2482[1], io.inner.acquire.bits.a_type) node T_2489 = eq(T_2482[2], io.inner.acquire.bits.a_type) node T_2491 = or(UInt<1>("h00"), T_2487) node T_2492 = or(T_2491, T_2488) node T_2493 = or(T_2492, T_2489) node T_2494 = and(io.inner.acquire.bits.is_builtin_type, T_2493) node T_2495 = dshl(T_2494, io.inner.acquire.bits.addr_beat) iacq_data_valid := T_2495 node T_2497 = neq(mask_incoherent, UInt<1>("h00")) when T_2497 : pending_probes := mask_incoherent node T_2498 = bit(mask_incoherent, 0) node T_2499 = bit(mask_incoherent, 1) node T_2500 = bit(mask_incoherent, 2) node T_2501 = bit(mask_incoherent, 3) node T_2503 = cat(UInt<1>("h00"), T_2499) node T_2504 = addw(T_2498, T_2503) node T_2507 = cat(UInt<1>("h00"), T_2501) node T_2508 = addw(T_2500, T_2507) node T_2509 = cat(UInt<1>("h00"), T_2508) node T_2510 = addw(T_2504, T_2509) release_count := T_2510 skip node T_2511 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_2512 = mux(pending_outer_write_, UInt<2>("h03"), T_2511) node T_2513 = mux(T_2497, UInt<1>("h01"), T_2512) state := T_2513 skip skip node T_2514 = eq(UInt<1>("h01"), state) when T_2514 : node T_2516 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid := T_2516 when io.inner.probe.ready : node T_2518 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_2519 = not(T_2518) node T_2520 = and(pending_probes, T_2519) pending_probes := T_2520 skip wire T_2522 : UInt<2>[3] T_2522[0] := UInt<1>("h00") T_2522[1] := UInt<1>("h01") T_2522[2] := UInt<2>("h02") node T_2527 = eq(T_2522[0], io.inner.release.bits.r_type) node T_2528 = eq(T_2522[1], io.inner.release.bits.r_type) node T_2529 = eq(T_2522[2], io.inner.release.bits.r_type) node T_2531 = or(UInt<1>("h00"), T_2527) node T_2532 = or(T_2531, T_2528) node T_2533 = or(T_2532, T_2529) node T_2535 = eq(T_2533, UInt<1>("h00")) node T_2536 = or(T_2535, io.outer.acquire.ready) io.inner.release.ready := T_2536 when io.inner.release.valid : wire T_2538 : UInt<2>[3] T_2538[0] := UInt<1>("h00") T_2538[1] := UInt<1>("h01") T_2538[2] := UInt<2>("h02") node T_2543 = eq(T_2538[0], io.inner.release.bits.r_type) node T_2544 = eq(T_2538[1], io.inner.release.bits.r_type) node T_2545 = eq(T_2538[2], io.inner.release.bits.r_type) node T_2547 = or(UInt<1>("h00"), T_2543) node T_2548 = or(T_2547, T_2544) node T_2549 = or(T_2548, T_2545) when T_2549 : io.outer.acquire.valid := UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2553 = subw(release_count, UInt<1>("h01")) release_count := T_2553 node T_2555 = eq(release_count, UInt<1>("h01")) when T_2555 : node T_2556 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2557 = mux(pending_outer_write, UInt<2>("h03"), T_2556) state := T_2557 skip skip skip skip else : node T_2559 = subw(release_count, UInt<1>("h01")) release_count := T_2559 node T_2561 = eq(release_count, UInt<1>("h01")) when T_2561 : node T_2562 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_2563 = mux(pending_outer_write, UInt<2>("h03"), T_2562) state := T_2563 skip skip skip skip node T_2564 = eq(UInt<2>("h03"), state) when T_2564 : node T_2566 = eq(pending_ognt_ack, UInt<1>("h00")) node T_2568 = eq(collect_iacq_data, UInt<1>("h00")) node T_2569 = or(T_2566, T_2568) node T_2570 = dshr(iacq_data_valid, oacq_data_cnt) node T_2571 = bit(T_2570, 0) node T_2572 = or(T_2569, T_2571) io.outer.acquire.valid := T_2572 when oacq_data_done : pending_ognt_ack := UInt<1>("h01") node T_2574 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state := T_2574 skip skip node T_2575 = eq(UInt<2>("h02"), state) when T_2575 : node T_2577 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid := T_2577 node T_2578 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_2578 : state := UInt<3>("h05") skip skip node T_2579 = eq(UInt<3>("h05"), state) when T_2579 : io.outer.grant.ready := io.inner.grant.ready io.inner.grant.valid := io.outer.grant.valid when ignt_data_done : node T_2582 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2584 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2585 = and(io.inner.grant.bits.is_builtin_type, T_2584) node T_2587 = eq(T_2585, UInt<1>("h00")) node T_2588 = and(T_2582, T_2587) node T_2589 = mux(T_2588, UInt<3>("h06"), UInt<1>("h00")) state := T_2589 skip skip node T_2590 = eq(UInt<3>("h04"), state) when T_2590 : io.inner.grant.valid := UInt<1>("h01") when io.inner.grant.ready : node T_2594 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_2596 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_2597 = and(io.inner.grant.bits.is_builtin_type, T_2596) node T_2599 = eq(T_2597, UInt<1>("h00")) node T_2600 = and(T_2594, T_2599) node T_2601 = mux(T_2600, UInt<3>("h06"), UInt<1>("h00")) state := T_2601 skip skip node T_2602 = eq(UInt<3>("h06"), state) when T_2602 : io.inner.finish.ready := UInt<1>("h01") when io.inner.finish.valid : state := UInt<1>("h00") skip skip module LockingRRArbiter_33 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, chosen : UInt<3>} io.chosen := UInt<1>("h00") io.out.bits.client_id := UInt<1>("h00") io.out.bits.g_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.manager_xact_id := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") io.in[4].ready := UInt<1>("h00") io.in[5].ready := UInt<1>("h00") io.in[6].ready := UInt<1>("h00") io.in[7].ready := UInt<1>("h00") reg T_1502 : UInt<1>, clock, reset onreset T_1502 := UInt<1>("h00") reg T_1504 : UInt, clock, reset onreset T_1504 := UInt<3>("h07") wire T_1506 : UInt<3> T_1506 := UInt<1>("h00") infer accessor T_1508 = io.in[T_1506] io.out.valid := T_1508.valid infer accessor T_1573 = io.in[T_1506] io.out.bits <> T_1573.bits io.chosen := T_1506 infer accessor T_1638 = io.in[T_1506] T_1638.ready := UInt<1>("h00") reg last_grant : UInt<3>, clock, reset onreset last_grant := UInt<3>("h00") node T_1707 = gt(UInt<1>("h00"), last_grant) node T_1708 = and(io.in[0].valid, T_1707) node T_1710 = gt(UInt<1>("h01"), last_grant) node T_1711 = and(io.in[1].valid, T_1710) node T_1713 = gt(UInt<2>("h02"), last_grant) node T_1714 = and(io.in[2].valid, T_1713) node T_1716 = gt(UInt<2>("h03"), last_grant) node T_1717 = and(io.in[3].valid, T_1716) node T_1719 = gt(UInt<3>("h04"), last_grant) node T_1720 = and(io.in[4].valid, T_1719) node T_1722 = gt(UInt<3>("h05"), last_grant) node T_1723 = and(io.in[5].valid, T_1722) node T_1725 = gt(UInt<3>("h06"), last_grant) node T_1726 = and(io.in[6].valid, T_1725) node T_1728 = gt(UInt<3>("h07"), last_grant) node T_1729 = and(io.in[7].valid, T_1728) node T_1732 = or(UInt<1>("h00"), T_1708) node T_1734 = eq(T_1732, UInt<1>("h00")) node T_1736 = or(UInt<1>("h00"), T_1708) node T_1737 = or(T_1736, T_1711) node T_1739 = eq(T_1737, UInt<1>("h00")) node T_1741 = or(UInt<1>("h00"), T_1708) node T_1742 = or(T_1741, T_1711) node T_1743 = or(T_1742, T_1714) node T_1745 = eq(T_1743, UInt<1>("h00")) node T_1747 = or(UInt<1>("h00"), T_1708) node T_1748 = or(T_1747, T_1711) node T_1749 = or(T_1748, T_1714) node T_1750 = or(T_1749, T_1717) node T_1752 = eq(T_1750, UInt<1>("h00")) node T_1754 = or(UInt<1>("h00"), T_1708) node T_1755 = or(T_1754, T_1711) node T_1756 = or(T_1755, T_1714) node T_1757 = or(T_1756, T_1717) node T_1758 = or(T_1757, T_1720) node T_1760 = eq(T_1758, UInt<1>("h00")) node T_1762 = or(UInt<1>("h00"), T_1708) node T_1763 = or(T_1762, T_1711) node T_1764 = or(T_1763, T_1714) node T_1765 = or(T_1764, T_1717) node T_1766 = or(T_1765, T_1720) node T_1767 = or(T_1766, T_1723) node T_1769 = eq(T_1767, UInt<1>("h00")) node T_1771 = or(UInt<1>("h00"), T_1708) node T_1772 = or(T_1771, T_1711) node T_1773 = or(T_1772, T_1714) node T_1774 = or(T_1773, T_1717) node T_1775 = or(T_1774, T_1720) node T_1776 = or(T_1775, T_1723) node T_1777 = or(T_1776, T_1726) node T_1779 = eq(T_1777, UInt<1>("h00")) node T_1781 = or(UInt<1>("h00"), T_1708) node T_1782 = or(T_1781, T_1711) node T_1783 = or(T_1782, T_1714) node T_1784 = or(T_1783, T_1717) node T_1785 = or(T_1784, T_1720) node T_1786 = or(T_1785, T_1723) node T_1787 = or(T_1786, T_1726) node T_1788 = or(T_1787, T_1729) node T_1790 = eq(T_1788, UInt<1>("h00")) node T_1792 = or(UInt<1>("h00"), T_1708) node T_1793 = or(T_1792, T_1711) node T_1794 = or(T_1793, T_1714) node T_1795 = or(T_1794, T_1717) node T_1796 = or(T_1795, T_1720) node T_1797 = or(T_1796, T_1723) node T_1798 = or(T_1797, T_1726) node T_1799 = or(T_1798, T_1729) node T_1800 = or(T_1799, io.in[0].valid) node T_1802 = eq(T_1800, UInt<1>("h00")) node T_1804 = or(UInt<1>("h00"), T_1708) node T_1805 = or(T_1804, T_1711) node T_1806 = or(T_1805, T_1714) node T_1807 = or(T_1806, T_1717) node T_1808 = or(T_1807, T_1720) node T_1809 = or(T_1808, T_1723) node T_1810 = or(T_1809, T_1726) node T_1811 = or(T_1810, T_1729) node T_1812 = or(T_1811, io.in[0].valid) node T_1813 = or(T_1812, io.in[1].valid) node T_1815 = eq(T_1813, UInt<1>("h00")) node T_1817 = or(UInt<1>("h00"), T_1708) node T_1818 = or(T_1817, T_1711) node T_1819 = or(T_1818, T_1714) node T_1820 = or(T_1819, T_1717) node T_1821 = or(T_1820, T_1720) node T_1822 = or(T_1821, T_1723) node T_1823 = or(T_1822, T_1726) node T_1824 = or(T_1823, T_1729) node T_1825 = or(T_1824, io.in[0].valid) node T_1826 = or(T_1825, io.in[1].valid) node T_1827 = or(T_1826, io.in[2].valid) node T_1829 = eq(T_1827, UInt<1>("h00")) node T_1831 = or(UInt<1>("h00"), T_1708) node T_1832 = or(T_1831, T_1711) node T_1833 = or(T_1832, T_1714) node T_1834 = or(T_1833, T_1717) node T_1835 = or(T_1834, T_1720) node T_1836 = or(T_1835, T_1723) node T_1837 = or(T_1836, T_1726) node T_1838 = or(T_1837, T_1729) node T_1839 = or(T_1838, io.in[0].valid) node T_1840 = or(T_1839, io.in[1].valid) node T_1841 = or(T_1840, io.in[2].valid) node T_1842 = or(T_1841, io.in[3].valid) node T_1844 = eq(T_1842, UInt<1>("h00")) node T_1846 = or(UInt<1>("h00"), T_1708) node T_1847 = or(T_1846, T_1711) node T_1848 = or(T_1847, T_1714) node T_1849 = or(T_1848, T_1717) node T_1850 = or(T_1849, T_1720) node T_1851 = or(T_1850, T_1723) node T_1852 = or(T_1851, T_1726) node T_1853 = or(T_1852, T_1729) node T_1854 = or(T_1853, io.in[0].valid) node T_1855 = or(T_1854, io.in[1].valid) node T_1856 = or(T_1855, io.in[2].valid) node T_1857 = or(T_1856, io.in[3].valid) node T_1858 = or(T_1857, io.in[4].valid) node T_1860 = eq(T_1858, UInt<1>("h00")) node T_1862 = or(UInt<1>("h00"), T_1708) node T_1863 = or(T_1862, T_1711) node T_1864 = or(T_1863, T_1714) node T_1865 = or(T_1864, T_1717) node T_1866 = or(T_1865, T_1720) node T_1867 = or(T_1866, T_1723) node T_1868 = or(T_1867, T_1726) node T_1869 = or(T_1868, T_1729) node T_1870 = or(T_1869, io.in[0].valid) node T_1871 = or(T_1870, io.in[1].valid) node T_1872 = or(T_1871, io.in[2].valid) node T_1873 = or(T_1872, io.in[3].valid) node T_1874 = or(T_1873, io.in[4].valid) node T_1875 = or(T_1874, io.in[5].valid) node T_1877 = eq(T_1875, UInt<1>("h00")) node T_1879 = or(UInt<1>("h00"), T_1708) node T_1880 = or(T_1879, T_1711) node T_1881 = or(T_1880, T_1714) node T_1882 = or(T_1881, T_1717) node T_1883 = or(T_1882, T_1720) node T_1884 = or(T_1883, T_1723) node T_1885 = or(T_1884, T_1726) node T_1886 = or(T_1885, T_1729) node T_1887 = or(T_1886, io.in[0].valid) node T_1888 = or(T_1887, io.in[1].valid) node T_1889 = or(T_1888, io.in[2].valid) node T_1890 = or(T_1889, io.in[3].valid) node T_1891 = or(T_1890, io.in[4].valid) node T_1892 = or(T_1891, io.in[5].valid) node T_1893 = or(T_1892, io.in[6].valid) node T_1895 = eq(T_1893, UInt<1>("h00")) node T_1897 = gt(UInt<1>("h00"), last_grant) node T_1898 = and(UInt<1>("h01"), T_1897) node T_1899 = or(T_1898, T_1790) node T_1901 = gt(UInt<1>("h01"), last_grant) node T_1902 = and(T_1734, T_1901) node T_1903 = or(T_1902, T_1802) node T_1905 = gt(UInt<2>("h02"), last_grant) node T_1906 = and(T_1739, T_1905) node T_1907 = or(T_1906, T_1815) node T_1909 = gt(UInt<2>("h03"), last_grant) node T_1910 = and(T_1745, T_1909) node T_1911 = or(T_1910, T_1829) node T_1913 = gt(UInt<3>("h04"), last_grant) node T_1914 = and(T_1752, T_1913) node T_1915 = or(T_1914, T_1844) node T_1917 = gt(UInt<3>("h05"), last_grant) node T_1918 = and(T_1760, T_1917) node T_1919 = or(T_1918, T_1860) node T_1921 = gt(UInt<3>("h06"), last_grant) node T_1922 = and(T_1769, T_1921) node T_1923 = or(T_1922, T_1877) node T_1925 = gt(UInt<3>("h07"), last_grant) node T_1926 = and(T_1779, T_1925) node T_1927 = or(T_1926, T_1895) node T_1929 = eq(T_1504, UInt<1>("h00")) node T_1930 = mux(T_1502, T_1929, T_1899) node T_1931 = and(T_1930, io.out.ready) io.in[0].ready := T_1931 node T_1933 = eq(T_1504, UInt<1>("h01")) node T_1934 = mux(T_1502, T_1933, T_1903) node T_1935 = and(T_1934, io.out.ready) io.in[1].ready := T_1935 node T_1937 = eq(T_1504, UInt<2>("h02")) node T_1938 = mux(T_1502, T_1937, T_1907) node T_1939 = and(T_1938, io.out.ready) io.in[2].ready := T_1939 node T_1941 = eq(T_1504, UInt<2>("h03")) node T_1942 = mux(T_1502, T_1941, T_1911) node T_1943 = and(T_1942, io.out.ready) io.in[3].ready := T_1943 node T_1945 = eq(T_1504, UInt<3>("h04")) node T_1946 = mux(T_1502, T_1945, T_1915) node T_1947 = and(T_1946, io.out.ready) io.in[4].ready := T_1947 node T_1949 = eq(T_1504, UInt<3>("h05")) node T_1950 = mux(T_1502, T_1949, T_1919) node T_1951 = and(T_1950, io.out.ready) io.in[5].ready := T_1951 node T_1953 = eq(T_1504, UInt<3>("h06")) node T_1954 = mux(T_1502, T_1953, T_1923) node T_1955 = and(T_1954, io.out.ready) io.in[6].ready := T_1955 node T_1957 = eq(T_1504, UInt<3>("h07")) node T_1958 = mux(T_1502, T_1957, T_1927) node T_1959 = and(T_1958, io.out.ready) io.in[7].ready := T_1959 reg T_1961 : UInt<2>, clock, reset onreset T_1961 := UInt<2>("h00") node T_1963 = addw(T_1961, UInt<1>("h01")) node T_1964 = and(io.out.ready, io.out.valid) when T_1964 : wire T_1968 : UInt<3>[1] T_1968[0] := UInt<3>("h05") node T_1971 = eq(T_1968[0], io.out.bits.g_type) node T_1973 = or(UInt<1>("h00"), T_1971) wire T_1975 : UInt<1>[2] T_1975[0] := UInt<1>("h00") T_1975[1] := UInt<1>("h01") node T_1979 = eq(T_1975[0], io.out.bits.g_type) node T_1980 = eq(T_1975[1], io.out.bits.g_type) node T_1982 = or(UInt<1>("h00"), T_1979) node T_1983 = or(T_1982, T_1980) node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983) node T_1985 = and(UInt<1>("h01"), T_1984) when T_1985 : T_1961 := T_1963 node T_1987 = eq(T_1502, UInt<1>("h00")) when T_1987 : T_1502 := UInt<1>("h01") node T_1989 = and(io.in[0].ready, io.in[0].valid) node T_1990 = and(io.in[1].ready, io.in[1].valid) node T_1991 = and(io.in[2].ready, io.in[2].valid) node T_1992 = and(io.in[3].ready, io.in[3].valid) node T_1993 = and(io.in[4].ready, io.in[4].valid) node T_1994 = and(io.in[5].ready, io.in[5].valid) node T_1995 = and(io.in[6].ready, io.in[6].valid) node T_1996 = and(io.in[7].ready, io.in[7].valid) wire T_1998 : UInt<1>[8] T_1998[0] := T_1989 T_1998[1] := T_1990 T_1998[2] := T_1991 T_1998[3] := T_1992 T_1998[4] := T_1993 T_1998[5] := T_1994 T_1998[6] := T_1995 T_1998[7] := T_1996 node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07")) node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016) node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017) node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018) node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019) node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020) node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021) T_1504 := T_2022 skip skip node T_2024 = eq(T_1963, UInt<1>("h00")) when T_2024 : T_1502 := UInt<1>("h00") skip skip node T_2028 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_2030 = mux(io.in[5].valid, UInt<3>("h05"), T_2028) node T_2032 = mux(io.in[4].valid, UInt<3>("h04"), T_2030) node T_2034 = mux(io.in[3].valid, UInt<2>("h03"), T_2032) node T_2036 = mux(io.in[2].valid, UInt<2>("h02"), T_2034) node T_2038 = mux(io.in[1].valid, UInt<1>("h01"), T_2036) node T_2040 = mux(io.in[0].valid, UInt<1>("h00"), T_2038) node T_2042 = gt(UInt<3>("h07"), last_grant) node T_2043 = and(io.in[7].valid, T_2042) node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040) node T_2047 = gt(UInt<3>("h06"), last_grant) node T_2048 = and(io.in[6].valid, T_2047) node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045) node T_2052 = gt(UInt<3>("h05"), last_grant) node T_2053 = and(io.in[5].valid, T_2052) node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050) node T_2057 = gt(UInt<3>("h04"), last_grant) node T_2058 = and(io.in[4].valid, T_2057) node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055) node T_2062 = gt(UInt<2>("h03"), last_grant) node T_2063 = and(io.in[3].valid, T_2062) node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060) node T_2067 = gt(UInt<2>("h02"), last_grant) node T_2068 = and(io.in[2].valid, T_2067) node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065) node T_2072 = gt(UInt<1>("h01"), last_grant) node T_2073 = and(io.in[1].valid, T_2072) node choose = mux(T_2073, UInt<1>("h01"), T_2070) node T_2076 = mux(T_1502, T_1504, choose) T_1506 := T_2076 node T_2077 = and(io.out.ready, io.out.valid) when T_2077 : last_grant := T_1506 skip module LockingRRArbiter_34 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>} io.chosen := UInt<1>("h00") io.out.bits.client_id := UInt<1>("h00") io.out.bits.p_type := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") io.in[4].ready := UInt<1>("h00") io.in[5].ready := UInt<1>("h00") io.in[6].ready := UInt<1>("h00") io.in[7].ready := UInt<1>("h00") reg T_1318 : UInt<1>, clock, reset onreset T_1318 := UInt<1>("h00") reg T_1320 : UInt, clock, reset onreset T_1320 := UInt<3>("h07") wire T_1322 : UInt<3> T_1322 := UInt<1>("h00") infer accessor T_1324 = io.in[T_1322] io.out.valid := T_1324.valid infer accessor T_1381 = io.in[T_1322] io.out.bits <> T_1381.bits io.chosen := T_1322 infer accessor T_1438 = io.in[T_1322] T_1438.ready := UInt<1>("h00") reg last_grant : UInt<3>, clock, reset onreset last_grant := UInt<3>("h00") node T_1499 = gt(UInt<1>("h00"), last_grant) node T_1500 = and(io.in[0].valid, T_1499) node T_1502 = gt(UInt<1>("h01"), last_grant) node T_1503 = and(io.in[1].valid, T_1502) node T_1505 = gt(UInt<2>("h02"), last_grant) node T_1506 = and(io.in[2].valid, T_1505) node T_1508 = gt(UInt<2>("h03"), last_grant) node T_1509 = and(io.in[3].valid, T_1508) node T_1511 = gt(UInt<3>("h04"), last_grant) node T_1512 = and(io.in[4].valid, T_1511) node T_1514 = gt(UInt<3>("h05"), last_grant) node T_1515 = and(io.in[5].valid, T_1514) node T_1517 = gt(UInt<3>("h06"), last_grant) node T_1518 = and(io.in[6].valid, T_1517) node T_1520 = gt(UInt<3>("h07"), last_grant) node T_1521 = and(io.in[7].valid, T_1520) node T_1524 = or(UInt<1>("h00"), T_1500) node T_1526 = eq(T_1524, UInt<1>("h00")) node T_1528 = or(UInt<1>("h00"), T_1500) node T_1529 = or(T_1528, T_1503) node T_1531 = eq(T_1529, UInt<1>("h00")) node T_1533 = or(UInt<1>("h00"), T_1500) node T_1534 = or(T_1533, T_1503) node T_1535 = or(T_1534, T_1506) node T_1537 = eq(T_1535, UInt<1>("h00")) node T_1539 = or(UInt<1>("h00"), T_1500) node T_1540 = or(T_1539, T_1503) node T_1541 = or(T_1540, T_1506) node T_1542 = or(T_1541, T_1509) node T_1544 = eq(T_1542, UInt<1>("h00")) node T_1546 = or(UInt<1>("h00"), T_1500) node T_1547 = or(T_1546, T_1503) node T_1548 = or(T_1547, T_1506) node T_1549 = or(T_1548, T_1509) node T_1550 = or(T_1549, T_1512) node T_1552 = eq(T_1550, UInt<1>("h00")) node T_1554 = or(UInt<1>("h00"), T_1500) node T_1555 = or(T_1554, T_1503) node T_1556 = or(T_1555, T_1506) node T_1557 = or(T_1556, T_1509) node T_1558 = or(T_1557, T_1512) node T_1559 = or(T_1558, T_1515) node T_1561 = eq(T_1559, UInt<1>("h00")) node T_1563 = or(UInt<1>("h00"), T_1500) node T_1564 = or(T_1563, T_1503) node T_1565 = or(T_1564, T_1506) node T_1566 = or(T_1565, T_1509) node T_1567 = or(T_1566, T_1512) node T_1568 = or(T_1567, T_1515) node T_1569 = or(T_1568, T_1518) node T_1571 = eq(T_1569, UInt<1>("h00")) node T_1573 = or(UInt<1>("h00"), T_1500) node T_1574 = or(T_1573, T_1503) node T_1575 = or(T_1574, T_1506) node T_1576 = or(T_1575, T_1509) node T_1577 = or(T_1576, T_1512) node T_1578 = or(T_1577, T_1515) node T_1579 = or(T_1578, T_1518) node T_1580 = or(T_1579, T_1521) node T_1582 = eq(T_1580, UInt<1>("h00")) node T_1584 = or(UInt<1>("h00"), T_1500) node T_1585 = or(T_1584, T_1503) node T_1586 = or(T_1585, T_1506) node T_1587 = or(T_1586, T_1509) node T_1588 = or(T_1587, T_1512) node T_1589 = or(T_1588, T_1515) node T_1590 = or(T_1589, T_1518) node T_1591 = or(T_1590, T_1521) node T_1592 = or(T_1591, io.in[0].valid) node T_1594 = eq(T_1592, UInt<1>("h00")) node T_1596 = or(UInt<1>("h00"), T_1500) node T_1597 = or(T_1596, T_1503) node T_1598 = or(T_1597, T_1506) node T_1599 = or(T_1598, T_1509) node T_1600 = or(T_1599, T_1512) node T_1601 = or(T_1600, T_1515) node T_1602 = or(T_1601, T_1518) node T_1603 = or(T_1602, T_1521) node T_1604 = or(T_1603, io.in[0].valid) node T_1605 = or(T_1604, io.in[1].valid) node T_1607 = eq(T_1605, UInt<1>("h00")) node T_1609 = or(UInt<1>("h00"), T_1500) node T_1610 = or(T_1609, T_1503) node T_1611 = or(T_1610, T_1506) node T_1612 = or(T_1611, T_1509) node T_1613 = or(T_1612, T_1512) node T_1614 = or(T_1613, T_1515) node T_1615 = or(T_1614, T_1518) node T_1616 = or(T_1615, T_1521) node T_1617 = or(T_1616, io.in[0].valid) node T_1618 = or(T_1617, io.in[1].valid) node T_1619 = or(T_1618, io.in[2].valid) node T_1621 = eq(T_1619, UInt<1>("h00")) node T_1623 = or(UInt<1>("h00"), T_1500) node T_1624 = or(T_1623, T_1503) node T_1625 = or(T_1624, T_1506) node T_1626 = or(T_1625, T_1509) node T_1627 = or(T_1626, T_1512) node T_1628 = or(T_1627, T_1515) node T_1629 = or(T_1628, T_1518) node T_1630 = or(T_1629, T_1521) node T_1631 = or(T_1630, io.in[0].valid) node T_1632 = or(T_1631, io.in[1].valid) node T_1633 = or(T_1632, io.in[2].valid) node T_1634 = or(T_1633, io.in[3].valid) node T_1636 = eq(T_1634, UInt<1>("h00")) node T_1638 = or(UInt<1>("h00"), T_1500) node T_1639 = or(T_1638, T_1503) node T_1640 = or(T_1639, T_1506) node T_1641 = or(T_1640, T_1509) node T_1642 = or(T_1641, T_1512) node T_1643 = or(T_1642, T_1515) node T_1644 = or(T_1643, T_1518) node T_1645 = or(T_1644, T_1521) node T_1646 = or(T_1645, io.in[0].valid) node T_1647 = or(T_1646, io.in[1].valid) node T_1648 = or(T_1647, io.in[2].valid) node T_1649 = or(T_1648, io.in[3].valid) node T_1650 = or(T_1649, io.in[4].valid) node T_1652 = eq(T_1650, UInt<1>("h00")) node T_1654 = or(UInt<1>("h00"), T_1500) node T_1655 = or(T_1654, T_1503) node T_1656 = or(T_1655, T_1506) node T_1657 = or(T_1656, T_1509) node T_1658 = or(T_1657, T_1512) node T_1659 = or(T_1658, T_1515) node T_1660 = or(T_1659, T_1518) node T_1661 = or(T_1660, T_1521) node T_1662 = or(T_1661, io.in[0].valid) node T_1663 = or(T_1662, io.in[1].valid) node T_1664 = or(T_1663, io.in[2].valid) node T_1665 = or(T_1664, io.in[3].valid) node T_1666 = or(T_1665, io.in[4].valid) node T_1667 = or(T_1666, io.in[5].valid) node T_1669 = eq(T_1667, UInt<1>("h00")) node T_1671 = or(UInt<1>("h00"), T_1500) node T_1672 = or(T_1671, T_1503) node T_1673 = or(T_1672, T_1506) node T_1674 = or(T_1673, T_1509) node T_1675 = or(T_1674, T_1512) node T_1676 = or(T_1675, T_1515) node T_1677 = or(T_1676, T_1518) node T_1678 = or(T_1677, T_1521) node T_1679 = or(T_1678, io.in[0].valid) node T_1680 = or(T_1679, io.in[1].valid) node T_1681 = or(T_1680, io.in[2].valid) node T_1682 = or(T_1681, io.in[3].valid) node T_1683 = or(T_1682, io.in[4].valid) node T_1684 = or(T_1683, io.in[5].valid) node T_1685 = or(T_1684, io.in[6].valid) node T_1687 = eq(T_1685, UInt<1>("h00")) node T_1689 = gt(UInt<1>("h00"), last_grant) node T_1690 = and(UInt<1>("h01"), T_1689) node T_1691 = or(T_1690, T_1582) node T_1693 = gt(UInt<1>("h01"), last_grant) node T_1694 = and(T_1526, T_1693) node T_1695 = or(T_1694, T_1594) node T_1697 = gt(UInt<2>("h02"), last_grant) node T_1698 = and(T_1531, T_1697) node T_1699 = or(T_1698, T_1607) node T_1701 = gt(UInt<2>("h03"), last_grant) node T_1702 = and(T_1537, T_1701) node T_1703 = or(T_1702, T_1621) node T_1705 = gt(UInt<3>("h04"), last_grant) node T_1706 = and(T_1544, T_1705) node T_1707 = or(T_1706, T_1636) node T_1709 = gt(UInt<3>("h05"), last_grant) node T_1710 = and(T_1552, T_1709) node T_1711 = or(T_1710, T_1652) node T_1713 = gt(UInt<3>("h06"), last_grant) node T_1714 = and(T_1561, T_1713) node T_1715 = or(T_1714, T_1669) node T_1717 = gt(UInt<3>("h07"), last_grant) node T_1718 = and(T_1571, T_1717) node T_1719 = or(T_1718, T_1687) node T_1721 = eq(T_1320, UInt<1>("h00")) node T_1722 = mux(T_1318, T_1721, T_1691) node T_1723 = and(T_1722, io.out.ready) io.in[0].ready := T_1723 node T_1725 = eq(T_1320, UInt<1>("h01")) node T_1726 = mux(T_1318, T_1725, T_1695) node T_1727 = and(T_1726, io.out.ready) io.in[1].ready := T_1727 node T_1729 = eq(T_1320, UInt<2>("h02")) node T_1730 = mux(T_1318, T_1729, T_1699) node T_1731 = and(T_1730, io.out.ready) io.in[2].ready := T_1731 node T_1733 = eq(T_1320, UInt<2>("h03")) node T_1734 = mux(T_1318, T_1733, T_1703) node T_1735 = and(T_1734, io.out.ready) io.in[3].ready := T_1735 node T_1737 = eq(T_1320, UInt<3>("h04")) node T_1738 = mux(T_1318, T_1737, T_1707) node T_1739 = and(T_1738, io.out.ready) io.in[4].ready := T_1739 node T_1741 = eq(T_1320, UInt<3>("h05")) node T_1742 = mux(T_1318, T_1741, T_1711) node T_1743 = and(T_1742, io.out.ready) io.in[5].ready := T_1743 node T_1745 = eq(T_1320, UInt<3>("h06")) node T_1746 = mux(T_1318, T_1745, T_1715) node T_1747 = and(T_1746, io.out.ready) io.in[6].ready := T_1747 node T_1749 = eq(T_1320, UInt<3>("h07")) node T_1750 = mux(T_1318, T_1749, T_1719) node T_1751 = and(T_1750, io.out.ready) io.in[7].ready := T_1751 reg T_1753 : UInt<2>, clock, reset onreset T_1753 := UInt<2>("h00") node T_1755 = addw(T_1753, UInt<1>("h01")) node T_1756 = and(io.out.ready, io.out.valid) when T_1756 : when UInt<1>("h00") : T_1753 := T_1755 node T_1759 = eq(T_1318, UInt<1>("h00")) when T_1759 : T_1318 := UInt<1>("h01") node T_1761 = and(io.in[0].ready, io.in[0].valid) node T_1762 = and(io.in[1].ready, io.in[1].valid) node T_1763 = and(io.in[2].ready, io.in[2].valid) node T_1764 = and(io.in[3].ready, io.in[3].valid) node T_1765 = and(io.in[4].ready, io.in[4].valid) node T_1766 = and(io.in[5].ready, io.in[5].valid) node T_1767 = and(io.in[6].ready, io.in[6].valid) node T_1768 = and(io.in[7].ready, io.in[7].valid) wire T_1770 : UInt<1>[8] T_1770[0] := T_1761 T_1770[1] := T_1762 T_1770[2] := T_1763 T_1770[3] := T_1764 T_1770[4] := T_1765 T_1770[5] := T_1766 T_1770[6] := T_1767 T_1770[7] := T_1768 node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07")) node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788) node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789) node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790) node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791) node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792) node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793) T_1320 := T_1794 skip skip node T_1796 = eq(T_1755, UInt<1>("h00")) when T_1796 : T_1318 := UInt<1>("h00") skip skip node T_1800 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_1802 = mux(io.in[5].valid, UInt<3>("h05"), T_1800) node T_1804 = mux(io.in[4].valid, UInt<3>("h04"), T_1802) node T_1806 = mux(io.in[3].valid, UInt<2>("h03"), T_1804) node T_1808 = mux(io.in[2].valid, UInt<2>("h02"), T_1806) node T_1810 = mux(io.in[1].valid, UInt<1>("h01"), T_1808) node T_1812 = mux(io.in[0].valid, UInt<1>("h00"), T_1810) node T_1814 = gt(UInt<3>("h07"), last_grant) node T_1815 = and(io.in[7].valid, T_1814) node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812) node T_1819 = gt(UInt<3>("h06"), last_grant) node T_1820 = and(io.in[6].valid, T_1819) node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817) node T_1824 = gt(UInt<3>("h05"), last_grant) node T_1825 = and(io.in[5].valid, T_1824) node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822) node T_1829 = gt(UInt<3>("h04"), last_grant) node T_1830 = and(io.in[4].valid, T_1829) node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827) node T_1834 = gt(UInt<2>("h03"), last_grant) node T_1835 = and(io.in[3].valid, T_1834) node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832) node T_1839 = gt(UInt<2>("h02"), last_grant) node T_1840 = and(io.in[2].valid, T_1839) node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837) node T_1844 = gt(UInt<1>("h01"), last_grant) node T_1845 = and(io.in[1].valid, T_1844) node choose = mux(T_1845, UInt<1>("h01"), T_1842) node T_1848 = mux(T_1318, T_1320, choose) T_1322 := T_1848 node T_1849 = and(io.out.ready, io.out.valid) when T_1849 : last_grant := T_1322 skip module LockingRRArbiter_35 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, chosen : UInt<3>} io.chosen := UInt<1>("h00") io.out.bits.union := UInt<1>("h00") io.out.bits.a_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") io.in[4].ready := UInt<1>("h00") io.in[5].ready := UInt<1>("h00") io.in[6].ready := UInt<1>("h00") io.in[7].ready := UInt<1>("h00") reg T_1364 : UInt<1>, clock, reset onreset T_1364 := UInt<1>("h00") reg T_1366 : UInt, clock, reset onreset T_1366 := UInt<3>("h07") wire T_1368 : UInt<3> T_1368 := UInt<1>("h00") infer accessor T_1370 = io.in[T_1368] io.out.valid := T_1370.valid infer accessor T_1429 = io.in[T_1368] io.out.bits <> T_1429.bits io.chosen := T_1368 infer accessor T_1488 = io.in[T_1368] T_1488.ready := UInt<1>("h00") reg last_grant : UInt<3>, clock, reset onreset last_grant := UInt<3>("h00") node T_1551 = gt(UInt<1>("h00"), last_grant) node T_1552 = and(io.in[0].valid, T_1551) node T_1554 = gt(UInt<1>("h01"), last_grant) node T_1555 = and(io.in[1].valid, T_1554) node T_1557 = gt(UInt<2>("h02"), last_grant) node T_1558 = and(io.in[2].valid, T_1557) node T_1560 = gt(UInt<2>("h03"), last_grant) node T_1561 = and(io.in[3].valid, T_1560) node T_1563 = gt(UInt<3>("h04"), last_grant) node T_1564 = and(io.in[4].valid, T_1563) node T_1566 = gt(UInt<3>("h05"), last_grant) node T_1567 = and(io.in[5].valid, T_1566) node T_1569 = gt(UInt<3>("h06"), last_grant) node T_1570 = and(io.in[6].valid, T_1569) node T_1572 = gt(UInt<3>("h07"), last_grant) node T_1573 = and(io.in[7].valid, T_1572) node T_1576 = or(UInt<1>("h00"), T_1552) node T_1578 = eq(T_1576, UInt<1>("h00")) node T_1580 = or(UInt<1>("h00"), T_1552) node T_1581 = or(T_1580, T_1555) node T_1583 = eq(T_1581, UInt<1>("h00")) node T_1585 = or(UInt<1>("h00"), T_1552) node T_1586 = or(T_1585, T_1555) node T_1587 = or(T_1586, T_1558) node T_1589 = eq(T_1587, UInt<1>("h00")) node T_1591 = or(UInt<1>("h00"), T_1552) node T_1592 = or(T_1591, T_1555) node T_1593 = or(T_1592, T_1558) node T_1594 = or(T_1593, T_1561) node T_1596 = eq(T_1594, UInt<1>("h00")) node T_1598 = or(UInt<1>("h00"), T_1552) node T_1599 = or(T_1598, T_1555) node T_1600 = or(T_1599, T_1558) node T_1601 = or(T_1600, T_1561) node T_1602 = or(T_1601, T_1564) node T_1604 = eq(T_1602, UInt<1>("h00")) node T_1606 = or(UInt<1>("h00"), T_1552) node T_1607 = or(T_1606, T_1555) node T_1608 = or(T_1607, T_1558) node T_1609 = or(T_1608, T_1561) node T_1610 = or(T_1609, T_1564) node T_1611 = or(T_1610, T_1567) node T_1613 = eq(T_1611, UInt<1>("h00")) node T_1615 = or(UInt<1>("h00"), T_1552) node T_1616 = or(T_1615, T_1555) node T_1617 = or(T_1616, T_1558) node T_1618 = or(T_1617, T_1561) node T_1619 = or(T_1618, T_1564) node T_1620 = or(T_1619, T_1567) node T_1621 = or(T_1620, T_1570) node T_1623 = eq(T_1621, UInt<1>("h00")) node T_1625 = or(UInt<1>("h00"), T_1552) node T_1626 = or(T_1625, T_1555) node T_1627 = or(T_1626, T_1558) node T_1628 = or(T_1627, T_1561) node T_1629 = or(T_1628, T_1564) node T_1630 = or(T_1629, T_1567) node T_1631 = or(T_1630, T_1570) node T_1632 = or(T_1631, T_1573) node T_1634 = eq(T_1632, UInt<1>("h00")) node T_1636 = or(UInt<1>("h00"), T_1552) node T_1637 = or(T_1636, T_1555) node T_1638 = or(T_1637, T_1558) node T_1639 = or(T_1638, T_1561) node T_1640 = or(T_1639, T_1564) node T_1641 = or(T_1640, T_1567) node T_1642 = or(T_1641, T_1570) node T_1643 = or(T_1642, T_1573) node T_1644 = or(T_1643, io.in[0].valid) node T_1646 = eq(T_1644, UInt<1>("h00")) node T_1648 = or(UInt<1>("h00"), T_1552) node T_1649 = or(T_1648, T_1555) node T_1650 = or(T_1649, T_1558) node T_1651 = or(T_1650, T_1561) node T_1652 = or(T_1651, T_1564) node T_1653 = or(T_1652, T_1567) node T_1654 = or(T_1653, T_1570) node T_1655 = or(T_1654, T_1573) node T_1656 = or(T_1655, io.in[0].valid) node T_1657 = or(T_1656, io.in[1].valid) node T_1659 = eq(T_1657, UInt<1>("h00")) node T_1661 = or(UInt<1>("h00"), T_1552) node T_1662 = or(T_1661, T_1555) node T_1663 = or(T_1662, T_1558) node T_1664 = or(T_1663, T_1561) node T_1665 = or(T_1664, T_1564) node T_1666 = or(T_1665, T_1567) node T_1667 = or(T_1666, T_1570) node T_1668 = or(T_1667, T_1573) node T_1669 = or(T_1668, io.in[0].valid) node T_1670 = or(T_1669, io.in[1].valid) node T_1671 = or(T_1670, io.in[2].valid) node T_1673 = eq(T_1671, UInt<1>("h00")) node T_1675 = or(UInt<1>("h00"), T_1552) node T_1676 = or(T_1675, T_1555) node T_1677 = or(T_1676, T_1558) node T_1678 = or(T_1677, T_1561) node T_1679 = or(T_1678, T_1564) node T_1680 = or(T_1679, T_1567) node T_1681 = or(T_1680, T_1570) node T_1682 = or(T_1681, T_1573) node T_1683 = or(T_1682, io.in[0].valid) node T_1684 = or(T_1683, io.in[1].valid) node T_1685 = or(T_1684, io.in[2].valid) node T_1686 = or(T_1685, io.in[3].valid) node T_1688 = eq(T_1686, UInt<1>("h00")) node T_1690 = or(UInt<1>("h00"), T_1552) node T_1691 = or(T_1690, T_1555) node T_1692 = or(T_1691, T_1558) node T_1693 = or(T_1692, T_1561) node T_1694 = or(T_1693, T_1564) node T_1695 = or(T_1694, T_1567) node T_1696 = or(T_1695, T_1570) node T_1697 = or(T_1696, T_1573) node T_1698 = or(T_1697, io.in[0].valid) node T_1699 = or(T_1698, io.in[1].valid) node T_1700 = or(T_1699, io.in[2].valid) node T_1701 = or(T_1700, io.in[3].valid) node T_1702 = or(T_1701, io.in[4].valid) node T_1704 = eq(T_1702, UInt<1>("h00")) node T_1706 = or(UInt<1>("h00"), T_1552) node T_1707 = or(T_1706, T_1555) node T_1708 = or(T_1707, T_1558) node T_1709 = or(T_1708, T_1561) node T_1710 = or(T_1709, T_1564) node T_1711 = or(T_1710, T_1567) node T_1712 = or(T_1711, T_1570) node T_1713 = or(T_1712, T_1573) node T_1714 = or(T_1713, io.in[0].valid) node T_1715 = or(T_1714, io.in[1].valid) node T_1716 = or(T_1715, io.in[2].valid) node T_1717 = or(T_1716, io.in[3].valid) node T_1718 = or(T_1717, io.in[4].valid) node T_1719 = or(T_1718, io.in[5].valid) node T_1721 = eq(T_1719, UInt<1>("h00")) node T_1723 = or(UInt<1>("h00"), T_1552) node T_1724 = or(T_1723, T_1555) node T_1725 = or(T_1724, T_1558) node T_1726 = or(T_1725, T_1561) node T_1727 = or(T_1726, T_1564) node T_1728 = or(T_1727, T_1567) node T_1729 = or(T_1728, T_1570) node T_1730 = or(T_1729, T_1573) node T_1731 = or(T_1730, io.in[0].valid) node T_1732 = or(T_1731, io.in[1].valid) node T_1733 = or(T_1732, io.in[2].valid) node T_1734 = or(T_1733, io.in[3].valid) node T_1735 = or(T_1734, io.in[4].valid) node T_1736 = or(T_1735, io.in[5].valid) node T_1737 = or(T_1736, io.in[6].valid) node T_1739 = eq(T_1737, UInt<1>("h00")) node T_1741 = gt(UInt<1>("h00"), last_grant) node T_1742 = and(UInt<1>("h01"), T_1741) node T_1743 = or(T_1742, T_1634) node T_1745 = gt(UInt<1>("h01"), last_grant) node T_1746 = and(T_1578, T_1745) node T_1747 = or(T_1746, T_1646) node T_1749 = gt(UInt<2>("h02"), last_grant) node T_1750 = and(T_1583, T_1749) node T_1751 = or(T_1750, T_1659) node T_1753 = gt(UInt<2>("h03"), last_grant) node T_1754 = and(T_1589, T_1753) node T_1755 = or(T_1754, T_1673) node T_1757 = gt(UInt<3>("h04"), last_grant) node T_1758 = and(T_1596, T_1757) node T_1759 = or(T_1758, T_1688) node T_1761 = gt(UInt<3>("h05"), last_grant) node T_1762 = and(T_1604, T_1761) node T_1763 = or(T_1762, T_1704) node T_1765 = gt(UInt<3>("h06"), last_grant) node T_1766 = and(T_1613, T_1765) node T_1767 = or(T_1766, T_1721) node T_1769 = gt(UInt<3>("h07"), last_grant) node T_1770 = and(T_1623, T_1769) node T_1771 = or(T_1770, T_1739) node T_1773 = eq(T_1366, UInt<1>("h00")) node T_1774 = mux(T_1364, T_1773, T_1743) node T_1775 = and(T_1774, io.out.ready) io.in[0].ready := T_1775 node T_1777 = eq(T_1366, UInt<1>("h01")) node T_1778 = mux(T_1364, T_1777, T_1747) node T_1779 = and(T_1778, io.out.ready) io.in[1].ready := T_1779 node T_1781 = eq(T_1366, UInt<2>("h02")) node T_1782 = mux(T_1364, T_1781, T_1751) node T_1783 = and(T_1782, io.out.ready) io.in[2].ready := T_1783 node T_1785 = eq(T_1366, UInt<2>("h03")) node T_1786 = mux(T_1364, T_1785, T_1755) node T_1787 = and(T_1786, io.out.ready) io.in[3].ready := T_1787 node T_1789 = eq(T_1366, UInt<3>("h04")) node T_1790 = mux(T_1364, T_1789, T_1759) node T_1791 = and(T_1790, io.out.ready) io.in[4].ready := T_1791 node T_1793 = eq(T_1366, UInt<3>("h05")) node T_1794 = mux(T_1364, T_1793, T_1763) node T_1795 = and(T_1794, io.out.ready) io.in[5].ready := T_1795 node T_1797 = eq(T_1366, UInt<3>("h06")) node T_1798 = mux(T_1364, T_1797, T_1767) node T_1799 = and(T_1798, io.out.ready) io.in[6].ready := T_1799 node T_1801 = eq(T_1366, UInt<3>("h07")) node T_1802 = mux(T_1364, T_1801, T_1771) node T_1803 = and(T_1802, io.out.ready) io.in[7].ready := T_1803 reg T_1805 : UInt<2>, clock, reset onreset T_1805 := UInt<2>("h00") node T_1807 = addw(T_1805, UInt<1>("h01")) node T_1808 = and(io.out.ready, io.out.valid) when T_1808 : node T_1810 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_1813 : UInt<3>[1] T_1813[0] := UInt<3>("h03") node T_1816 = eq(T_1813[0], io.out.bits.a_type) node T_1818 = or(UInt<1>("h00"), T_1816) node T_1819 = and(T_1810, T_1818) when T_1819 : T_1805 := T_1807 node T_1821 = eq(T_1364, UInt<1>("h00")) when T_1821 : T_1364 := UInt<1>("h01") node T_1823 = and(io.in[0].ready, io.in[0].valid) node T_1824 = and(io.in[1].ready, io.in[1].valid) node T_1825 = and(io.in[2].ready, io.in[2].valid) node T_1826 = and(io.in[3].ready, io.in[3].valid) node T_1827 = and(io.in[4].ready, io.in[4].valid) node T_1828 = and(io.in[5].ready, io.in[5].valid) node T_1829 = and(io.in[6].ready, io.in[6].valid) node T_1830 = and(io.in[7].ready, io.in[7].valid) wire T_1832 : UInt<1>[8] T_1832[0] := T_1823 T_1832[1] := T_1824 T_1832[2] := T_1825 T_1832[3] := T_1826 T_1832[4] := T_1827 T_1832[5] := T_1828 T_1832[6] := T_1829 T_1832[7] := T_1830 node T_1850 = mux(T_1832[6], UInt<3>("h06"), UInt<3>("h07")) node T_1851 = mux(T_1832[5], UInt<3>("h05"), T_1850) node T_1852 = mux(T_1832[4], UInt<3>("h04"), T_1851) node T_1853 = mux(T_1832[3], UInt<2>("h03"), T_1852) node T_1854 = mux(T_1832[2], UInt<2>("h02"), T_1853) node T_1855 = mux(T_1832[1], UInt<1>("h01"), T_1854) node T_1856 = mux(T_1832[0], UInt<1>("h00"), T_1855) T_1366 := T_1856 skip skip node T_1858 = eq(T_1807, UInt<1>("h00")) when T_1858 : T_1364 := UInt<1>("h00") skip skip node T_1862 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_1864 = mux(io.in[5].valid, UInt<3>("h05"), T_1862) node T_1866 = mux(io.in[4].valid, UInt<3>("h04"), T_1864) node T_1868 = mux(io.in[3].valid, UInt<2>("h03"), T_1866) node T_1870 = mux(io.in[2].valid, UInt<2>("h02"), T_1868) node T_1872 = mux(io.in[1].valid, UInt<1>("h01"), T_1870) node T_1874 = mux(io.in[0].valid, UInt<1>("h00"), T_1872) node T_1876 = gt(UInt<3>("h07"), last_grant) node T_1877 = and(io.in[7].valid, T_1876) node T_1879 = mux(T_1877, UInt<3>("h07"), T_1874) node T_1881 = gt(UInt<3>("h06"), last_grant) node T_1882 = and(io.in[6].valid, T_1881) node T_1884 = mux(T_1882, UInt<3>("h06"), T_1879) node T_1886 = gt(UInt<3>("h05"), last_grant) node T_1887 = and(io.in[5].valid, T_1886) node T_1889 = mux(T_1887, UInt<3>("h05"), T_1884) node T_1891 = gt(UInt<3>("h04"), last_grant) node T_1892 = and(io.in[4].valid, T_1891) node T_1894 = mux(T_1892, UInt<3>("h04"), T_1889) node T_1896 = gt(UInt<2>("h03"), last_grant) node T_1897 = and(io.in[3].valid, T_1896) node T_1899 = mux(T_1897, UInt<2>("h03"), T_1894) node T_1901 = gt(UInt<2>("h02"), last_grant) node T_1902 = and(io.in[2].valid, T_1901) node T_1904 = mux(T_1902, UInt<2>("h02"), T_1899) node T_1906 = gt(UInt<1>("h01"), last_grant) node T_1907 = and(io.in[1].valid, T_1906) node choose = mux(T_1907, UInt<1>("h01"), T_1904) node T_1910 = mux(T_1364, T_1366, choose) T_1368 := T_1910 node T_1911 = and(io.out.ready, io.out.valid) when T_1911 : last_grant := T_1368 skip module ClientUncachedTileLinkIOArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.out.grant.ready := UInt<1>("h00") io.out.acquire.bits.union := UInt<1>("h00") io.out.acquire.bits.a_type := UInt<1>("h00") io.out.acquire.bits.is_builtin_type := UInt<1>("h00") io.out.acquire.bits.data := UInt<1>("h00") io.out.acquire.bits.addr_beat := UInt<1>("h00") io.out.acquire.bits.client_xact_id := UInt<1>("h00") io.out.acquire.bits.addr_block := UInt<1>("h00") io.out.acquire.valid := UInt<1>("h00") io.in[0].grant.bits.g_type := UInt<1>("h00") io.in[0].grant.bits.is_builtin_type := UInt<1>("h00") io.in[0].grant.bits.manager_xact_id := UInt<1>("h00") io.in[0].grant.bits.client_xact_id := UInt<1>("h00") io.in[0].grant.bits.data := UInt<1>("h00") io.in[0].grant.bits.addr_beat := UInt<1>("h00") io.in[0].grant.valid := UInt<1>("h00") io.in[0].acquire.ready := UInt<1>("h00") io.in[1].grant.bits.g_type := UInt<1>("h00") io.in[1].grant.bits.is_builtin_type := UInt<1>("h00") io.in[1].grant.bits.manager_xact_id := UInt<1>("h00") io.in[1].grant.bits.client_xact_id := UInt<1>("h00") io.in[1].grant.bits.data := UInt<1>("h00") io.in[1].grant.bits.addr_beat := UInt<1>("h00") io.in[1].grant.valid := UInt<1>("h00") io.in[1].acquire.ready := UInt<1>("h00") io.in[2].grant.bits.g_type := UInt<1>("h00") io.in[2].grant.bits.is_builtin_type := UInt<1>("h00") io.in[2].grant.bits.manager_xact_id := UInt<1>("h00") io.in[2].grant.bits.client_xact_id := UInt<1>("h00") io.in[2].grant.bits.data := UInt<1>("h00") io.in[2].grant.bits.addr_beat := UInt<1>("h00") io.in[2].grant.valid := UInt<1>("h00") io.in[2].acquire.ready := UInt<1>("h00") io.in[3].grant.bits.g_type := UInt<1>("h00") io.in[3].grant.bits.is_builtin_type := UInt<1>("h00") io.in[3].grant.bits.manager_xact_id := UInt<1>("h00") io.in[3].grant.bits.client_xact_id := UInt<1>("h00") io.in[3].grant.bits.data := UInt<1>("h00") io.in[3].grant.bits.addr_beat := UInt<1>("h00") io.in[3].grant.valid := UInt<1>("h00") io.in[3].acquire.ready := UInt<1>("h00") io.in[4].grant.bits.g_type := UInt<1>("h00") io.in[4].grant.bits.is_builtin_type := UInt<1>("h00") io.in[4].grant.bits.manager_xact_id := UInt<1>("h00") io.in[4].grant.bits.client_xact_id := UInt<1>("h00") io.in[4].grant.bits.data := UInt<1>("h00") io.in[4].grant.bits.addr_beat := UInt<1>("h00") io.in[4].grant.valid := UInt<1>("h00") io.in[4].acquire.ready := UInt<1>("h00") io.in[5].grant.bits.g_type := UInt<1>("h00") io.in[5].grant.bits.is_builtin_type := UInt<1>("h00") io.in[5].grant.bits.manager_xact_id := UInt<1>("h00") io.in[5].grant.bits.client_xact_id := UInt<1>("h00") io.in[5].grant.bits.data := UInt<1>("h00") io.in[5].grant.bits.addr_beat := UInt<1>("h00") io.in[5].grant.valid := UInt<1>("h00") io.in[5].acquire.ready := UInt<1>("h00") io.in[6].grant.bits.g_type := UInt<1>("h00") io.in[6].grant.bits.is_builtin_type := UInt<1>("h00") io.in[6].grant.bits.manager_xact_id := UInt<1>("h00") io.in[6].grant.bits.client_xact_id := UInt<1>("h00") io.in[6].grant.bits.data := UInt<1>("h00") io.in[6].grant.bits.addr_beat := UInt<1>("h00") io.in[6].grant.valid := UInt<1>("h00") io.in[6].acquire.ready := UInt<1>("h00") io.in[7].grant.bits.g_type := UInt<1>("h00") io.in[7].grant.bits.is_builtin_type := UInt<1>("h00") io.in[7].grant.bits.manager_xact_id := UInt<1>("h00") io.in[7].grant.bits.client_xact_id := UInt<1>("h00") io.in[7].grant.bits.data := UInt<1>("h00") io.in[7].grant.bits.addr_beat := UInt<1>("h00") io.in[7].grant.valid := UInt<1>("h00") io.in[7].acquire.ready := UInt<1>("h00") inst T_5753 of LockingRRArbiter_35 T_5753.io.out.ready := UInt<1>("h00") T_5753.io.in[0].bits.union := UInt<1>("h00") T_5753.io.in[0].bits.a_type := UInt<1>("h00") T_5753.io.in[0].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[0].bits.data := UInt<1>("h00") T_5753.io.in[0].bits.addr_beat := UInt<1>("h00") T_5753.io.in[0].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[0].bits.addr_block := UInt<1>("h00") T_5753.io.in[0].valid := UInt<1>("h00") T_5753.io.in[1].bits.union := UInt<1>("h00") T_5753.io.in[1].bits.a_type := UInt<1>("h00") T_5753.io.in[1].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[1].bits.data := UInt<1>("h00") T_5753.io.in[1].bits.addr_beat := UInt<1>("h00") T_5753.io.in[1].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[1].bits.addr_block := UInt<1>("h00") T_5753.io.in[1].valid := UInt<1>("h00") T_5753.io.in[2].bits.union := UInt<1>("h00") T_5753.io.in[2].bits.a_type := UInt<1>("h00") T_5753.io.in[2].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[2].bits.data := UInt<1>("h00") T_5753.io.in[2].bits.addr_beat := UInt<1>("h00") T_5753.io.in[2].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[2].bits.addr_block := UInt<1>("h00") T_5753.io.in[2].valid := UInt<1>("h00") T_5753.io.in[3].bits.union := UInt<1>("h00") T_5753.io.in[3].bits.a_type := UInt<1>("h00") T_5753.io.in[3].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[3].bits.data := UInt<1>("h00") T_5753.io.in[3].bits.addr_beat := UInt<1>("h00") T_5753.io.in[3].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[3].bits.addr_block := UInt<1>("h00") T_5753.io.in[3].valid := UInt<1>("h00") T_5753.io.in[4].bits.union := UInt<1>("h00") T_5753.io.in[4].bits.a_type := UInt<1>("h00") T_5753.io.in[4].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[4].bits.data := UInt<1>("h00") T_5753.io.in[4].bits.addr_beat := UInt<1>("h00") T_5753.io.in[4].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[4].bits.addr_block := UInt<1>("h00") T_5753.io.in[4].valid := UInt<1>("h00") T_5753.io.in[5].bits.union := UInt<1>("h00") T_5753.io.in[5].bits.a_type := UInt<1>("h00") T_5753.io.in[5].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[5].bits.data := UInt<1>("h00") T_5753.io.in[5].bits.addr_beat := UInt<1>("h00") T_5753.io.in[5].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[5].bits.addr_block := UInt<1>("h00") T_5753.io.in[5].valid := UInt<1>("h00") T_5753.io.in[6].bits.union := UInt<1>("h00") T_5753.io.in[6].bits.a_type := UInt<1>("h00") T_5753.io.in[6].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[6].bits.data := UInt<1>("h00") T_5753.io.in[6].bits.addr_beat := UInt<1>("h00") T_5753.io.in[6].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[6].bits.addr_block := UInt<1>("h00") T_5753.io.in[6].valid := UInt<1>("h00") T_5753.io.in[7].bits.union := UInt<1>("h00") T_5753.io.in[7].bits.a_type := UInt<1>("h00") T_5753.io.in[7].bits.is_builtin_type := UInt<1>("h00") T_5753.io.in[7].bits.data := UInt<1>("h00") T_5753.io.in[7].bits.addr_beat := UInt<1>("h00") T_5753.io.in[7].bits.client_xact_id := UInt<1>("h00") T_5753.io.in[7].bits.addr_block := UInt<1>("h00") T_5753.io.in[7].valid := UInt<1>("h00") T_5753.clock := clock T_5753.reset := reset T_5753.io.in[0].valid := io.in[0].acquire.valid T_5753.io.in[0].bits <> io.in[0].acquire.bits node T_5820 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) T_5753.io.in[0].bits.client_xact_id := T_5820 io.in[0].acquire.ready := T_5753.io.in[0].ready T_5753.io.in[1].valid := io.in[1].acquire.valid T_5753.io.in[1].bits <> io.in[1].acquire.bits node T_5822 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) T_5753.io.in[1].bits.client_xact_id := T_5822 io.in[1].acquire.ready := T_5753.io.in[1].ready T_5753.io.in[2].valid := io.in[2].acquire.valid T_5753.io.in[2].bits <> io.in[2].acquire.bits node T_5824 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) T_5753.io.in[2].bits.client_xact_id := T_5824 io.in[2].acquire.ready := T_5753.io.in[2].ready T_5753.io.in[3].valid := io.in[3].acquire.valid T_5753.io.in[3].bits <> io.in[3].acquire.bits node T_5826 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) T_5753.io.in[3].bits.client_xact_id := T_5826 io.in[3].acquire.ready := T_5753.io.in[3].ready T_5753.io.in[4].valid := io.in[4].acquire.valid T_5753.io.in[4].bits <> io.in[4].acquire.bits node T_5828 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) T_5753.io.in[4].bits.client_xact_id := T_5828 io.in[4].acquire.ready := T_5753.io.in[4].ready T_5753.io.in[5].valid := io.in[5].acquire.valid T_5753.io.in[5].bits <> io.in[5].acquire.bits node T_5830 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) T_5753.io.in[5].bits.client_xact_id := T_5830 io.in[5].acquire.ready := T_5753.io.in[5].ready T_5753.io.in[6].valid := io.in[6].acquire.valid T_5753.io.in[6].bits <> io.in[6].acquire.bits node T_5832 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) T_5753.io.in[6].bits.client_xact_id := T_5832 io.in[6].acquire.ready := T_5753.io.in[6].ready T_5753.io.in[7].valid := io.in[7].acquire.valid T_5753.io.in[7].bits <> io.in[7].acquire.bits node T_5834 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) T_5753.io.in[7].bits.client_xact_id := T_5834 io.in[7].acquire.ready := T_5753.io.in[7].ready io.out.acquire <> T_5753.io.out io.out.grant.ready := UInt<1>("h00") io.in[0].grant.valid := UInt<1>("h00") node T_5837 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5839 = eq(T_5837, UInt<1>("h00")) when T_5839 : io.in[0].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[0].grant.ready skip io.in[0].grant.bits <> io.out.grant.bits node T_5840 = shr(io.out.grant.bits.client_xact_id, 3) io.in[0].grant.bits.client_xact_id := T_5840 io.in[1].grant.valid := UInt<1>("h00") node T_5842 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5844 = eq(T_5842, UInt<1>("h01")) when T_5844 : io.in[1].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[1].grant.ready skip io.in[1].grant.bits <> io.out.grant.bits node T_5845 = shr(io.out.grant.bits.client_xact_id, 3) io.in[1].grant.bits.client_xact_id := T_5845 io.in[2].grant.valid := UInt<1>("h00") node T_5847 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5849 = eq(T_5847, UInt<2>("h02")) when T_5849 : io.in[2].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[2].grant.ready skip io.in[2].grant.bits <> io.out.grant.bits node T_5850 = shr(io.out.grant.bits.client_xact_id, 3) io.in[2].grant.bits.client_xact_id := T_5850 io.in[3].grant.valid := UInt<1>("h00") node T_5852 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5854 = eq(T_5852, UInt<2>("h03")) when T_5854 : io.in[3].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[3].grant.ready skip io.in[3].grant.bits <> io.out.grant.bits node T_5855 = shr(io.out.grant.bits.client_xact_id, 3) io.in[3].grant.bits.client_xact_id := T_5855 io.in[4].grant.valid := UInt<1>("h00") node T_5857 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5859 = eq(T_5857, UInt<3>("h04")) when T_5859 : io.in[4].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[4].grant.ready skip io.in[4].grant.bits <> io.out.grant.bits node T_5860 = shr(io.out.grant.bits.client_xact_id, 3) io.in[4].grant.bits.client_xact_id := T_5860 io.in[5].grant.valid := UInt<1>("h00") node T_5862 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5864 = eq(T_5862, UInt<3>("h05")) when T_5864 : io.in[5].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[5].grant.ready skip io.in[5].grant.bits <> io.out.grant.bits node T_5865 = shr(io.out.grant.bits.client_xact_id, 3) io.in[5].grant.bits.client_xact_id := T_5865 io.in[6].grant.valid := UInt<1>("h00") node T_5867 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5869 = eq(T_5867, UInt<3>("h06")) when T_5869 : io.in[6].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[6].grant.ready skip io.in[6].grant.bits <> io.out.grant.bits node T_5870 = shr(io.out.grant.bits.client_xact_id, 3) io.in[6].grant.bits.client_xact_id := T_5870 io.in[7].grant.valid := UInt<1>("h00") node T_5872 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_5874 = eq(T_5872, UInt<3>("h07")) when T_5874 : io.in[7].grant.valid := io.out.grant.valid io.out.grant.ready := io.in[7].grant.ready skip io.in[7].grant.bits <> io.out.grant.bits node T_5875 = shr(io.out.grant.bits.client_xact_id, 3) io.in[7].grant.bits.client_xact_id := T_5875 module L2BroadcastHub : input clock : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.outer.grant.ready := UInt<1>("h00") io.outer.acquire.bits.union := UInt<1>("h00") io.outer.acquire.bits.a_type := UInt<1>("h00") io.outer.acquire.bits.is_builtin_type := UInt<1>("h00") io.outer.acquire.bits.data := UInt<1>("h00") io.outer.acquire.bits.addr_beat := UInt<1>("h00") io.outer.acquire.bits.client_xact_id := UInt<1>("h00") io.outer.acquire.bits.addr_block := UInt<1>("h00") io.outer.acquire.valid := UInt<1>("h00") io.inner.release.ready := UInt<1>("h00") io.inner.probe.bits.client_id := UInt<1>("h00") io.inner.probe.bits.p_type := UInt<1>("h00") io.inner.probe.bits.addr_block := UInt<1>("h00") io.inner.probe.valid := UInt<1>("h00") io.inner.finish.ready := UInt<1>("h00") io.inner.grant.bits.client_id := UInt<1>("h00") io.inner.grant.bits.g_type := UInt<1>("h00") io.inner.grant.bits.is_builtin_type := UInt<1>("h00") io.inner.grant.bits.manager_xact_id := UInt<1>("h00") io.inner.grant.bits.client_xact_id := UInt<1>("h00") io.inner.grant.bits.data := UInt<1>("h00") io.inner.grant.bits.addr_beat := UInt<1>("h00") io.inner.grant.valid := UInt<1>("h00") io.inner.acquire.ready := UInt<1>("h00") inst T_931 of BroadcastVoluntaryReleaseTracker T_931.io.outer.grant.bits.g_type := UInt<1>("h00") T_931.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_931.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_931.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_931.io.outer.grant.bits.data := UInt<1>("h00") T_931.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_931.io.outer.grant.valid := UInt<1>("h00") T_931.io.outer.acquire.ready := UInt<1>("h00") T_931.io.incoherent[0] := UInt<1>("h00") T_931.io.inner.release.bits.client_id := UInt<1>("h00") T_931.io.inner.release.bits.voluntary := UInt<1>("h00") T_931.io.inner.release.bits.r_type := UInt<1>("h00") T_931.io.inner.release.bits.data := UInt<1>("h00") T_931.io.inner.release.bits.addr_beat := UInt<1>("h00") T_931.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_931.io.inner.release.bits.addr_block := UInt<1>("h00") T_931.io.inner.release.valid := UInt<1>("h00") T_931.io.inner.probe.ready := UInt<1>("h00") T_931.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_931.io.inner.finish.valid := UInt<1>("h00") T_931.io.inner.grant.ready := UInt<1>("h00") T_931.io.inner.acquire.bits.client_id := UInt<1>("h00") T_931.io.inner.acquire.bits.union := UInt<1>("h00") T_931.io.inner.acquire.bits.a_type := UInt<1>("h00") T_931.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_931.io.inner.acquire.bits.data := UInt<1>("h00") T_931.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_931.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_931.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_931.io.inner.acquire.valid := UInt<1>("h00") T_931.clock := clock T_931.reset := reset inst T_962 of BroadcastAcquireTracker T_962.io.outer.grant.bits.g_type := UInt<1>("h00") T_962.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_962.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_962.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_962.io.outer.grant.bits.data := UInt<1>("h00") T_962.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_962.io.outer.grant.valid := UInt<1>("h00") T_962.io.outer.acquire.ready := UInt<1>("h00") T_962.io.incoherent[0] := UInt<1>("h00") T_962.io.inner.release.bits.client_id := UInt<1>("h00") T_962.io.inner.release.bits.voluntary := UInt<1>("h00") T_962.io.inner.release.bits.r_type := UInt<1>("h00") T_962.io.inner.release.bits.data := UInt<1>("h00") T_962.io.inner.release.bits.addr_beat := UInt<1>("h00") T_962.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_962.io.inner.release.bits.addr_block := UInt<1>("h00") T_962.io.inner.release.valid := UInt<1>("h00") T_962.io.inner.probe.ready := UInt<1>("h00") T_962.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_962.io.inner.finish.valid := UInt<1>("h00") T_962.io.inner.grant.ready := UInt<1>("h00") T_962.io.inner.acquire.bits.client_id := UInt<1>("h00") T_962.io.inner.acquire.bits.union := UInt<1>("h00") T_962.io.inner.acquire.bits.a_type := UInt<1>("h00") T_962.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_962.io.inner.acquire.bits.data := UInt<1>("h00") T_962.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_962.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_962.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_962.io.inner.acquire.valid := UInt<1>("h00") T_962.clock := clock T_962.reset := reset inst T_993 of BroadcastAcquireTracker_27 T_993.io.outer.grant.bits.g_type := UInt<1>("h00") T_993.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_993.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_993.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_993.io.outer.grant.bits.data := UInt<1>("h00") T_993.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_993.io.outer.grant.valid := UInt<1>("h00") T_993.io.outer.acquire.ready := UInt<1>("h00") T_993.io.incoherent[0] := UInt<1>("h00") T_993.io.inner.release.bits.client_id := UInt<1>("h00") T_993.io.inner.release.bits.voluntary := UInt<1>("h00") T_993.io.inner.release.bits.r_type := UInt<1>("h00") T_993.io.inner.release.bits.data := UInt<1>("h00") T_993.io.inner.release.bits.addr_beat := UInt<1>("h00") T_993.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_993.io.inner.release.bits.addr_block := UInt<1>("h00") T_993.io.inner.release.valid := UInt<1>("h00") T_993.io.inner.probe.ready := UInt<1>("h00") T_993.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_993.io.inner.finish.valid := UInt<1>("h00") T_993.io.inner.grant.ready := UInt<1>("h00") T_993.io.inner.acquire.bits.client_id := UInt<1>("h00") T_993.io.inner.acquire.bits.union := UInt<1>("h00") T_993.io.inner.acquire.bits.a_type := UInt<1>("h00") T_993.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_993.io.inner.acquire.bits.data := UInt<1>("h00") T_993.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_993.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_993.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_993.io.inner.acquire.valid := UInt<1>("h00") T_993.clock := clock T_993.reset := reset inst T_1024 of BroadcastAcquireTracker_28 T_1024.io.outer.grant.bits.g_type := UInt<1>("h00") T_1024.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_1024.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_1024.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_1024.io.outer.grant.bits.data := UInt<1>("h00") T_1024.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_1024.io.outer.grant.valid := UInt<1>("h00") T_1024.io.outer.acquire.ready := UInt<1>("h00") T_1024.io.incoherent[0] := UInt<1>("h00") T_1024.io.inner.release.bits.client_id := UInt<1>("h00") T_1024.io.inner.release.bits.voluntary := UInt<1>("h00") T_1024.io.inner.release.bits.r_type := UInt<1>("h00") T_1024.io.inner.release.bits.data := UInt<1>("h00") T_1024.io.inner.release.bits.addr_beat := UInt<1>("h00") T_1024.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_1024.io.inner.release.bits.addr_block := UInt<1>("h00") T_1024.io.inner.release.valid := UInt<1>("h00") T_1024.io.inner.probe.ready := UInt<1>("h00") T_1024.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_1024.io.inner.finish.valid := UInt<1>("h00") T_1024.io.inner.grant.ready := UInt<1>("h00") T_1024.io.inner.acquire.bits.client_id := UInt<1>("h00") T_1024.io.inner.acquire.bits.union := UInt<1>("h00") T_1024.io.inner.acquire.bits.a_type := UInt<1>("h00") T_1024.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_1024.io.inner.acquire.bits.data := UInt<1>("h00") T_1024.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_1024.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_1024.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_1024.io.inner.acquire.valid := UInt<1>("h00") T_1024.clock := clock T_1024.reset := reset inst T_1055 of BroadcastAcquireTracker_29 T_1055.io.outer.grant.bits.g_type := UInt<1>("h00") T_1055.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_1055.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_1055.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_1055.io.outer.grant.bits.data := UInt<1>("h00") T_1055.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_1055.io.outer.grant.valid := UInt<1>("h00") T_1055.io.outer.acquire.ready := UInt<1>("h00") T_1055.io.incoherent[0] := UInt<1>("h00") T_1055.io.inner.release.bits.client_id := UInt<1>("h00") T_1055.io.inner.release.bits.voluntary := UInt<1>("h00") T_1055.io.inner.release.bits.r_type := UInt<1>("h00") T_1055.io.inner.release.bits.data := UInt<1>("h00") T_1055.io.inner.release.bits.addr_beat := UInt<1>("h00") T_1055.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_1055.io.inner.release.bits.addr_block := UInt<1>("h00") T_1055.io.inner.release.valid := UInt<1>("h00") T_1055.io.inner.probe.ready := UInt<1>("h00") T_1055.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_1055.io.inner.finish.valid := UInt<1>("h00") T_1055.io.inner.grant.ready := UInt<1>("h00") T_1055.io.inner.acquire.bits.client_id := UInt<1>("h00") T_1055.io.inner.acquire.bits.union := UInt<1>("h00") T_1055.io.inner.acquire.bits.a_type := UInt<1>("h00") T_1055.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_1055.io.inner.acquire.bits.data := UInt<1>("h00") T_1055.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_1055.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_1055.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_1055.io.inner.acquire.valid := UInt<1>("h00") T_1055.clock := clock T_1055.reset := reset inst T_1086 of BroadcastAcquireTracker_30 T_1086.io.outer.grant.bits.g_type := UInt<1>("h00") T_1086.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_1086.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_1086.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_1086.io.outer.grant.bits.data := UInt<1>("h00") T_1086.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_1086.io.outer.grant.valid := UInt<1>("h00") T_1086.io.outer.acquire.ready := UInt<1>("h00") T_1086.io.incoherent[0] := UInt<1>("h00") T_1086.io.inner.release.bits.client_id := UInt<1>("h00") T_1086.io.inner.release.bits.voluntary := UInt<1>("h00") T_1086.io.inner.release.bits.r_type := UInt<1>("h00") T_1086.io.inner.release.bits.data := UInt<1>("h00") T_1086.io.inner.release.bits.addr_beat := UInt<1>("h00") T_1086.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_1086.io.inner.release.bits.addr_block := UInt<1>("h00") T_1086.io.inner.release.valid := UInt<1>("h00") T_1086.io.inner.probe.ready := UInt<1>("h00") T_1086.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_1086.io.inner.finish.valid := UInt<1>("h00") T_1086.io.inner.grant.ready := UInt<1>("h00") T_1086.io.inner.acquire.bits.client_id := UInt<1>("h00") T_1086.io.inner.acquire.bits.union := UInt<1>("h00") T_1086.io.inner.acquire.bits.a_type := UInt<1>("h00") T_1086.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_1086.io.inner.acquire.bits.data := UInt<1>("h00") T_1086.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_1086.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_1086.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_1086.io.inner.acquire.valid := UInt<1>("h00") T_1086.clock := clock T_1086.reset := reset inst T_1117 of BroadcastAcquireTracker_31 T_1117.io.outer.grant.bits.g_type := UInt<1>("h00") T_1117.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_1117.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_1117.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_1117.io.outer.grant.bits.data := UInt<1>("h00") T_1117.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_1117.io.outer.grant.valid := UInt<1>("h00") T_1117.io.outer.acquire.ready := UInt<1>("h00") T_1117.io.incoherent[0] := UInt<1>("h00") T_1117.io.inner.release.bits.client_id := UInt<1>("h00") T_1117.io.inner.release.bits.voluntary := UInt<1>("h00") T_1117.io.inner.release.bits.r_type := UInt<1>("h00") T_1117.io.inner.release.bits.data := UInt<1>("h00") T_1117.io.inner.release.bits.addr_beat := UInt<1>("h00") T_1117.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_1117.io.inner.release.bits.addr_block := UInt<1>("h00") T_1117.io.inner.release.valid := UInt<1>("h00") T_1117.io.inner.probe.ready := UInt<1>("h00") T_1117.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_1117.io.inner.finish.valid := UInt<1>("h00") T_1117.io.inner.grant.ready := UInt<1>("h00") T_1117.io.inner.acquire.bits.client_id := UInt<1>("h00") T_1117.io.inner.acquire.bits.union := UInt<1>("h00") T_1117.io.inner.acquire.bits.a_type := UInt<1>("h00") T_1117.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_1117.io.inner.acquire.bits.data := UInt<1>("h00") T_1117.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_1117.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_1117.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_1117.io.inner.acquire.valid := UInt<1>("h00") T_1117.clock := clock T_1117.reset := reset inst T_1148 of BroadcastAcquireTracker_32 T_1148.io.outer.grant.bits.g_type := UInt<1>("h00") T_1148.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_1148.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_1148.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_1148.io.outer.grant.bits.data := UInt<1>("h00") T_1148.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_1148.io.outer.grant.valid := UInt<1>("h00") T_1148.io.outer.acquire.ready := UInt<1>("h00") T_1148.io.incoherent[0] := UInt<1>("h00") T_1148.io.inner.release.bits.client_id := UInt<1>("h00") T_1148.io.inner.release.bits.voluntary := UInt<1>("h00") T_1148.io.inner.release.bits.r_type := UInt<1>("h00") T_1148.io.inner.release.bits.data := UInt<1>("h00") T_1148.io.inner.release.bits.addr_beat := UInt<1>("h00") T_1148.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_1148.io.inner.release.bits.addr_block := UInt<1>("h00") T_1148.io.inner.release.valid := UInt<1>("h00") T_1148.io.inner.probe.ready := UInt<1>("h00") T_1148.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_1148.io.inner.finish.valid := UInt<1>("h00") T_1148.io.inner.grant.ready := UInt<1>("h00") T_1148.io.inner.acquire.bits.client_id := UInt<1>("h00") T_1148.io.inner.acquire.bits.union := UInt<1>("h00") T_1148.io.inner.acquire.bits.a_type := UInt<1>("h00") T_1148.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_1148.io.inner.acquire.bits.data := UInt<1>("h00") T_1148.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_1148.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_1148.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_1148.io.inner.acquire.valid := UInt<1>("h00") T_1148.clock := clock T_1148.reset := reset T_931.io.incoherent := io.incoherent T_962.io.incoherent := io.incoherent T_993.io.incoherent := io.incoherent T_1024.io.incoherent := io.incoherent T_1055.io.incoherent := io.incoherent T_1086.io.incoherent := io.incoherent T_1117.io.incoherent := io.incoherent T_1148.io.incoherent := io.incoherent reg sdq : UInt<128>[4], clock, reset reg sdq_val : UInt<4>, clock, reset onreset sdq_val := UInt<4>("h00") node T_1196 = not(sdq_val) node T_1197 = bit(T_1196, 0) node T_1198 = bit(T_1196, 1) node T_1199 = bit(T_1196, 2) node T_1200 = bit(T_1196, 3) wire T_1202 : UInt<1>[4] T_1202[0] := T_1197 T_1202[1] := T_1198 T_1202[2] := T_1199 T_1202[3] := T_1200 node T_1212 = mux(T_1202[2], UInt<2>("h02"), UInt<2>("h03")) node T_1213 = mux(T_1202[1], UInt<1>("h01"), T_1212) node sdq_alloc_id = mux(T_1202[0], UInt<1>("h00"), T_1213) node T_1215 = not(sdq_val) node T_1217 = eq(T_1215, UInt<1>("h00")) node sdq_rdy = eq(T_1217, UInt<1>("h00")) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) wire T_1225 : UInt<3>[3] T_1225[0] := UInt<3>("h02") T_1225[1] := UInt<3>("h03") T_1225[2] := UInt<3>("h04") node T_1230 = eq(T_1225[0], io.inner.acquire.bits.a_type) node T_1231 = eq(T_1225[1], io.inner.acquire.bits.a_type) node T_1232 = eq(T_1225[2], io.inner.acquire.bits.a_type) node T_1234 = or(UInt<1>("h00"), T_1230) node T_1235 = or(T_1234, T_1231) node T_1236 = or(T_1235, T_1232) node T_1237 = and(io.inner.acquire.bits.is_builtin_type, T_1236) node sdq_enq = and(T_1220, T_1237) when sdq_enq : infer accessor T_1239 = sdq[sdq_alloc_id] T_1239 := io.inner.acquire.bits.data skip wire T_1241 : UInt<1>[8] T_1241[0] := T_931.io.has_acquire_conflict T_1241[1] := T_962.io.has_acquire_conflict T_1241[2] := T_993.io.has_acquire_conflict T_1241[3] := T_1024.io.has_acquire_conflict T_1241[4] := T_1055.io.has_acquire_conflict T_1241[5] := T_1086.io.has_acquire_conflict T_1241[6] := T_1117.io.has_acquire_conflict T_1241[7] := T_1148.io.has_acquire_conflict node T_1251 = cat(T_1241[7], T_1241[6]) node T_1252 = cat(T_1241[5], T_1241[4]) node T_1253 = cat(T_1251, T_1252) node T_1254 = cat(T_1241[3], T_1241[2]) node T_1255 = cat(T_1241[1], T_1241[0]) node T_1256 = cat(T_1254, T_1255) node acquireConflicts = cat(T_1253, T_1256) wire T_1259 : UInt<1>[8] T_1259[0] := T_931.io.has_acquire_match T_1259[1] := T_962.io.has_acquire_match T_1259[2] := T_993.io.has_acquire_match T_1259[3] := T_1024.io.has_acquire_match T_1259[4] := T_1055.io.has_acquire_match T_1259[5] := T_1086.io.has_acquire_match T_1259[6] := T_1117.io.has_acquire_match T_1259[7] := T_1148.io.has_acquire_match node T_1269 = cat(T_1259[7], T_1259[6]) node T_1270 = cat(T_1259[5], T_1259[4]) node T_1271 = cat(T_1269, T_1270) node T_1272 = cat(T_1259[3], T_1259[2]) node T_1273 = cat(T_1259[1], T_1259[0]) node T_1274 = cat(T_1272, T_1273) node acquireMatches = cat(T_1271, T_1274) wire T_1277 : UInt<1>[8] T_1277[0] := T_931.io.inner.acquire.ready T_1277[1] := T_962.io.inner.acquire.ready T_1277[2] := T_993.io.inner.acquire.ready T_1277[3] := T_1024.io.inner.acquire.ready T_1277[4] := T_1055.io.inner.acquire.ready T_1277[5] := T_1086.io.inner.acquire.ready T_1277[6] := T_1117.io.inner.acquire.ready T_1277[7] := T_1148.io.inner.acquire.ready node T_1287 = cat(T_1277[7], T_1277[6]) node T_1288 = cat(T_1277[5], T_1277[4]) node T_1289 = cat(T_1287, T_1288) node T_1290 = cat(T_1277[3], T_1277[2]) node T_1291 = cat(T_1277[1], T_1277[0]) node T_1292 = cat(T_1290, T_1291) node acquireReadys = cat(T_1289, T_1292) node T_1295 = neq(acquireMatches, UInt<1>("h00")) node T_1296 = bit(acquireMatches, 0) node T_1297 = bit(acquireMatches, 1) node T_1298 = bit(acquireMatches, 2) node T_1299 = bit(acquireMatches, 3) node T_1300 = bit(acquireMatches, 4) node T_1301 = bit(acquireMatches, 5) node T_1302 = bit(acquireMatches, 6) node T_1303 = bit(acquireMatches, 7) wire T_1305 : UInt<1>[8] T_1305[0] := T_1296 T_1305[1] := T_1297 T_1305[2] := T_1298 T_1305[3] := T_1299 T_1305[4] := T_1300 T_1305[5] := T_1301 T_1305[6] := T_1302 T_1305[7] := T_1303 node T_1323 = mux(T_1305[6], UInt<3>("h06"), UInt<3>("h07")) node T_1324 = mux(T_1305[5], UInt<3>("h05"), T_1323) node T_1325 = mux(T_1305[4], UInt<3>("h04"), T_1324) node T_1326 = mux(T_1305[3], UInt<2>("h03"), T_1325) node T_1327 = mux(T_1305[2], UInt<2>("h02"), T_1326) node T_1328 = mux(T_1305[1], UInt<1>("h01"), T_1327) node T_1329 = mux(T_1305[0], UInt<1>("h00"), T_1328) node T_1330 = bit(acquireReadys, 0) node T_1331 = bit(acquireReadys, 1) node T_1332 = bit(acquireReadys, 2) node T_1333 = bit(acquireReadys, 3) node T_1334 = bit(acquireReadys, 4) node T_1335 = bit(acquireReadys, 5) node T_1336 = bit(acquireReadys, 6) node T_1337 = bit(acquireReadys, 7) wire T_1339 : UInt<1>[8] T_1339[0] := T_1330 T_1339[1] := T_1331 T_1339[2] := T_1332 T_1339[3] := T_1333 T_1339[4] := T_1334 T_1339[5] := T_1335 T_1339[6] := T_1336 T_1339[7] := T_1337 node T_1357 = mux(T_1339[6], UInt<3>("h06"), UInt<3>("h07")) node T_1358 = mux(T_1339[5], UInt<3>("h05"), T_1357) node T_1359 = mux(T_1339[4], UInt<3>("h04"), T_1358) node T_1360 = mux(T_1339[3], UInt<2>("h03"), T_1359) node T_1361 = mux(T_1339[2], UInt<2>("h02"), T_1360) node T_1362 = mux(T_1339[1], UInt<1>("h01"), T_1361) node T_1363 = mux(T_1339[0], UInt<1>("h00"), T_1362) node acquire_idx = mux(T_1295, T_1329, T_1363) node T_1366 = neq(acquireConflicts, UInt<1>("h00")) node T_1368 = eq(sdq_rdy, UInt<1>("h00")) node block_acquires = or(T_1366, T_1368) node T_1371 = neq(acquireReadys, UInt<1>("h00")) node T_1373 = eq(block_acquires, UInt<1>("h00")) node T_1374 = and(T_1371, T_1373) io.inner.acquire.ready := T_1374 T_931.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1378 : {idx : UInt<2>, loc : UInt<2>} T_1378.loc := UInt<1>("h00") T_1378.idx := UInt<1>("h00") T_1378.idx := sdq_alloc_id T_1378.loc := UInt<1>("h00") node T_1383 = cat(T_1378.idx, T_1378.loc) T_931.io.inner.acquire.bits.data := T_1383 node T_1385 = eq(block_acquires, UInt<1>("h00")) node T_1386 = and(io.inner.acquire.valid, T_1385) node T_1388 = eq(acquire_idx, UInt<1>("h00")) node T_1389 = and(T_1386, T_1388) T_931.io.inner.acquire.valid := T_1389 T_962.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1393 : {idx : UInt<2>, loc : UInt<2>} T_1393.loc := UInt<1>("h00") T_1393.idx := UInt<1>("h00") T_1393.idx := sdq_alloc_id T_1393.loc := UInt<1>("h00") node T_1398 = cat(T_1393.idx, T_1393.loc) T_962.io.inner.acquire.bits.data := T_1398 node T_1400 = eq(block_acquires, UInt<1>("h00")) node T_1401 = and(io.inner.acquire.valid, T_1400) node T_1403 = eq(acquire_idx, UInt<1>("h01")) node T_1404 = and(T_1401, T_1403) T_962.io.inner.acquire.valid := T_1404 T_993.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1408 : {idx : UInt<2>, loc : UInt<2>} T_1408.loc := UInt<1>("h00") T_1408.idx := UInt<1>("h00") T_1408.idx := sdq_alloc_id T_1408.loc := UInt<1>("h00") node T_1413 = cat(T_1408.idx, T_1408.loc) T_993.io.inner.acquire.bits.data := T_1413 node T_1415 = eq(block_acquires, UInt<1>("h00")) node T_1416 = and(io.inner.acquire.valid, T_1415) node T_1418 = eq(acquire_idx, UInt<2>("h02")) node T_1419 = and(T_1416, T_1418) T_993.io.inner.acquire.valid := T_1419 T_1024.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1423 : {idx : UInt<2>, loc : UInt<2>} T_1423.loc := UInt<1>("h00") T_1423.idx := UInt<1>("h00") T_1423.idx := sdq_alloc_id T_1423.loc := UInt<1>("h00") node T_1428 = cat(T_1423.idx, T_1423.loc) T_1024.io.inner.acquire.bits.data := T_1428 node T_1430 = eq(block_acquires, UInt<1>("h00")) node T_1431 = and(io.inner.acquire.valid, T_1430) node T_1433 = eq(acquire_idx, UInt<2>("h03")) node T_1434 = and(T_1431, T_1433) T_1024.io.inner.acquire.valid := T_1434 T_1055.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1438 : {idx : UInt<2>, loc : UInt<2>} T_1438.loc := UInt<1>("h00") T_1438.idx := UInt<1>("h00") T_1438.idx := sdq_alloc_id T_1438.loc := UInt<1>("h00") node T_1443 = cat(T_1438.idx, T_1438.loc) T_1055.io.inner.acquire.bits.data := T_1443 node T_1445 = eq(block_acquires, UInt<1>("h00")) node T_1446 = and(io.inner.acquire.valid, T_1445) node T_1448 = eq(acquire_idx, UInt<3>("h04")) node T_1449 = and(T_1446, T_1448) T_1055.io.inner.acquire.valid := T_1449 T_1086.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1453 : {idx : UInt<2>, loc : UInt<2>} T_1453.loc := UInt<1>("h00") T_1453.idx := UInt<1>("h00") T_1453.idx := sdq_alloc_id T_1453.loc := UInt<1>("h00") node T_1458 = cat(T_1453.idx, T_1453.loc) T_1086.io.inner.acquire.bits.data := T_1458 node T_1460 = eq(block_acquires, UInt<1>("h00")) node T_1461 = and(io.inner.acquire.valid, T_1460) node T_1463 = eq(acquire_idx, UInt<3>("h05")) node T_1464 = and(T_1461, T_1463) T_1086.io.inner.acquire.valid := T_1464 T_1117.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1468 : {idx : UInt<2>, loc : UInt<2>} T_1468.loc := UInt<1>("h00") T_1468.idx := UInt<1>("h00") T_1468.idx := sdq_alloc_id T_1468.loc := UInt<1>("h00") node T_1473 = cat(T_1468.idx, T_1468.loc) T_1117.io.inner.acquire.bits.data := T_1473 node T_1475 = eq(block_acquires, UInt<1>("h00")) node T_1476 = and(io.inner.acquire.valid, T_1475) node T_1478 = eq(acquire_idx, UInt<3>("h06")) node T_1479 = and(T_1476, T_1478) T_1117.io.inner.acquire.valid := T_1479 T_1148.io.inner.acquire.bits <> io.inner.acquire.bits wire T_1483 : {idx : UInt<2>, loc : UInt<2>} T_1483.loc := UInt<1>("h00") T_1483.idx := UInt<1>("h00") T_1483.idx := sdq_alloc_id T_1483.loc := UInt<1>("h00") node T_1488 = cat(T_1483.idx, T_1483.loc) T_1148.io.inner.acquire.bits.data := T_1488 node T_1490 = eq(block_acquires, UInt<1>("h00")) node T_1491 = and(io.inner.acquire.valid, T_1490) node T_1493 = eq(acquire_idx, UInt<3>("h07")) node T_1494 = and(T_1491, T_1493) T_1148.io.inner.acquire.valid := T_1494 node T_1495 = and(io.inner.release.ready, io.inner.release.valid) node T_1496 = and(T_1495, io.inner.release.bits.voluntary) wire T_1498 : UInt<2>[3] T_1498[0] := UInt<1>("h00") T_1498[1] := UInt<1>("h01") T_1498[2] := UInt<2>("h02") node T_1503 = eq(T_1498[0], io.inner.release.bits.r_type) node T_1504 = eq(T_1498[1], io.inner.release.bits.r_type) node T_1505 = eq(T_1498[2], io.inner.release.bits.r_type) node T_1507 = or(UInt<1>("h00"), T_1503) node T_1508 = or(T_1507, T_1504) node T_1509 = or(T_1508, T_1505) node vwbdq_enq = and(T_1496, T_1509) reg rel_data_cnt : UInt<2>, clock, reset onreset rel_data_cnt := UInt<2>("h00") when vwbdq_enq : node T_1514 = eq(rel_data_cnt, UInt<2>("h03")) node T_1516 = and(UInt<1>("h00"), T_1514) node T_1519 = addw(rel_data_cnt, UInt<1>("h01")) node T_1520 = mux(T_1516, UInt<1>("h00"), T_1519) rel_data_cnt := T_1520 skip node rel_data_done = and(vwbdq_enq, T_1514) reg vwbdq : UInt<128>[4], clock, reset when vwbdq_enq : infer accessor T_1537 = vwbdq[rel_data_cnt] T_1537 := io.inner.release.bits.data skip wire T_1539 : UInt<1>[8] T_1539[0] := T_931.io.inner.release.ready T_1539[1] := T_962.io.inner.release.ready T_1539[2] := T_993.io.inner.release.ready T_1539[3] := T_1024.io.inner.release.ready T_1539[4] := T_1055.io.inner.release.ready T_1539[5] := T_1086.io.inner.release.ready T_1539[6] := T_1117.io.inner.release.ready T_1539[7] := T_1148.io.inner.release.ready node T_1549 = cat(T_1539[7], T_1539[6]) node T_1550 = cat(T_1539[5], T_1539[4]) node T_1551 = cat(T_1549, T_1550) node T_1552 = cat(T_1539[3], T_1539[2]) node T_1553 = cat(T_1539[1], T_1539[0]) node T_1554 = cat(T_1552, T_1553) node releaseReadys = cat(T_1551, T_1554) wire T_1557 : UInt<1>[8] T_1557[0] := T_931.io.has_release_match T_1557[1] := T_962.io.has_release_match T_1557[2] := T_993.io.has_release_match T_1557[3] := T_1024.io.has_release_match T_1557[4] := T_1055.io.has_release_match T_1557[5] := T_1086.io.has_release_match T_1557[6] := T_1117.io.has_release_match T_1557[7] := T_1148.io.has_release_match node T_1567 = cat(T_1557[7], T_1557[6]) node T_1568 = cat(T_1557[5], T_1557[4]) node T_1569 = cat(T_1567, T_1568) node T_1570 = cat(T_1557[3], T_1557[2]) node T_1571 = cat(T_1557[1], T_1557[0]) node T_1572 = cat(T_1570, T_1571) node releaseMatches = cat(T_1569, T_1572) node T_1574 = bit(releaseMatches, 0) node T_1575 = bit(releaseMatches, 1) node T_1576 = bit(releaseMatches, 2) node T_1577 = bit(releaseMatches, 3) node T_1578 = bit(releaseMatches, 4) node T_1579 = bit(releaseMatches, 5) node T_1580 = bit(releaseMatches, 6) node T_1581 = bit(releaseMatches, 7) wire T_1583 : UInt<1>[8] T_1583[0] := T_1574 T_1583[1] := T_1575 T_1583[2] := T_1576 T_1583[3] := T_1577 T_1583[4] := T_1578 T_1583[5] := T_1579 T_1583[6] := T_1580 T_1583[7] := T_1581 node T_1601 = mux(T_1583[6], UInt<3>("h06"), UInt<3>("h07")) node T_1602 = mux(T_1583[5], UInt<3>("h05"), T_1601) node T_1603 = mux(T_1583[4], UInt<3>("h04"), T_1602) node T_1604 = mux(T_1583[3], UInt<2>("h03"), T_1603) node T_1605 = mux(T_1583[2], UInt<2>("h02"), T_1604) node T_1606 = mux(T_1583[1], UInt<1>("h01"), T_1605) node release_idx = mux(T_1583[0], UInt<1>("h00"), T_1606) node T_1608 = dshr(releaseReadys, release_idx) node T_1609 = bit(T_1608, 0) io.inner.release.ready := T_1609 node T_1611 = eq(release_idx, UInt<1>("h00")) node T_1612 = and(io.inner.release.valid, T_1611) T_931.io.inner.release.valid := T_1612 T_931.io.inner.release.bits <> io.inner.release.bits wire T_1616 : {idx : UInt<2>, loc : UInt<2>} T_1616.loc := UInt<1>("h00") T_1616.idx := UInt<1>("h00") T_1616.idx := rel_data_cnt T_1616.loc := UInt<1>("h01") node T_1621 = cat(T_1616.idx, T_1616.loc) T_931.io.inner.release.bits.data := T_1621 node T_1623 = eq(release_idx, UInt<1>("h01")) node T_1624 = and(io.inner.release.valid, T_1623) T_962.io.inner.release.valid := T_1624 T_962.io.inner.release.bits <> io.inner.release.bits wire T_1628 : {idx : UInt<2>, loc : UInt<2>} T_1628.loc := UInt<1>("h00") T_1628.idx := UInt<1>("h00") T_1628.idx := rel_data_cnt T_1628.loc := UInt<2>("h02") node T_1633 = cat(T_1628.idx, T_1628.loc) T_962.io.inner.release.bits.data := T_1633 node T_1635 = eq(release_idx, UInt<2>("h02")) node T_1636 = and(io.inner.release.valid, T_1635) T_993.io.inner.release.valid := T_1636 T_993.io.inner.release.bits <> io.inner.release.bits wire T_1640 : {idx : UInt<2>, loc : UInt<2>} T_1640.loc := UInt<1>("h00") T_1640.idx := UInt<1>("h00") T_1640.idx := rel_data_cnt T_1640.loc := UInt<2>("h02") node T_1645 = cat(T_1640.idx, T_1640.loc) T_993.io.inner.release.bits.data := T_1645 node T_1647 = eq(release_idx, UInt<2>("h03")) node T_1648 = and(io.inner.release.valid, T_1647) T_1024.io.inner.release.valid := T_1648 T_1024.io.inner.release.bits <> io.inner.release.bits wire T_1652 : {idx : UInt<2>, loc : UInt<2>} T_1652.loc := UInt<1>("h00") T_1652.idx := UInt<1>("h00") T_1652.idx := rel_data_cnt T_1652.loc := UInt<2>("h02") node T_1657 = cat(T_1652.idx, T_1652.loc) T_1024.io.inner.release.bits.data := T_1657 node T_1659 = eq(release_idx, UInt<3>("h04")) node T_1660 = and(io.inner.release.valid, T_1659) T_1055.io.inner.release.valid := T_1660 T_1055.io.inner.release.bits <> io.inner.release.bits wire T_1664 : {idx : UInt<2>, loc : UInt<2>} T_1664.loc := UInt<1>("h00") T_1664.idx := UInt<1>("h00") T_1664.idx := rel_data_cnt T_1664.loc := UInt<2>("h02") node T_1669 = cat(T_1664.idx, T_1664.loc) T_1055.io.inner.release.bits.data := T_1669 node T_1671 = eq(release_idx, UInt<3>("h05")) node T_1672 = and(io.inner.release.valid, T_1671) T_1086.io.inner.release.valid := T_1672 T_1086.io.inner.release.bits <> io.inner.release.bits wire T_1676 : {idx : UInt<2>, loc : UInt<2>} T_1676.loc := UInt<1>("h00") T_1676.idx := UInt<1>("h00") T_1676.idx := rel_data_cnt T_1676.loc := UInt<2>("h02") node T_1681 = cat(T_1676.idx, T_1676.loc) T_1086.io.inner.release.bits.data := T_1681 node T_1683 = eq(release_idx, UInt<3>("h06")) node T_1684 = and(io.inner.release.valid, T_1683) T_1117.io.inner.release.valid := T_1684 T_1117.io.inner.release.bits <> io.inner.release.bits wire T_1688 : {idx : UInt<2>, loc : UInt<2>} T_1688.loc := UInt<1>("h00") T_1688.idx := UInt<1>("h00") T_1688.idx := rel_data_cnt T_1688.loc := UInt<2>("h02") node T_1693 = cat(T_1688.idx, T_1688.loc) T_1117.io.inner.release.bits.data := T_1693 node T_1695 = eq(release_idx, UInt<3>("h07")) node T_1696 = and(io.inner.release.valid, T_1695) T_1148.io.inner.release.valid := T_1696 T_1148.io.inner.release.bits <> io.inner.release.bits wire T_1700 : {idx : UInt<2>, loc : UInt<2>} T_1700.loc := UInt<1>("h00") T_1700.idx := UInt<1>("h00") T_1700.idx := rel_data_cnt T_1700.loc := UInt<2>("h02") node T_1705 = cat(T_1700.idx, T_1700.loc) T_1148.io.inner.release.bits.data := T_1705 node T_1707 = neq(releaseMatches, UInt<1>("h00")) node T_1709 = eq(T_1707, UInt<1>("h00")) node T_1710 = and(io.inner.release.valid, T_1709) node T_1712 = eq(T_1710, UInt<1>("h00")) inst T_1713 of LockingRRArbiter_33 T_1713.io.out.ready := UInt<1>("h00") T_1713.io.in[0].bits.client_id := UInt<1>("h00") T_1713.io.in[0].bits.g_type := UInt<1>("h00") T_1713.io.in[0].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[0].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[0].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[0].bits.data := UInt<1>("h00") T_1713.io.in[0].bits.addr_beat := UInt<1>("h00") T_1713.io.in[0].valid := UInt<1>("h00") T_1713.io.in[1].bits.client_id := UInt<1>("h00") T_1713.io.in[1].bits.g_type := UInt<1>("h00") T_1713.io.in[1].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[1].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[1].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[1].bits.data := UInt<1>("h00") T_1713.io.in[1].bits.addr_beat := UInt<1>("h00") T_1713.io.in[1].valid := UInt<1>("h00") T_1713.io.in[2].bits.client_id := UInt<1>("h00") T_1713.io.in[2].bits.g_type := UInt<1>("h00") T_1713.io.in[2].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[2].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[2].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[2].bits.data := UInt<1>("h00") T_1713.io.in[2].bits.addr_beat := UInt<1>("h00") T_1713.io.in[2].valid := UInt<1>("h00") T_1713.io.in[3].bits.client_id := UInt<1>("h00") T_1713.io.in[3].bits.g_type := UInt<1>("h00") T_1713.io.in[3].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[3].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[3].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[3].bits.data := UInt<1>("h00") T_1713.io.in[3].bits.addr_beat := UInt<1>("h00") T_1713.io.in[3].valid := UInt<1>("h00") T_1713.io.in[4].bits.client_id := UInt<1>("h00") T_1713.io.in[4].bits.g_type := UInt<1>("h00") T_1713.io.in[4].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[4].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[4].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[4].bits.data := UInt<1>("h00") T_1713.io.in[4].bits.addr_beat := UInt<1>("h00") T_1713.io.in[4].valid := UInt<1>("h00") T_1713.io.in[5].bits.client_id := UInt<1>("h00") T_1713.io.in[5].bits.g_type := UInt<1>("h00") T_1713.io.in[5].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[5].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[5].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[5].bits.data := UInt<1>("h00") T_1713.io.in[5].bits.addr_beat := UInt<1>("h00") T_1713.io.in[5].valid := UInt<1>("h00") T_1713.io.in[6].bits.client_id := UInt<1>("h00") T_1713.io.in[6].bits.g_type := UInt<1>("h00") T_1713.io.in[6].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[6].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[6].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[6].bits.data := UInt<1>("h00") T_1713.io.in[6].bits.addr_beat := UInt<1>("h00") T_1713.io.in[6].valid := UInt<1>("h00") T_1713.io.in[7].bits.client_id := UInt<1>("h00") T_1713.io.in[7].bits.g_type := UInt<1>("h00") T_1713.io.in[7].bits.is_builtin_type := UInt<1>("h00") T_1713.io.in[7].bits.manager_xact_id := UInt<1>("h00") T_1713.io.in[7].bits.client_xact_id := UInt<1>("h00") T_1713.io.in[7].bits.data := UInt<1>("h00") T_1713.io.in[7].bits.addr_beat := UInt<1>("h00") T_1713.io.in[7].valid := UInt<1>("h00") T_1713.clock := clock T_1713.reset := reset io.inner.grant <> T_1713.io.out T_1713.io.in[0] <> T_931.io.inner.grant T_1713.io.in[1] <> T_962.io.inner.grant T_1713.io.in[2] <> T_993.io.inner.grant T_1713.io.in[3] <> T_1024.io.inner.grant T_1713.io.in[4] <> T_1055.io.inner.grant T_1713.io.in[5] <> T_1086.io.inner.grant T_1713.io.in[6] <> T_1117.io.inner.grant T_1713.io.in[7] <> T_1148.io.inner.grant io.inner.grant.bits.data := io.outer.grant.bits.data io.inner.grant.bits.addr_beat := io.outer.grant.bits.addr_beat inst T_1779 of LockingRRArbiter_34 T_1779.io.out.ready := UInt<1>("h00") T_1779.io.in[0].bits.client_id := UInt<1>("h00") T_1779.io.in[0].bits.p_type := UInt<1>("h00") T_1779.io.in[0].bits.addr_block := UInt<1>("h00") T_1779.io.in[0].valid := UInt<1>("h00") T_1779.io.in[1].bits.client_id := UInt<1>("h00") T_1779.io.in[1].bits.p_type := UInt<1>("h00") T_1779.io.in[1].bits.addr_block := UInt<1>("h00") T_1779.io.in[1].valid := UInt<1>("h00") T_1779.io.in[2].bits.client_id := UInt<1>("h00") T_1779.io.in[2].bits.p_type := UInt<1>("h00") T_1779.io.in[2].bits.addr_block := UInt<1>("h00") T_1779.io.in[2].valid := UInt<1>("h00") T_1779.io.in[3].bits.client_id := UInt<1>("h00") T_1779.io.in[3].bits.p_type := UInt<1>("h00") T_1779.io.in[3].bits.addr_block := UInt<1>("h00") T_1779.io.in[3].valid := UInt<1>("h00") T_1779.io.in[4].bits.client_id := UInt<1>("h00") T_1779.io.in[4].bits.p_type := UInt<1>("h00") T_1779.io.in[4].bits.addr_block := UInt<1>("h00") T_1779.io.in[4].valid := UInt<1>("h00") T_1779.io.in[5].bits.client_id := UInt<1>("h00") T_1779.io.in[5].bits.p_type := UInt<1>("h00") T_1779.io.in[5].bits.addr_block := UInt<1>("h00") T_1779.io.in[5].valid := UInt<1>("h00") T_1779.io.in[6].bits.client_id := UInt<1>("h00") T_1779.io.in[6].bits.p_type := UInt<1>("h00") T_1779.io.in[6].bits.addr_block := UInt<1>("h00") T_1779.io.in[6].valid := UInt<1>("h00") T_1779.io.in[7].bits.client_id := UInt<1>("h00") T_1779.io.in[7].bits.p_type := UInt<1>("h00") T_1779.io.in[7].bits.addr_block := UInt<1>("h00") T_1779.io.in[7].valid := UInt<1>("h00") T_1779.clock := clock T_1779.reset := reset io.inner.probe <> T_1779.io.out T_1779.io.in[0] <> T_931.io.inner.probe T_1779.io.in[1] <> T_962.io.inner.probe T_1779.io.in[2] <> T_993.io.inner.probe T_1779.io.in[3] <> T_1024.io.inner.probe T_1779.io.in[4] <> T_1055.io.inner.probe T_1779.io.in[5] <> T_1086.io.inner.probe T_1779.io.in[6] <> T_1117.io.inner.probe T_1779.io.in[7] <> T_1148.io.inner.probe T_931.io.inner.finish.bits <> io.inner.finish.bits T_962.io.inner.finish.bits <> io.inner.finish.bits T_993.io.inner.finish.bits <> io.inner.finish.bits T_1024.io.inner.finish.bits <> io.inner.finish.bits T_1055.io.inner.finish.bits <> io.inner.finish.bits T_1086.io.inner.finish.bits <> io.inner.finish.bits T_1117.io.inner.finish.bits <> io.inner.finish.bits T_1148.io.inner.finish.bits <> io.inner.finish.bits node T_1814 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) node T_1815 = and(io.inner.finish.valid, T_1814) T_931.io.inner.finish.valid := T_1815 node T_1817 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) node T_1818 = and(io.inner.finish.valid, T_1817) T_962.io.inner.finish.valid := T_1818 node T_1820 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) node T_1821 = and(io.inner.finish.valid, T_1820) T_993.io.inner.finish.valid := T_1821 node T_1823 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) node T_1824 = and(io.inner.finish.valid, T_1823) T_1024.io.inner.finish.valid := T_1824 node T_1826 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) node T_1827 = and(io.inner.finish.valid, T_1826) T_1055.io.inner.finish.valid := T_1827 node T_1829 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) node T_1830 = and(io.inner.finish.valid, T_1829) T_1086.io.inner.finish.valid := T_1830 node T_1832 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) node T_1833 = and(io.inner.finish.valid, T_1832) T_1117.io.inner.finish.valid := T_1833 node T_1835 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) node T_1836 = and(io.inner.finish.valid, T_1835) T_1148.io.inner.finish.valid := T_1836 wire T_1838 : UInt<1>[8] T_1838[0] := T_931.io.inner.finish.ready T_1838[1] := T_962.io.inner.finish.ready T_1838[2] := T_993.io.inner.finish.ready T_1838[3] := T_1024.io.inner.finish.ready T_1838[4] := T_1055.io.inner.finish.ready T_1838[5] := T_1086.io.inner.finish.ready T_1838[6] := T_1117.io.inner.finish.ready T_1838[7] := T_1148.io.inner.finish.ready infer accessor T_1848 = T_1838[io.inner.finish.bits.manager_xact_id] io.inner.finish.ready := T_1848 inst outer_arb of ClientUncachedTileLinkIOArbiter outer_arb.io.out.grant.bits.g_type := UInt<1>("h00") outer_arb.io.out.grant.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.out.grant.bits.manager_xact_id := UInt<1>("h00") outer_arb.io.out.grant.bits.client_xact_id := UInt<1>("h00") outer_arb.io.out.grant.bits.data := UInt<1>("h00") outer_arb.io.out.grant.bits.addr_beat := UInt<1>("h00") outer_arb.io.out.grant.valid := UInt<1>("h00") outer_arb.io.out.acquire.ready := UInt<1>("h00") outer_arb.io.in[0].grant.ready := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[0].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[0].acquire.valid := UInt<1>("h00") outer_arb.io.in[1].grant.ready := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[1].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[1].acquire.valid := UInt<1>("h00") outer_arb.io.in[2].grant.ready := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[2].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[2].acquire.valid := UInt<1>("h00") outer_arb.io.in[3].grant.ready := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[3].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[3].acquire.valid := UInt<1>("h00") outer_arb.io.in[4].grant.ready := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[4].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[4].acquire.valid := UInt<1>("h00") outer_arb.io.in[5].grant.ready := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[5].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[5].acquire.valid := UInt<1>("h00") outer_arb.io.in[6].grant.ready := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[6].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[6].acquire.valid := UInt<1>("h00") outer_arb.io.in[7].grant.ready := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.union := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.a_type := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.is_builtin_type := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.data := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.addr_beat := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.client_xact_id := UInt<1>("h00") outer_arb.io.in[7].acquire.bits.addr_block := UInt<1>("h00") outer_arb.io.in[7].acquire.valid := UInt<1>("h00") outer_arb.clock := clock outer_arb.reset := reset outer_arb.io.in[0] <> T_931.io.outer outer_arb.io.in[1] <> T_962.io.outer outer_arb.io.in[2] <> T_993.io.outer outer_arb.io.in[3] <> T_1024.io.outer outer_arb.io.in[4] <> T_1055.io.outer outer_arb.io.in[5] <> T_1086.io.outer outer_arb.io.in[6] <> T_1117.io.outer outer_arb.io.in[7] <> T_1148.io.outer wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} outer_data_ptr.loc := UInt<1>("h00") outer_data_ptr.idx := UInt<1>("h00") node T_1941 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) outer_data_ptr.loc := T_1941 node T_1942 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) outer_data_ptr.idx := T_1942 node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) node T_1944 = and(io.outer.acquire.ready, io.outer.acquire.valid) wire T_1949 : UInt<3>[3] T_1949[0] := UInt<3>("h02") T_1949[1] := UInt<3>("h03") T_1949[2] := UInt<3>("h04") node T_1954 = eq(T_1949[0], io.outer.acquire.bits.a_type) node T_1955 = eq(T_1949[1], io.outer.acquire.bits.a_type) node T_1956 = eq(T_1949[2], io.outer.acquire.bits.a_type) node T_1958 = or(UInt<1>("h00"), T_1954) node T_1959 = or(T_1958, T_1955) node T_1960 = or(T_1959, T_1956) node T_1961 = and(io.outer.acquire.bits.is_builtin_type, T_1960) node T_1962 = and(T_1944, T_1961) node T_1963 = eq(outer_data_ptr.loc, UInt<1>("h00")) node free_sdq = and(T_1962, T_1963) io.outer <> outer_arb.io.out infer accessor T_1965 = sdq[outer_data_ptr.idx] infer accessor T_1966 = vwbdq[outer_data_ptr.idx] node T_1967 = eq(UInt<1>("h01"), outer_data_ptr.loc) node T_1968 = mux(T_1967, T_1966, io.inner.release.bits.data) node T_1969 = eq(UInt<1>("h00"), outer_data_ptr.loc) node T_1970 = mux(T_1969, T_1965, T_1968) io.outer.acquire.bits.data := T_1970 node T_1971 = or(io.outer.acquire.valid, sdq_enq) when T_1971 : node T_1973 = dshl(UInt<1>("h01"), outer_data_ptr.idx) node T_1975 = subw(UInt<4>("h00"), free_sdq) node T_1976 = and(T_1973, T_1975) node T_1977 = not(T_1976) node T_1978 = and(sdq_val, T_1977) node T_1979 = bits(sdq_val, 3, 0) node T_1980 = not(T_1979) node T_1981 = bit(T_1980, 0) node T_1982 = bit(T_1980, 1) node T_1983 = bit(T_1980, 2) node T_1984 = bit(T_1980, 3) wire T_1990 : UInt<4>[4] T_1990[0] := UInt<4>("h01") T_1990[1] := UInt<4>("h02") T_1990[2] := UInt<4>("h04") T_1990[3] := UInt<4>("h08") node T_1998 = mux(T_1984, T_1990[3], UInt<4>("h00")) node T_1999 = mux(T_1983, T_1990[2], T_1998) node T_2000 = mux(T_1982, T_1990[1], T_1999) node T_2001 = mux(T_1981, T_1990[0], T_2000) node T_2003 = subw(UInt<4>("h00"), sdq_enq) node T_2004 = and(T_2001, T_2003) node T_2005 = or(T_1978, T_2004) sdq_val := T_2005 skip module Queue_36 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.user := UInt<1>("h00") io.deq.bits.id := UInt<1>("h00") io.deq.bits.region := UInt<1>("h00") io.deq.bits.qos := UInt<1>("h00") io.deq.bits.prot := UInt<1>("h00") io.deq.bits.cache := UInt<1>("h00") io.deq.bits.lock := UInt<1>("h00") io.deq.bits.burst := UInt<1>("h00") io.deq.bits.size := UInt<1>("h00") io.deq.bits.len := UInt<1>("h00") io.deq.bits.addr := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}[2], clock reg T_125 : UInt<1>, clock, reset onreset T_125 := UInt<1>("h00") reg T_127 : UInt<1>, clock, reset onreset T_127 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_125, T_127) node T_132 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_132) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_138 = and(io.enq.ready, io.enq.valid) node T_140 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_138, T_140) node T_142 = and(io.deq.ready, io.deq.valid) node T_144 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_142, T_144) when do_enq : infer accessor T_146 = ram[T_125] T_146 <> io.enq.bits node T_159 = eq(T_125, UInt<1>("h01")) node T_161 = and(UInt<1>("h00"), T_159) node T_164 = addw(T_125, UInt<1>("h01")) node T_165 = mux(T_161, UInt<1>("h00"), T_164) T_125 := T_165 skip when do_deq : node T_167 = eq(T_127, UInt<1>("h01")) node T_169 = and(UInt<1>("h00"), T_167) node T_172 = addw(T_127, UInt<1>("h01")) node T_173 = mux(T_169, UInt<1>("h00"), T_172) T_127 := T_173 skip node T_174 = neq(do_enq, do_deq) when T_174 : maybe_full := do_enq skip node T_176 = eq(empty, UInt<1>("h00")) node T_178 = and(UInt<1>("h00"), io.enq.valid) node T_179 = or(T_176, T_178) io.deq.valid := T_179 node T_181 = eq(full, UInt<1>("h00")) node T_183 = and(UInt<1>("h00"), io.deq.ready) node T_184 = or(T_181, T_183) io.enq.ready := T_184 infer accessor T_185 = ram[T_127] wire T_209 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>} T_209 <> T_185 when maybe_flow : T_209 <> io.enq.bits skip io.deq.bits <> T_209 node ptr_diff = subw(T_125, T_127) node T_222 = and(maybe_full, ptr_match) node T_223 = cat(T_222, ptr_diff) io.count := T_223 module Queue_37 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : UInt<6>[2], clock reg T_26 : UInt<1>, clock, reset onreset T_26 := UInt<1>("h00") reg T_28 : UInt<1>, clock, reset onreset T_28 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_39 = and(io.enq.ready, io.enq.valid) node T_41 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_39, T_41) node T_43 = and(io.deq.ready, io.deq.valid) node T_45 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_43, T_45) when do_enq : infer accessor T_47 = ram[T_26] T_47 := io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) node T_54 = addw(T_26, UInt<1>("h01")) node T_55 = mux(T_51, UInt<1>("h00"), T_54) T_26 := T_55 skip when do_deq : node T_57 = eq(T_28, UInt<1>("h01")) node T_59 = and(UInt<1>("h00"), T_57) node T_62 = addw(T_28, UInt<1>("h01")) node T_63 = mux(T_59, UInt<1>("h00"), T_62) T_28 := T_63 skip node T_64 = neq(do_enq, do_deq) when T_64 : maybe_full := do_enq skip node T_66 = eq(empty, UInt<1>("h00")) node T_68 = and(UInt<1>("h00"), io.enq.valid) node T_69 = or(T_66, T_68) io.deq.valid := T_69 node T_71 = eq(full, UInt<1>("h00")) node T_73 = and(UInt<1>("h00"), io.deq.ready) node T_74 = or(T_71, T_73) io.enq.ready := T_74 infer accessor T_75 = ram[T_28] node T_76 = mux(maybe_flow, io.enq.bits, T_75) io.deq.bits := T_76 node ptr_diff = subw(T_26, T_28) node T_78 = and(maybe_full, ptr_match) node T_79 = cat(T_78, ptr_diff) io.count := T_79 module NASTIErrorSlave : input clock : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}} io.r.bits.user := UInt<1>("h00") io.r.bits.id := UInt<1>("h00") io.r.bits.last := UInt<1>("h00") io.r.bits.data := UInt<1>("h00") io.r.bits.resp := UInt<1>("h00") io.r.valid := UInt<1>("h00") io.ar.ready := UInt<1>("h00") io.b.bits.user := UInt<1>("h00") io.b.bits.id := UInt<1>("h00") io.b.bits.resp := UInt<1>("h00") io.b.valid := UInt<1>("h00") io.w.ready := UInt<1>("h00") io.aw.ready := UInt<1>("h00") node T_322 = and(io.ar.ready, io.ar.valid) when T_322 : skip node T_323 = and(io.aw.ready, io.aw.valid) when T_323 : skip inst r_queue of Queue_36 r_queue.io.deq.ready := UInt<1>("h00") r_queue.io.enq.bits.user := UInt<1>("h00") r_queue.io.enq.bits.id := UInt<1>("h00") r_queue.io.enq.bits.region := UInt<1>("h00") r_queue.io.enq.bits.qos := UInt<1>("h00") r_queue.io.enq.bits.prot := UInt<1>("h00") r_queue.io.enq.bits.cache := UInt<1>("h00") r_queue.io.enq.bits.lock := UInt<1>("h00") r_queue.io.enq.bits.burst := UInt<1>("h00") r_queue.io.enq.bits.size := UInt<1>("h00") r_queue.io.enq.bits.len := UInt<1>("h00") r_queue.io.enq.bits.addr := UInt<1>("h00") r_queue.io.enq.valid := UInt<1>("h00") r_queue.clock := clock r_queue.reset := reset r_queue.io.enq <> io.ar reg responding : UInt<1>, clock, reset onreset responding := UInt<1>("h00") reg beats_left : UInt<8>, clock, reset onreset beats_left := UInt<8>("h00") node T_355 = eq(responding, UInt<1>("h00")) node T_356 = and(T_355, r_queue.io.deq.valid) when T_356 : responding := UInt<1>("h01") beats_left := r_queue.io.deq.bits.len skip node T_358 = and(r_queue.io.deq.valid, responding) io.r.valid := T_358 io.r.bits.id := r_queue.io.deq.bits.id io.r.bits.data := UInt<1>("h00") io.r.bits.resp := UInt<2>("h03") node T_362 = eq(beats_left, UInt<1>("h00")) io.r.bits.last := T_362 node T_363 = and(io.r.ready, io.r.valid) node T_364 = and(T_363, io.r.bits.last) r_queue.io.deq.ready := T_364 node T_365 = and(io.r.ready, io.r.valid) when T_365 : node T_367 = eq(beats_left, UInt<1>("h00")) when T_367 : responding := UInt<1>("h00") skip else : node T_370 = subw(beats_left, UInt<1>("h00")) beats_left := T_370 skip skip reg draining : UInt<1>, clock, reset onreset draining := UInt<1>("h00") io.w.ready := draining node T_373 = and(io.aw.ready, io.aw.valid) when T_373 : draining := UInt<1>("h01") skip node T_375 = and(io.w.ready, io.w.valid) node T_376 = and(T_375, io.w.bits.last) when T_376 : draining := UInt<1>("h00") skip inst b_queue of Queue_37 b_queue.io.deq.ready := UInt<1>("h00") b_queue.io.enq.bits := UInt<1>("h00") b_queue.io.enq.valid := UInt<1>("h00") b_queue.clock := clock b_queue.reset := reset node T_384 = eq(draining, UInt<1>("h00")) node T_385 = and(io.aw.valid, T_384) b_queue.io.enq.valid := T_385 b_queue.io.enq.bits := io.aw.bits.id node T_387 = eq(draining, UInt<1>("h00")) node T_388 = and(b_queue.io.enq.ready, T_387) io.aw.ready := T_388 node T_390 = eq(draining, UInt<1>("h00")) node T_391 = and(b_queue.io.deq.valid, T_390) io.b.valid := T_391 io.b.bits.id := b_queue.io.deq.bits io.b.bits.resp := UInt<2>("h03") node T_394 = eq(draining, UInt<1>("h00")) node T_395 = and(io.b.ready, T_394) b_queue.io.deq.ready := T_395 module RRArbiter_38 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.user := UInt<1>("h00") io.out.bits.id := UInt<1>("h00") io.out.bits.resp := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") wire T_174 : UInt<2> T_174 := UInt<1>("h00") infer accessor T_176 = io.in[T_174] io.out.valid := T_176.valid infer accessor T_187 = io.in[T_174] io.out.bits <> T_187.bits io.chosen := T_174 infer accessor T_198 = io.in[T_174] T_198.ready := UInt<1>("h00") reg T_212 : UInt<2>, clock, reset onreset T_212 := UInt<2>("h00") node T_213 = gt(UInt<1>("h00"), T_212) node T_214 = and(io.in[0].valid, T_213) node T_216 = gt(UInt<1>("h01"), T_212) node T_217 = and(io.in[1].valid, T_216) node T_219 = gt(UInt<2>("h02"), T_212) node T_220 = and(io.in[2].valid, T_219) node T_222 = gt(UInt<2>("h03"), T_212) node T_223 = and(io.in[3].valid, T_222) node T_226 = or(UInt<1>("h00"), T_214) node T_228 = eq(T_226, UInt<1>("h00")) node T_230 = or(UInt<1>("h00"), T_214) node T_231 = or(T_230, T_217) node T_233 = eq(T_231, UInt<1>("h00")) node T_235 = or(UInt<1>("h00"), T_214) node T_236 = or(T_235, T_217) node T_237 = or(T_236, T_220) node T_239 = eq(T_237, UInt<1>("h00")) node T_241 = or(UInt<1>("h00"), T_214) node T_242 = or(T_241, T_217) node T_243 = or(T_242, T_220) node T_244 = or(T_243, T_223) node T_246 = eq(T_244, UInt<1>("h00")) node T_248 = or(UInt<1>("h00"), T_214) node T_249 = or(T_248, T_217) node T_250 = or(T_249, T_220) node T_251 = or(T_250, T_223) node T_252 = or(T_251, io.in[0].valid) node T_254 = eq(T_252, UInt<1>("h00")) node T_256 = or(UInt<1>("h00"), T_214) node T_257 = or(T_256, T_217) node T_258 = or(T_257, T_220) node T_259 = or(T_258, T_223) node T_260 = or(T_259, io.in[0].valid) node T_261 = or(T_260, io.in[1].valid) node T_263 = eq(T_261, UInt<1>("h00")) node T_265 = or(UInt<1>("h00"), T_214) node T_266 = or(T_265, T_217) node T_267 = or(T_266, T_220) node T_268 = or(T_267, T_223) node T_269 = or(T_268, io.in[0].valid) node T_270 = or(T_269, io.in[1].valid) node T_271 = or(T_270, io.in[2].valid) node T_273 = eq(T_271, UInt<1>("h00")) node T_275 = gt(UInt<1>("h00"), T_212) node T_276 = and(UInt<1>("h01"), T_275) node T_277 = or(T_276, T_246) node T_279 = gt(UInt<1>("h01"), T_212) node T_280 = and(T_228, T_279) node T_281 = or(T_280, T_254) node T_283 = gt(UInt<2>("h02"), T_212) node T_284 = and(T_233, T_283) node T_285 = or(T_284, T_263) node T_287 = gt(UInt<2>("h03"), T_212) node T_288 = and(T_239, T_287) node T_289 = or(T_288, T_273) node T_291 = eq(UInt<2>("h03"), UInt<1>("h00")) node T_292 = mux(UInt<1>("h00"), T_291, T_277) node T_293 = and(T_292, io.out.ready) io.in[0].ready := T_293 node T_295 = eq(UInt<2>("h03"), UInt<1>("h01")) node T_296 = mux(UInt<1>("h00"), T_295, T_281) node T_297 = and(T_296, io.out.ready) io.in[1].ready := T_297 node T_299 = eq(UInt<2>("h03"), UInt<2>("h02")) node T_300 = mux(UInt<1>("h00"), T_299, T_285) node T_301 = and(T_300, io.out.ready) io.in[2].ready := T_301 node T_303 = eq(UInt<2>("h03"), UInt<2>("h03")) node T_304 = mux(UInt<1>("h00"), T_303, T_289) node T_305 = and(T_304, io.out.ready) io.in[3].ready := T_305 node T_308 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) node T_310 = mux(io.in[1].valid, UInt<1>("h01"), T_308) node T_312 = mux(io.in[0].valid, UInt<1>("h00"), T_310) node T_314 = gt(UInt<2>("h03"), T_212) node T_315 = and(io.in[3].valid, T_314) node T_317 = mux(T_315, UInt<2>("h03"), T_312) node T_319 = gt(UInt<2>("h02"), T_212) node T_320 = and(io.in[2].valid, T_319) node T_322 = mux(T_320, UInt<2>("h02"), T_317) node T_324 = gt(UInt<1>("h01"), T_212) node T_325 = and(io.in[1].valid, T_324) node T_327 = mux(T_325, UInt<1>("h01"), T_322) node T_328 = mux(UInt<1>("h00"), UInt<2>("h03"), T_327) T_174 := T_328 node T_329 = and(io.out.ready, io.out.valid) when T_329 : T_212 := T_174 skip module NASTIReadDataArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}} io.out.bits.user := UInt<1>("h00") io.out.bits.id := UInt<1>("h00") io.out.bits.last := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.resp := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") reg lockIdx : UInt<2>, clock, reset onreset lockIdx := UInt<2>("h00") reg locked : UInt<1>, clock, reset onreset locked := UInt<1>("h00") wire T_248 : UInt<1>[4] T_248[0] := io.in[0].valid T_248[1] := io.in[1].valid T_248[2] := io.in[2].valid T_248[3] := io.in[3].valid node T_255 = addw(lockIdx, UInt<1>("h01")) node T_257 = lt(T_255, UInt<3>("h04")) node T_259 = addw(UInt<1>("h00"), T_255) infer accessor T_260 = T_248[T_259] node T_262 = subw(T_255, UInt<3>("h04")) infer accessor T_263 = T_248[T_262] node T_264 = mux(T_257, T_260, T_263) node T_266 = lt(T_255, UInt<2>("h03")) node T_268 = addw(UInt<1>("h01"), T_255) infer accessor T_269 = T_248[T_268] node T_271 = subw(T_255, UInt<2>("h03")) infer accessor T_272 = T_248[T_271] node T_273 = mux(T_266, T_269, T_272) node T_275 = lt(T_255, UInt<2>("h02")) node T_277 = addw(UInt<2>("h02"), T_255) infer accessor T_278 = T_248[T_277] node T_280 = subw(T_255, UInt<2>("h02")) infer accessor T_281 = T_248[T_280] node T_282 = mux(T_275, T_278, T_281) node T_284 = lt(T_255, UInt<1>("h01")) node T_286 = addw(UInt<2>("h03"), T_255) infer accessor T_287 = T_248[T_286] node T_289 = subw(T_255, UInt<1>("h01")) infer accessor T_290 = T_248[T_289] node T_291 = mux(T_284, T_287, T_290) wire T_293 : UInt<1>[4] T_293[0] := T_264 T_293[1] := T_273 T_293[2] := T_282 T_293[3] := T_291 wire T_304 : UInt<2>[4] T_304[0] := UInt<1>("h00") T_304[1] := UInt<1>("h01") T_304[2] := UInt<2>("h02") T_304[3] := UInt<2>("h03") node T_311 = addw(lockIdx, UInt<1>("h01")) node T_313 = lt(T_311, UInt<3>("h04")) node T_315 = addw(UInt<1>("h00"), T_311) infer accessor T_316 = T_304[T_315] node T_318 = subw(T_311, UInt<3>("h04")) infer accessor T_319 = T_304[T_318] node T_320 = mux(T_313, T_316, T_319) node T_322 = lt(T_311, UInt<2>("h03")) node T_324 = addw(UInt<1>("h01"), T_311) infer accessor T_325 = T_304[T_324] node T_327 = subw(T_311, UInt<2>("h03")) infer accessor T_328 = T_304[T_327] node T_329 = mux(T_322, T_325, T_328) node T_331 = lt(T_311, UInt<2>("h02")) node T_333 = addw(UInt<2>("h02"), T_311) infer accessor T_334 = T_304[T_333] node T_336 = subw(T_311, UInt<2>("h02")) infer accessor T_337 = T_304[T_336] node T_338 = mux(T_331, T_334, T_337) node T_340 = lt(T_311, UInt<1>("h01")) node T_342 = addw(UInt<2>("h03"), T_311) infer accessor T_343 = T_304[T_342] node T_345 = subw(T_311, UInt<1>("h01")) infer accessor T_346 = T_304[T_345] node T_347 = mux(T_340, T_343, T_346) wire T_349 : UInt<2>[4] T_349[0] := T_320 T_349[1] := T_329 T_349[2] := T_338 T_349[3] := T_347 node T_355 = mux(T_293[2], T_349[2], T_349[3]) node T_356 = mux(T_293[1], T_349[1], T_355) node choice = mux(T_293[0], T_349[0], T_356) node chosen = mux(locked, lockIdx, choice) node T_360 = eq(chosen, UInt<1>("h00")) node T_361 = and(io.out.ready, T_360) io.in[0].ready := T_361 node T_363 = eq(chosen, UInt<1>("h01")) node T_364 = and(io.out.ready, T_363) io.in[1].ready := T_364 node T_366 = eq(chosen, UInt<2>("h02")) node T_367 = and(io.out.ready, T_366) io.in[2].ready := T_367 node T_369 = eq(chosen, UInt<2>("h03")) node T_370 = and(io.out.ready, T_369) io.in[3].ready := T_370 infer accessor T_371 = io.in[chosen] io.out.valid := T_371.valid infer accessor T_386 = io.in[chosen] io.out.bits <> T_386.bits node T_401 = and(io.out.ready, io.out.valid) when T_401 : node T_403 = eq(locked, UInt<1>("h00")) when T_403 : lockIdx := choice node T_405 = eq(io.out.bits.last, UInt<1>("h00")) locked := T_405 skip else : when io.out.bits.last : locked := UInt<1>("h00") skip skip skip module NASTIRouter : input clock : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[3]} io.slave[0].r.ready := UInt<1>("h00") io.slave[0].ar.bits.user := UInt<1>("h00") io.slave[0].ar.bits.id := UInt<1>("h00") io.slave[0].ar.bits.region := UInt<1>("h00") io.slave[0].ar.bits.qos := UInt<1>("h00") io.slave[0].ar.bits.prot := UInt<1>("h00") io.slave[0].ar.bits.cache := UInt<1>("h00") io.slave[0].ar.bits.lock := UInt<1>("h00") io.slave[0].ar.bits.burst := UInt<1>("h00") io.slave[0].ar.bits.size := UInt<1>("h00") io.slave[0].ar.bits.len := UInt<1>("h00") io.slave[0].ar.bits.addr := UInt<1>("h00") io.slave[0].ar.valid := UInt<1>("h00") io.slave[0].b.ready := UInt<1>("h00") io.slave[0].w.bits.user := UInt<1>("h00") io.slave[0].w.bits.strb := UInt<1>("h00") io.slave[0].w.bits.last := UInt<1>("h00") io.slave[0].w.bits.data := UInt<1>("h00") io.slave[0].w.valid := UInt<1>("h00") io.slave[0].aw.bits.user := UInt<1>("h00") io.slave[0].aw.bits.id := UInt<1>("h00") io.slave[0].aw.bits.region := UInt<1>("h00") io.slave[0].aw.bits.qos := UInt<1>("h00") io.slave[0].aw.bits.prot := UInt<1>("h00") io.slave[0].aw.bits.cache := UInt<1>("h00") io.slave[0].aw.bits.lock := UInt<1>("h00") io.slave[0].aw.bits.burst := UInt<1>("h00") io.slave[0].aw.bits.size := UInt<1>("h00") io.slave[0].aw.bits.len := UInt<1>("h00") io.slave[0].aw.bits.addr := UInt<1>("h00") io.slave[0].aw.valid := UInt<1>("h00") io.slave[1].r.ready := UInt<1>("h00") io.slave[1].ar.bits.user := UInt<1>("h00") io.slave[1].ar.bits.id := UInt<1>("h00") io.slave[1].ar.bits.region := UInt<1>("h00") io.slave[1].ar.bits.qos := UInt<1>("h00") io.slave[1].ar.bits.prot := UInt<1>("h00") io.slave[1].ar.bits.cache := UInt<1>("h00") io.slave[1].ar.bits.lock := UInt<1>("h00") io.slave[1].ar.bits.burst := UInt<1>("h00") io.slave[1].ar.bits.size := UInt<1>("h00") io.slave[1].ar.bits.len := UInt<1>("h00") io.slave[1].ar.bits.addr := UInt<1>("h00") io.slave[1].ar.valid := UInt<1>("h00") io.slave[1].b.ready := UInt<1>("h00") io.slave[1].w.bits.user := UInt<1>("h00") io.slave[1].w.bits.strb := UInt<1>("h00") io.slave[1].w.bits.last := UInt<1>("h00") io.slave[1].w.bits.data := UInt<1>("h00") io.slave[1].w.valid := UInt<1>("h00") io.slave[1].aw.bits.user := UInt<1>("h00") io.slave[1].aw.bits.id := UInt<1>("h00") io.slave[1].aw.bits.region := UInt<1>("h00") io.slave[1].aw.bits.qos := UInt<1>("h00") io.slave[1].aw.bits.prot := UInt<1>("h00") io.slave[1].aw.bits.cache := UInt<1>("h00") io.slave[1].aw.bits.lock := UInt<1>("h00") io.slave[1].aw.bits.burst := UInt<1>("h00") io.slave[1].aw.bits.size := UInt<1>("h00") io.slave[1].aw.bits.len := UInt<1>("h00") io.slave[1].aw.bits.addr := UInt<1>("h00") io.slave[1].aw.valid := UInt<1>("h00") io.slave[2].r.ready := UInt<1>("h00") io.slave[2].ar.bits.user := UInt<1>("h00") io.slave[2].ar.bits.id := UInt<1>("h00") io.slave[2].ar.bits.region := UInt<1>("h00") io.slave[2].ar.bits.qos := UInt<1>("h00") io.slave[2].ar.bits.prot := UInt<1>("h00") io.slave[2].ar.bits.cache := UInt<1>("h00") io.slave[2].ar.bits.lock := UInt<1>("h00") io.slave[2].ar.bits.burst := UInt<1>("h00") io.slave[2].ar.bits.size := UInt<1>("h00") io.slave[2].ar.bits.len := UInt<1>("h00") io.slave[2].ar.bits.addr := UInt<1>("h00") io.slave[2].ar.valid := UInt<1>("h00") io.slave[2].b.ready := UInt<1>("h00") io.slave[2].w.bits.user := UInt<1>("h00") io.slave[2].w.bits.strb := UInt<1>("h00") io.slave[2].w.bits.last := UInt<1>("h00") io.slave[2].w.bits.data := UInt<1>("h00") io.slave[2].w.valid := UInt<1>("h00") io.slave[2].aw.bits.user := UInt<1>("h00") io.slave[2].aw.bits.id := UInt<1>("h00") io.slave[2].aw.bits.region := UInt<1>("h00") io.slave[2].aw.bits.qos := UInt<1>("h00") io.slave[2].aw.bits.prot := UInt<1>("h00") io.slave[2].aw.bits.cache := UInt<1>("h00") io.slave[2].aw.bits.lock := UInt<1>("h00") io.slave[2].aw.bits.burst := UInt<1>("h00") io.slave[2].aw.bits.size := UInt<1>("h00") io.slave[2].aw.bits.len := UInt<1>("h00") io.slave[2].aw.bits.addr := UInt<1>("h00") io.slave[2].aw.valid := UInt<1>("h00") io.master.r.bits.user := UInt<1>("h00") io.master.r.bits.id := UInt<1>("h00") io.master.r.bits.last := UInt<1>("h00") io.master.r.bits.data := UInt<1>("h00") io.master.r.bits.resp := UInt<1>("h00") io.master.r.valid := UInt<1>("h00") io.master.ar.ready := UInt<1>("h00") io.master.b.bits.user := UInt<1>("h00") io.master.b.bits.id := UInt<1>("h00") io.master.b.bits.resp := UInt<1>("h00") io.master.b.valid := UInt<1>("h00") io.master.w.ready := UInt<1>("h00") io.master.aw.ready := UInt<1>("h00") node T_1283 = geq(io.master.ar.bits.addr, UInt<1>("h00")) node T_1285 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1286 = and(T_1283, T_1285) node T_1287 = and(io.master.ar.valid, T_1286) io.slave[0].ar.valid := T_1287 io.slave[0].ar.bits <> io.master.ar.bits node T_1288 = and(io.slave[0].ar.ready, T_1286) node T_1289 = or(UInt<1>("h00"), T_1288) node T_1290 = or(UInt<1>("h00"), T_1286) node T_1292 = geq(io.master.aw.bits.addr, UInt<1>("h00")) node T_1294 = lt(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1295 = and(T_1292, T_1294) node T_1296 = and(io.master.aw.valid, T_1295) io.slave[0].aw.valid := T_1296 io.slave[0].aw.bits <> io.master.aw.bits node T_1297 = and(io.slave[0].aw.ready, T_1295) node T_1298 = or(UInt<1>("h00"), T_1297) node T_1299 = or(UInt<1>("h00"), T_1295) reg T_1301 : UInt<1>, clock, reset onreset T_1301 := UInt<1>("h00") node T_1302 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1302 : T_1301 := UInt<1>("h01") skip node T_1304 = and(io.slave[0].w.ready, io.slave[0].w.valid) node T_1305 = and(T_1304, io.slave[0].w.bits.last) when T_1305 : T_1301 := UInt<1>("h00") skip node T_1307 = and(io.master.w.valid, T_1301) io.slave[0].w.valid := T_1307 io.slave[0].w.bits <> io.master.w.bits node T_1308 = and(io.slave[0].w.ready, T_1301) node T_1309 = or(UInt<1>("h00"), T_1308) node T_1311 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1313 = lt(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1314 = and(T_1311, T_1313) node T_1315 = and(io.master.ar.valid, T_1314) io.slave[1].ar.valid := T_1315 io.slave[1].ar.bits <> io.master.ar.bits node T_1316 = and(io.slave[1].ar.ready, T_1314) node T_1317 = or(T_1289, T_1316) node T_1318 = or(T_1290, T_1314) node T_1320 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1322 = lt(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1323 = and(T_1320, T_1322) node T_1324 = and(io.master.aw.valid, T_1323) io.slave[1].aw.valid := T_1324 io.slave[1].aw.bits <> io.master.aw.bits node T_1325 = and(io.slave[1].aw.ready, T_1323) node T_1326 = or(T_1298, T_1325) node T_1327 = or(T_1299, T_1323) reg T_1329 : UInt<1>, clock, reset onreset T_1329 := UInt<1>("h00") node T_1330 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1330 : T_1329 := UInt<1>("h01") skip node T_1332 = and(io.slave[1].w.ready, io.slave[1].w.valid) node T_1333 = and(T_1332, io.slave[1].w.bits.last) when T_1333 : T_1329 := UInt<1>("h00") skip node T_1335 = and(io.master.w.valid, T_1329) io.slave[1].w.valid := T_1335 io.slave[1].w.bits <> io.master.w.bits node T_1336 = and(io.slave[1].w.ready, T_1329) node T_1337 = or(T_1309, T_1336) node T_1339 = geq(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1341 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000")) node T_1342 = and(T_1339, T_1341) node T_1343 = and(io.master.ar.valid, T_1342) io.slave[2].ar.valid := T_1343 io.slave[2].ar.bits <> io.master.ar.bits node T_1344 = and(io.slave[2].ar.ready, T_1342) node ar_ready = or(T_1317, T_1344) node r_valid_addr = or(T_1318, T_1342) node T_1348 = geq(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1350 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000")) node T_1351 = and(T_1348, T_1350) node T_1352 = and(io.master.aw.valid, T_1351) io.slave[2].aw.valid := T_1352 io.slave[2].aw.bits <> io.master.aw.bits node T_1353 = and(io.slave[2].aw.ready, T_1351) node aw_ready = or(T_1326, T_1353) node w_valid_addr = or(T_1327, T_1351) reg T_1357 : UInt<1>, clock, reset onreset T_1357 := UInt<1>("h00") node T_1358 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1358 : T_1357 := UInt<1>("h01") skip node T_1360 = and(io.slave[2].w.ready, io.slave[2].w.valid) node T_1361 = and(T_1360, io.slave[2].w.bits.last) when T_1361 : T_1357 := UInt<1>("h00") skip node T_1363 = and(io.master.w.valid, T_1357) io.slave[2].w.valid := T_1363 io.slave[2].w.bits <> io.master.w.bits node T_1364 = and(io.slave[2].w.ready, T_1357) node w_ready = or(T_1337, T_1364) inst err_slave of NASTIErrorSlave err_slave.io.r.ready := UInt<1>("h00") err_slave.io.ar.bits.user := UInt<1>("h00") err_slave.io.ar.bits.id := UInt<1>("h00") err_slave.io.ar.bits.region := UInt<1>("h00") err_slave.io.ar.bits.qos := UInt<1>("h00") err_slave.io.ar.bits.prot := UInt<1>("h00") err_slave.io.ar.bits.cache := UInt<1>("h00") err_slave.io.ar.bits.lock := UInt<1>("h00") err_slave.io.ar.bits.burst := UInt<1>("h00") err_slave.io.ar.bits.size := UInt<1>("h00") err_slave.io.ar.bits.len := UInt<1>("h00") err_slave.io.ar.bits.addr := UInt<1>("h00") err_slave.io.ar.valid := UInt<1>("h00") err_slave.io.b.ready := UInt<1>("h00") err_slave.io.w.bits.user := UInt<1>("h00") err_slave.io.w.bits.strb := UInt<1>("h00") err_slave.io.w.bits.last := UInt<1>("h00") err_slave.io.w.bits.data := UInt<1>("h00") err_slave.io.w.valid := UInt<1>("h00") err_slave.io.aw.bits.user := UInt<1>("h00") err_slave.io.aw.bits.id := UInt<1>("h00") err_slave.io.aw.bits.region := UInt<1>("h00") err_slave.io.aw.bits.qos := UInt<1>("h00") err_slave.io.aw.bits.prot := UInt<1>("h00") err_slave.io.aw.bits.cache := UInt<1>("h00") err_slave.io.aw.bits.lock := UInt<1>("h00") err_slave.io.aw.bits.burst := UInt<1>("h00") err_slave.io.aw.bits.size := UInt<1>("h00") err_slave.io.aw.bits.len := UInt<1>("h00") err_slave.io.aw.bits.addr := UInt<1>("h00") err_slave.io.aw.valid := UInt<1>("h00") err_slave.clock := clock err_slave.reset := reset node T_1399 = eq(r_valid_addr, UInt<1>("h00")) node T_1400 = and(T_1399, io.master.ar.valid) err_slave.io.ar.valid := T_1400 err_slave.io.ar.bits <> io.master.ar.bits node T_1402 = eq(w_valid_addr, UInt<1>("h00")) node T_1403 = and(T_1402, io.master.aw.valid) err_slave.io.aw.valid := T_1403 err_slave.io.aw.bits <> io.master.aw.bits err_slave.io.w.valid := io.master.w.valid err_slave.io.w.bits <> io.master.w.bits node T_1405 = eq(r_valid_addr, UInt<1>("h00")) node T_1406 = and(T_1405, err_slave.io.ar.ready) node T_1407 = or(ar_ready, T_1406) io.master.ar.ready := T_1407 node T_1409 = eq(w_valid_addr, UInt<1>("h00")) node T_1410 = and(T_1409, err_slave.io.aw.ready) node T_1411 = or(aw_ready, T_1410) io.master.aw.ready := T_1411 node T_1412 = or(w_ready, err_slave.io.w.ready) io.master.w.ready := T_1412 inst b_arb of RRArbiter_38 b_arb.io.out.ready := UInt<1>("h00") b_arb.io.in[0].bits.user := UInt<1>("h00") b_arb.io.in[0].bits.id := UInt<1>("h00") b_arb.io.in[0].bits.resp := UInt<1>("h00") b_arb.io.in[0].valid := UInt<1>("h00") b_arb.io.in[1].bits.user := UInt<1>("h00") b_arb.io.in[1].bits.id := UInt<1>("h00") b_arb.io.in[1].bits.resp := UInt<1>("h00") b_arb.io.in[1].valid := UInt<1>("h00") b_arb.io.in[2].bits.user := UInt<1>("h00") b_arb.io.in[2].bits.id := UInt<1>("h00") b_arb.io.in[2].bits.resp := UInt<1>("h00") b_arb.io.in[2].valid := UInt<1>("h00") b_arb.io.in[3].bits.user := UInt<1>("h00") b_arb.io.in[3].bits.id := UInt<1>("h00") b_arb.io.in[3].bits.resp := UInt<1>("h00") b_arb.io.in[3].valid := UInt<1>("h00") b_arb.clock := clock b_arb.reset := reset inst r_arb of NASTIReadDataArbiter r_arb.io.out.ready := UInt<1>("h00") r_arb.io.in[0].bits.user := UInt<1>("h00") r_arb.io.in[0].bits.id := UInt<1>("h00") r_arb.io.in[0].bits.last := UInt<1>("h00") r_arb.io.in[0].bits.data := UInt<1>("h00") r_arb.io.in[0].bits.resp := UInt<1>("h00") r_arb.io.in[0].valid := UInt<1>("h00") r_arb.io.in[1].bits.user := UInt<1>("h00") r_arb.io.in[1].bits.id := UInt<1>("h00") r_arb.io.in[1].bits.last := UInt<1>("h00") r_arb.io.in[1].bits.data := UInt<1>("h00") r_arb.io.in[1].bits.resp := UInt<1>("h00") r_arb.io.in[1].valid := UInt<1>("h00") r_arb.io.in[2].bits.user := UInt<1>("h00") r_arb.io.in[2].bits.id := UInt<1>("h00") r_arb.io.in[2].bits.last := UInt<1>("h00") r_arb.io.in[2].bits.data := UInt<1>("h00") r_arb.io.in[2].bits.resp := UInt<1>("h00") r_arb.io.in[2].valid := UInt<1>("h00") r_arb.io.in[3].bits.user := UInt<1>("h00") r_arb.io.in[3].bits.id := UInt<1>("h00") r_arb.io.in[3].bits.last := UInt<1>("h00") r_arb.io.in[3].bits.data := UInt<1>("h00") r_arb.io.in[3].bits.resp := UInt<1>("h00") r_arb.io.in[3].valid := UInt<1>("h00") r_arb.clock := clock r_arb.reset := reset b_arb.io.in[0] <> io.slave[0].b r_arb.io.in[0] <> io.slave[0].r b_arb.io.in[1] <> io.slave[1].b r_arb.io.in[1] <> io.slave[1].r b_arb.io.in[2] <> io.slave[2].b r_arb.io.in[2] <> io.slave[2].r b_arb.io.in[3] <> err_slave.io.b r_arb.io.in[3] <> err_slave.io.r io.master.b <> b_arb.io.out io.master.r <> r_arb.io.out module RRArbiter_45 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.user := UInt<1>("h00") io.out.bits.id := UInt<1>("h00") io.out.bits.region := UInt<1>("h00") io.out.bits.qos := UInt<1>("h00") io.out.bits.prot := UInt<1>("h00") io.out.bits.cache := UInt<1>("h00") io.out.bits.lock := UInt<1>("h00") io.out.bits.burst := UInt<1>("h00") io.out.bits.size := UInt<1>("h00") io.out.bits.len := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_306 : UInt<1> T_306 := UInt<1>("h00") infer accessor T_308 = io.in[T_306] io.out.valid := T_308.valid infer accessor T_335 = io.in[T_306] io.out.bits <> T_335.bits io.chosen := T_306 infer accessor T_362 = io.in[T_306] T_362.ready := UInt<1>("h00") reg T_392 : UInt<1>, clock, reset onreset T_392 := UInt<1>("h00") node T_393 = gt(UInt<1>("h00"), T_392) node T_394 = and(io.in[0].valid, T_393) node T_396 = gt(UInt<1>("h01"), T_392) node T_397 = and(io.in[1].valid, T_396) node T_400 = or(UInt<1>("h00"), T_394) node T_402 = eq(T_400, UInt<1>("h00")) node T_404 = or(UInt<1>("h00"), T_394) node T_405 = or(T_404, T_397) node T_407 = eq(T_405, UInt<1>("h00")) node T_409 = or(UInt<1>("h00"), T_394) node T_410 = or(T_409, T_397) node T_411 = or(T_410, io.in[0].valid) node T_413 = eq(T_411, UInt<1>("h00")) node T_415 = gt(UInt<1>("h00"), T_392) node T_416 = and(UInt<1>("h01"), T_415) node T_417 = or(T_416, T_407) node T_419 = gt(UInt<1>("h01"), T_392) node T_420 = and(T_402, T_419) node T_421 = or(T_420, T_413) node T_423 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_424 = mux(UInt<1>("h00"), T_423, T_417) node T_425 = and(T_424, io.out.ready) io.in[0].ready := T_425 node T_427 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_428 = mux(UInt<1>("h00"), T_427, T_421) node T_429 = and(T_428, io.out.ready) io.in[1].ready := T_429 node T_432 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_434 = gt(UInt<1>("h01"), T_392) node T_435 = and(io.in[1].valid, T_434) node T_437 = mux(T_435, UInt<1>("h01"), T_432) node T_438 = mux(UInt<1>("h00"), UInt<1>("h01"), T_437) T_306 := T_438 node T_439 = and(io.out.ready, io.out.valid) when T_439 : T_392 := T_306 skip module NASTIArbiter : input clock : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.slave.r.ready := UInt<1>("h00") io.slave.ar.bits.user := UInt<1>("h00") io.slave.ar.bits.id := UInt<1>("h00") io.slave.ar.bits.region := UInt<1>("h00") io.slave.ar.bits.qos := UInt<1>("h00") io.slave.ar.bits.prot := UInt<1>("h00") io.slave.ar.bits.cache := UInt<1>("h00") io.slave.ar.bits.lock := UInt<1>("h00") io.slave.ar.bits.burst := UInt<1>("h00") io.slave.ar.bits.size := UInt<1>("h00") io.slave.ar.bits.len := UInt<1>("h00") io.slave.ar.bits.addr := UInt<1>("h00") io.slave.ar.valid := UInt<1>("h00") io.slave.b.ready := UInt<1>("h00") io.slave.w.bits.user := UInt<1>("h00") io.slave.w.bits.strb := UInt<1>("h00") io.slave.w.bits.last := UInt<1>("h00") io.slave.w.bits.data := UInt<1>("h00") io.slave.w.valid := UInt<1>("h00") io.slave.aw.bits.user := UInt<1>("h00") io.slave.aw.bits.id := UInt<1>("h00") io.slave.aw.bits.region := UInt<1>("h00") io.slave.aw.bits.qos := UInt<1>("h00") io.slave.aw.bits.prot := UInt<1>("h00") io.slave.aw.bits.cache := UInt<1>("h00") io.slave.aw.bits.lock := UInt<1>("h00") io.slave.aw.bits.burst := UInt<1>("h00") io.slave.aw.bits.size := UInt<1>("h00") io.slave.aw.bits.len := UInt<1>("h00") io.slave.aw.bits.addr := UInt<1>("h00") io.slave.aw.valid := UInt<1>("h00") io.master[0].r.bits.user := UInt<1>("h00") io.master[0].r.bits.id := UInt<1>("h00") io.master[0].r.bits.last := UInt<1>("h00") io.master[0].r.bits.data := UInt<1>("h00") io.master[0].r.bits.resp := UInt<1>("h00") io.master[0].r.valid := UInt<1>("h00") io.master[0].ar.ready := UInt<1>("h00") io.master[0].b.bits.user := UInt<1>("h00") io.master[0].b.bits.id := UInt<1>("h00") io.master[0].b.bits.resp := UInt<1>("h00") io.master[0].b.valid := UInt<1>("h00") io.master[0].w.ready := UInt<1>("h00") io.master[0].aw.ready := UInt<1>("h00") io.master[1].r.bits.user := UInt<1>("h00") io.master[1].r.bits.id := UInt<1>("h00") io.master[1].r.bits.last := UInt<1>("h00") io.master[1].r.bits.data := UInt<1>("h00") io.master[1].r.bits.resp := UInt<1>("h00") io.master[1].r.valid := UInt<1>("h00") io.master[1].ar.ready := UInt<1>("h00") io.master[1].b.bits.user := UInt<1>("h00") io.master[1].b.bits.id := UInt<1>("h00") io.master[1].b.bits.resp := UInt<1>("h00") io.master[1].b.valid := UInt<1>("h00") io.master[1].w.ready := UInt<1>("h00") io.master[1].aw.ready := UInt<1>("h00") inst T_1767 of RRArbiter_45 T_1767.io.out.ready := UInt<1>("h00") T_1767.io.in[0].bits.user := UInt<1>("h00") T_1767.io.in[0].bits.id := UInt<1>("h00") T_1767.io.in[0].bits.region := UInt<1>("h00") T_1767.io.in[0].bits.qos := UInt<1>("h00") T_1767.io.in[0].bits.prot := UInt<1>("h00") T_1767.io.in[0].bits.cache := UInt<1>("h00") T_1767.io.in[0].bits.lock := UInt<1>("h00") T_1767.io.in[0].bits.burst := UInt<1>("h00") T_1767.io.in[0].bits.size := UInt<1>("h00") T_1767.io.in[0].bits.len := UInt<1>("h00") T_1767.io.in[0].bits.addr := UInt<1>("h00") T_1767.io.in[0].valid := UInt<1>("h00") T_1767.io.in[1].bits.user := UInt<1>("h00") T_1767.io.in[1].bits.id := UInt<1>("h00") T_1767.io.in[1].bits.region := UInt<1>("h00") T_1767.io.in[1].bits.qos := UInt<1>("h00") T_1767.io.in[1].bits.prot := UInt<1>("h00") T_1767.io.in[1].bits.cache := UInt<1>("h00") T_1767.io.in[1].bits.lock := UInt<1>("h00") T_1767.io.in[1].bits.burst := UInt<1>("h00") T_1767.io.in[1].bits.size := UInt<1>("h00") T_1767.io.in[1].bits.len := UInt<1>("h00") T_1767.io.in[1].bits.addr := UInt<1>("h00") T_1767.io.in[1].valid := UInt<1>("h00") T_1767.clock := clock T_1767.reset := reset inst T_1805 of RRArbiter_45 T_1805.io.out.ready := UInt<1>("h00") T_1805.io.in[0].bits.user := UInt<1>("h00") T_1805.io.in[0].bits.id := UInt<1>("h00") T_1805.io.in[0].bits.region := UInt<1>("h00") T_1805.io.in[0].bits.qos := UInt<1>("h00") T_1805.io.in[0].bits.prot := UInt<1>("h00") T_1805.io.in[0].bits.cache := UInt<1>("h00") T_1805.io.in[0].bits.lock := UInt<1>("h00") T_1805.io.in[0].bits.burst := UInt<1>("h00") T_1805.io.in[0].bits.size := UInt<1>("h00") T_1805.io.in[0].bits.len := UInt<1>("h00") T_1805.io.in[0].bits.addr := UInt<1>("h00") T_1805.io.in[0].valid := UInt<1>("h00") T_1805.io.in[1].bits.user := UInt<1>("h00") T_1805.io.in[1].bits.id := UInt<1>("h00") T_1805.io.in[1].bits.region := UInt<1>("h00") T_1805.io.in[1].bits.qos := UInt<1>("h00") T_1805.io.in[1].bits.prot := UInt<1>("h00") T_1805.io.in[1].bits.cache := UInt<1>("h00") T_1805.io.in[1].bits.lock := UInt<1>("h00") T_1805.io.in[1].bits.burst := UInt<1>("h00") T_1805.io.in[1].bits.size := UInt<1>("h00") T_1805.io.in[1].bits.len := UInt<1>("h00") T_1805.io.in[1].bits.addr := UInt<1>("h00") T_1805.io.in[1].valid := UInt<1>("h00") T_1805.clock := clock T_1805.reset := reset node T_1831 = bits(io.slave.r.bits.id, 0, 0) node T_1832 = bits(io.slave.b.bits.id, 0, 0) reg T_1834 : UInt<1>, clock, reset reg T_1836 : UInt<1>, clock, reset onreset T_1836 := UInt<1>("h01") node T_1837 = and(T_1805.io.out.ready, T_1805.io.out.valid) when T_1837 : T_1834 := T_1805.io.chosen T_1836 := UInt<1>("h00") skip node T_1839 = and(io.slave.w.ready, io.slave.w.valid) node T_1840 = and(T_1839, io.slave.w.bits.last) when T_1840 : T_1836 := UInt<1>("h01") skip T_1767.io.in[0] <> io.master[0].ar node T_1843 = cat(io.master[0].ar.bits.id, UInt<1>("h00")) T_1767.io.in[0].bits.id := T_1843 T_1805.io.in[0] <> io.master[0].aw node T_1845 = cat(io.master[0].aw.bits.id, UInt<1>("h00")) T_1805.io.in[0].bits.id := T_1845 node T_1847 = eq(T_1831, UInt<1>("h00")) node T_1848 = and(io.slave.r.valid, T_1847) io.master[0].r.valid := T_1848 io.master[0].r.bits <> io.slave.r.bits node T_1850 = dshr(io.slave.r.bits.id, UInt<1>("h01")) io.master[0].r.bits.id := T_1850 node T_1852 = eq(T_1832, UInt<1>("h00")) node T_1853 = and(io.slave.b.valid, T_1852) io.master[0].b.valid := T_1853 io.master[0].b.bits <> io.slave.b.bits node T_1855 = dshr(io.slave.b.bits.id, UInt<1>("h01")) io.master[0].b.bits.id := T_1855 node T_1857 = eq(T_1834, UInt<1>("h00")) node T_1858 = and(io.slave.w.ready, T_1857) node T_1860 = eq(T_1836, UInt<1>("h00")) node T_1861 = and(T_1858, T_1860) io.master[0].w.ready := T_1861 T_1767.io.in[1] <> io.master[1].ar node T_1863 = cat(io.master[1].ar.bits.id, UInt<1>("h01")) T_1767.io.in[1].bits.id := T_1863 T_1805.io.in[1] <> io.master[1].aw node T_1865 = cat(io.master[1].aw.bits.id, UInt<1>("h01")) T_1805.io.in[1].bits.id := T_1865 node T_1867 = eq(T_1831, UInt<1>("h01")) node T_1868 = and(io.slave.r.valid, T_1867) io.master[1].r.valid := T_1868 io.master[1].r.bits <> io.slave.r.bits node T_1870 = dshr(io.slave.r.bits.id, UInt<1>("h01")) io.master[1].r.bits.id := T_1870 node T_1872 = eq(T_1832, UInt<1>("h01")) node T_1873 = and(io.slave.b.valid, T_1872) io.master[1].b.valid := T_1873 io.master[1].b.bits <> io.slave.b.bits node T_1875 = dshr(io.slave.b.bits.id, UInt<1>("h01")) io.master[1].b.bits.id := T_1875 node T_1877 = eq(T_1834, UInt<1>("h01")) node T_1878 = and(io.slave.w.ready, T_1877) node T_1880 = eq(T_1836, UInt<1>("h00")) node T_1881 = and(T_1878, T_1880) io.master[1].w.ready := T_1881 infer accessor T_1882 = io.master[T_1831] io.slave.r.ready := T_1882.r.ready infer accessor T_2041 = io.master[T_1832] io.slave.b.ready := T_2041.b.ready infer accessor T_2200 = io.master[T_1834] io.slave.w.bits <> T_2200.w.bits infer accessor T_2359 = io.master[T_1834] node T_2519 = eq(T_1836, UInt<1>("h00")) node T_2520 = and(T_2359.w.valid, T_2519) io.slave.w.valid := T_2520 io.slave.ar <> T_1767.io.out io.slave.aw.bits <> T_1805.io.out.bits node T_2521 = and(T_1805.io.out.valid, T_1836) io.slave.aw.valid := T_2521 node T_2522 = and(io.slave.aw.ready, T_1836) T_1805.io.out.ready := T_2522 module NASTICrossbar : input clock : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[3]} io.slaves[0].r.ready := UInt<1>("h00") io.slaves[0].ar.bits.user := UInt<1>("h00") io.slaves[0].ar.bits.id := UInt<1>("h00") io.slaves[0].ar.bits.region := UInt<1>("h00") io.slaves[0].ar.bits.qos := UInt<1>("h00") io.slaves[0].ar.bits.prot := UInt<1>("h00") io.slaves[0].ar.bits.cache := UInt<1>("h00") io.slaves[0].ar.bits.lock := UInt<1>("h00") io.slaves[0].ar.bits.burst := UInt<1>("h00") io.slaves[0].ar.bits.size := UInt<1>("h00") io.slaves[0].ar.bits.len := UInt<1>("h00") io.slaves[0].ar.bits.addr := UInt<1>("h00") io.slaves[0].ar.valid := UInt<1>("h00") io.slaves[0].b.ready := UInt<1>("h00") io.slaves[0].w.bits.user := UInt<1>("h00") io.slaves[0].w.bits.strb := UInt<1>("h00") io.slaves[0].w.bits.last := UInt<1>("h00") io.slaves[0].w.bits.data := UInt<1>("h00") io.slaves[0].w.valid := UInt<1>("h00") io.slaves[0].aw.bits.user := UInt<1>("h00") io.slaves[0].aw.bits.id := UInt<1>("h00") io.slaves[0].aw.bits.region := UInt<1>("h00") io.slaves[0].aw.bits.qos := UInt<1>("h00") io.slaves[0].aw.bits.prot := UInt<1>("h00") io.slaves[0].aw.bits.cache := UInt<1>("h00") io.slaves[0].aw.bits.lock := UInt<1>("h00") io.slaves[0].aw.bits.burst := UInt<1>("h00") io.slaves[0].aw.bits.size := UInt<1>("h00") io.slaves[0].aw.bits.len := UInt<1>("h00") io.slaves[0].aw.bits.addr := UInt<1>("h00") io.slaves[0].aw.valid := UInt<1>("h00") io.slaves[1].r.ready := UInt<1>("h00") io.slaves[1].ar.bits.user := UInt<1>("h00") io.slaves[1].ar.bits.id := UInt<1>("h00") io.slaves[1].ar.bits.region := UInt<1>("h00") io.slaves[1].ar.bits.qos := UInt<1>("h00") io.slaves[1].ar.bits.prot := UInt<1>("h00") io.slaves[1].ar.bits.cache := UInt<1>("h00") io.slaves[1].ar.bits.lock := UInt<1>("h00") io.slaves[1].ar.bits.burst := UInt<1>("h00") io.slaves[1].ar.bits.size := UInt<1>("h00") io.slaves[1].ar.bits.len := UInt<1>("h00") io.slaves[1].ar.bits.addr := UInt<1>("h00") io.slaves[1].ar.valid := UInt<1>("h00") io.slaves[1].b.ready := UInt<1>("h00") io.slaves[1].w.bits.user := UInt<1>("h00") io.slaves[1].w.bits.strb := UInt<1>("h00") io.slaves[1].w.bits.last := UInt<1>("h00") io.slaves[1].w.bits.data := UInt<1>("h00") io.slaves[1].w.valid := UInt<1>("h00") io.slaves[1].aw.bits.user := UInt<1>("h00") io.slaves[1].aw.bits.id := UInt<1>("h00") io.slaves[1].aw.bits.region := UInt<1>("h00") io.slaves[1].aw.bits.qos := UInt<1>("h00") io.slaves[1].aw.bits.prot := UInt<1>("h00") io.slaves[1].aw.bits.cache := UInt<1>("h00") io.slaves[1].aw.bits.lock := UInt<1>("h00") io.slaves[1].aw.bits.burst := UInt<1>("h00") io.slaves[1].aw.bits.size := UInt<1>("h00") io.slaves[1].aw.bits.len := UInt<1>("h00") io.slaves[1].aw.bits.addr := UInt<1>("h00") io.slaves[1].aw.valid := UInt<1>("h00") io.slaves[2].r.ready := UInt<1>("h00") io.slaves[2].ar.bits.user := UInt<1>("h00") io.slaves[2].ar.bits.id := UInt<1>("h00") io.slaves[2].ar.bits.region := UInt<1>("h00") io.slaves[2].ar.bits.qos := UInt<1>("h00") io.slaves[2].ar.bits.prot := UInt<1>("h00") io.slaves[2].ar.bits.cache := UInt<1>("h00") io.slaves[2].ar.bits.lock := UInt<1>("h00") io.slaves[2].ar.bits.burst := UInt<1>("h00") io.slaves[2].ar.bits.size := UInt<1>("h00") io.slaves[2].ar.bits.len := UInt<1>("h00") io.slaves[2].ar.bits.addr := UInt<1>("h00") io.slaves[2].ar.valid := UInt<1>("h00") io.slaves[2].b.ready := UInt<1>("h00") io.slaves[2].w.bits.user := UInt<1>("h00") io.slaves[2].w.bits.strb := UInt<1>("h00") io.slaves[2].w.bits.last := UInt<1>("h00") io.slaves[2].w.bits.data := UInt<1>("h00") io.slaves[2].w.valid := UInt<1>("h00") io.slaves[2].aw.bits.user := UInt<1>("h00") io.slaves[2].aw.bits.id := UInt<1>("h00") io.slaves[2].aw.bits.region := UInt<1>("h00") io.slaves[2].aw.bits.qos := UInt<1>("h00") io.slaves[2].aw.bits.prot := UInt<1>("h00") io.slaves[2].aw.bits.cache := UInt<1>("h00") io.slaves[2].aw.bits.lock := UInt<1>("h00") io.slaves[2].aw.bits.burst := UInt<1>("h00") io.slaves[2].aw.bits.size := UInt<1>("h00") io.slaves[2].aw.bits.len := UInt<1>("h00") io.slaves[2].aw.bits.addr := UInt<1>("h00") io.slaves[2].aw.valid := UInt<1>("h00") io.masters[0].r.bits.user := UInt<1>("h00") io.masters[0].r.bits.id := UInt<1>("h00") io.masters[0].r.bits.last := UInt<1>("h00") io.masters[0].r.bits.data := UInt<1>("h00") io.masters[0].r.bits.resp := UInt<1>("h00") io.masters[0].r.valid := UInt<1>("h00") io.masters[0].ar.ready := UInt<1>("h00") io.masters[0].b.bits.user := UInt<1>("h00") io.masters[0].b.bits.id := UInt<1>("h00") io.masters[0].b.bits.resp := UInt<1>("h00") io.masters[0].b.valid := UInt<1>("h00") io.masters[0].w.ready := UInt<1>("h00") io.masters[0].aw.ready := UInt<1>("h00") io.masters[1].r.bits.user := UInt<1>("h00") io.masters[1].r.bits.id := UInt<1>("h00") io.masters[1].r.bits.last := UInt<1>("h00") io.masters[1].r.bits.data := UInt<1>("h00") io.masters[1].r.bits.resp := UInt<1>("h00") io.masters[1].r.valid := UInt<1>("h00") io.masters[1].ar.ready := UInt<1>("h00") io.masters[1].b.bits.user := UInt<1>("h00") io.masters[1].b.bits.id := UInt<1>("h00") io.masters[1].b.bits.resp := UInt<1>("h00") io.masters[1].b.valid := UInt<1>("h00") io.masters[1].w.ready := UInt<1>("h00") io.masters[1].aw.ready := UInt<1>("h00") inst T_2551 of NASTIRouter T_2551.io.slave[0].r.bits.user := UInt<1>("h00") T_2551.io.slave[0].r.bits.id := UInt<1>("h00") T_2551.io.slave[0].r.bits.last := UInt<1>("h00") T_2551.io.slave[0].r.bits.data := UInt<1>("h00") T_2551.io.slave[0].r.bits.resp := UInt<1>("h00") T_2551.io.slave[0].r.valid := UInt<1>("h00") T_2551.io.slave[0].ar.ready := UInt<1>("h00") T_2551.io.slave[0].b.bits.user := UInt<1>("h00") T_2551.io.slave[0].b.bits.id := UInt<1>("h00") T_2551.io.slave[0].b.bits.resp := UInt<1>("h00") T_2551.io.slave[0].b.valid := UInt<1>("h00") T_2551.io.slave[0].w.ready := UInt<1>("h00") T_2551.io.slave[0].aw.ready := UInt<1>("h00") T_2551.io.slave[1].r.bits.user := UInt<1>("h00") T_2551.io.slave[1].r.bits.id := UInt<1>("h00") T_2551.io.slave[1].r.bits.last := UInt<1>("h00") T_2551.io.slave[1].r.bits.data := UInt<1>("h00") T_2551.io.slave[1].r.bits.resp := UInt<1>("h00") T_2551.io.slave[1].r.valid := UInt<1>("h00") T_2551.io.slave[1].ar.ready := UInt<1>("h00") T_2551.io.slave[1].b.bits.user := UInt<1>("h00") T_2551.io.slave[1].b.bits.id := UInt<1>("h00") T_2551.io.slave[1].b.bits.resp := UInt<1>("h00") T_2551.io.slave[1].b.valid := UInt<1>("h00") T_2551.io.slave[1].w.ready := UInt<1>("h00") T_2551.io.slave[1].aw.ready := UInt<1>("h00") T_2551.io.slave[2].r.bits.user := UInt<1>("h00") T_2551.io.slave[2].r.bits.id := UInt<1>("h00") T_2551.io.slave[2].r.bits.last := UInt<1>("h00") T_2551.io.slave[2].r.bits.data := UInt<1>("h00") T_2551.io.slave[2].r.bits.resp := UInt<1>("h00") T_2551.io.slave[2].r.valid := UInt<1>("h00") T_2551.io.slave[2].ar.ready := UInt<1>("h00") T_2551.io.slave[2].b.bits.user := UInt<1>("h00") T_2551.io.slave[2].b.bits.id := UInt<1>("h00") T_2551.io.slave[2].b.bits.resp := UInt<1>("h00") T_2551.io.slave[2].b.valid := UInt<1>("h00") T_2551.io.slave[2].w.ready := UInt<1>("h00") T_2551.io.slave[2].aw.ready := UInt<1>("h00") T_2551.io.master.r.ready := UInt<1>("h00") T_2551.io.master.ar.bits.user := UInt<1>("h00") T_2551.io.master.ar.bits.id := UInt<1>("h00") T_2551.io.master.ar.bits.region := UInt<1>("h00") T_2551.io.master.ar.bits.qos := UInt<1>("h00") T_2551.io.master.ar.bits.prot := UInt<1>("h00") T_2551.io.master.ar.bits.cache := UInt<1>("h00") T_2551.io.master.ar.bits.lock := UInt<1>("h00") T_2551.io.master.ar.bits.burst := UInt<1>("h00") T_2551.io.master.ar.bits.size := UInt<1>("h00") T_2551.io.master.ar.bits.len := UInt<1>("h00") T_2551.io.master.ar.bits.addr := UInt<1>("h00") T_2551.io.master.ar.valid := UInt<1>("h00") T_2551.io.master.b.ready := UInt<1>("h00") T_2551.io.master.w.bits.user := UInt<1>("h00") T_2551.io.master.w.bits.strb := UInt<1>("h00") T_2551.io.master.w.bits.last := UInt<1>("h00") T_2551.io.master.w.bits.data := UInt<1>("h00") T_2551.io.master.w.valid := UInt<1>("h00") T_2551.io.master.aw.bits.user := UInt<1>("h00") T_2551.io.master.aw.bits.id := UInt<1>("h00") T_2551.io.master.aw.bits.region := UInt<1>("h00") T_2551.io.master.aw.bits.qos := UInt<1>("h00") T_2551.io.master.aw.bits.prot := UInt<1>("h00") T_2551.io.master.aw.bits.cache := UInt<1>("h00") T_2551.io.master.aw.bits.lock := UInt<1>("h00") T_2551.io.master.aw.bits.burst := UInt<1>("h00") T_2551.io.master.aw.bits.size := UInt<1>("h00") T_2551.io.master.aw.bits.len := UInt<1>("h00") T_2551.io.master.aw.bits.addr := UInt<1>("h00") T_2551.io.master.aw.valid := UInt<1>("h00") T_2551.clock := clock T_2551.reset := reset inst T_2622 of NASTIRouter T_2622.io.slave[0].r.bits.user := UInt<1>("h00") T_2622.io.slave[0].r.bits.id := UInt<1>("h00") T_2622.io.slave[0].r.bits.last := UInt<1>("h00") T_2622.io.slave[0].r.bits.data := UInt<1>("h00") T_2622.io.slave[0].r.bits.resp := UInt<1>("h00") T_2622.io.slave[0].r.valid := UInt<1>("h00") T_2622.io.slave[0].ar.ready := UInt<1>("h00") T_2622.io.slave[0].b.bits.user := UInt<1>("h00") T_2622.io.slave[0].b.bits.id := UInt<1>("h00") T_2622.io.slave[0].b.bits.resp := UInt<1>("h00") T_2622.io.slave[0].b.valid := UInt<1>("h00") T_2622.io.slave[0].w.ready := UInt<1>("h00") T_2622.io.slave[0].aw.ready := UInt<1>("h00") T_2622.io.slave[1].r.bits.user := UInt<1>("h00") T_2622.io.slave[1].r.bits.id := UInt<1>("h00") T_2622.io.slave[1].r.bits.last := UInt<1>("h00") T_2622.io.slave[1].r.bits.data := UInt<1>("h00") T_2622.io.slave[1].r.bits.resp := UInt<1>("h00") T_2622.io.slave[1].r.valid := UInt<1>("h00") T_2622.io.slave[1].ar.ready := UInt<1>("h00") T_2622.io.slave[1].b.bits.user := UInt<1>("h00") T_2622.io.slave[1].b.bits.id := UInt<1>("h00") T_2622.io.slave[1].b.bits.resp := UInt<1>("h00") T_2622.io.slave[1].b.valid := UInt<1>("h00") T_2622.io.slave[1].w.ready := UInt<1>("h00") T_2622.io.slave[1].aw.ready := UInt<1>("h00") T_2622.io.slave[2].r.bits.user := UInt<1>("h00") T_2622.io.slave[2].r.bits.id := UInt<1>("h00") T_2622.io.slave[2].r.bits.last := UInt<1>("h00") T_2622.io.slave[2].r.bits.data := UInt<1>("h00") T_2622.io.slave[2].r.bits.resp := UInt<1>("h00") T_2622.io.slave[2].r.valid := UInt<1>("h00") T_2622.io.slave[2].ar.ready := UInt<1>("h00") T_2622.io.slave[2].b.bits.user := UInt<1>("h00") T_2622.io.slave[2].b.bits.id := UInt<1>("h00") T_2622.io.slave[2].b.bits.resp := UInt<1>("h00") T_2622.io.slave[2].b.valid := UInt<1>("h00") T_2622.io.slave[2].w.ready := UInt<1>("h00") T_2622.io.slave[2].aw.ready := UInt<1>("h00") T_2622.io.master.r.ready := UInt<1>("h00") T_2622.io.master.ar.bits.user := UInt<1>("h00") T_2622.io.master.ar.bits.id := UInt<1>("h00") T_2622.io.master.ar.bits.region := UInt<1>("h00") T_2622.io.master.ar.bits.qos := UInt<1>("h00") T_2622.io.master.ar.bits.prot := UInt<1>("h00") T_2622.io.master.ar.bits.cache := UInt<1>("h00") T_2622.io.master.ar.bits.lock := UInt<1>("h00") T_2622.io.master.ar.bits.burst := UInt<1>("h00") T_2622.io.master.ar.bits.size := UInt<1>("h00") T_2622.io.master.ar.bits.len := UInt<1>("h00") T_2622.io.master.ar.bits.addr := UInt<1>("h00") T_2622.io.master.ar.valid := UInt<1>("h00") T_2622.io.master.b.ready := UInt<1>("h00") T_2622.io.master.w.bits.user := UInt<1>("h00") T_2622.io.master.w.bits.strb := UInt<1>("h00") T_2622.io.master.w.bits.last := UInt<1>("h00") T_2622.io.master.w.bits.data := UInt<1>("h00") T_2622.io.master.w.valid := UInt<1>("h00") T_2622.io.master.aw.bits.user := UInt<1>("h00") T_2622.io.master.aw.bits.id := UInt<1>("h00") T_2622.io.master.aw.bits.region := UInt<1>("h00") T_2622.io.master.aw.bits.qos := UInt<1>("h00") T_2622.io.master.aw.bits.prot := UInt<1>("h00") T_2622.io.master.aw.bits.cache := UInt<1>("h00") T_2622.io.master.aw.bits.lock := UInt<1>("h00") T_2622.io.master.aw.bits.burst := UInt<1>("h00") T_2622.io.master.aw.bits.size := UInt<1>("h00") T_2622.io.master.aw.bits.len := UInt<1>("h00") T_2622.io.master.aw.bits.addr := UInt<1>("h00") T_2622.io.master.aw.valid := UInt<1>("h00") T_2622.clock := clock T_2622.reset := reset wire routers : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[3]}[2] routers[0] <> T_2551.io routers[1] <> T_2622.io inst T_9702 of NASTIArbiter T_9702.io.slave.r.bits.user := UInt<1>("h00") T_9702.io.slave.r.bits.id := UInt<1>("h00") T_9702.io.slave.r.bits.last := UInt<1>("h00") T_9702.io.slave.r.bits.data := UInt<1>("h00") T_9702.io.slave.r.bits.resp := UInt<1>("h00") T_9702.io.slave.r.valid := UInt<1>("h00") T_9702.io.slave.ar.ready := UInt<1>("h00") T_9702.io.slave.b.bits.user := UInt<1>("h00") T_9702.io.slave.b.bits.id := UInt<1>("h00") T_9702.io.slave.b.bits.resp := UInt<1>("h00") T_9702.io.slave.b.valid := UInt<1>("h00") T_9702.io.slave.w.ready := UInt<1>("h00") T_9702.io.slave.aw.ready := UInt<1>("h00") T_9702.io.master[0].r.ready := UInt<1>("h00") T_9702.io.master[0].ar.bits.user := UInt<1>("h00") T_9702.io.master[0].ar.bits.id := UInt<1>("h00") T_9702.io.master[0].ar.bits.region := UInt<1>("h00") T_9702.io.master[0].ar.bits.qos := UInt<1>("h00") T_9702.io.master[0].ar.bits.prot := UInt<1>("h00") T_9702.io.master[0].ar.bits.cache := UInt<1>("h00") T_9702.io.master[0].ar.bits.lock := UInt<1>("h00") T_9702.io.master[0].ar.bits.burst := UInt<1>("h00") T_9702.io.master[0].ar.bits.size := UInt<1>("h00") T_9702.io.master[0].ar.bits.len := UInt<1>("h00") T_9702.io.master[0].ar.bits.addr := UInt<1>("h00") T_9702.io.master[0].ar.valid := UInt<1>("h00") T_9702.io.master[0].b.ready := UInt<1>("h00") T_9702.io.master[0].w.bits.user := UInt<1>("h00") T_9702.io.master[0].w.bits.strb := UInt<1>("h00") T_9702.io.master[0].w.bits.last := UInt<1>("h00") T_9702.io.master[0].w.bits.data := UInt<1>("h00") T_9702.io.master[0].w.valid := UInt<1>("h00") T_9702.io.master[0].aw.bits.user := UInt<1>("h00") T_9702.io.master[0].aw.bits.id := UInt<1>("h00") T_9702.io.master[0].aw.bits.region := UInt<1>("h00") T_9702.io.master[0].aw.bits.qos := UInt<1>("h00") T_9702.io.master[0].aw.bits.prot := UInt<1>("h00") T_9702.io.master[0].aw.bits.cache := UInt<1>("h00") T_9702.io.master[0].aw.bits.lock := UInt<1>("h00") T_9702.io.master[0].aw.bits.burst := UInt<1>("h00") T_9702.io.master[0].aw.bits.size := UInt<1>("h00") T_9702.io.master[0].aw.bits.len := UInt<1>("h00") T_9702.io.master[0].aw.bits.addr := UInt<1>("h00") T_9702.io.master[0].aw.valid := UInt<1>("h00") T_9702.io.master[1].r.ready := UInt<1>("h00") T_9702.io.master[1].ar.bits.user := UInt<1>("h00") T_9702.io.master[1].ar.bits.id := UInt<1>("h00") T_9702.io.master[1].ar.bits.region := UInt<1>("h00") T_9702.io.master[1].ar.bits.qos := UInt<1>("h00") T_9702.io.master[1].ar.bits.prot := UInt<1>("h00") T_9702.io.master[1].ar.bits.cache := UInt<1>("h00") T_9702.io.master[1].ar.bits.lock := UInt<1>("h00") T_9702.io.master[1].ar.bits.burst := UInt<1>("h00") T_9702.io.master[1].ar.bits.size := UInt<1>("h00") T_9702.io.master[1].ar.bits.len := UInt<1>("h00") T_9702.io.master[1].ar.bits.addr := UInt<1>("h00") T_9702.io.master[1].ar.valid := UInt<1>("h00") T_9702.io.master[1].b.ready := UInt<1>("h00") T_9702.io.master[1].w.bits.user := UInt<1>("h00") T_9702.io.master[1].w.bits.strb := UInt<1>("h00") T_9702.io.master[1].w.bits.last := UInt<1>("h00") T_9702.io.master[1].w.bits.data := UInt<1>("h00") T_9702.io.master[1].w.valid := UInt<1>("h00") T_9702.io.master[1].aw.bits.user := UInt<1>("h00") T_9702.io.master[1].aw.bits.id := UInt<1>("h00") T_9702.io.master[1].aw.bits.region := UInt<1>("h00") T_9702.io.master[1].aw.bits.qos := UInt<1>("h00") T_9702.io.master[1].aw.bits.prot := UInt<1>("h00") T_9702.io.master[1].aw.bits.cache := UInt<1>("h00") T_9702.io.master[1].aw.bits.lock := UInt<1>("h00") T_9702.io.master[1].aw.bits.burst := UInt<1>("h00") T_9702.io.master[1].aw.bits.size := UInt<1>("h00") T_9702.io.master[1].aw.bits.len := UInt<1>("h00") T_9702.io.master[1].aw.bits.addr := UInt<1>("h00") T_9702.io.master[1].aw.valid := UInt<1>("h00") T_9702.clock := clock T_9702.reset := reset inst T_9778 of NASTIArbiter T_9778.io.slave.r.bits.user := UInt<1>("h00") T_9778.io.slave.r.bits.id := UInt<1>("h00") T_9778.io.slave.r.bits.last := UInt<1>("h00") T_9778.io.slave.r.bits.data := UInt<1>("h00") T_9778.io.slave.r.bits.resp := UInt<1>("h00") T_9778.io.slave.r.valid := UInt<1>("h00") T_9778.io.slave.ar.ready := UInt<1>("h00") T_9778.io.slave.b.bits.user := UInt<1>("h00") T_9778.io.slave.b.bits.id := UInt<1>("h00") T_9778.io.slave.b.bits.resp := UInt<1>("h00") T_9778.io.slave.b.valid := UInt<1>("h00") T_9778.io.slave.w.ready := UInt<1>("h00") T_9778.io.slave.aw.ready := UInt<1>("h00") T_9778.io.master[0].r.ready := UInt<1>("h00") T_9778.io.master[0].ar.bits.user := UInt<1>("h00") T_9778.io.master[0].ar.bits.id := UInt<1>("h00") T_9778.io.master[0].ar.bits.region := UInt<1>("h00") T_9778.io.master[0].ar.bits.qos := UInt<1>("h00") T_9778.io.master[0].ar.bits.prot := UInt<1>("h00") T_9778.io.master[0].ar.bits.cache := UInt<1>("h00") T_9778.io.master[0].ar.bits.lock := UInt<1>("h00") T_9778.io.master[0].ar.bits.burst := UInt<1>("h00") T_9778.io.master[0].ar.bits.size := UInt<1>("h00") T_9778.io.master[0].ar.bits.len := UInt<1>("h00") T_9778.io.master[0].ar.bits.addr := UInt<1>("h00") T_9778.io.master[0].ar.valid := UInt<1>("h00") T_9778.io.master[0].b.ready := UInt<1>("h00") T_9778.io.master[0].w.bits.user := UInt<1>("h00") T_9778.io.master[0].w.bits.strb := UInt<1>("h00") T_9778.io.master[0].w.bits.last := UInt<1>("h00") T_9778.io.master[0].w.bits.data := UInt<1>("h00") T_9778.io.master[0].w.valid := UInt<1>("h00") T_9778.io.master[0].aw.bits.user := UInt<1>("h00") T_9778.io.master[0].aw.bits.id := UInt<1>("h00") T_9778.io.master[0].aw.bits.region := UInt<1>("h00") T_9778.io.master[0].aw.bits.qos := UInt<1>("h00") T_9778.io.master[0].aw.bits.prot := UInt<1>("h00") T_9778.io.master[0].aw.bits.cache := UInt<1>("h00") T_9778.io.master[0].aw.bits.lock := UInt<1>("h00") T_9778.io.master[0].aw.bits.burst := UInt<1>("h00") T_9778.io.master[0].aw.bits.size := UInt<1>("h00") T_9778.io.master[0].aw.bits.len := UInt<1>("h00") T_9778.io.master[0].aw.bits.addr := UInt<1>("h00") T_9778.io.master[0].aw.valid := UInt<1>("h00") T_9778.io.master[1].r.ready := UInt<1>("h00") T_9778.io.master[1].ar.bits.user := UInt<1>("h00") T_9778.io.master[1].ar.bits.id := UInt<1>("h00") T_9778.io.master[1].ar.bits.region := UInt<1>("h00") T_9778.io.master[1].ar.bits.qos := UInt<1>("h00") T_9778.io.master[1].ar.bits.prot := UInt<1>("h00") T_9778.io.master[1].ar.bits.cache := UInt<1>("h00") T_9778.io.master[1].ar.bits.lock := UInt<1>("h00") T_9778.io.master[1].ar.bits.burst := UInt<1>("h00") T_9778.io.master[1].ar.bits.size := UInt<1>("h00") T_9778.io.master[1].ar.bits.len := UInt<1>("h00") T_9778.io.master[1].ar.bits.addr := UInt<1>("h00") T_9778.io.master[1].ar.valid := UInt<1>("h00") T_9778.io.master[1].b.ready := UInt<1>("h00") T_9778.io.master[1].w.bits.user := UInt<1>("h00") T_9778.io.master[1].w.bits.strb := UInt<1>("h00") T_9778.io.master[1].w.bits.last := UInt<1>("h00") T_9778.io.master[1].w.bits.data := UInt<1>("h00") T_9778.io.master[1].w.valid := UInt<1>("h00") T_9778.io.master[1].aw.bits.user := UInt<1>("h00") T_9778.io.master[1].aw.bits.id := UInt<1>("h00") T_9778.io.master[1].aw.bits.region := UInt<1>("h00") T_9778.io.master[1].aw.bits.qos := UInt<1>("h00") T_9778.io.master[1].aw.bits.prot := UInt<1>("h00") T_9778.io.master[1].aw.bits.cache := UInt<1>("h00") T_9778.io.master[1].aw.bits.lock := UInt<1>("h00") T_9778.io.master[1].aw.bits.burst := UInt<1>("h00") T_9778.io.master[1].aw.bits.size := UInt<1>("h00") T_9778.io.master[1].aw.bits.len := UInt<1>("h00") T_9778.io.master[1].aw.bits.addr := UInt<1>("h00") T_9778.io.master[1].aw.valid := UInt<1>("h00") T_9778.clock := clock T_9778.reset := reset inst T_9854 of NASTIArbiter T_9854.io.slave.r.bits.user := UInt<1>("h00") T_9854.io.slave.r.bits.id := UInt<1>("h00") T_9854.io.slave.r.bits.last := UInt<1>("h00") T_9854.io.slave.r.bits.data := UInt<1>("h00") T_9854.io.slave.r.bits.resp := UInt<1>("h00") T_9854.io.slave.r.valid := UInt<1>("h00") T_9854.io.slave.ar.ready := UInt<1>("h00") T_9854.io.slave.b.bits.user := UInt<1>("h00") T_9854.io.slave.b.bits.id := UInt<1>("h00") T_9854.io.slave.b.bits.resp := UInt<1>("h00") T_9854.io.slave.b.valid := UInt<1>("h00") T_9854.io.slave.w.ready := UInt<1>("h00") T_9854.io.slave.aw.ready := UInt<1>("h00") T_9854.io.master[0].r.ready := UInt<1>("h00") T_9854.io.master[0].ar.bits.user := UInt<1>("h00") T_9854.io.master[0].ar.bits.id := UInt<1>("h00") T_9854.io.master[0].ar.bits.region := UInt<1>("h00") T_9854.io.master[0].ar.bits.qos := UInt<1>("h00") T_9854.io.master[0].ar.bits.prot := UInt<1>("h00") T_9854.io.master[0].ar.bits.cache := UInt<1>("h00") T_9854.io.master[0].ar.bits.lock := UInt<1>("h00") T_9854.io.master[0].ar.bits.burst := UInt<1>("h00") T_9854.io.master[0].ar.bits.size := UInt<1>("h00") T_9854.io.master[0].ar.bits.len := UInt<1>("h00") T_9854.io.master[0].ar.bits.addr := UInt<1>("h00") T_9854.io.master[0].ar.valid := UInt<1>("h00") T_9854.io.master[0].b.ready := UInt<1>("h00") T_9854.io.master[0].w.bits.user := UInt<1>("h00") T_9854.io.master[0].w.bits.strb := UInt<1>("h00") T_9854.io.master[0].w.bits.last := UInt<1>("h00") T_9854.io.master[0].w.bits.data := UInt<1>("h00") T_9854.io.master[0].w.valid := UInt<1>("h00") T_9854.io.master[0].aw.bits.user := UInt<1>("h00") T_9854.io.master[0].aw.bits.id := UInt<1>("h00") T_9854.io.master[0].aw.bits.region := UInt<1>("h00") T_9854.io.master[0].aw.bits.qos := UInt<1>("h00") T_9854.io.master[0].aw.bits.prot := UInt<1>("h00") T_9854.io.master[0].aw.bits.cache := UInt<1>("h00") T_9854.io.master[0].aw.bits.lock := UInt<1>("h00") T_9854.io.master[0].aw.bits.burst := UInt<1>("h00") T_9854.io.master[0].aw.bits.size := UInt<1>("h00") T_9854.io.master[0].aw.bits.len := UInt<1>("h00") T_9854.io.master[0].aw.bits.addr := UInt<1>("h00") T_9854.io.master[0].aw.valid := UInt<1>("h00") T_9854.io.master[1].r.ready := UInt<1>("h00") T_9854.io.master[1].ar.bits.user := UInt<1>("h00") T_9854.io.master[1].ar.bits.id := UInt<1>("h00") T_9854.io.master[1].ar.bits.region := UInt<1>("h00") T_9854.io.master[1].ar.bits.qos := UInt<1>("h00") T_9854.io.master[1].ar.bits.prot := UInt<1>("h00") T_9854.io.master[1].ar.bits.cache := UInt<1>("h00") T_9854.io.master[1].ar.bits.lock := UInt<1>("h00") T_9854.io.master[1].ar.bits.burst := UInt<1>("h00") T_9854.io.master[1].ar.bits.size := UInt<1>("h00") T_9854.io.master[1].ar.bits.len := UInt<1>("h00") T_9854.io.master[1].ar.bits.addr := UInt<1>("h00") T_9854.io.master[1].ar.valid := UInt<1>("h00") T_9854.io.master[1].b.ready := UInt<1>("h00") T_9854.io.master[1].w.bits.user := UInt<1>("h00") T_9854.io.master[1].w.bits.strb := UInt<1>("h00") T_9854.io.master[1].w.bits.last := UInt<1>("h00") T_9854.io.master[1].w.bits.data := UInt<1>("h00") T_9854.io.master[1].w.valid := UInt<1>("h00") T_9854.io.master[1].aw.bits.user := UInt<1>("h00") T_9854.io.master[1].aw.bits.id := UInt<1>("h00") T_9854.io.master[1].aw.bits.region := UInt<1>("h00") T_9854.io.master[1].aw.bits.qos := UInt<1>("h00") T_9854.io.master[1].aw.bits.prot := UInt<1>("h00") T_9854.io.master[1].aw.bits.cache := UInt<1>("h00") T_9854.io.master[1].aw.bits.lock := UInt<1>("h00") T_9854.io.master[1].aw.bits.burst := UInt<1>("h00") T_9854.io.master[1].aw.bits.size := UInt<1>("h00") T_9854.io.master[1].aw.bits.len := UInt<1>("h00") T_9854.io.master[1].aw.bits.addr := UInt<1>("h00") T_9854.io.master[1].aw.valid := UInt<1>("h00") T_9854.clock := clock T_9854.reset := reset wire arbiters : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}}[3] arbiters[0] <> T_9702.io arbiters[1] <> T_9778.io arbiters[2] <> T_9854.io routers[0].master <> io.masters[0] routers[1].master <> io.masters[1] wire T_19650 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2] T_19650[0] <> routers[0].slave[0] T_19650[1] <> routers[1].slave[0] arbiters[0].master <> T_19650 io.slaves[0] <> arbiters[0].slave wire T_20287 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2] T_20287[0] <> routers[0].slave[1] T_20287[1] <> routers[1].slave[1] arbiters[1].master <> T_20287 io.slaves[1] <> arbiters[1].slave wire T_20924 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2] T_20924[0] <> routers[0].slave[2] T_20924[1] <> routers[1].slave[2] arbiters[2].master <> T_20924 io.slaves[2] <> arbiters[2].slave module RRArbiter_58 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.user := UInt<1>("h00") io.out.bits.id := UInt<1>("h00") io.out.bits.resp := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") wire T_152 : UInt<2> T_152 := UInt<1>("h00") infer accessor T_154 = io.in[T_152] io.out.valid := T_154.valid infer accessor T_165 = io.in[T_152] io.out.bits <> T_165.bits io.chosen := T_152 infer accessor T_176 = io.in[T_152] T_176.ready := UInt<1>("h00") reg T_190 : UInt<2>, clock, reset onreset T_190 := UInt<2>("h00") node T_191 = gt(UInt<1>("h00"), T_190) node T_192 = and(io.in[0].valid, T_191) node T_194 = gt(UInt<1>("h01"), T_190) node T_195 = and(io.in[1].valid, T_194) node T_197 = gt(UInt<2>("h02"), T_190) node T_198 = and(io.in[2].valid, T_197) node T_201 = or(UInt<1>("h00"), T_192) node T_203 = eq(T_201, UInt<1>("h00")) node T_205 = or(UInt<1>("h00"), T_192) node T_206 = or(T_205, T_195) node T_208 = eq(T_206, UInt<1>("h00")) node T_210 = or(UInt<1>("h00"), T_192) node T_211 = or(T_210, T_195) node T_212 = or(T_211, T_198) node T_214 = eq(T_212, UInt<1>("h00")) node T_216 = or(UInt<1>("h00"), T_192) node T_217 = or(T_216, T_195) node T_218 = or(T_217, T_198) node T_219 = or(T_218, io.in[0].valid) node T_221 = eq(T_219, UInt<1>("h00")) node T_223 = or(UInt<1>("h00"), T_192) node T_224 = or(T_223, T_195) node T_225 = or(T_224, T_198) node T_226 = or(T_225, io.in[0].valid) node T_227 = or(T_226, io.in[1].valid) node T_229 = eq(T_227, UInt<1>("h00")) node T_231 = gt(UInt<1>("h00"), T_190) node T_232 = and(UInt<1>("h01"), T_231) node T_233 = or(T_232, T_214) node T_235 = gt(UInt<1>("h01"), T_190) node T_236 = and(T_203, T_235) node T_237 = or(T_236, T_221) node T_239 = gt(UInt<2>("h02"), T_190) node T_240 = and(T_208, T_239) node T_241 = or(T_240, T_229) node T_243 = eq(UInt<2>("h02"), UInt<1>("h00")) node T_244 = mux(UInt<1>("h00"), T_243, T_233) node T_245 = and(T_244, io.out.ready) io.in[0].ready := T_245 node T_247 = eq(UInt<2>("h02"), UInt<1>("h01")) node T_248 = mux(UInt<1>("h00"), T_247, T_237) node T_249 = and(T_248, io.out.ready) io.in[1].ready := T_249 node T_251 = eq(UInt<2>("h02"), UInt<2>("h02")) node T_252 = mux(UInt<1>("h00"), T_251, T_241) node T_253 = and(T_252, io.out.ready) io.in[2].ready := T_253 node T_256 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_258 = mux(io.in[0].valid, UInt<1>("h00"), T_256) node T_260 = gt(UInt<2>("h02"), T_190) node T_261 = and(io.in[2].valid, T_260) node T_263 = mux(T_261, UInt<2>("h02"), T_258) node T_265 = gt(UInt<1>("h01"), T_190) node T_266 = and(io.in[1].valid, T_265) node T_268 = mux(T_266, UInt<1>("h01"), T_263) node T_269 = mux(UInt<1>("h00"), UInt<2>("h02"), T_268) T_152 := T_269 node T_270 = and(io.out.ready, io.out.valid) when T_270 : T_190 := T_152 skip module NASTIReadDataArbiter_59 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}} io.out.bits.user := UInt<1>("h00") io.out.bits.id := UInt<1>("h00") io.out.bits.last := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.resp := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") reg lockIdx : UInt<2>, clock, reset onreset lockIdx := UInt<2>("h00") reg locked : UInt<1>, clock, reset onreset locked := UInt<1>("h00") wire T_218 : UInt<1>[3] T_218[0] := io.in[0].valid T_218[1] := io.in[1].valid T_218[2] := io.in[2].valid node T_224 = addw(lockIdx, UInt<1>("h01")) node T_226 = lt(T_224, UInt<2>("h03")) node T_228 = addw(UInt<1>("h00"), T_224) infer accessor T_229 = T_218[T_228] node T_231 = subw(T_224, UInt<2>("h03")) infer accessor T_232 = T_218[T_231] node T_233 = mux(T_226, T_229, T_232) node T_235 = lt(T_224, UInt<2>("h02")) node T_237 = addw(UInt<1>("h01"), T_224) infer accessor T_238 = T_218[T_237] node T_240 = subw(T_224, UInt<2>("h02")) infer accessor T_241 = T_218[T_240] node T_242 = mux(T_235, T_238, T_241) node T_244 = lt(T_224, UInt<1>("h01")) node T_246 = addw(UInt<2>("h02"), T_224) infer accessor T_247 = T_218[T_246] node T_249 = subw(T_224, UInt<1>("h01")) infer accessor T_250 = T_218[T_249] node T_251 = mux(T_244, T_247, T_250) wire T_253 : UInt<1>[3] T_253[0] := T_233 T_253[1] := T_242 T_253[2] := T_251 wire T_262 : UInt<2>[3] T_262[0] := UInt<1>("h00") T_262[1] := UInt<1>("h01") T_262[2] := UInt<2>("h02") node T_268 = addw(lockIdx, UInt<1>("h01")) node T_270 = lt(T_268, UInt<2>("h03")) node T_272 = addw(UInt<1>("h00"), T_268) infer accessor T_273 = T_262[T_272] node T_275 = subw(T_268, UInt<2>("h03")) infer accessor T_276 = T_262[T_275] node T_277 = mux(T_270, T_273, T_276) node T_279 = lt(T_268, UInt<2>("h02")) node T_281 = addw(UInt<1>("h01"), T_268) infer accessor T_282 = T_262[T_281] node T_284 = subw(T_268, UInt<2>("h02")) infer accessor T_285 = T_262[T_284] node T_286 = mux(T_279, T_282, T_285) node T_288 = lt(T_268, UInt<1>("h01")) node T_290 = addw(UInt<2>("h02"), T_268) infer accessor T_291 = T_262[T_290] node T_293 = subw(T_268, UInt<1>("h01")) infer accessor T_294 = T_262[T_293] node T_295 = mux(T_288, T_291, T_294) wire T_297 : UInt<2>[3] T_297[0] := T_277 T_297[1] := T_286 T_297[2] := T_295 node T_302 = mux(T_253[1], T_297[1], T_297[2]) node choice = mux(T_253[0], T_297[0], T_302) node chosen = mux(locked, lockIdx, choice) node T_306 = eq(chosen, UInt<1>("h00")) node T_307 = and(io.out.ready, T_306) io.in[0].ready := T_307 node T_309 = eq(chosen, UInt<1>("h01")) node T_310 = and(io.out.ready, T_309) io.in[1].ready := T_310 node T_312 = eq(chosen, UInt<2>("h02")) node T_313 = and(io.out.ready, T_312) io.in[2].ready := T_313 infer accessor T_314 = io.in[chosen] io.out.valid := T_314.valid infer accessor T_329 = io.in[chosen] io.out.bits <> T_329.bits node T_344 = and(io.out.ready, io.out.valid) when T_344 : node T_346 = eq(locked, UInt<1>("h00")) when T_346 : lockIdx := choice node T_348 = eq(io.out.bits.last, UInt<1>("h00")) locked := T_348 skip else : when io.out.bits.last : locked := UInt<1>("h00") skip skip skip module NASTIRouter_54 : input clock : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2]} io.slave[0].r.ready := UInt<1>("h00") io.slave[0].ar.bits.user := UInt<1>("h00") io.slave[0].ar.bits.id := UInt<1>("h00") io.slave[0].ar.bits.region := UInt<1>("h00") io.slave[0].ar.bits.qos := UInt<1>("h00") io.slave[0].ar.bits.prot := UInt<1>("h00") io.slave[0].ar.bits.cache := UInt<1>("h00") io.slave[0].ar.bits.lock := UInt<1>("h00") io.slave[0].ar.bits.burst := UInt<1>("h00") io.slave[0].ar.bits.size := UInt<1>("h00") io.slave[0].ar.bits.len := UInt<1>("h00") io.slave[0].ar.bits.addr := UInt<1>("h00") io.slave[0].ar.valid := UInt<1>("h00") io.slave[0].b.ready := UInt<1>("h00") io.slave[0].w.bits.user := UInt<1>("h00") io.slave[0].w.bits.strb := UInt<1>("h00") io.slave[0].w.bits.last := UInt<1>("h00") io.slave[0].w.bits.data := UInt<1>("h00") io.slave[0].w.valid := UInt<1>("h00") io.slave[0].aw.bits.user := UInt<1>("h00") io.slave[0].aw.bits.id := UInt<1>("h00") io.slave[0].aw.bits.region := UInt<1>("h00") io.slave[0].aw.bits.qos := UInt<1>("h00") io.slave[0].aw.bits.prot := UInt<1>("h00") io.slave[0].aw.bits.cache := UInt<1>("h00") io.slave[0].aw.bits.lock := UInt<1>("h00") io.slave[0].aw.bits.burst := UInt<1>("h00") io.slave[0].aw.bits.size := UInt<1>("h00") io.slave[0].aw.bits.len := UInt<1>("h00") io.slave[0].aw.bits.addr := UInt<1>("h00") io.slave[0].aw.valid := UInt<1>("h00") io.slave[1].r.ready := UInt<1>("h00") io.slave[1].ar.bits.user := UInt<1>("h00") io.slave[1].ar.bits.id := UInt<1>("h00") io.slave[1].ar.bits.region := UInt<1>("h00") io.slave[1].ar.bits.qos := UInt<1>("h00") io.slave[1].ar.bits.prot := UInt<1>("h00") io.slave[1].ar.bits.cache := UInt<1>("h00") io.slave[1].ar.bits.lock := UInt<1>("h00") io.slave[1].ar.bits.burst := UInt<1>("h00") io.slave[1].ar.bits.size := UInt<1>("h00") io.slave[1].ar.bits.len := UInt<1>("h00") io.slave[1].ar.bits.addr := UInt<1>("h00") io.slave[1].ar.valid := UInt<1>("h00") io.slave[1].b.ready := UInt<1>("h00") io.slave[1].w.bits.user := UInt<1>("h00") io.slave[1].w.bits.strb := UInt<1>("h00") io.slave[1].w.bits.last := UInt<1>("h00") io.slave[1].w.bits.data := UInt<1>("h00") io.slave[1].w.valid := UInt<1>("h00") io.slave[1].aw.bits.user := UInt<1>("h00") io.slave[1].aw.bits.id := UInt<1>("h00") io.slave[1].aw.bits.region := UInt<1>("h00") io.slave[1].aw.bits.qos := UInt<1>("h00") io.slave[1].aw.bits.prot := UInt<1>("h00") io.slave[1].aw.bits.cache := UInt<1>("h00") io.slave[1].aw.bits.lock := UInt<1>("h00") io.slave[1].aw.bits.burst := UInt<1>("h00") io.slave[1].aw.bits.size := UInt<1>("h00") io.slave[1].aw.bits.len := UInt<1>("h00") io.slave[1].aw.bits.addr := UInt<1>("h00") io.slave[1].aw.valid := UInt<1>("h00") io.master.r.bits.user := UInt<1>("h00") io.master.r.bits.id := UInt<1>("h00") io.master.r.bits.last := UInt<1>("h00") io.master.r.bits.data := UInt<1>("h00") io.master.r.bits.resp := UInt<1>("h00") io.master.r.valid := UInt<1>("h00") io.master.ar.ready := UInt<1>("h00") io.master.b.bits.user := UInt<1>("h00") io.master.b.bits.id := UInt<1>("h00") io.master.b.bits.resp := UInt<1>("h00") io.master.b.valid := UInt<1>("h00") io.master.w.ready := UInt<1>("h00") io.master.aw.ready := UInt<1>("h00") node T_1124 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1126 = lt(io.master.ar.bits.addr, UInt<31>("h040008000")) node T_1127 = and(T_1124, T_1126) node T_1128 = and(io.master.ar.valid, T_1127) io.slave[0].ar.valid := T_1128 io.slave[0].ar.bits <> io.master.ar.bits node T_1129 = and(io.slave[0].ar.ready, T_1127) node T_1130 = or(UInt<1>("h00"), T_1129) node T_1131 = or(UInt<1>("h00"), T_1127) node T_1133 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1135 = lt(io.master.aw.bits.addr, UInt<31>("h040008000")) node T_1136 = and(T_1133, T_1135) node T_1137 = and(io.master.aw.valid, T_1136) io.slave[0].aw.valid := T_1137 io.slave[0].aw.bits <> io.master.aw.bits node T_1138 = and(io.slave[0].aw.ready, T_1136) node T_1139 = or(UInt<1>("h00"), T_1138) node T_1140 = or(UInt<1>("h00"), T_1136) reg T_1142 : UInt<1>, clock, reset onreset T_1142 := UInt<1>("h00") node T_1143 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1143 : T_1142 := UInt<1>("h01") skip node T_1145 = and(io.slave[0].w.ready, io.slave[0].w.valid) node T_1146 = and(T_1145, io.slave[0].w.bits.last) when T_1146 : T_1142 := UInt<1>("h00") skip node T_1148 = and(io.master.w.valid, T_1142) io.slave[0].w.valid := T_1148 io.slave[0].w.bits <> io.master.w.bits node T_1149 = and(io.slave[0].w.ready, T_1142) node T_1150 = or(UInt<1>("h00"), T_1149) node T_1152 = geq(io.master.ar.bits.addr, UInt<31>("h040008000")) node T_1154 = lt(io.master.ar.bits.addr, UInt<31>("h040008200")) node T_1155 = and(T_1152, T_1154) node T_1156 = and(io.master.ar.valid, T_1155) io.slave[1].ar.valid := T_1156 io.slave[1].ar.bits <> io.master.ar.bits node T_1157 = and(io.slave[1].ar.ready, T_1155) node ar_ready = or(T_1130, T_1157) node r_valid_addr = or(T_1131, T_1155) node T_1161 = geq(io.master.aw.bits.addr, UInt<31>("h040008000")) node T_1163 = lt(io.master.aw.bits.addr, UInt<31>("h040008200")) node T_1164 = and(T_1161, T_1163) node T_1165 = and(io.master.aw.valid, T_1164) io.slave[1].aw.valid := T_1165 io.slave[1].aw.bits <> io.master.aw.bits node T_1166 = and(io.slave[1].aw.ready, T_1164) node aw_ready = or(T_1139, T_1166) node w_valid_addr = or(T_1140, T_1164) reg T_1170 : UInt<1>, clock, reset onreset T_1170 := UInt<1>("h00") node T_1171 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1171 : T_1170 := UInt<1>("h01") skip node T_1173 = and(io.slave[1].w.ready, io.slave[1].w.valid) node T_1174 = and(T_1173, io.slave[1].w.bits.last) when T_1174 : T_1170 := UInt<1>("h00") skip node T_1176 = and(io.master.w.valid, T_1170) io.slave[1].w.valid := T_1176 io.slave[1].w.bits <> io.master.w.bits node T_1177 = and(io.slave[1].w.ready, T_1170) node w_ready = or(T_1150, T_1177) inst err_slave of NASTIErrorSlave err_slave.io.r.ready := UInt<1>("h00") err_slave.io.ar.bits.user := UInt<1>("h00") err_slave.io.ar.bits.id := UInt<1>("h00") err_slave.io.ar.bits.region := UInt<1>("h00") err_slave.io.ar.bits.qos := UInt<1>("h00") err_slave.io.ar.bits.prot := UInt<1>("h00") err_slave.io.ar.bits.cache := UInt<1>("h00") err_slave.io.ar.bits.lock := UInt<1>("h00") err_slave.io.ar.bits.burst := UInt<1>("h00") err_slave.io.ar.bits.size := UInt<1>("h00") err_slave.io.ar.bits.len := UInt<1>("h00") err_slave.io.ar.bits.addr := UInt<1>("h00") err_slave.io.ar.valid := UInt<1>("h00") err_slave.io.b.ready := UInt<1>("h00") err_slave.io.w.bits.user := UInt<1>("h00") err_slave.io.w.bits.strb := UInt<1>("h00") err_slave.io.w.bits.last := UInt<1>("h00") err_slave.io.w.bits.data := UInt<1>("h00") err_slave.io.w.valid := UInt<1>("h00") err_slave.io.aw.bits.user := UInt<1>("h00") err_slave.io.aw.bits.id := UInt<1>("h00") err_slave.io.aw.bits.region := UInt<1>("h00") err_slave.io.aw.bits.qos := UInt<1>("h00") err_slave.io.aw.bits.prot := UInt<1>("h00") err_slave.io.aw.bits.cache := UInt<1>("h00") err_slave.io.aw.bits.lock := UInt<1>("h00") err_slave.io.aw.bits.burst := UInt<1>("h00") err_slave.io.aw.bits.size := UInt<1>("h00") err_slave.io.aw.bits.len := UInt<1>("h00") err_slave.io.aw.bits.addr := UInt<1>("h00") err_slave.io.aw.valid := UInt<1>("h00") err_slave.clock := clock err_slave.reset := reset node T_1212 = eq(r_valid_addr, UInt<1>("h00")) node T_1213 = and(T_1212, io.master.ar.valid) err_slave.io.ar.valid := T_1213 err_slave.io.ar.bits <> io.master.ar.bits node T_1215 = eq(w_valid_addr, UInt<1>("h00")) node T_1216 = and(T_1215, io.master.aw.valid) err_slave.io.aw.valid := T_1216 err_slave.io.aw.bits <> io.master.aw.bits err_slave.io.w.valid := io.master.w.valid err_slave.io.w.bits <> io.master.w.bits node T_1218 = eq(r_valid_addr, UInt<1>("h00")) node T_1219 = and(T_1218, err_slave.io.ar.ready) node T_1220 = or(ar_ready, T_1219) io.master.ar.ready := T_1220 node T_1222 = eq(w_valid_addr, UInt<1>("h00")) node T_1223 = and(T_1222, err_slave.io.aw.ready) node T_1224 = or(aw_ready, T_1223) io.master.aw.ready := T_1224 node T_1225 = or(w_ready, err_slave.io.w.ready) io.master.w.ready := T_1225 inst b_arb of RRArbiter_58 b_arb.io.out.ready := UInt<1>("h00") b_arb.io.in[0].bits.user := UInt<1>("h00") b_arb.io.in[0].bits.id := UInt<1>("h00") b_arb.io.in[0].bits.resp := UInt<1>("h00") b_arb.io.in[0].valid := UInt<1>("h00") b_arb.io.in[1].bits.user := UInt<1>("h00") b_arb.io.in[1].bits.id := UInt<1>("h00") b_arb.io.in[1].bits.resp := UInt<1>("h00") b_arb.io.in[1].valid := UInt<1>("h00") b_arb.io.in[2].bits.user := UInt<1>("h00") b_arb.io.in[2].bits.id := UInt<1>("h00") b_arb.io.in[2].bits.resp := UInt<1>("h00") b_arb.io.in[2].valid := UInt<1>("h00") b_arb.clock := clock b_arb.reset := reset inst r_arb of NASTIReadDataArbiter_59 r_arb.io.out.ready := UInt<1>("h00") r_arb.io.in[0].bits.user := UInt<1>("h00") r_arb.io.in[0].bits.id := UInt<1>("h00") r_arb.io.in[0].bits.last := UInt<1>("h00") r_arb.io.in[0].bits.data := UInt<1>("h00") r_arb.io.in[0].bits.resp := UInt<1>("h00") r_arb.io.in[0].valid := UInt<1>("h00") r_arb.io.in[1].bits.user := UInt<1>("h00") r_arb.io.in[1].bits.id := UInt<1>("h00") r_arb.io.in[1].bits.last := UInt<1>("h00") r_arb.io.in[1].bits.data := UInt<1>("h00") r_arb.io.in[1].bits.resp := UInt<1>("h00") r_arb.io.in[1].valid := UInt<1>("h00") r_arb.io.in[2].bits.user := UInt<1>("h00") r_arb.io.in[2].bits.id := UInt<1>("h00") r_arb.io.in[2].bits.last := UInt<1>("h00") r_arb.io.in[2].bits.data := UInt<1>("h00") r_arb.io.in[2].bits.resp := UInt<1>("h00") r_arb.io.in[2].valid := UInt<1>("h00") r_arb.clock := clock r_arb.reset := reset b_arb.io.in[0] <> io.slave[0].b r_arb.io.in[0] <> io.slave[0].r b_arb.io.in[1] <> io.slave[1].b r_arb.io.in[1] <> io.slave[1].r b_arb.io.in[2] <> err_slave.io.b r_arb.io.in[2] <> err_slave.io.r io.master.b <> b_arb.io.out io.master.r <> r_arb.io.out module NASTIRecursiveInterconnect_53 : input clock : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2]} io.slaves[0].r.ready := UInt<1>("h00") io.slaves[0].ar.bits.user := UInt<1>("h00") io.slaves[0].ar.bits.id := UInt<1>("h00") io.slaves[0].ar.bits.region := UInt<1>("h00") io.slaves[0].ar.bits.qos := UInt<1>("h00") io.slaves[0].ar.bits.prot := UInt<1>("h00") io.slaves[0].ar.bits.cache := UInt<1>("h00") io.slaves[0].ar.bits.lock := UInt<1>("h00") io.slaves[0].ar.bits.burst := UInt<1>("h00") io.slaves[0].ar.bits.size := UInt<1>("h00") io.slaves[0].ar.bits.len := UInt<1>("h00") io.slaves[0].ar.bits.addr := UInt<1>("h00") io.slaves[0].ar.valid := UInt<1>("h00") io.slaves[0].b.ready := UInt<1>("h00") io.slaves[0].w.bits.user := UInt<1>("h00") io.slaves[0].w.bits.strb := UInt<1>("h00") io.slaves[0].w.bits.last := UInt<1>("h00") io.slaves[0].w.bits.data := UInt<1>("h00") io.slaves[0].w.valid := UInt<1>("h00") io.slaves[0].aw.bits.user := UInt<1>("h00") io.slaves[0].aw.bits.id := UInt<1>("h00") io.slaves[0].aw.bits.region := UInt<1>("h00") io.slaves[0].aw.bits.qos := UInt<1>("h00") io.slaves[0].aw.bits.prot := UInt<1>("h00") io.slaves[0].aw.bits.cache := UInt<1>("h00") io.slaves[0].aw.bits.lock := UInt<1>("h00") io.slaves[0].aw.bits.burst := UInt<1>("h00") io.slaves[0].aw.bits.size := UInt<1>("h00") io.slaves[0].aw.bits.len := UInt<1>("h00") io.slaves[0].aw.bits.addr := UInt<1>("h00") io.slaves[0].aw.valid := UInt<1>("h00") io.slaves[1].r.ready := UInt<1>("h00") io.slaves[1].ar.bits.user := UInt<1>("h00") io.slaves[1].ar.bits.id := UInt<1>("h00") io.slaves[1].ar.bits.region := UInt<1>("h00") io.slaves[1].ar.bits.qos := UInt<1>("h00") io.slaves[1].ar.bits.prot := UInt<1>("h00") io.slaves[1].ar.bits.cache := UInt<1>("h00") io.slaves[1].ar.bits.lock := UInt<1>("h00") io.slaves[1].ar.bits.burst := UInt<1>("h00") io.slaves[1].ar.bits.size := UInt<1>("h00") io.slaves[1].ar.bits.len := UInt<1>("h00") io.slaves[1].ar.bits.addr := UInt<1>("h00") io.slaves[1].ar.valid := UInt<1>("h00") io.slaves[1].b.ready := UInt<1>("h00") io.slaves[1].w.bits.user := UInt<1>("h00") io.slaves[1].w.bits.strb := UInt<1>("h00") io.slaves[1].w.bits.last := UInt<1>("h00") io.slaves[1].w.bits.data := UInt<1>("h00") io.slaves[1].w.valid := UInt<1>("h00") io.slaves[1].aw.bits.user := UInt<1>("h00") io.slaves[1].aw.bits.id := UInt<1>("h00") io.slaves[1].aw.bits.region := UInt<1>("h00") io.slaves[1].aw.bits.qos := UInt<1>("h00") io.slaves[1].aw.bits.prot := UInt<1>("h00") io.slaves[1].aw.bits.cache := UInt<1>("h00") io.slaves[1].aw.bits.lock := UInt<1>("h00") io.slaves[1].aw.bits.burst := UInt<1>("h00") io.slaves[1].aw.bits.size := UInt<1>("h00") io.slaves[1].aw.bits.len := UInt<1>("h00") io.slaves[1].aw.bits.addr := UInt<1>("h00") io.slaves[1].aw.valid := UInt<1>("h00") io.masters[0].r.bits.user := UInt<1>("h00") io.masters[0].r.bits.id := UInt<1>("h00") io.masters[0].r.bits.last := UInt<1>("h00") io.masters[0].r.bits.data := UInt<1>("h00") io.masters[0].r.bits.resp := UInt<1>("h00") io.masters[0].r.valid := UInt<1>("h00") io.masters[0].ar.ready := UInt<1>("h00") io.masters[0].b.bits.user := UInt<1>("h00") io.masters[0].b.bits.id := UInt<1>("h00") io.masters[0].b.bits.resp := UInt<1>("h00") io.masters[0].b.valid := UInt<1>("h00") io.masters[0].w.ready := UInt<1>("h00") io.masters[0].aw.ready := UInt<1>("h00") inst T_2 of NASTIRouter_54 T_2.io.slave[0].r.bits.user := UInt<1>("h00") T_2.io.slave[0].r.bits.id := UInt<1>("h00") T_2.io.slave[0].r.bits.last := UInt<1>("h00") T_2.io.slave[0].r.bits.data := UInt<1>("h00") T_2.io.slave[0].r.bits.resp := UInt<1>("h00") T_2.io.slave[0].r.valid := UInt<1>("h00") T_2.io.slave[0].ar.ready := UInt<1>("h00") T_2.io.slave[0].b.bits.user := UInt<1>("h00") T_2.io.slave[0].b.bits.id := UInt<1>("h00") T_2.io.slave[0].b.bits.resp := UInt<1>("h00") T_2.io.slave[0].b.valid := UInt<1>("h00") T_2.io.slave[0].w.ready := UInt<1>("h00") T_2.io.slave[0].aw.ready := UInt<1>("h00") T_2.io.slave[1].r.bits.user := UInt<1>("h00") T_2.io.slave[1].r.bits.id := UInt<1>("h00") T_2.io.slave[1].r.bits.last := UInt<1>("h00") T_2.io.slave[1].r.bits.data := UInt<1>("h00") T_2.io.slave[1].r.bits.resp := UInt<1>("h00") T_2.io.slave[1].r.valid := UInt<1>("h00") T_2.io.slave[1].ar.ready := UInt<1>("h00") T_2.io.slave[1].b.bits.user := UInt<1>("h00") T_2.io.slave[1].b.bits.id := UInt<1>("h00") T_2.io.slave[1].b.bits.resp := UInt<1>("h00") T_2.io.slave[1].b.valid := UInt<1>("h00") T_2.io.slave[1].w.ready := UInt<1>("h00") T_2.io.slave[1].aw.ready := UInt<1>("h00") T_2.io.master.r.ready := UInt<1>("h00") T_2.io.master.ar.bits.user := UInt<1>("h00") T_2.io.master.ar.bits.id := UInt<1>("h00") T_2.io.master.ar.bits.region := UInt<1>("h00") T_2.io.master.ar.bits.qos := UInt<1>("h00") T_2.io.master.ar.bits.prot := UInt<1>("h00") T_2.io.master.ar.bits.cache := UInt<1>("h00") T_2.io.master.ar.bits.lock := UInt<1>("h00") T_2.io.master.ar.bits.burst := UInt<1>("h00") T_2.io.master.ar.bits.size := UInt<1>("h00") T_2.io.master.ar.bits.len := UInt<1>("h00") T_2.io.master.ar.bits.addr := UInt<1>("h00") T_2.io.master.ar.valid := UInt<1>("h00") T_2.io.master.b.ready := UInt<1>("h00") T_2.io.master.w.bits.user := UInt<1>("h00") T_2.io.master.w.bits.strb := UInt<1>("h00") T_2.io.master.w.bits.last := UInt<1>("h00") T_2.io.master.w.bits.data := UInt<1>("h00") T_2.io.master.w.valid := UInt<1>("h00") T_2.io.master.aw.bits.user := UInt<1>("h00") T_2.io.master.aw.bits.id := UInt<1>("h00") T_2.io.master.aw.bits.region := UInt<1>("h00") T_2.io.master.aw.bits.qos := UInt<1>("h00") T_2.io.master.aw.bits.prot := UInt<1>("h00") T_2.io.master.aw.bits.cache := UInt<1>("h00") T_2.io.master.aw.bits.lock := UInt<1>("h00") T_2.io.master.aw.bits.burst := UInt<1>("h00") T_2.io.master.aw.bits.size := UInt<1>("h00") T_2.io.master.aw.bits.len := UInt<1>("h00") T_2.io.master.aw.bits.addr := UInt<1>("h00") T_2.io.master.aw.valid := UInt<1>("h00") T_2.clock := clock T_2.reset := reset T_2.io.master <> io.masters[0] io.slaves[0] <> T_2.io.slave[0] io.slaves[1] <> T_2.io.slave[1] module NASTIRecursiveInterconnect : input clock : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[4]} io.slaves[0].r.ready := UInt<1>("h00") io.slaves[0].ar.bits.user := UInt<1>("h00") io.slaves[0].ar.bits.id := UInt<1>("h00") io.slaves[0].ar.bits.region := UInt<1>("h00") io.slaves[0].ar.bits.qos := UInt<1>("h00") io.slaves[0].ar.bits.prot := UInt<1>("h00") io.slaves[0].ar.bits.cache := UInt<1>("h00") io.slaves[0].ar.bits.lock := UInt<1>("h00") io.slaves[0].ar.bits.burst := UInt<1>("h00") io.slaves[0].ar.bits.size := UInt<1>("h00") io.slaves[0].ar.bits.len := UInt<1>("h00") io.slaves[0].ar.bits.addr := UInt<1>("h00") io.slaves[0].ar.valid := UInt<1>("h00") io.slaves[0].b.ready := UInt<1>("h00") io.slaves[0].w.bits.user := UInt<1>("h00") io.slaves[0].w.bits.strb := UInt<1>("h00") io.slaves[0].w.bits.last := UInt<1>("h00") io.slaves[0].w.bits.data := UInt<1>("h00") io.slaves[0].w.valid := UInt<1>("h00") io.slaves[0].aw.bits.user := UInt<1>("h00") io.slaves[0].aw.bits.id := UInt<1>("h00") io.slaves[0].aw.bits.region := UInt<1>("h00") io.slaves[0].aw.bits.qos := UInt<1>("h00") io.slaves[0].aw.bits.prot := UInt<1>("h00") io.slaves[0].aw.bits.cache := UInt<1>("h00") io.slaves[0].aw.bits.lock := UInt<1>("h00") io.slaves[0].aw.bits.burst := UInt<1>("h00") io.slaves[0].aw.bits.size := UInt<1>("h00") io.slaves[0].aw.bits.len := UInt<1>("h00") io.slaves[0].aw.bits.addr := UInt<1>("h00") io.slaves[0].aw.valid := UInt<1>("h00") io.slaves[1].r.ready := UInt<1>("h00") io.slaves[1].ar.bits.user := UInt<1>("h00") io.slaves[1].ar.bits.id := UInt<1>("h00") io.slaves[1].ar.bits.region := UInt<1>("h00") io.slaves[1].ar.bits.qos := UInt<1>("h00") io.slaves[1].ar.bits.prot := UInt<1>("h00") io.slaves[1].ar.bits.cache := UInt<1>("h00") io.slaves[1].ar.bits.lock := UInt<1>("h00") io.slaves[1].ar.bits.burst := UInt<1>("h00") io.slaves[1].ar.bits.size := UInt<1>("h00") io.slaves[1].ar.bits.len := UInt<1>("h00") io.slaves[1].ar.bits.addr := UInt<1>("h00") io.slaves[1].ar.valid := UInt<1>("h00") io.slaves[1].b.ready := UInt<1>("h00") io.slaves[1].w.bits.user := UInt<1>("h00") io.slaves[1].w.bits.strb := UInt<1>("h00") io.slaves[1].w.bits.last := UInt<1>("h00") io.slaves[1].w.bits.data := UInt<1>("h00") io.slaves[1].w.valid := UInt<1>("h00") io.slaves[1].aw.bits.user := UInt<1>("h00") io.slaves[1].aw.bits.id := UInt<1>("h00") io.slaves[1].aw.bits.region := UInt<1>("h00") io.slaves[1].aw.bits.qos := UInt<1>("h00") io.slaves[1].aw.bits.prot := UInt<1>("h00") io.slaves[1].aw.bits.cache := UInt<1>("h00") io.slaves[1].aw.bits.lock := UInt<1>("h00") io.slaves[1].aw.bits.burst := UInt<1>("h00") io.slaves[1].aw.bits.size := UInt<1>("h00") io.slaves[1].aw.bits.len := UInt<1>("h00") io.slaves[1].aw.bits.addr := UInt<1>("h00") io.slaves[1].aw.valid := UInt<1>("h00") io.slaves[2].r.ready := UInt<1>("h00") io.slaves[2].ar.bits.user := UInt<1>("h00") io.slaves[2].ar.bits.id := UInt<1>("h00") io.slaves[2].ar.bits.region := UInt<1>("h00") io.slaves[2].ar.bits.qos := UInt<1>("h00") io.slaves[2].ar.bits.prot := UInt<1>("h00") io.slaves[2].ar.bits.cache := UInt<1>("h00") io.slaves[2].ar.bits.lock := UInt<1>("h00") io.slaves[2].ar.bits.burst := UInt<1>("h00") io.slaves[2].ar.bits.size := UInt<1>("h00") io.slaves[2].ar.bits.len := UInt<1>("h00") io.slaves[2].ar.bits.addr := UInt<1>("h00") io.slaves[2].ar.valid := UInt<1>("h00") io.slaves[2].b.ready := UInt<1>("h00") io.slaves[2].w.bits.user := UInt<1>("h00") io.slaves[2].w.bits.strb := UInt<1>("h00") io.slaves[2].w.bits.last := UInt<1>("h00") io.slaves[2].w.bits.data := UInt<1>("h00") io.slaves[2].w.valid := UInt<1>("h00") io.slaves[2].aw.bits.user := UInt<1>("h00") io.slaves[2].aw.bits.id := UInt<1>("h00") io.slaves[2].aw.bits.region := UInt<1>("h00") io.slaves[2].aw.bits.qos := UInt<1>("h00") io.slaves[2].aw.bits.prot := UInt<1>("h00") io.slaves[2].aw.bits.cache := UInt<1>("h00") io.slaves[2].aw.bits.lock := UInt<1>("h00") io.slaves[2].aw.bits.burst := UInt<1>("h00") io.slaves[2].aw.bits.size := UInt<1>("h00") io.slaves[2].aw.bits.len := UInt<1>("h00") io.slaves[2].aw.bits.addr := UInt<1>("h00") io.slaves[2].aw.valid := UInt<1>("h00") io.slaves[3].r.ready := UInt<1>("h00") io.slaves[3].ar.bits.user := UInt<1>("h00") io.slaves[3].ar.bits.id := UInt<1>("h00") io.slaves[3].ar.bits.region := UInt<1>("h00") io.slaves[3].ar.bits.qos := UInt<1>("h00") io.slaves[3].ar.bits.prot := UInt<1>("h00") io.slaves[3].ar.bits.cache := UInt<1>("h00") io.slaves[3].ar.bits.lock := UInt<1>("h00") io.slaves[3].ar.bits.burst := UInt<1>("h00") io.slaves[3].ar.bits.size := UInt<1>("h00") io.slaves[3].ar.bits.len := UInt<1>("h00") io.slaves[3].ar.bits.addr := UInt<1>("h00") io.slaves[3].ar.valid := UInt<1>("h00") io.slaves[3].b.ready := UInt<1>("h00") io.slaves[3].w.bits.user := UInt<1>("h00") io.slaves[3].w.bits.strb := UInt<1>("h00") io.slaves[3].w.bits.last := UInt<1>("h00") io.slaves[3].w.bits.data := UInt<1>("h00") io.slaves[3].w.valid := UInt<1>("h00") io.slaves[3].aw.bits.user := UInt<1>("h00") io.slaves[3].aw.bits.id := UInt<1>("h00") io.slaves[3].aw.bits.region := UInt<1>("h00") io.slaves[3].aw.bits.qos := UInt<1>("h00") io.slaves[3].aw.bits.prot := UInt<1>("h00") io.slaves[3].aw.bits.cache := UInt<1>("h00") io.slaves[3].aw.bits.lock := UInt<1>("h00") io.slaves[3].aw.bits.burst := UInt<1>("h00") io.slaves[3].aw.bits.size := UInt<1>("h00") io.slaves[3].aw.bits.len := UInt<1>("h00") io.slaves[3].aw.bits.addr := UInt<1>("h00") io.slaves[3].aw.valid := UInt<1>("h00") io.masters[0].r.bits.user := UInt<1>("h00") io.masters[0].r.bits.id := UInt<1>("h00") io.masters[0].r.bits.last := UInt<1>("h00") io.masters[0].r.bits.data := UInt<1>("h00") io.masters[0].r.bits.resp := UInt<1>("h00") io.masters[0].r.valid := UInt<1>("h00") io.masters[0].ar.ready := UInt<1>("h00") io.masters[0].b.bits.user := UInt<1>("h00") io.masters[0].b.bits.id := UInt<1>("h00") io.masters[0].b.bits.resp := UInt<1>("h00") io.masters[0].b.valid := UInt<1>("h00") io.masters[0].w.ready := UInt<1>("h00") io.masters[0].aw.ready := UInt<1>("h00") io.masters[1].r.bits.user := UInt<1>("h00") io.masters[1].r.bits.id := UInt<1>("h00") io.masters[1].r.bits.last := UInt<1>("h00") io.masters[1].r.bits.data := UInt<1>("h00") io.masters[1].r.bits.resp := UInt<1>("h00") io.masters[1].r.valid := UInt<1>("h00") io.masters[1].ar.ready := UInt<1>("h00") io.masters[1].b.bits.user := UInt<1>("h00") io.masters[1].b.bits.id := UInt<1>("h00") io.masters[1].b.bits.resp := UInt<1>("h00") io.masters[1].b.valid := UInt<1>("h00") io.masters[1].w.ready := UInt<1>("h00") io.masters[1].aw.ready := UInt<1>("h00") inst T_2 of NASTICrossbar T_2.io.slaves[0].r.bits.user := UInt<1>("h00") T_2.io.slaves[0].r.bits.id := UInt<1>("h00") T_2.io.slaves[0].r.bits.last := UInt<1>("h00") T_2.io.slaves[0].r.bits.data := UInt<1>("h00") T_2.io.slaves[0].r.bits.resp := UInt<1>("h00") T_2.io.slaves[0].r.valid := UInt<1>("h00") T_2.io.slaves[0].ar.ready := UInt<1>("h00") T_2.io.slaves[0].b.bits.user := UInt<1>("h00") T_2.io.slaves[0].b.bits.id := UInt<1>("h00") T_2.io.slaves[0].b.bits.resp := UInt<1>("h00") T_2.io.slaves[0].b.valid := UInt<1>("h00") T_2.io.slaves[0].w.ready := UInt<1>("h00") T_2.io.slaves[0].aw.ready := UInt<1>("h00") T_2.io.slaves[1].r.bits.user := UInt<1>("h00") T_2.io.slaves[1].r.bits.id := UInt<1>("h00") T_2.io.slaves[1].r.bits.last := UInt<1>("h00") T_2.io.slaves[1].r.bits.data := UInt<1>("h00") T_2.io.slaves[1].r.bits.resp := UInt<1>("h00") T_2.io.slaves[1].r.valid := UInt<1>("h00") T_2.io.slaves[1].ar.ready := UInt<1>("h00") T_2.io.slaves[1].b.bits.user := UInt<1>("h00") T_2.io.slaves[1].b.bits.id := UInt<1>("h00") T_2.io.slaves[1].b.bits.resp := UInt<1>("h00") T_2.io.slaves[1].b.valid := UInt<1>("h00") T_2.io.slaves[1].w.ready := UInt<1>("h00") T_2.io.slaves[1].aw.ready := UInt<1>("h00") T_2.io.slaves[2].r.bits.user := UInt<1>("h00") T_2.io.slaves[2].r.bits.id := UInt<1>("h00") T_2.io.slaves[2].r.bits.last := UInt<1>("h00") T_2.io.slaves[2].r.bits.data := UInt<1>("h00") T_2.io.slaves[2].r.bits.resp := UInt<1>("h00") T_2.io.slaves[2].r.valid := UInt<1>("h00") T_2.io.slaves[2].ar.ready := UInt<1>("h00") T_2.io.slaves[2].b.bits.user := UInt<1>("h00") T_2.io.slaves[2].b.bits.id := UInt<1>("h00") T_2.io.slaves[2].b.bits.resp := UInt<1>("h00") T_2.io.slaves[2].b.valid := UInt<1>("h00") T_2.io.slaves[2].w.ready := UInt<1>("h00") T_2.io.slaves[2].aw.ready := UInt<1>("h00") T_2.io.masters[0].r.ready := UInt<1>("h00") T_2.io.masters[0].ar.bits.user := UInt<1>("h00") T_2.io.masters[0].ar.bits.id := UInt<1>("h00") T_2.io.masters[0].ar.bits.region := UInt<1>("h00") T_2.io.masters[0].ar.bits.qos := UInt<1>("h00") T_2.io.masters[0].ar.bits.prot := UInt<1>("h00") T_2.io.masters[0].ar.bits.cache := UInt<1>("h00") T_2.io.masters[0].ar.bits.lock := UInt<1>("h00") T_2.io.masters[0].ar.bits.burst := UInt<1>("h00") T_2.io.masters[0].ar.bits.size := UInt<1>("h00") T_2.io.masters[0].ar.bits.len := UInt<1>("h00") T_2.io.masters[0].ar.bits.addr := UInt<1>("h00") T_2.io.masters[0].ar.valid := UInt<1>("h00") T_2.io.masters[0].b.ready := UInt<1>("h00") T_2.io.masters[0].w.bits.user := UInt<1>("h00") T_2.io.masters[0].w.bits.strb := UInt<1>("h00") T_2.io.masters[0].w.bits.last := UInt<1>("h00") T_2.io.masters[0].w.bits.data := UInt<1>("h00") T_2.io.masters[0].w.valid := UInt<1>("h00") T_2.io.masters[0].aw.bits.user := UInt<1>("h00") T_2.io.masters[0].aw.bits.id := UInt<1>("h00") T_2.io.masters[0].aw.bits.region := UInt<1>("h00") T_2.io.masters[0].aw.bits.qos := UInt<1>("h00") T_2.io.masters[0].aw.bits.prot := UInt<1>("h00") T_2.io.masters[0].aw.bits.cache := UInt<1>("h00") T_2.io.masters[0].aw.bits.lock := UInt<1>("h00") T_2.io.masters[0].aw.bits.burst := UInt<1>("h00") T_2.io.masters[0].aw.bits.size := UInt<1>("h00") T_2.io.masters[0].aw.bits.len := UInt<1>("h00") T_2.io.masters[0].aw.bits.addr := UInt<1>("h00") T_2.io.masters[0].aw.valid := UInt<1>("h00") T_2.io.masters[1].r.ready := UInt<1>("h00") T_2.io.masters[1].ar.bits.user := UInt<1>("h00") T_2.io.masters[1].ar.bits.id := UInt<1>("h00") T_2.io.masters[1].ar.bits.region := UInt<1>("h00") T_2.io.masters[1].ar.bits.qos := UInt<1>("h00") T_2.io.masters[1].ar.bits.prot := UInt<1>("h00") T_2.io.masters[1].ar.bits.cache := UInt<1>("h00") T_2.io.masters[1].ar.bits.lock := UInt<1>("h00") T_2.io.masters[1].ar.bits.burst := UInt<1>("h00") T_2.io.masters[1].ar.bits.size := UInt<1>("h00") T_2.io.masters[1].ar.bits.len := UInt<1>("h00") T_2.io.masters[1].ar.bits.addr := UInt<1>("h00") T_2.io.masters[1].ar.valid := UInt<1>("h00") T_2.io.masters[1].b.ready := UInt<1>("h00") T_2.io.masters[1].w.bits.user := UInt<1>("h00") T_2.io.masters[1].w.bits.strb := UInt<1>("h00") T_2.io.masters[1].w.bits.last := UInt<1>("h00") T_2.io.masters[1].w.bits.data := UInt<1>("h00") T_2.io.masters[1].w.valid := UInt<1>("h00") T_2.io.masters[1].aw.bits.user := UInt<1>("h00") T_2.io.masters[1].aw.bits.id := UInt<1>("h00") T_2.io.masters[1].aw.bits.region := UInt<1>("h00") T_2.io.masters[1].aw.bits.qos := UInt<1>("h00") T_2.io.masters[1].aw.bits.prot := UInt<1>("h00") T_2.io.masters[1].aw.bits.cache := UInt<1>("h00") T_2.io.masters[1].aw.bits.lock := UInt<1>("h00") T_2.io.masters[1].aw.bits.burst := UInt<1>("h00") T_2.io.masters[1].aw.bits.size := UInt<1>("h00") T_2.io.masters[1].aw.bits.len := UInt<1>("h00") T_2.io.masters[1].aw.bits.addr := UInt<1>("h00") T_2.io.masters[1].aw.valid := UInt<1>("h00") T_2.clock := clock T_2.reset := reset T_2.io.masters <> io.masters io.slaves[0] <> T_2.io.slaves[0] inst T_2811 of NASTIRecursiveInterconnect_53 T_2811.io.slaves[0].r.bits.user := UInt<1>("h00") T_2811.io.slaves[0].r.bits.id := UInt<1>("h00") T_2811.io.slaves[0].r.bits.last := UInt<1>("h00") T_2811.io.slaves[0].r.bits.data := UInt<1>("h00") T_2811.io.slaves[0].r.bits.resp := UInt<1>("h00") T_2811.io.slaves[0].r.valid := UInt<1>("h00") T_2811.io.slaves[0].ar.ready := UInt<1>("h00") T_2811.io.slaves[0].b.bits.user := UInt<1>("h00") T_2811.io.slaves[0].b.bits.id := UInt<1>("h00") T_2811.io.slaves[0].b.bits.resp := UInt<1>("h00") T_2811.io.slaves[0].b.valid := UInt<1>("h00") T_2811.io.slaves[0].w.ready := UInt<1>("h00") T_2811.io.slaves[0].aw.ready := UInt<1>("h00") T_2811.io.slaves[1].r.bits.user := UInt<1>("h00") T_2811.io.slaves[1].r.bits.id := UInt<1>("h00") T_2811.io.slaves[1].r.bits.last := UInt<1>("h00") T_2811.io.slaves[1].r.bits.data := UInt<1>("h00") T_2811.io.slaves[1].r.bits.resp := UInt<1>("h00") T_2811.io.slaves[1].r.valid := UInt<1>("h00") T_2811.io.slaves[1].ar.ready := UInt<1>("h00") T_2811.io.slaves[1].b.bits.user := UInt<1>("h00") T_2811.io.slaves[1].b.bits.id := UInt<1>("h00") T_2811.io.slaves[1].b.bits.resp := UInt<1>("h00") T_2811.io.slaves[1].b.valid := UInt<1>("h00") T_2811.io.slaves[1].w.ready := UInt<1>("h00") T_2811.io.slaves[1].aw.ready := UInt<1>("h00") T_2811.io.masters[0].r.ready := UInt<1>("h00") T_2811.io.masters[0].ar.bits.user := UInt<1>("h00") T_2811.io.masters[0].ar.bits.id := UInt<1>("h00") T_2811.io.masters[0].ar.bits.region := UInt<1>("h00") T_2811.io.masters[0].ar.bits.qos := UInt<1>("h00") T_2811.io.masters[0].ar.bits.prot := UInt<1>("h00") T_2811.io.masters[0].ar.bits.cache := UInt<1>("h00") T_2811.io.masters[0].ar.bits.lock := UInt<1>("h00") T_2811.io.masters[0].ar.bits.burst := UInt<1>("h00") T_2811.io.masters[0].ar.bits.size := UInt<1>("h00") T_2811.io.masters[0].ar.bits.len := UInt<1>("h00") T_2811.io.masters[0].ar.bits.addr := UInt<1>("h00") T_2811.io.masters[0].ar.valid := UInt<1>("h00") T_2811.io.masters[0].b.ready := UInt<1>("h00") T_2811.io.masters[0].w.bits.user := UInt<1>("h00") T_2811.io.masters[0].w.bits.strb := UInt<1>("h00") T_2811.io.masters[0].w.bits.last := UInt<1>("h00") T_2811.io.masters[0].w.bits.data := UInt<1>("h00") T_2811.io.masters[0].w.valid := UInt<1>("h00") T_2811.io.masters[0].aw.bits.user := UInt<1>("h00") T_2811.io.masters[0].aw.bits.id := UInt<1>("h00") T_2811.io.masters[0].aw.bits.region := UInt<1>("h00") T_2811.io.masters[0].aw.bits.qos := UInt<1>("h00") T_2811.io.masters[0].aw.bits.prot := UInt<1>("h00") T_2811.io.masters[0].aw.bits.cache := UInt<1>("h00") T_2811.io.masters[0].aw.bits.lock := UInt<1>("h00") T_2811.io.masters[0].aw.bits.burst := UInt<1>("h00") T_2811.io.masters[0].aw.bits.size := UInt<1>("h00") T_2811.io.masters[0].aw.bits.len := UInt<1>("h00") T_2811.io.masters[0].aw.bits.addr := UInt<1>("h00") T_2811.io.masters[0].aw.valid := UInt<1>("h00") T_2811.clock := clock T_2811.reset := reset T_2811.io.masters[0] <> T_2.io.slaves[1] io.slaves[1] <> T_2811.io.slaves[0] io.slaves[2] <> T_2811.io.slaves[1] io.slaves[3] <> T_2.io.slaves[2] module Queue_60 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.user := UInt<1>("h00") io.deq.bits.strb := UInt<1>("h00") io.deq.bits.last := UInt<1>("h00") io.deq.bits.data := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}[2], clock reg T_62 : UInt<1>, clock, reset onreset T_62 := UInt<1>("h00") reg T_64 : UInt<1>, clock, reset onreset T_64 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_62, T_64) node T_69 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_69) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_75 = and(io.enq.ready, io.enq.valid) node T_77 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_75, T_77) node T_79 = and(io.deq.ready, io.deq.valid) node T_81 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_79, T_81) when do_enq : infer accessor T_83 = ram[T_62] T_83 <> io.enq.bits node T_89 = eq(T_62, UInt<1>("h01")) node T_91 = and(UInt<1>("h00"), T_89) node T_94 = addw(T_62, UInt<1>("h01")) node T_95 = mux(T_91, UInt<1>("h00"), T_94) T_62 := T_95 skip when do_deq : node T_97 = eq(T_64, UInt<1>("h01")) node T_99 = and(UInt<1>("h00"), T_97) node T_102 = addw(T_64, UInt<1>("h01")) node T_103 = mux(T_99, UInt<1>("h00"), T_102) T_64 := T_103 skip node T_104 = neq(do_enq, do_deq) when T_104 : maybe_full := do_enq skip node T_106 = eq(empty, UInt<1>("h00")) node T_108 = and(UInt<1>("h00"), io.enq.valid) node T_109 = or(T_106, T_108) io.deq.valid := T_109 node T_111 = eq(full, UInt<1>("h00")) node T_113 = and(UInt<1>("h00"), io.deq.ready) node T_114 = or(T_111, T_113) io.enq.ready := T_114 infer accessor T_115 = ram[T_64] wire T_125 : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>} T_125 <> T_115 when maybe_flow : T_125 <> io.enq.bits skip io.deq.bits <> T_125 node ptr_diff = subw(T_62, T_64) node T_131 = and(maybe_full, ptr_match) node T_132 = cat(T_131, ptr_diff) io.count := T_132 module NASTITopInterconnect : input clock : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[4]} io.slaves[0].r.ready := UInt<1>("h00") io.slaves[0].ar.bits.user := UInt<1>("h00") io.slaves[0].ar.bits.id := UInt<1>("h00") io.slaves[0].ar.bits.region := UInt<1>("h00") io.slaves[0].ar.bits.qos := UInt<1>("h00") io.slaves[0].ar.bits.prot := UInt<1>("h00") io.slaves[0].ar.bits.cache := UInt<1>("h00") io.slaves[0].ar.bits.lock := UInt<1>("h00") io.slaves[0].ar.bits.burst := UInt<1>("h00") io.slaves[0].ar.bits.size := UInt<1>("h00") io.slaves[0].ar.bits.len := UInt<1>("h00") io.slaves[0].ar.bits.addr := UInt<1>("h00") io.slaves[0].ar.valid := UInt<1>("h00") io.slaves[0].b.ready := UInt<1>("h00") io.slaves[0].w.bits.user := UInt<1>("h00") io.slaves[0].w.bits.strb := UInt<1>("h00") io.slaves[0].w.bits.last := UInt<1>("h00") io.slaves[0].w.bits.data := UInt<1>("h00") io.slaves[0].w.valid := UInt<1>("h00") io.slaves[0].aw.bits.user := UInt<1>("h00") io.slaves[0].aw.bits.id := UInt<1>("h00") io.slaves[0].aw.bits.region := UInt<1>("h00") io.slaves[0].aw.bits.qos := UInt<1>("h00") io.slaves[0].aw.bits.prot := UInt<1>("h00") io.slaves[0].aw.bits.cache := UInt<1>("h00") io.slaves[0].aw.bits.lock := UInt<1>("h00") io.slaves[0].aw.bits.burst := UInt<1>("h00") io.slaves[0].aw.bits.size := UInt<1>("h00") io.slaves[0].aw.bits.len := UInt<1>("h00") io.slaves[0].aw.bits.addr := UInt<1>("h00") io.slaves[0].aw.valid := UInt<1>("h00") io.slaves[1].r.ready := UInt<1>("h00") io.slaves[1].ar.bits.user := UInt<1>("h00") io.slaves[1].ar.bits.id := UInt<1>("h00") io.slaves[1].ar.bits.region := UInt<1>("h00") io.slaves[1].ar.bits.qos := UInt<1>("h00") io.slaves[1].ar.bits.prot := UInt<1>("h00") io.slaves[1].ar.bits.cache := UInt<1>("h00") io.slaves[1].ar.bits.lock := UInt<1>("h00") io.slaves[1].ar.bits.burst := UInt<1>("h00") io.slaves[1].ar.bits.size := UInt<1>("h00") io.slaves[1].ar.bits.len := UInt<1>("h00") io.slaves[1].ar.bits.addr := UInt<1>("h00") io.slaves[1].ar.valid := UInt<1>("h00") io.slaves[1].b.ready := UInt<1>("h00") io.slaves[1].w.bits.user := UInt<1>("h00") io.slaves[1].w.bits.strb := UInt<1>("h00") io.slaves[1].w.bits.last := UInt<1>("h00") io.slaves[1].w.bits.data := UInt<1>("h00") io.slaves[1].w.valid := UInt<1>("h00") io.slaves[1].aw.bits.user := UInt<1>("h00") io.slaves[1].aw.bits.id := UInt<1>("h00") io.slaves[1].aw.bits.region := UInt<1>("h00") io.slaves[1].aw.bits.qos := UInt<1>("h00") io.slaves[1].aw.bits.prot := UInt<1>("h00") io.slaves[1].aw.bits.cache := UInt<1>("h00") io.slaves[1].aw.bits.lock := UInt<1>("h00") io.slaves[1].aw.bits.burst := UInt<1>("h00") io.slaves[1].aw.bits.size := UInt<1>("h00") io.slaves[1].aw.bits.len := UInt<1>("h00") io.slaves[1].aw.bits.addr := UInt<1>("h00") io.slaves[1].aw.valid := UInt<1>("h00") io.slaves[2].r.ready := UInt<1>("h00") io.slaves[2].ar.bits.user := UInt<1>("h00") io.slaves[2].ar.bits.id := UInt<1>("h00") io.slaves[2].ar.bits.region := UInt<1>("h00") io.slaves[2].ar.bits.qos := UInt<1>("h00") io.slaves[2].ar.bits.prot := UInt<1>("h00") io.slaves[2].ar.bits.cache := UInt<1>("h00") io.slaves[2].ar.bits.lock := UInt<1>("h00") io.slaves[2].ar.bits.burst := UInt<1>("h00") io.slaves[2].ar.bits.size := UInt<1>("h00") io.slaves[2].ar.bits.len := UInt<1>("h00") io.slaves[2].ar.bits.addr := UInt<1>("h00") io.slaves[2].ar.valid := UInt<1>("h00") io.slaves[2].b.ready := UInt<1>("h00") io.slaves[2].w.bits.user := UInt<1>("h00") io.slaves[2].w.bits.strb := UInt<1>("h00") io.slaves[2].w.bits.last := UInt<1>("h00") io.slaves[2].w.bits.data := UInt<1>("h00") io.slaves[2].w.valid := UInt<1>("h00") io.slaves[2].aw.bits.user := UInt<1>("h00") io.slaves[2].aw.bits.id := UInt<1>("h00") io.slaves[2].aw.bits.region := UInt<1>("h00") io.slaves[2].aw.bits.qos := UInt<1>("h00") io.slaves[2].aw.bits.prot := UInt<1>("h00") io.slaves[2].aw.bits.cache := UInt<1>("h00") io.slaves[2].aw.bits.lock := UInt<1>("h00") io.slaves[2].aw.bits.burst := UInt<1>("h00") io.slaves[2].aw.bits.size := UInt<1>("h00") io.slaves[2].aw.bits.len := UInt<1>("h00") io.slaves[2].aw.bits.addr := UInt<1>("h00") io.slaves[2].aw.valid := UInt<1>("h00") io.slaves[3].r.ready := UInt<1>("h00") io.slaves[3].ar.bits.user := UInt<1>("h00") io.slaves[3].ar.bits.id := UInt<1>("h00") io.slaves[3].ar.bits.region := UInt<1>("h00") io.slaves[3].ar.bits.qos := UInt<1>("h00") io.slaves[3].ar.bits.prot := UInt<1>("h00") io.slaves[3].ar.bits.cache := UInt<1>("h00") io.slaves[3].ar.bits.lock := UInt<1>("h00") io.slaves[3].ar.bits.burst := UInt<1>("h00") io.slaves[3].ar.bits.size := UInt<1>("h00") io.slaves[3].ar.bits.len := UInt<1>("h00") io.slaves[3].ar.bits.addr := UInt<1>("h00") io.slaves[3].ar.valid := UInt<1>("h00") io.slaves[3].b.ready := UInt<1>("h00") io.slaves[3].w.bits.user := UInt<1>("h00") io.slaves[3].w.bits.strb := UInt<1>("h00") io.slaves[3].w.bits.last := UInt<1>("h00") io.slaves[3].w.bits.data := UInt<1>("h00") io.slaves[3].w.valid := UInt<1>("h00") io.slaves[3].aw.bits.user := UInt<1>("h00") io.slaves[3].aw.bits.id := UInt<1>("h00") io.slaves[3].aw.bits.region := UInt<1>("h00") io.slaves[3].aw.bits.qos := UInt<1>("h00") io.slaves[3].aw.bits.prot := UInt<1>("h00") io.slaves[3].aw.bits.cache := UInt<1>("h00") io.slaves[3].aw.bits.lock := UInt<1>("h00") io.slaves[3].aw.bits.burst := UInt<1>("h00") io.slaves[3].aw.bits.size := UInt<1>("h00") io.slaves[3].aw.bits.len := UInt<1>("h00") io.slaves[3].aw.bits.addr := UInt<1>("h00") io.slaves[3].aw.valid := UInt<1>("h00") io.masters[0].r.bits.user := UInt<1>("h00") io.masters[0].r.bits.id := UInt<1>("h00") io.masters[0].r.bits.last := UInt<1>("h00") io.masters[0].r.bits.data := UInt<1>("h00") io.masters[0].r.bits.resp := UInt<1>("h00") io.masters[0].r.valid := UInt<1>("h00") io.masters[0].ar.ready := UInt<1>("h00") io.masters[0].b.bits.user := UInt<1>("h00") io.masters[0].b.bits.id := UInt<1>("h00") io.masters[0].b.bits.resp := UInt<1>("h00") io.masters[0].b.valid := UInt<1>("h00") io.masters[0].w.ready := UInt<1>("h00") io.masters[0].aw.ready := UInt<1>("h00") io.masters[1].r.bits.user := UInt<1>("h00") io.masters[1].r.bits.id := UInt<1>("h00") io.masters[1].r.bits.last := UInt<1>("h00") io.masters[1].r.bits.data := UInt<1>("h00") io.masters[1].r.bits.resp := UInt<1>("h00") io.masters[1].r.valid := UInt<1>("h00") io.masters[1].ar.ready := UInt<1>("h00") io.masters[1].b.bits.user := UInt<1>("h00") io.masters[1].b.bits.id := UInt<1>("h00") io.masters[1].b.bits.resp := UInt<1>("h00") io.masters[1].b.valid := UInt<1>("h00") io.masters[1].w.ready := UInt<1>("h00") io.masters[1].aw.ready := UInt<1>("h00") inst temp of NASTIRecursiveInterconnect temp.io.slaves[0].r.bits.user := UInt<1>("h00") temp.io.slaves[0].r.bits.id := UInt<1>("h00") temp.io.slaves[0].r.bits.last := UInt<1>("h00") temp.io.slaves[0].r.bits.data := UInt<1>("h00") temp.io.slaves[0].r.bits.resp := UInt<1>("h00") temp.io.slaves[0].r.valid := UInt<1>("h00") temp.io.slaves[0].ar.ready := UInt<1>("h00") temp.io.slaves[0].b.bits.user := UInt<1>("h00") temp.io.slaves[0].b.bits.id := UInt<1>("h00") temp.io.slaves[0].b.bits.resp := UInt<1>("h00") temp.io.slaves[0].b.valid := UInt<1>("h00") temp.io.slaves[0].w.ready := UInt<1>("h00") temp.io.slaves[0].aw.ready := UInt<1>("h00") temp.io.slaves[1].r.bits.user := UInt<1>("h00") temp.io.slaves[1].r.bits.id := UInt<1>("h00") temp.io.slaves[1].r.bits.last := UInt<1>("h00") temp.io.slaves[1].r.bits.data := UInt<1>("h00") temp.io.slaves[1].r.bits.resp := UInt<1>("h00") temp.io.slaves[1].r.valid := UInt<1>("h00") temp.io.slaves[1].ar.ready := UInt<1>("h00") temp.io.slaves[1].b.bits.user := UInt<1>("h00") temp.io.slaves[1].b.bits.id := UInt<1>("h00") temp.io.slaves[1].b.bits.resp := UInt<1>("h00") temp.io.slaves[1].b.valid := UInt<1>("h00") temp.io.slaves[1].w.ready := UInt<1>("h00") temp.io.slaves[1].aw.ready := UInt<1>("h00") temp.io.slaves[2].r.bits.user := UInt<1>("h00") temp.io.slaves[2].r.bits.id := UInt<1>("h00") temp.io.slaves[2].r.bits.last := UInt<1>("h00") temp.io.slaves[2].r.bits.data := UInt<1>("h00") temp.io.slaves[2].r.bits.resp := UInt<1>("h00") temp.io.slaves[2].r.valid := UInt<1>("h00") temp.io.slaves[2].ar.ready := UInt<1>("h00") temp.io.slaves[2].b.bits.user := UInt<1>("h00") temp.io.slaves[2].b.bits.id := UInt<1>("h00") temp.io.slaves[2].b.bits.resp := UInt<1>("h00") temp.io.slaves[2].b.valid := UInt<1>("h00") temp.io.slaves[2].w.ready := UInt<1>("h00") temp.io.slaves[2].aw.ready := UInt<1>("h00") temp.io.slaves[3].r.bits.user := UInt<1>("h00") temp.io.slaves[3].r.bits.id := UInt<1>("h00") temp.io.slaves[3].r.bits.last := UInt<1>("h00") temp.io.slaves[3].r.bits.data := UInt<1>("h00") temp.io.slaves[3].r.bits.resp := UInt<1>("h00") temp.io.slaves[3].r.valid := UInt<1>("h00") temp.io.slaves[3].ar.ready := UInt<1>("h00") temp.io.slaves[3].b.bits.user := UInt<1>("h00") temp.io.slaves[3].b.bits.id := UInt<1>("h00") temp.io.slaves[3].b.bits.resp := UInt<1>("h00") temp.io.slaves[3].b.valid := UInt<1>("h00") temp.io.slaves[3].w.ready := UInt<1>("h00") temp.io.slaves[3].aw.ready := UInt<1>("h00") temp.io.masters[0].r.ready := UInt<1>("h00") temp.io.masters[0].ar.bits.user := UInt<1>("h00") temp.io.masters[0].ar.bits.id := UInt<1>("h00") temp.io.masters[0].ar.bits.region := UInt<1>("h00") temp.io.masters[0].ar.bits.qos := UInt<1>("h00") temp.io.masters[0].ar.bits.prot := UInt<1>("h00") temp.io.masters[0].ar.bits.cache := UInt<1>("h00") temp.io.masters[0].ar.bits.lock := UInt<1>("h00") temp.io.masters[0].ar.bits.burst := UInt<1>("h00") temp.io.masters[0].ar.bits.size := UInt<1>("h00") temp.io.masters[0].ar.bits.len := UInt<1>("h00") temp.io.masters[0].ar.bits.addr := UInt<1>("h00") temp.io.masters[0].ar.valid := UInt<1>("h00") temp.io.masters[0].b.ready := UInt<1>("h00") temp.io.masters[0].w.bits.user := UInt<1>("h00") temp.io.masters[0].w.bits.strb := UInt<1>("h00") temp.io.masters[0].w.bits.last := UInt<1>("h00") temp.io.masters[0].w.bits.data := UInt<1>("h00") temp.io.masters[0].w.valid := UInt<1>("h00") temp.io.masters[0].aw.bits.user := UInt<1>("h00") temp.io.masters[0].aw.bits.id := UInt<1>("h00") temp.io.masters[0].aw.bits.region := UInt<1>("h00") temp.io.masters[0].aw.bits.qos := UInt<1>("h00") temp.io.masters[0].aw.bits.prot := UInt<1>("h00") temp.io.masters[0].aw.bits.cache := UInt<1>("h00") temp.io.masters[0].aw.bits.lock := UInt<1>("h00") temp.io.masters[0].aw.bits.burst := UInt<1>("h00") temp.io.masters[0].aw.bits.size := UInt<1>("h00") temp.io.masters[0].aw.bits.len := UInt<1>("h00") temp.io.masters[0].aw.bits.addr := UInt<1>("h00") temp.io.masters[0].aw.valid := UInt<1>("h00") temp.io.masters[1].r.ready := UInt<1>("h00") temp.io.masters[1].ar.bits.user := UInt<1>("h00") temp.io.masters[1].ar.bits.id := UInt<1>("h00") temp.io.masters[1].ar.bits.region := UInt<1>("h00") temp.io.masters[1].ar.bits.qos := UInt<1>("h00") temp.io.masters[1].ar.bits.prot := UInt<1>("h00") temp.io.masters[1].ar.bits.cache := UInt<1>("h00") temp.io.masters[1].ar.bits.lock := UInt<1>("h00") temp.io.masters[1].ar.bits.burst := UInt<1>("h00") temp.io.masters[1].ar.bits.size := UInt<1>("h00") temp.io.masters[1].ar.bits.len := UInt<1>("h00") temp.io.masters[1].ar.bits.addr := UInt<1>("h00") temp.io.masters[1].ar.valid := UInt<1>("h00") temp.io.masters[1].b.ready := UInt<1>("h00") temp.io.masters[1].w.bits.user := UInt<1>("h00") temp.io.masters[1].w.bits.strb := UInt<1>("h00") temp.io.masters[1].w.bits.last := UInt<1>("h00") temp.io.masters[1].w.bits.data := UInt<1>("h00") temp.io.masters[1].w.valid := UInt<1>("h00") temp.io.masters[1].aw.bits.user := UInt<1>("h00") temp.io.masters[1].aw.bits.id := UInt<1>("h00") temp.io.masters[1].aw.bits.region := UInt<1>("h00") temp.io.masters[1].aw.bits.qos := UInt<1>("h00") temp.io.masters[1].aw.bits.prot := UInt<1>("h00") temp.io.masters[1].aw.bits.cache := UInt<1>("h00") temp.io.masters[1].aw.bits.lock := UInt<1>("h00") temp.io.masters[1].aw.bits.burst := UInt<1>("h00") temp.io.masters[1].aw.bits.size := UInt<1>("h00") temp.io.masters[1].aw.bits.len := UInt<1>("h00") temp.io.masters[1].aw.bits.addr := UInt<1>("h00") temp.io.masters[1].aw.valid := UInt<1>("h00") temp.clock := clock temp.reset := reset temp.io.masters[0].ar <> io.masters[0].ar temp.io.masters[0].aw <> io.masters[0].aw inst T_2829 of Queue_60 T_2829.io.deq.ready := UInt<1>("h00") T_2829.io.enq.bits.user := UInt<1>("h00") T_2829.io.enq.bits.strb := UInt<1>("h00") T_2829.io.enq.bits.last := UInt<1>("h00") T_2829.io.enq.bits.data := UInt<1>("h00") T_2829.io.enq.valid := UInt<1>("h00") T_2829.clock := clock T_2829.reset := reset T_2829.io.enq.valid := io.masters[0].w.valid T_2829.io.enq.bits <> io.masters[0].w.bits io.masters[0].w.ready := T_2829.io.enq.ready temp.io.masters[0].w <> T_2829.io.deq io.masters[0].b <> temp.io.masters[0].b io.masters[0].r <> temp.io.masters[0].r temp.io.masters[1].ar <> io.masters[1].ar temp.io.masters[1].aw <> io.masters[1].aw inst T_2841 of Queue_60 T_2841.io.deq.ready := UInt<1>("h00") T_2841.io.enq.bits.user := UInt<1>("h00") T_2841.io.enq.bits.strb := UInt<1>("h00") T_2841.io.enq.bits.last := UInt<1>("h00") T_2841.io.enq.bits.data := UInt<1>("h00") T_2841.io.enq.valid := UInt<1>("h00") T_2841.clock := clock T_2841.reset := reset T_2841.io.enq.valid := io.masters[1].w.valid T_2841.io.enq.bits <> io.masters[1].w.bits io.masters[1].w.ready := T_2841.io.enq.ready temp.io.masters[1].w <> T_2841.io.deq io.masters[1].b <> temp.io.masters[1].b io.masters[1].r <> temp.io.masters[1].r io.slaves <> temp.io.slaves module LockingRRArbiter_62 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.union := UInt<1>("h00") io.out.bits.a_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") reg T_656 : UInt<1>, clock, reset onreset T_656 := UInt<1>("h00") reg T_658 : UInt, clock, reset onreset T_658 := UInt<1>("h01") wire T_660 : UInt<1> T_660 := UInt<1>("h00") infer accessor T_662 = io.in[T_660] io.out.valid := T_662.valid infer accessor T_721 = io.in[T_660] io.out.bits <> T_721.bits io.chosen := T_660 infer accessor T_780 = io.in[T_660] T_780.ready := UInt<1>("h00") reg last_grant : UInt<1>, clock, reset onreset last_grant := UInt<1>("h00") node T_843 = gt(UInt<1>("h00"), last_grant) node T_844 = and(io.in[0].valid, T_843) node T_846 = gt(UInt<1>("h01"), last_grant) node T_847 = and(io.in[1].valid, T_846) node T_850 = or(UInt<1>("h00"), T_844) node T_852 = eq(T_850, UInt<1>("h00")) node T_854 = or(UInt<1>("h00"), T_844) node T_855 = or(T_854, T_847) node T_857 = eq(T_855, UInt<1>("h00")) node T_859 = or(UInt<1>("h00"), T_844) node T_860 = or(T_859, T_847) node T_861 = or(T_860, io.in[0].valid) node T_863 = eq(T_861, UInt<1>("h00")) node T_865 = gt(UInt<1>("h00"), last_grant) node T_866 = and(UInt<1>("h01"), T_865) node T_867 = or(T_866, T_857) node T_869 = gt(UInt<1>("h01"), last_grant) node T_870 = and(T_852, T_869) node T_871 = or(T_870, T_863) node T_873 = eq(T_658, UInt<1>("h00")) node T_874 = mux(T_656, T_873, T_867) node T_875 = and(T_874, io.out.ready) io.in[0].ready := T_875 node T_877 = eq(T_658, UInt<1>("h01")) node T_878 = mux(T_656, T_877, T_871) node T_879 = and(T_878, io.out.ready) io.in[1].ready := T_879 reg T_881 : UInt<2>, clock, reset onreset T_881 := UInt<2>("h00") node T_883 = addw(T_881, UInt<1>("h01")) node T_884 = and(io.out.ready, io.out.valid) when T_884 : node T_886 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_889 : UInt<3>[1] T_889[0] := UInt<3>("h03") node T_892 = eq(T_889[0], io.out.bits.a_type) node T_894 = or(UInt<1>("h00"), T_892) node T_895 = and(T_886, T_894) when T_895 : T_881 := T_883 node T_897 = eq(T_656, UInt<1>("h00")) when T_897 : T_656 := UInt<1>("h01") node T_899 = and(io.in[0].ready, io.in[0].valid) node T_900 = and(io.in[1].ready, io.in[1].valid) wire T_902 : UInt<1>[2] T_902[0] := T_899 T_902[1] := T_900 node T_908 = mux(T_902[0], UInt<1>("h00"), UInt<1>("h01")) T_658 := T_908 skip skip node T_910 = eq(T_883, UInt<1>("h00")) when T_910 : T_656 := UInt<1>("h00") skip skip node T_914 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_916 = gt(UInt<1>("h01"), last_grant) node T_917 = and(io.in[1].valid, T_916) node choose = mux(T_917, UInt<1>("h01"), T_914) node T_920 = mux(T_656, T_658, choose) T_660 := T_920 node T_921 = and(io.out.ready, io.out.valid) when T_921 : last_grant := T_660 skip module RRArbiter_63 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {voluntary : UInt<1>, builtin : UInt<1>}, tag : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {voluntary : UInt<1>, builtin : UInt<1>}, tag : UInt<4>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.tag := UInt<1>("h00") io.out.bits.data.builtin := UInt<1>("h00") io.out.bits.data.voluntary := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_152 : UInt<1> T_152 := UInt<1>("h00") infer accessor T_154 = io.in[T_152] io.out.valid := T_154.valid infer accessor T_167 = io.in[T_152] io.out.bits <> T_167.bits io.chosen := T_152 infer accessor T_180 = io.in[T_152] T_180.ready := UInt<1>("h00") reg T_196 : UInt<1>, clock, reset onreset T_196 := UInt<1>("h00") node T_197 = gt(UInt<1>("h00"), T_196) node T_198 = and(io.in[0].valid, T_197) node T_200 = gt(UInt<1>("h01"), T_196) node T_201 = and(io.in[1].valid, T_200) node T_204 = or(UInt<1>("h00"), T_198) node T_206 = eq(T_204, UInt<1>("h00")) node T_208 = or(UInt<1>("h00"), T_198) node T_209 = or(T_208, T_201) node T_211 = eq(T_209, UInt<1>("h00")) node T_213 = or(UInt<1>("h00"), T_198) node T_214 = or(T_213, T_201) node T_215 = or(T_214, io.in[0].valid) node T_217 = eq(T_215, UInt<1>("h00")) node T_219 = gt(UInt<1>("h00"), T_196) node T_220 = and(UInt<1>("h01"), T_219) node T_221 = or(T_220, T_211) node T_223 = gt(UInt<1>("h01"), T_196) node T_224 = and(T_206, T_223) node T_225 = or(T_224, T_217) node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_228 = mux(UInt<1>("h00"), T_227, T_221) node T_229 = and(T_228, io.out.ready) io.in[0].ready := T_229 node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_232 = mux(UInt<1>("h00"), T_231, T_225) node T_233 = and(T_232, io.out.ready) io.in[1].ready := T_233 node T_236 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_238 = gt(UInt<1>("h01"), T_196) node T_239 = and(io.in[1].valid, T_238) node T_241 = mux(T_239, UInt<1>("h01"), T_236) node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) T_152 := T_242 node T_243 = and(io.out.ready, io.out.valid) when T_243 : T_196 := T_152 skip module ReorderQueue : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {voluntary : UInt<1>, builtin : UInt<1>}, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : {voluntary : UInt<1>, builtin : UInt<1>}}, full : UInt<1>} io.full := UInt<1>("h00") io.deq.data.builtin := UInt<1>("h00") io.deq.data.voluntary := UInt<1>("h00") io.enq.ready := UInt<1>("h00") reg roq_data : {voluntary : UInt<1>, builtin : UInt<1>}[9], clock, reset reg roq_tags : UInt<4>[9], clock, reset wire T_155 : UInt<1>[9] T_155[0] := UInt<1>("h01") T_155[1] := UInt<1>("h01") T_155[2] := UInt<1>("h01") T_155[3] := UInt<1>("h01") T_155[4] := UInt<1>("h01") T_155[5] := UInt<1>("h01") T_155[6] := UInt<1>("h01") T_155[7] := UInt<1>("h01") T_155[8] := UInt<1>("h01") reg roq_free : UInt<1>[9], clock, reset onreset roq_free := T_155 node T_188 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) node T_189 = mux(roq_free[6], UInt<3>("h06"), T_188) node T_190 = mux(roq_free[5], UInt<3>("h05"), T_189) node T_191 = mux(roq_free[4], UInt<3>("h04"), T_190) node T_192 = mux(roq_free[3], UInt<2>("h03"), T_191) node T_193 = mux(roq_free[2], UInt<2>("h02"), T_192) node T_194 = mux(roq_free[1], UInt<1>("h01"), T_193) node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_194) node T_196 = eq(roq_tags[0], io.deq.tag) node T_197 = eq(roq_tags[1], io.deq.tag) node T_198 = eq(roq_tags[2], io.deq.tag) node T_199 = eq(roq_tags[3], io.deq.tag) node T_200 = eq(roq_tags[4], io.deq.tag) node T_201 = eq(roq_tags[5], io.deq.tag) node T_202 = eq(roq_tags[6], io.deq.tag) node T_203 = eq(roq_tags[7], io.deq.tag) node T_204 = eq(roq_tags[8], io.deq.tag) node T_214 = mux(T_203, UInt<3>("h07"), UInt<4>("h08")) node T_215 = mux(T_202, UInt<3>("h06"), T_214) node T_216 = mux(T_201, UInt<3>("h05"), T_215) node T_217 = mux(T_200, UInt<3>("h04"), T_216) node T_218 = mux(T_199, UInt<2>("h03"), T_217) node T_219 = mux(T_198, UInt<2>("h02"), T_218) node T_220 = mux(T_197, UInt<1>("h01"), T_219) node roq_deq_addr = mux(T_196, UInt<1>("h00"), T_220) node T_222 = or(roq_free[0], roq_free[1]) node T_223 = or(T_222, roq_free[2]) node T_224 = or(T_223, roq_free[3]) node T_225 = or(T_224, roq_free[4]) node T_226 = or(T_225, roq_free[5]) node T_227 = or(T_226, roq_free[6]) node T_228 = or(T_227, roq_free[7]) node T_229 = or(T_228, roq_free[8]) io.enq.ready := T_229 infer accessor T_230 = roq_data[roq_deq_addr] io.deq.data <> T_230 node T_233 = and(io.enq.valid, io.enq.ready) when T_233 : infer accessor T_234 = roq_data[roq_enq_addr] T_234 <> io.enq.bits.data infer accessor T_237 = roq_tags[roq_enq_addr] T_237 := io.enq.bits.tag infer accessor T_238 = roq_free[roq_enq_addr] T_238 := UInt<1>("h00") skip when io.deq.valid : infer accessor T_240 = roq_free[roq_deq_addr] T_240 := UInt<1>("h01") skip module ClientTileLinkIOUnwrapper : input clock : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.out.grant.ready := UInt<1>("h00") io.out.acquire.bits.union := UInt<1>("h00") io.out.acquire.bits.a_type := UInt<1>("h00") io.out.acquire.bits.is_builtin_type := UInt<1>("h00") io.out.acquire.bits.data := UInt<1>("h00") io.out.acquire.bits.addr_beat := UInt<1>("h00") io.out.acquire.bits.client_xact_id := UInt<1>("h00") io.out.acquire.bits.addr_block := UInt<1>("h00") io.out.acquire.valid := UInt<1>("h00") io.in.release.ready := UInt<1>("h00") io.in.probe.bits.p_type := UInt<1>("h00") io.in.probe.bits.addr_block := UInt<1>("h00") io.in.probe.valid := UInt<1>("h00") io.in.grant.bits.g_type := UInt<1>("h00") io.in.grant.bits.is_builtin_type := UInt<1>("h00") io.in.grant.bits.manager_xact_id := UInt<1>("h00") io.in.grant.bits.client_xact_id := UInt<1>("h00") io.in.grant.bits.data := UInt<1>("h00") io.in.grant.bits.addr_beat := UInt<1>("h00") io.in.grant.valid := UInt<1>("h00") io.in.acquire.ready := UInt<1>("h00") inst acqArb of LockingRRArbiter_62 acqArb.io.out.ready := UInt<1>("h00") acqArb.io.in[0].bits.union := UInt<1>("h00") acqArb.io.in[0].bits.a_type := UInt<1>("h00") acqArb.io.in[0].bits.is_builtin_type := UInt<1>("h00") acqArb.io.in[0].bits.data := UInt<1>("h00") acqArb.io.in[0].bits.addr_beat := UInt<1>("h00") acqArb.io.in[0].bits.client_xact_id := UInt<1>("h00") acqArb.io.in[0].bits.addr_block := UInt<1>("h00") acqArb.io.in[0].valid := UInt<1>("h00") acqArb.io.in[1].bits.union := UInt<1>("h00") acqArb.io.in[1].bits.a_type := UInt<1>("h00") acqArb.io.in[1].bits.is_builtin_type := UInt<1>("h00") acqArb.io.in[1].bits.data := UInt<1>("h00") acqArb.io.in[1].bits.addr_beat := UInt<1>("h00") acqArb.io.in[1].bits.client_xact_id := UInt<1>("h00") acqArb.io.in[1].bits.addr_block := UInt<1>("h00") acqArb.io.in[1].valid := UInt<1>("h00") acqArb.clock := clock acqArb.reset := reset inst roqArb of RRArbiter_63 roqArb.io.out.ready := UInt<1>("h00") roqArb.io.in[0].bits.tag := UInt<1>("h00") roqArb.io.in[0].bits.data.builtin := UInt<1>("h00") roqArb.io.in[0].bits.data.voluntary := UInt<1>("h00") roqArb.io.in[0].valid := UInt<1>("h00") roqArb.io.in[1].bits.tag := UInt<1>("h00") roqArb.io.in[1].bits.data.builtin := UInt<1>("h00") roqArb.io.in[1].bits.data.voluntary := UInt<1>("h00") roqArb.io.in[1].valid := UInt<1>("h00") roqArb.clock := clock roqArb.reset := reset node T_1246 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) wire T_1249 : UInt<3>[1] T_1249[0] := UInt<3>("h03") node T_1252 = eq(T_1249[0], io.in.acquire.bits.a_type) node T_1254 = or(UInt<1>("h00"), T_1252) node T_1255 = and(T_1246, T_1254) node T_1257 = eq(T_1255, UInt<1>("h00")) node T_1259 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) node T_1260 = or(T_1257, T_1259) node T_1262 = eq(roqArb.io.in[0].ready, UInt<1>("h00")) node iacq_wait = and(T_1260, T_1262) wire T_1266 : UInt<2>[3] T_1266[0] := UInt<1>("h00") T_1266[1] := UInt<1>("h01") T_1266[2] := UInt<2>("h02") node T_1271 = eq(T_1266[0], io.in.release.bits.r_type) node T_1272 = eq(T_1266[1], io.in.release.bits.r_type) node T_1273 = eq(T_1266[2], io.in.release.bits.r_type) node T_1275 = or(UInt<1>("h00"), T_1271) node T_1276 = or(T_1275, T_1272) node T_1277 = or(T_1276, T_1273) node T_1278 = and(UInt<1>("h01"), T_1277) node T_1280 = eq(T_1278, UInt<1>("h00")) node T_1282 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) node T_1283 = or(T_1280, T_1282) node T_1285 = eq(roqArb.io.in[1].ready, UInt<1>("h00")) node irel_wait = and(T_1283, T_1285) node T_1288 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) wire T_1291 : UInt<3>[1] T_1291[0] := UInt<3>("h03") node T_1294 = eq(T_1291[0], io.in.acquire.bits.a_type) node T_1296 = or(UInt<1>("h00"), T_1294) node T_1297 = and(T_1288, T_1296) node T_1299 = eq(T_1297, UInt<1>("h00")) node T_1301 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) node T_1302 = or(T_1299, T_1301) node T_1303 = and(io.in.acquire.valid, T_1302) roqArb.io.in[0].valid := T_1303 roqArb.io.in[0].bits.data.voluntary := UInt<1>("h00") roqArb.io.in[0].bits.data.builtin := io.in.acquire.bits.is_builtin_type roqArb.io.in[0].bits.tag := io.in.acquire.bits.client_xact_id node T_1306 = eq(iacq_wait, UInt<1>("h00")) node T_1307 = and(io.in.acquire.valid, T_1306) acqArb.io.in[0].valid := T_1307 node T_1310 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) node T_1340 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1342 = cat(T_1340, UInt<1>("h00")) node T_1343 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1342) wire T_1372 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1372.union := UInt<1>("h00") T_1372.a_type := UInt<1>("h00") T_1372.is_builtin_type := UInt<1>("h00") T_1372.data := UInt<1>("h00") T_1372.addr_beat := UInt<1>("h00") T_1372.client_xact_id := UInt<1>("h00") T_1372.addr_block := UInt<1>("h00") T_1372.is_builtin_type := UInt<1>("h01") T_1372.a_type := T_1310 T_1372.client_xact_id := io.in.acquire.bits.client_xact_id T_1372.addr_block := io.in.acquire.bits.addr_block T_1372.addr_beat := io.in.acquire.bits.addr_beat T_1372.data := io.in.acquire.bits.data T_1372.union := T_1343 acqArb.io.in[0].bits <> T_1372 node T_1408 = eq(iacq_wait, UInt<1>("h00")) node T_1409 = and(acqArb.io.in[0].ready, T_1408) io.in.acquire.ready := T_1409 node T_1411 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) wire T_1414 : UInt<3>[1] T_1414[0] := UInt<3>("h03") node T_1417 = eq(T_1414[0], io.in.acquire.bits.a_type) node T_1419 = or(UInt<1>("h00"), T_1417) node T_1420 = and(T_1411, T_1419) node T_1422 = eq(T_1420, UInt<1>("h00")) node T_1424 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) node T_1425 = or(T_1422, T_1424) node T_1426 = and(io.in.release.valid, T_1425) roqArb.io.in[1].valid := T_1426 roqArb.io.in[1].bits.data.voluntary := io.in.release.bits.voluntary roqArb.io.in[1].bits.data.builtin := UInt<1>("h01") roqArb.io.in[1].bits.tag := io.in.release.bits.client_xact_id node T_1429 = eq(irel_wait, UInt<1>("h00")) node T_1430 = and(io.in.release.valid, T_1429) acqArb.io.in[1].valid := T_1430 node T_1460 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1492 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1493 = neq(T_1460, T_1492) node T_1494 = cat(T_1460, T_1493) wire T_1523 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1523.union := UInt<1>("h00") T_1523.a_type := UInt<1>("h00") T_1523.is_builtin_type := UInt<1>("h00") T_1523.data := UInt<1>("h00") T_1523.addr_beat := UInt<1>("h00") T_1523.client_xact_id := UInt<1>("h00") T_1523.addr_block := UInt<1>("h00") T_1523.is_builtin_type := UInt<1>("h01") T_1523.a_type := UInt<3>("h03") T_1523.client_xact_id := io.in.release.bits.client_xact_id T_1523.addr_block := io.in.release.bits.addr_block T_1523.addr_beat := io.in.release.bits.addr_beat T_1523.data := io.in.release.bits.data T_1523.union := T_1494 acqArb.io.in[1].bits <> T_1523 node T_1559 = eq(irel_wait, UInt<1>("h00")) node T_1560 = and(acqArb.io.in[1].ready, T_1559) io.in.release.ready := T_1560 io.out.acquire <> acqArb.io.out inst roq of ReorderQueue roq.io.deq.tag := UInt<1>("h00") roq.io.deq.valid := UInt<1>("h00") roq.io.enq.bits.tag := UInt<1>("h00") roq.io.enq.bits.data.builtin := UInt<1>("h00") roq.io.enq.bits.data.voluntary := UInt<1>("h00") roq.io.enq.valid := UInt<1>("h00") roq.clock := clock roq.reset := reset roq.io.enq <> roqArb.io.out wire T_1574 : UInt<3>[1] T_1574[0] := UInt<3>("h05") node T_1577 = eq(T_1574[0], io.out.grant.bits.g_type) node T_1579 = or(UInt<1>("h00"), T_1577) wire T_1581 : UInt<1>[1] T_1581[0] := UInt<1>("h00") node T_1584 = eq(T_1581[0], io.out.grant.bits.g_type) node T_1586 = or(UInt<1>("h00"), T_1584) node T_1587 = mux(io.out.grant.bits.is_builtin_type, T_1579, T_1586) node T_1588 = and(UInt<1>("h01"), T_1587) node T_1590 = eq(T_1588, UInt<1>("h00")) node T_1592 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) node T_1593 = or(T_1590, T_1592) node T_1594 = and(io.out.grant.valid, T_1593) roq.io.deq.valid := T_1594 roq.io.deq.tag := io.out.grant.bits.client_xact_id io.in.grant.valid := io.out.grant.valid node T_1596 = eq(roq.io.deq.data.builtin, UInt<1>("h00")) node T_1598 = mux(roq.io.deq.data.voluntary, UInt<3>("h00"), io.out.grant.bits.g_type) node T_1599 = mux(T_1596, UInt<1>("h00"), T_1598) wire T_1627 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>} T_1627.g_type := UInt<1>("h00") T_1627.is_builtin_type := UInt<1>("h00") T_1627.manager_xact_id := UInt<1>("h00") T_1627.client_xact_id := UInt<1>("h00") T_1627.data := UInt<1>("h00") T_1627.addr_beat := UInt<1>("h00") T_1627.is_builtin_type := roq.io.deq.data.builtin T_1627.g_type := T_1599 T_1627.client_xact_id := io.out.grant.bits.client_xact_id T_1627.manager_xact_id := io.out.grant.bits.manager_xact_id T_1627.addr_beat := io.out.grant.bits.addr_beat T_1627.data := io.out.grant.bits.data io.in.grant.bits <> T_1627 io.out.grant.ready := io.in.grant.ready io.in.probe.valid := UInt<1>("h00") module TileLinkIONarrower : input clock : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.out.grant.ready := UInt<1>("h00") io.out.acquire.bits.union := UInt<1>("h00") io.out.acquire.bits.a_type := UInt<1>("h00") io.out.acquire.bits.is_builtin_type := UInt<1>("h00") io.out.acquire.bits.data := UInt<1>("h00") io.out.acquire.bits.addr_beat := UInt<1>("h00") io.out.acquire.bits.client_xact_id := UInt<1>("h00") io.out.acquire.bits.addr_block := UInt<1>("h00") io.out.acquire.valid := UInt<1>("h00") io.in.grant.bits.g_type := UInt<1>("h00") io.in.grant.bits.is_builtin_type := UInt<1>("h00") io.in.grant.bits.manager_xact_id := UInt<1>("h00") io.in.grant.bits.client_xact_id := UInt<1>("h00") io.in.grant.bits.data := UInt<1>("h00") io.in.grant.bits.addr_beat := UInt<1>("h00") io.in.grant.valid := UInt<1>("h00") io.in.acquire.ready := UInt<1>("h00") io.out <> io.in module ReorderQueue_64 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {byteOff : UInt<4>, subblock : UInt<1>}, tag : UInt<6>}}, deq : {flip valid : UInt<1>, flip tag : UInt<6>, data : {byteOff : UInt<4>, subblock : UInt<1>}}, full : UInt<1>} io.full := UInt<1>("h00") io.deq.data.subblock := UInt<1>("h00") io.deq.data.byteOff := UInt<1>("h00") io.enq.ready := UInt<1>("h00") reg roq_data : {byteOff : UInt<4>, subblock : UInt<1>}[9], clock, reset reg roq_tags : UInt<6>[9], clock, reset wire T_775 : UInt<1>[9] T_775[0] := UInt<1>("h01") T_775[1] := UInt<1>("h01") T_775[2] := UInt<1>("h01") T_775[3] := UInt<1>("h01") T_775[4] := UInt<1>("h01") T_775[5] := UInt<1>("h01") T_775[6] := UInt<1>("h01") T_775[7] := UInt<1>("h01") T_775[8] := UInt<1>("h01") reg roq_free : UInt<1>[9], clock, reset onreset roq_free := T_775 node T_808 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) node T_809 = mux(roq_free[6], UInt<3>("h06"), T_808) node T_810 = mux(roq_free[5], UInt<3>("h05"), T_809) node T_811 = mux(roq_free[4], UInt<3>("h04"), T_810) node T_812 = mux(roq_free[3], UInt<2>("h03"), T_811) node T_813 = mux(roq_free[2], UInt<2>("h02"), T_812) node T_814 = mux(roq_free[1], UInt<1>("h01"), T_813) node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_814) node T_816 = eq(roq_tags[0], io.deq.tag) node T_817 = eq(roq_tags[1], io.deq.tag) node T_818 = eq(roq_tags[2], io.deq.tag) node T_819 = eq(roq_tags[3], io.deq.tag) node T_820 = eq(roq_tags[4], io.deq.tag) node T_821 = eq(roq_tags[5], io.deq.tag) node T_822 = eq(roq_tags[6], io.deq.tag) node T_823 = eq(roq_tags[7], io.deq.tag) node T_824 = eq(roq_tags[8], io.deq.tag) node T_834 = mux(T_823, UInt<3>("h07"), UInt<4>("h08")) node T_835 = mux(T_822, UInt<3>("h06"), T_834) node T_836 = mux(T_821, UInt<3>("h05"), T_835) node T_837 = mux(T_820, UInt<3>("h04"), T_836) node T_838 = mux(T_819, UInt<2>("h03"), T_837) node T_839 = mux(T_818, UInt<2>("h02"), T_838) node T_840 = mux(T_817, UInt<1>("h01"), T_839) node roq_deq_addr = mux(T_816, UInt<1>("h00"), T_840) node T_842 = or(roq_free[0], roq_free[1]) node T_843 = or(T_842, roq_free[2]) node T_844 = or(T_843, roq_free[3]) node T_845 = or(T_844, roq_free[4]) node T_846 = or(T_845, roq_free[5]) node T_847 = or(T_846, roq_free[6]) node T_848 = or(T_847, roq_free[7]) node T_849 = or(T_848, roq_free[8]) io.enq.ready := T_849 infer accessor T_850 = roq_data[roq_deq_addr] io.deq.data <> T_850 node T_873 = and(io.enq.valid, io.enq.ready) when T_873 : infer accessor T_874 = roq_data[roq_enq_addr] T_874 <> io.enq.bits.data infer accessor T_897 = roq_tags[roq_enq_addr] T_897 := io.enq.bits.tag infer accessor T_898 = roq_free[roq_enq_addr] T_898 := UInt<1>("h00") skip when io.deq.valid : infer accessor T_900 = roq_free[roq_deq_addr] T_900 := UInt<1>("h01") skip module Arbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.client_id := UInt<1>("h00") io.out.bits.g_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.manager_xact_id := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_658 : UInt<1> T_658 := UInt<1>("h00") infer accessor T_660 = io.in[T_658] io.out.valid := T_660.valid infer accessor T_719 = io.in[T_658] io.out.bits <> T_719.bits io.chosen := T_658 infer accessor T_778 = io.in[T_658] T_778.ready := UInt<1>("h00") node T_840 = or(UInt<1>("h00"), io.in[0].valid) node T_842 = eq(T_840, UInt<1>("h00")) node T_844 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_845 = mux(UInt<1>("h00"), T_844, UInt<1>("h01")) node T_846 = and(T_845, io.out.ready) io.in[0].ready := T_846 node T_848 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_849 = mux(UInt<1>("h00"), T_848, T_842) node T_850 = and(T_849, io.out.ready) io.in[1].ready := T_850 node T_853 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_854 = mux(UInt<1>("h00"), UInt<1>("h01"), T_853) T_658 := T_854 module NASTIIOTileLinkIOConverter : input clock : Clock input reset : UInt<1> output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.nasti.r.ready := UInt<1>("h00") io.nasti.ar.bits.user := UInt<1>("h00") io.nasti.ar.bits.id := UInt<1>("h00") io.nasti.ar.bits.region := UInt<1>("h00") io.nasti.ar.bits.qos := UInt<1>("h00") io.nasti.ar.bits.prot := UInt<1>("h00") io.nasti.ar.bits.cache := UInt<1>("h00") io.nasti.ar.bits.lock := UInt<1>("h00") io.nasti.ar.bits.burst := UInt<1>("h00") io.nasti.ar.bits.size := UInt<1>("h00") io.nasti.ar.bits.len := UInt<1>("h00") io.nasti.ar.bits.addr := UInt<1>("h00") io.nasti.ar.valid := UInt<1>("h00") io.nasti.b.ready := UInt<1>("h00") io.nasti.w.bits.user := UInt<1>("h00") io.nasti.w.bits.strb := UInt<1>("h00") io.nasti.w.bits.last := UInt<1>("h00") io.nasti.w.bits.data := UInt<1>("h00") io.nasti.w.valid := UInt<1>("h00") io.nasti.aw.bits.user := UInt<1>("h00") io.nasti.aw.bits.id := UInt<1>("h00") io.nasti.aw.bits.region := UInt<1>("h00") io.nasti.aw.bits.qos := UInt<1>("h00") io.nasti.aw.bits.prot := UInt<1>("h00") io.nasti.aw.bits.cache := UInt<1>("h00") io.nasti.aw.bits.lock := UInt<1>("h00") io.nasti.aw.bits.burst := UInt<1>("h00") io.nasti.aw.bits.size := UInt<1>("h00") io.nasti.aw.bits.len := UInt<1>("h00") io.nasti.aw.bits.addr := UInt<1>("h00") io.nasti.aw.valid := UInt<1>("h00") io.tl.grant.bits.g_type := UInt<1>("h00") io.tl.grant.bits.is_builtin_type := UInt<1>("h00") io.tl.grant.bits.manager_xact_id := UInt<1>("h00") io.tl.grant.bits.client_xact_id := UInt<1>("h00") io.tl.grant.bits.data := UInt<1>("h00") io.tl.grant.bits.addr_beat := UInt<1>("h00") io.tl.grant.valid := UInt<1>("h00") io.tl.acquire.ready := UInt<1>("h00") io.tl.acquire.ready := UInt<1>("h00") io.nasti.b.ready := UInt<1>("h00") io.nasti.r.ready := UInt<1>("h00") io.nasti.ar.valid := UInt<1>("h00") io.nasti.aw.valid := UInt<1>("h00") io.nasti.w.valid := UInt<1>("h00") wire T_691 : UInt<3>[3] T_691[0] := UInt<3>("h02") T_691[1] := UInt<3>("h03") T_691[2] := UInt<3>("h04") node T_696 = eq(T_691[0], io.tl.acquire.bits.a_type) node T_697 = eq(T_691[1], io.tl.acquire.bits.a_type) node T_698 = eq(T_691[2], io.tl.acquire.bits.a_type) node T_700 = or(UInt<1>("h00"), T_696) node T_701 = or(T_700, T_697) node T_702 = or(T_701, T_698) node acq_has_data = and(io.tl.acquire.bits.is_builtin_type, T_702) node is_write = and(io.tl.acquire.valid, acq_has_data) reg active_out : UInt<1>, clock, reset onreset active_out := UInt<1>("h00") reg cmd_sent_out : UInt<1>, clock, reset onreset cmd_sent_out := UInt<1>("h00") reg tag_out : UInt<6>, clock, reset reg addr_out : UInt<32>, clock, reset reg has_data : UInt<1>, clock, reset onreset has_data := UInt<1>("h00") wire T_719 : UInt<3>[3] T_719[0] := UInt<3>("h02") T_719[1] := UInt<3>("h00") T_719[2] := UInt<3>("h04") node T_724 = eq(T_719[0], io.tl.acquire.bits.a_type) node T_725 = eq(T_719[1], io.tl.acquire.bits.a_type) node T_726 = eq(T_719[2], io.tl.acquire.bits.a_type) node T_728 = or(UInt<1>("h00"), T_724) node T_729 = or(T_728, T_725) node T_730 = or(T_729, T_726) node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_730) node T_732 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_734 = and(UInt<1>("h01"), io.tl.acquire.bits.is_builtin_type) wire T_737 : UInt<3>[1] T_737[0] := UInt<3>("h03") node T_740 = eq(T_737[0], io.tl.acquire.bits.a_type) node T_742 = or(UInt<1>("h00"), T_740) node T_743 = and(T_734, T_742) node T_744 = and(T_732, T_743) reg tl_cnt_out : UInt<2>, clock, reset onreset tl_cnt_out := UInt<2>("h00") when T_744 : node T_748 = eq(tl_cnt_out, UInt<2>("h03")) node T_750 = and(UInt<1>("h00"), T_748) node T_753 = addw(tl_cnt_out, UInt<1>("h01")) node T_754 = mux(T_750, UInt<1>("h00"), T_753) tl_cnt_out := T_754 skip node tl_wrap_out = and(T_744, T_748) reg tl_done_out : UInt<1>, clock, reset onreset tl_done_out := UInt<1>("h00") inst roq of ReorderQueue_64 roq.io.deq.tag := UInt<1>("h00") roq.io.deq.valid := UInt<1>("h00") roq.io.enq.bits.tag := UInt<1>("h00") roq.io.enq.bits.data.subblock := UInt<1>("h00") roq.io.enq.bits.data.byteOff := UInt<1>("h00") roq.io.enq.valid := UInt<1>("h00") roq.clock := clock roq.reset := reset node T_788 = and(io.nasti.r.ready, io.nasti.r.valid) node T_790 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) node T_791 = and(T_788, T_790) reg nasti_cnt_out : UInt<2>, clock, reset onreset nasti_cnt_out := UInt<2>("h00") when T_791 : node T_795 = eq(nasti_cnt_out, UInt<2>("h03")) node T_797 = and(UInt<1>("h00"), T_795) node T_800 = addw(nasti_cnt_out, UInt<1>("h01")) node T_801 = mux(T_797, UInt<1>("h00"), T_800) nasti_cnt_out := T_801 skip node nasti_wrap_out = and(T_791, T_795) node T_803 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_805 = eq(acq_has_data, UInt<1>("h00")) node T_806 = and(T_803, T_805) roq.io.enq.valid := T_806 roq.io.enq.bits.tag := io.nasti.ar.bits.id node T_807 = bits(io.tl.acquire.bits.union, 12, 9) roq.io.enq.bits.data.byteOff := T_807 roq.io.enq.bits.data.subblock := is_subblock node T_808 = and(io.nasti.r.ready, io.nasti.r.valid) node T_809 = or(nasti_wrap_out, roq.io.deq.data.subblock) node T_810 = and(T_808, T_809) roq.io.deq.valid := T_810 roq.io.deq.tag := io.nasti.r.bits.id node T_814 = mux(has_data, UInt<2>("h03"), UInt<1>("h00")) wire T_827 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>} T_827.user := UInt<1>("h00") T_827.id := UInt<1>("h00") T_827.region := UInt<1>("h00") T_827.qos := UInt<1>("h00") T_827.prot := UInt<1>("h00") T_827.cache := UInt<1>("h00") T_827.lock := UInt<1>("h00") T_827.burst := UInt<1>("h00") T_827.size := UInt<1>("h00") T_827.len := UInt<1>("h00") T_827.addr := UInt<1>("h00") T_827.id := tag_out T_827.addr := addr_out T_827.len := T_814 T_827.size := UInt<3>("h04") T_827.burst := UInt<2>("h01") T_827.lock := UInt<1>("h00") T_827.cache := UInt<1>("h00") T_827.prot := UInt<1>("h00") T_827.qos := UInt<1>("h00") T_827.region := UInt<1>("h00") T_827.user := UInt<1>("h00") io.nasti.ar.bits <> T_827 io.nasti.aw.bits <> io.nasti.ar.bits node T_858 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) node T_859 = and(io.tl.acquire.bits.is_builtin_type, T_858) node T_860 = bits(io.tl.acquire.bits.union, 12, 9) node T_861 = bits(T_860, 3, 3) node T_863 = dshl(UInt<1>("h01"), T_861) node T_864 = bit(T_863, 0) node T_865 = bit(T_863, 1) wire T_867 : UInt<1>[2] T_867[0] := T_864 T_867[1] := T_865 node T_872 = subw(UInt<8>("h00"), T_867[0]) node T_874 = subw(UInt<8>("h00"), T_867[1]) wire T_876 : UInt<8>[2] T_876[0] := T_872 T_876[1] := T_874 node T_880 = cat(T_876[1], T_876[0]) node T_882 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) node T_883 = and(io.tl.acquire.bits.is_builtin_type, T_882) node T_885 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) node T_886 = and(io.tl.acquire.bits.is_builtin_type, T_885) node T_887 = or(T_883, T_886) node T_888 = bits(io.tl.acquire.bits.union, 16, 1) node T_890 = mux(T_887, T_888, UInt<16>("h00")) node T_891 = mux(T_859, T_880, T_890) node T_892 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_893 = and(T_892, is_subblock) node T_894 = or(tl_wrap_out, T_893) wire T_900 : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>} T_900.user := UInt<1>("h00") T_900.strb := UInt<1>("h00") T_900.last := UInt<1>("h00") T_900.data := UInt<1>("h00") T_900.strb := T_891 T_900.data := io.tl.acquire.bits.data T_900.last := T_894 T_900.user := UInt<1>("h00") io.nasti.w.bits <> T_900 node T_911 = eq(active_out, UInt<1>("h00")) when T_911 : io.tl.acquire.ready := io.nasti.w.ready io.nasti.w.valid := is_write node T_912 = and(io.tl.acquire.ready, io.tl.acquire.valid) when T_912 : node T_914 = eq(is_write, UInt<1>("h00")) node T_916 = eq(io.nasti.ar.ready, UInt<1>("h00")) node T_917 = and(T_914, T_916) node T_918 = and(io.nasti.aw.ready, io.nasti.w.ready) node T_920 = eq(T_918, UInt<1>("h00")) node T_921 = and(is_write, T_920) node T_922 = or(T_917, T_921) node T_924 = and(io.nasti.w.valid, UInt<1>("h01")) node T_925 = or(T_922, T_924) active_out := T_925 io.nasti.aw.valid := is_write node T_927 = eq(is_write, UInt<1>("h00")) io.nasti.ar.valid := T_927 node T_929 = eq(is_write, UInt<1>("h00")) node T_930 = and(T_929, io.nasti.ar.ready) node T_931 = and(is_write, io.nasti.aw.ready) node T_932 = or(T_930, T_931) cmd_sent_out := T_932 node T_933 = bits(io.tl.acquire.bits.union, 12, 9) node T_934 = cat(io.tl.acquire.bits.addr_beat, T_933) node T_935 = cat(io.tl.acquire.bits.addr_block, T_934) when is_write : io.nasti.aw.bits.id := io.tl.acquire.bits.client_xact_id io.nasti.aw.bits.addr := T_935 node T_937 = eq(is_subblock, UInt<1>("h00")) node T_940 = mux(T_937, UInt<2>("h03"), UInt<1>("h00")) io.nasti.aw.bits.len := T_940 skip else : io.nasti.ar.bits.id := io.tl.acquire.bits.client_xact_id io.nasti.ar.bits.addr := T_935 node T_942 = eq(is_subblock, UInt<1>("h00")) node T_945 = mux(T_942, UInt<2>("h03"), UInt<1>("h00")) io.nasti.ar.bits.len := T_945 node T_946 = bits(io.tl.acquire.bits.union, 8, 6) node T_955 = eq(UInt<3>("h07"), T_946) node T_956 = mux(T_955, UInt<3>("h04"), UInt<3>("h07")) node T_957 = eq(UInt<3>("h03"), T_946) node T_958 = mux(T_957, UInt<2>("h03"), T_956) node T_959 = eq(UInt<3>("h02"), T_946) node T_960 = mux(T_959, UInt<2>("h02"), T_958) node T_961 = eq(UInt<3>("h05"), T_946) node T_962 = mux(T_961, UInt<1>("h01"), T_960) node T_963 = eq(UInt<3>("h01"), T_946) node T_964 = mux(T_963, UInt<1>("h01"), T_962) node T_965 = eq(UInt<3>("h04"), T_946) node T_966 = mux(T_965, UInt<1>("h00"), T_964) node T_967 = eq(UInt<3>("h00"), T_946) node T_968 = mux(T_967, UInt<1>("h00"), T_966) io.nasti.ar.bits.size := T_968 skip tag_out := io.tl.acquire.bits.client_xact_id addr_out := T_935 has_data := acq_has_data node T_969 = or(tl_wrap_out, is_subblock) tl_done_out := T_969 skip skip when active_out : node T_971 = eq(cmd_sent_out, UInt<1>("h00")) node T_973 = eq(has_data, UInt<1>("h00")) node T_974 = and(T_971, T_973) io.nasti.ar.valid := T_974 node T_976 = eq(cmd_sent_out, UInt<1>("h00")) node T_977 = and(T_976, has_data) io.nasti.aw.valid := T_977 node T_978 = and(io.nasti.ar.ready, io.nasti.ar.valid) node T_979 = or(cmd_sent_out, T_978) node T_980 = and(io.nasti.aw.ready, io.nasti.aw.valid) node T_981 = or(T_979, T_980) cmd_sent_out := T_981 node T_983 = eq(tl_done_out, UInt<1>("h00")) node T_984 = and(has_data, T_983) when T_984 : io.tl.acquire.ready := io.nasti.w.ready io.nasti.w.valid := io.tl.acquire.valid skip when tl_wrap_out : tl_done_out := UInt<1>("h01") skip node T_986 = and(cmd_sent_out, roq.io.enq.ready) node T_988 = eq(has_data, UInt<1>("h00")) node T_989 = or(T_988, tl_done_out) node T_990 = and(T_986, T_989) when T_990 : active_out := UInt<1>("h00") skip skip node T_992 = and(io.tl.grant.ready, io.tl.grant.valid) wire T_996 : UInt<3>[1] T_996[0] := UInt<3>("h05") node T_999 = eq(T_996[0], io.tl.grant.bits.g_type) node T_1001 = or(UInt<1>("h00"), T_999) wire T_1003 : UInt<1>[1] T_1003[0] := UInt<1>("h00") node T_1006 = eq(T_1003[0], io.tl.grant.bits.g_type) node T_1008 = or(UInt<1>("h00"), T_1006) node T_1009 = mux(io.tl.grant.bits.is_builtin_type, T_1001, T_1008) node T_1010 = and(UInt<1>("h01"), T_1009) node T_1011 = and(T_992, T_1010) reg tl_cnt_in : UInt<2>, clock, reset onreset tl_cnt_in := UInt<2>("h00") when T_1011 : node T_1015 = eq(tl_cnt_in, UInt<2>("h03")) node T_1017 = and(UInt<1>("h00"), T_1015) node T_1020 = addw(tl_cnt_in, UInt<1>("h01")) node T_1021 = mux(T_1017, UInt<1>("h00"), T_1020) tl_cnt_in := T_1021 skip node tl_wrap_in = and(T_1011, T_1015) inst gnt_arb of Arbiter gnt_arb.io.out.ready := UInt<1>("h00") gnt_arb.io.in[0].bits.client_id := UInt<1>("h00") gnt_arb.io.in[0].bits.g_type := UInt<1>("h00") gnt_arb.io.in[0].bits.is_builtin_type := UInt<1>("h00") gnt_arb.io.in[0].bits.manager_xact_id := UInt<1>("h00") gnt_arb.io.in[0].bits.client_xact_id := UInt<1>("h00") gnt_arb.io.in[0].bits.data := UInt<1>("h00") gnt_arb.io.in[0].bits.addr_beat := UInt<1>("h00") gnt_arb.io.in[0].valid := UInt<1>("h00") gnt_arb.io.in[1].bits.client_id := UInt<1>("h00") gnt_arb.io.in[1].bits.g_type := UInt<1>("h00") gnt_arb.io.in[1].bits.is_builtin_type := UInt<1>("h00") gnt_arb.io.in[1].bits.manager_xact_id := UInt<1>("h00") gnt_arb.io.in[1].bits.client_xact_id := UInt<1>("h00") gnt_arb.io.in[1].bits.data := UInt<1>("h00") gnt_arb.io.in[1].bits.addr_beat := UInt<1>("h00") gnt_arb.io.in[1].valid := UInt<1>("h00") gnt_arb.clock := clock gnt_arb.reset := reset io.tl.grant <> gnt_arb.io.out node T_1070 = cat(roq.io.deq.data.byteOff, UInt<3>("h00")) node T_1071 = dshl(io.nasti.r.bits.data, T_1070) node r_aligned_data = mux(roq.io.deq.data.subblock, T_1071, io.nasti.r.bits.data) gnt_arb.io.in[0].valid := io.nasti.r.valid io.nasti.r.ready := gnt_arb.io.in[0].ready node T_1076 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) wire T_1105 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>} T_1105.g_type := UInt<1>("h00") T_1105.is_builtin_type := UInt<1>("h00") T_1105.manager_xact_id := UInt<1>("h00") T_1105.client_xact_id := UInt<1>("h00") T_1105.data := UInt<1>("h00") T_1105.addr_beat := UInt<1>("h00") T_1105.is_builtin_type := UInt<1>("h01") T_1105.g_type := T_1076 T_1105.client_xact_id := io.nasti.r.bits.id T_1105.manager_xact_id := UInt<1>("h00") T_1105.addr_beat := tl_cnt_in T_1105.data := r_aligned_data gnt_arb.io.in[0].bits <> T_1105 gnt_arb.io.in[1].valid := io.nasti.b.valid io.nasti.b.ready := gnt_arb.io.in[1].ready wire T_1170 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>} T_1170.g_type := UInt<1>("h00") T_1170.is_builtin_type := UInt<1>("h00") T_1170.manager_xact_id := UInt<1>("h00") T_1170.client_xact_id := UInt<1>("h00") T_1170.data := UInt<1>("h00") T_1170.addr_beat := UInt<1>("h00") T_1170.is_builtin_type := UInt<1>("h01") T_1170.g_type := UInt<3>("h03") T_1170.client_xact_id := io.nasti.b.bits.id T_1170.manager_xact_id := UInt<1>("h00") T_1170.addr_beat := UInt<1>("h00") T_1170.data := UInt<1>("h00") gnt_arb.io.in[1].bits <> T_1170 module ClientTileLinkIOWrapper_65 : input clock : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} io.out.release.bits.voluntary := UInt<1>("h00") io.out.release.bits.r_type := UInt<1>("h00") io.out.release.bits.data := UInt<1>("h00") io.out.release.bits.addr_beat := UInt<1>("h00") io.out.release.bits.client_xact_id := UInt<1>("h00") io.out.release.bits.addr_block := UInt<1>("h00") io.out.release.valid := UInt<1>("h00") io.out.probe.ready := UInt<1>("h00") io.out.grant.ready := UInt<1>("h00") io.out.acquire.bits.union := UInt<1>("h00") io.out.acquire.bits.a_type := UInt<1>("h00") io.out.acquire.bits.is_builtin_type := UInt<1>("h00") io.out.acquire.bits.data := UInt<1>("h00") io.out.acquire.bits.addr_beat := UInt<1>("h00") io.out.acquire.bits.client_xact_id := UInt<1>("h00") io.out.acquire.bits.addr_block := UInt<1>("h00") io.out.acquire.valid := UInt<1>("h00") io.in.grant.bits.g_type := UInt<1>("h00") io.in.grant.bits.is_builtin_type := UInt<1>("h00") io.in.grant.bits.manager_xact_id := UInt<1>("h00") io.in.grant.bits.client_xact_id := UInt<1>("h00") io.in.grant.bits.data := UInt<1>("h00") io.in.grant.bits.addr_beat := UInt<1>("h00") io.in.grant.valid := UInt<1>("h00") io.in.acquire.ready := UInt<1>("h00") io.out.acquire <> io.in.acquire io.in.grant <> io.out.grant io.out.probe.ready := UInt<1>("h01") io.out.release.valid := UInt<1>("h00") module RTC : input clock : Clock input reset : UInt<1> output io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}} io.r.ready := UInt<1>("h00") io.ar.bits.user := UInt<1>("h00") io.ar.bits.id := UInt<1>("h00") io.ar.bits.region := UInt<1>("h00") io.ar.bits.qos := UInt<1>("h00") io.ar.bits.prot := UInt<1>("h00") io.ar.bits.cache := UInt<1>("h00") io.ar.bits.lock := UInt<1>("h00") io.ar.bits.burst := UInt<1>("h00") io.ar.bits.size := UInt<1>("h00") io.ar.bits.len := UInt<1>("h00") io.ar.bits.addr := UInt<1>("h00") io.ar.valid := UInt<1>("h00") io.b.ready := UInt<1>("h00") io.w.bits.user := UInt<1>("h00") io.w.bits.strb := UInt<1>("h00") io.w.bits.last := UInt<1>("h00") io.w.bits.data := UInt<1>("h00") io.w.valid := UInt<1>("h00") io.aw.bits.user := UInt<1>("h00") io.aw.bits.id := UInt<1>("h00") io.aw.bits.region := UInt<1>("h00") io.aw.bits.qos := UInt<1>("h00") io.aw.bits.prot := UInt<1>("h00") io.aw.bits.cache := UInt<1>("h00") io.aw.bits.lock := UInt<1>("h00") io.aw.bits.burst := UInt<1>("h00") io.aw.bits.size := UInt<1>("h00") io.aw.bits.len := UInt<1>("h00") io.aw.bits.addr := UInt<1>("h00") io.aw.valid := UInt<1>("h00") wire addrTable : UInt<31>[1] addrTable[0] := UInt<31>("h040003808") reg rtc : UInt<64>, clock, reset onreset rtc := UInt<64>("h00") reg T_171 : UInt<7>, clock, reset onreset T_171 := UInt<7>("h00") node rtc_tick = eq(T_171, UInt<7>("h063")) node T_175 = and(UInt<1>("h01"), rtc_tick) node T_178 = addw(T_171, UInt<1>("h01")) node T_179 = mux(T_175, UInt<1>("h00"), T_178) T_171 := T_179 reg sending_addr : UInt<1>, clock, reset onreset sending_addr := UInt<1>("h00") reg sending_data : UInt<1>, clock, reset onreset sending_data := UInt<1>("h00") wire T_186 : UInt<1>[1] T_186[0] := UInt<1>("h01") reg send_acked : UInt<1>[1], clock, reset onreset send_acked := T_186 wire coreId : UInt<1> coreId := UInt<1>("h00") when rtc_tick : node T_198 = addw(rtc, UInt<1>("h01")) rtc := T_198 wire T_201 : UInt<1>[1] T_201[0] := UInt<1>("h00") send_acked := T_201 sending_addr := UInt<1>("h01") sending_data := UInt<1>("h01") skip node T_206 = and(io.aw.ready, io.aw.valid) when T_206 : sending_addr := UInt<1>("h00") skip node T_208 = and(io.w.ready, io.w.valid) when T_208 : sending_addr := UInt<1>("h00") skip coreId := UInt<1>("h00") node T_211 = and(io.b.ready, io.b.valid) when T_211 : infer accessor T_212 = send_acked[io.b.bits.id] T_212 := UInt<1>("h01") skip io.aw.valid := sending_addr infer accessor T_214 = addrTable[coreId] wire T_229 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>} T_229.user := UInt<1>("h00") T_229.id := UInt<1>("h00") T_229.region := UInt<1>("h00") T_229.qos := UInt<1>("h00") T_229.prot := UInt<1>("h00") T_229.cache := UInt<1>("h00") T_229.lock := UInt<1>("h00") T_229.burst := UInt<1>("h00") T_229.size := UInt<1>("h00") T_229.len := UInt<1>("h00") T_229.addr := UInt<1>("h00") T_229.id := coreId T_229.addr := T_214 T_229.len := UInt<1>("h00") T_229.size := UInt<2>("h03") T_229.burst := UInt<2>("h01") T_229.lock := UInt<1>("h00") T_229.cache := UInt<4>("h00") T_229.prot := UInt<3>("h00") T_229.qos := UInt<4>("h00") T_229.region := UInt<4>("h00") T_229.user := UInt<1>("h00") io.aw.bits <> T_229 io.w.valid := sending_data node T_265 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_266 = cat(T_265, T_265) node T_267 = cat(T_266, T_266) node T_268 = cat(T_267, T_267) wire T_275 : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>} T_275.user := UInt<1>("h00") T_275.strb := UInt<1>("h00") T_275.last := UInt<1>("h00") T_275.data := UInt<1>("h00") T_275.strb := T_268 T_275.data := rtc T_275.last := UInt<1>("h01") T_275.user := UInt<1>("h00") io.w.bits <> T_275 io.b.ready := UInt<1>("h01") io.ar.valid := UInt<1>("h00") io.r.ready := UInt<1>("h00") node T_289 = eq(rtc_tick, UInt<1>("h00")) node T_290 = or(T_289, send_acked[0]) module SMIIONASTIReadIOConverter : input clock : Clock input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.r.bits.user := UInt<1>("h00") io.r.bits.id := UInt<1>("h00") io.r.bits.last := UInt<1>("h00") io.r.bits.data := UInt<1>("h00") io.r.bits.resp := UInt<1>("h00") io.r.valid := UInt<1>("h00") io.ar.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg nWords : UInt<1>, clock, reset reg nBeats : UInt<8>, clock, reset reg addr : UInt<12>, clock, reset reg id : UInt<6>, clock, reset reg byteOff : UInt<3>, clock, reset reg sendInd : UInt<1>, clock, reset onreset sendInd := UInt<1>("h00") reg recvInd : UInt<1>, clock, reset onreset recvInd := UInt<1>("h00") reg sendDone : UInt<1>, clock, reset onreset sendDone := UInt<1>("h00") wire T_142 : UInt<64>[2] T_142[0] := UInt<64>("h00") T_142[1] := UInt<64>("h00") reg buffer : UInt<64>[2], clock, reset onreset buffer := T_142 node T_152 = eq(state, UInt<1>("h00")) io.ar.ready := T_152 node T_153 = eq(state, UInt<1>("h01")) node T_155 = eq(sendDone, UInt<1>("h00")) node T_156 = and(T_153, T_155) io.smi.req.valid := T_156 io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.bits.addr := addr node T_158 = eq(state, UInt<1>("h01")) io.smi.resp.ready := T_158 node T_159 = eq(state, UInt<2>("h02")) io.r.valid := T_159 node T_160 = cat(buffer[1], buffer[0]) node T_162 = eq(nBeats, UInt<1>("h00")) wire T_170 : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>} T_170.user := UInt<1>("h00") T_170.id := UInt<1>("h00") T_170.last := UInt<1>("h00") T_170.data := UInt<1>("h00") T_170.resp := UInt<1>("h00") T_170.id := id T_170.data := T_160 T_170.last := T_162 T_170.resp := UInt<1>("h00") T_170.user := UInt<1>("h00") io.r.bits <> T_170 node T_182 = and(io.ar.ready, io.ar.valid) when T_182 : node T_184 = lt(io.ar.bits.size, UInt<2>("h03")) when T_184 : nWords := UInt<1>("h00") node T_186 = bits(io.ar.bits.addr, 2, 0) byteOff := T_186 skip else : node T_189 = subw(io.ar.bits.size, UInt<2>("h03")) node T_190 = dshl(UInt<1>("h01"), T_189) node T_192 = subw(T_190, UInt<1>("h01")) nWords := T_192 byteOff := UInt<1>("h00") skip nBeats := io.ar.bits.len node T_194 = bits(io.ar.bits.addr, 14, 3) addr := T_194 id := io.ar.bits.id state := UInt<1>("h01") skip node T_195 = and(io.smi.req.ready, io.smi.req.valid) when T_195 : node T_197 = addw(addr, UInt<1>("h01")) addr := T_197 node T_199 = addw(sendInd, UInt<1>("h01")) sendInd := T_199 node T_200 = eq(sendInd, nWords) sendDone := T_200 skip node T_201 = and(io.smi.resp.ready, io.smi.resp.valid) when T_201 : node T_203 = addw(recvInd, UInt<1>("h01")) recvInd := T_203 infer accessor T_204 = buffer[recvInd] node T_206 = cat(byteOff, UInt<3>("h00")) node T_207 = dshr(io.smi.resp.bits, T_206) T_204 := T_207 node T_208 = eq(recvInd, nWords) when T_208 : state := UInt<2>("h02") skip skip node T_209 = and(io.r.ready, io.r.valid) when T_209 : recvInd := UInt<1>("h00") sendInd := UInt<1>("h00") sendDone := UInt<1>("h00") buffer[0] := UInt<1>("h00") buffer[1] := UInt<1>("h00") node T_216 = subw(nBeats, UInt<1>("h01")) nBeats := T_216 node T_217 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) state := T_217 skip module SMIIONASTIWriteIOConverter : input clock : Clock input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.b.bits.user := UInt<1>("h00") io.b.bits.id := UInt<1>("h00") io.b.bits.resp := UInt<1>("h00") io.b.valid := UInt<1>("h00") io.w.ready := UInt<1>("h00") io.aw.ready := UInt<1>("h00") node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) reg id : UInt<6>, clock, reset reg addr : UInt<12>, clock, reset reg size : UInt<3>, clock, reset reg strb : UInt<2>, clock, reset reg data : UInt<128>, clock, reset reg last : UInt<1>, clock, reset reg state : UInt, clock, reset onreset state := UInt<1>("h00") node T_167 = eq(state, UInt<1>("h00")) io.aw.ready := T_167 node T_168 = eq(state, UInt<1>("h01")) io.w.ready := T_168 node T_169 = eq(state, UInt<2>("h02")) node T_170 = bit(strb, 0) node T_171 = and(T_169, T_170) io.smi.req.valid := T_171 io.smi.req.bits.rw := UInt<1>("h01") io.smi.req.bits.addr := addr node T_173 = bits(data, 63, 0) io.smi.req.bits.data := T_173 node T_174 = eq(state, UInt<2>("h03")) io.smi.resp.ready := T_174 node T_175 = eq(state, UInt<3>("h04")) io.b.valid := T_175 wire T_181 : {resp : UInt<2>, id : UInt<6>, user : UInt<1>} T_181.user := UInt<1>("h00") T_181.id := UInt<1>("h00") T_181.resp := UInt<1>("h00") T_181.id := id T_181.resp := UInt<1>("h00") T_181.user := UInt<1>("h00") io.b.bits <> T_181 node T_189 = bits(strb, 1, 1) node T_191 = bit(T_189, 0) node T_192 = and(io.aw.ready, io.aw.valid) when T_192 : node T_193 = bits(io.aw.bits.addr, 14, 3) addr := T_193 id := io.aw.bits.id size := io.aw.bits.size last := UInt<1>("h00") state := UInt<1>("h01") skip node T_195 = and(io.w.ready, io.w.valid) when T_195 : last := io.w.bits.last node T_198 = dshl(UInt<1>("h01"), size) node T_199 = dshl(UInt<1>("h01"), T_198) node T_201 = subw(T_199, UInt<1>("h01")) node T_202 = and(T_201, io.w.bits.strb) node T_203 = bit(T_202, 0) node T_204 = bit(T_202, 8) wire T_206 : UInt<1>[2] T_206[0] := T_203 T_206[1] := T_204 node T_210 = cat(T_206[1], T_206[0]) strb := T_210 data := io.w.bits.data state := UInt<2>("h02") skip node T_211 = eq(state, UInt<2>("h02")) when T_211 : node T_213 = eq(strb, UInt<1>("h00")) when T_213 : node T_214 = mux(last, UInt<2>("h03"), UInt<1>("h01")) state := T_214 skip else : node T_215 = bit(strb, 0) node T_217 = eq(T_215, UInt<1>("h00")) node T_218 = or(io.smi.req.ready, T_217) when T_218 : node T_219 = dshr(strb, UInt<1>("h01")) strb := T_219 node T_221 = cat(UInt<1>("h01"), UInt<6>("h00")) node T_222 = dshr(data, T_221) data := T_222 node T_223 = addw(addr, UInt<1>("h01")) addr := T_223 skip skip skip node T_224 = and(io.smi.resp.ready, io.smi.resp.valid) when T_224 : state := UInt<3>("h04") skip node T_225 = and(io.b.ready, io.b.valid) when T_225 : state := UInt<1>("h00") skip module RRArbiter_66 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.bits.rw := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_130 : UInt<1> T_130 := UInt<1>("h00") infer accessor T_132 = io.in[T_130] io.out.valid := T_132.valid infer accessor T_143 = io.in[T_130] io.out.bits <> T_143.bits io.chosen := T_130 infer accessor T_154 = io.in[T_130] T_154.ready := UInt<1>("h00") reg T_168 : UInt<1>, clock, reset onreset T_168 := UInt<1>("h00") node T_169 = gt(UInt<1>("h00"), T_168) node T_170 = and(io.in[0].valid, T_169) node T_172 = gt(UInt<1>("h01"), T_168) node T_173 = and(io.in[1].valid, T_172) node T_176 = or(UInt<1>("h00"), T_170) node T_178 = eq(T_176, UInt<1>("h00")) node T_180 = or(UInt<1>("h00"), T_170) node T_181 = or(T_180, T_173) node T_183 = eq(T_181, UInt<1>("h00")) node T_185 = or(UInt<1>("h00"), T_170) node T_186 = or(T_185, T_173) node T_187 = or(T_186, io.in[0].valid) node T_189 = eq(T_187, UInt<1>("h00")) node T_191 = gt(UInt<1>("h00"), T_168) node T_192 = and(UInt<1>("h01"), T_191) node T_193 = or(T_192, T_183) node T_195 = gt(UInt<1>("h01"), T_168) node T_196 = and(T_178, T_195) node T_197 = or(T_196, T_189) node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_200 = mux(UInt<1>("h00"), T_199, T_193) node T_201 = and(T_200, io.out.ready) io.in[0].ready := T_201 node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_204 = mux(UInt<1>("h00"), T_203, T_197) node T_205 = and(T_204, io.out.ready) io.in[1].ready := T_205 node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_210 = gt(UInt<1>("h01"), T_168) node T_211 = and(io.in[1].valid, T_210) node T_213 = mux(T_211, UInt<1>("h01"), T_208) node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) T_130 := T_214 node T_215 = and(io.out.ready, io.out.valid) when T_215 : T_168 := T_130 skip module SMIArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.out.resp.ready := UInt<1>("h00") io.out.req.bits.data := UInt<1>("h00") io.out.req.bits.addr := UInt<1>("h00") io.out.req.bits.rw := UInt<1>("h00") io.out.req.valid := UInt<1>("h00") io.in[0].resp.bits := UInt<1>("h00") io.in[0].resp.valid := UInt<1>("h00") io.in[0].req.ready := UInt<1>("h00") io.in[1].resp.bits := UInt<1>("h00") io.in[1].resp.valid := UInt<1>("h00") io.in[1].req.ready := UInt<1>("h00") reg wait_resp : UInt<1>, clock, reset onreset wait_resp := UInt<1>("h00") reg choice : UInt<1>, clock, reset inst req_arb of RRArbiter_66 req_arb.io.out.ready := UInt<1>("h00") req_arb.io.in[0].bits.data := UInt<1>("h00") req_arb.io.in[0].bits.addr := UInt<1>("h00") req_arb.io.in[0].bits.rw := UInt<1>("h00") req_arb.io.in[0].valid := UInt<1>("h00") req_arb.io.in[1].bits.data := UInt<1>("h00") req_arb.io.in[1].bits.addr := UInt<1>("h00") req_arb.io.in[1].bits.rw := UInt<1>("h00") req_arb.io.in[1].valid := UInt<1>("h00") req_arb.clock := clock req_arb.reset := reset req_arb.io.in[0] <> io.in[0].req req_arb.io.in[1] <> io.in[1].req node T_322 = eq(wait_resp, UInt<1>("h00")) node T_323 = and(io.out.req.ready, T_322) req_arb.io.out.ready := T_323 io.out.req.bits <> req_arb.io.out.bits node T_325 = eq(wait_resp, UInt<1>("h00")) node T_326 = and(req_arb.io.out.valid, T_325) io.out.req.valid := T_326 node T_327 = and(io.out.req.ready, io.out.req.valid) when T_327 : choice := req_arb.io.chosen wait_resp := UInt<1>("h01") skip node T_329 = and(io.out.resp.ready, io.out.resp.valid) when T_329 : wait_resp := UInt<1>("h00") skip io.in[0].resp.bits := io.out.resp.bits node T_332 = eq(choice, UInt<1>("h00")) node T_333 = and(io.out.resp.valid, T_332) io.in[0].resp.valid := T_333 io.in[1].resp.bits := io.out.resp.bits node T_335 = eq(choice, UInt<1>("h01")) node T_336 = and(io.out.resp.valid, T_335) io.in[1].resp.valid := T_336 infer accessor T_337 = io.in[choice] io.out.resp.ready := T_337.resp.ready module SMIIONASTIIOConverter : input clock : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.nasti.r.bits.user := UInt<1>("h00") io.nasti.r.bits.id := UInt<1>("h00") io.nasti.r.bits.last := UInt<1>("h00") io.nasti.r.bits.data := UInt<1>("h00") io.nasti.r.bits.resp := UInt<1>("h00") io.nasti.r.valid := UInt<1>("h00") io.nasti.ar.ready := UInt<1>("h00") io.nasti.b.bits.user := UInt<1>("h00") io.nasti.b.bits.id := UInt<1>("h00") io.nasti.b.bits.resp := UInt<1>("h00") io.nasti.b.valid := UInt<1>("h00") io.nasti.w.ready := UInt<1>("h00") io.nasti.aw.ready := UInt<1>("h00") inst reader of SMIIONASTIReadIOConverter reader.io.smi.resp.bits := UInt<1>("h00") reader.io.smi.resp.valid := UInt<1>("h00") reader.io.smi.req.ready := UInt<1>("h00") reader.io.r.ready := UInt<1>("h00") reader.io.ar.bits.user := UInt<1>("h00") reader.io.ar.bits.id := UInt<1>("h00") reader.io.ar.bits.region := UInt<1>("h00") reader.io.ar.bits.qos := UInt<1>("h00") reader.io.ar.bits.prot := UInt<1>("h00") reader.io.ar.bits.cache := UInt<1>("h00") reader.io.ar.bits.lock := UInt<1>("h00") reader.io.ar.bits.burst := UInt<1>("h00") reader.io.ar.bits.size := UInt<1>("h00") reader.io.ar.bits.len := UInt<1>("h00") reader.io.ar.bits.addr := UInt<1>("h00") reader.io.ar.valid := UInt<1>("h00") reader.clock := clock reader.reset := reset reader.io.ar <> io.nasti.ar io.nasti.r <> reader.io.r inst writer of SMIIONASTIWriteIOConverter writer.io.smi.resp.bits := UInt<1>("h00") writer.io.smi.resp.valid := UInt<1>("h00") writer.io.smi.req.ready := UInt<1>("h00") writer.io.b.ready := UInt<1>("h00") writer.io.w.bits.user := UInt<1>("h00") writer.io.w.bits.strb := UInt<1>("h00") writer.io.w.bits.last := UInt<1>("h00") writer.io.w.bits.data := UInt<1>("h00") writer.io.w.valid := UInt<1>("h00") writer.io.aw.bits.user := UInt<1>("h00") writer.io.aw.bits.id := UInt<1>("h00") writer.io.aw.bits.region := UInt<1>("h00") writer.io.aw.bits.qos := UInt<1>("h00") writer.io.aw.bits.prot := UInt<1>("h00") writer.io.aw.bits.cache := UInt<1>("h00") writer.io.aw.bits.lock := UInt<1>("h00") writer.io.aw.bits.burst := UInt<1>("h00") writer.io.aw.bits.size := UInt<1>("h00") writer.io.aw.bits.len := UInt<1>("h00") writer.io.aw.bits.addr := UInt<1>("h00") writer.io.aw.valid := UInt<1>("h00") writer.clock := clock writer.reset := reset writer.io.aw <> io.nasti.aw writer.io.w <> io.nasti.w io.nasti.b <> writer.io.b inst arb of SMIArbiter arb.io.out.resp.bits := UInt<1>("h00") arb.io.out.resp.valid := UInt<1>("h00") arb.io.out.req.ready := UInt<1>("h00") arb.io.in[0].resp.ready := UInt<1>("h00") arb.io.in[0].req.bits.data := UInt<1>("h00") arb.io.in[0].req.bits.addr := UInt<1>("h00") arb.io.in[0].req.bits.rw := UInt<1>("h00") arb.io.in[0].req.valid := UInt<1>("h00") arb.io.in[1].resp.ready := UInt<1>("h00") arb.io.in[1].req.bits.data := UInt<1>("h00") arb.io.in[1].req.bits.addr := UInt<1>("h00") arb.io.in[1].req.bits.rw := UInt<1>("h00") arb.io.in[1].req.valid := UInt<1>("h00") arb.clock := clock arb.reset := reset arb.io.in[0] <> reader.io.smi arb.io.in[1] <> writer.io.smi io.smi <> arb.io.out module SMIIONASTIReadIOConverter_68 : input clock : Clock input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.r.bits.user := UInt<1>("h00") io.r.bits.id := UInt<1>("h00") io.r.bits.last := UInt<1>("h00") io.r.bits.data := UInt<1>("h00") io.r.bits.resp := UInt<1>("h00") io.r.valid := UInt<1>("h00") io.ar.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg nWords : UInt<1>, clock, reset reg nBeats : UInt<8>, clock, reset reg addr : UInt<6>, clock, reset reg id : UInt<6>, clock, reset reg byteOff : UInt<3>, clock, reset reg sendInd : UInt<1>, clock, reset onreset sendInd := UInt<1>("h00") reg recvInd : UInt<1>, clock, reset onreset recvInd := UInt<1>("h00") reg sendDone : UInt<1>, clock, reset onreset sendDone := UInt<1>("h00") wire T_142 : UInt<64>[2] T_142[0] := UInt<64>("h00") T_142[1] := UInt<64>("h00") reg buffer : UInt<64>[2], clock, reset onreset buffer := T_142 node T_152 = eq(state, UInt<1>("h00")) io.ar.ready := T_152 node T_153 = eq(state, UInt<1>("h01")) node T_155 = eq(sendDone, UInt<1>("h00")) node T_156 = and(T_153, T_155) io.smi.req.valid := T_156 io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.bits.addr := addr node T_158 = eq(state, UInt<1>("h01")) io.smi.resp.ready := T_158 node T_159 = eq(state, UInt<2>("h02")) io.r.valid := T_159 node T_160 = cat(buffer[1], buffer[0]) node T_162 = eq(nBeats, UInt<1>("h00")) wire T_170 : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>} T_170.user := UInt<1>("h00") T_170.id := UInt<1>("h00") T_170.last := UInt<1>("h00") T_170.data := UInt<1>("h00") T_170.resp := UInt<1>("h00") T_170.id := id T_170.data := T_160 T_170.last := T_162 T_170.resp := UInt<1>("h00") T_170.user := UInt<1>("h00") io.r.bits <> T_170 node T_182 = and(io.ar.ready, io.ar.valid) when T_182 : node T_184 = lt(io.ar.bits.size, UInt<2>("h03")) when T_184 : nWords := UInt<1>("h00") node T_186 = bits(io.ar.bits.addr, 2, 0) byteOff := T_186 skip else : node T_189 = subw(io.ar.bits.size, UInt<2>("h03")) node T_190 = dshl(UInt<1>("h01"), T_189) node T_192 = subw(T_190, UInt<1>("h01")) nWords := T_192 byteOff := UInt<1>("h00") skip nBeats := io.ar.bits.len node T_194 = bits(io.ar.bits.addr, 8, 3) addr := T_194 id := io.ar.bits.id state := UInt<1>("h01") skip node T_195 = and(io.smi.req.ready, io.smi.req.valid) when T_195 : node T_197 = addw(addr, UInt<1>("h01")) addr := T_197 node T_199 = addw(sendInd, UInt<1>("h01")) sendInd := T_199 node T_200 = eq(sendInd, nWords) sendDone := T_200 skip node T_201 = and(io.smi.resp.ready, io.smi.resp.valid) when T_201 : node T_203 = addw(recvInd, UInt<1>("h01")) recvInd := T_203 infer accessor T_204 = buffer[recvInd] node T_206 = cat(byteOff, UInt<3>("h00")) node T_207 = dshr(io.smi.resp.bits, T_206) T_204 := T_207 node T_208 = eq(recvInd, nWords) when T_208 : state := UInt<2>("h02") skip skip node T_209 = and(io.r.ready, io.r.valid) when T_209 : recvInd := UInt<1>("h00") sendInd := UInt<1>("h00") sendDone := UInt<1>("h00") buffer[0] := UInt<1>("h00") buffer[1] := UInt<1>("h00") node T_216 = subw(nBeats, UInt<1>("h01")) nBeats := T_216 node T_217 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) state := T_217 skip module SMIIONASTIWriteIOConverter_69 : input clock : Clock input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.b.bits.user := UInt<1>("h00") io.b.bits.id := UInt<1>("h00") io.b.bits.resp := UInt<1>("h00") io.b.valid := UInt<1>("h00") io.w.ready := UInt<1>("h00") io.aw.ready := UInt<1>("h00") node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) reg id : UInt<6>, clock, reset reg addr : UInt<6>, clock, reset reg size : UInt<3>, clock, reset reg strb : UInt<2>, clock, reset reg data : UInt<128>, clock, reset reg last : UInt<1>, clock, reset reg state : UInt, clock, reset onreset state := UInt<1>("h00") node T_167 = eq(state, UInt<1>("h00")) io.aw.ready := T_167 node T_168 = eq(state, UInt<1>("h01")) io.w.ready := T_168 node T_169 = eq(state, UInt<2>("h02")) node T_170 = bit(strb, 0) node T_171 = and(T_169, T_170) io.smi.req.valid := T_171 io.smi.req.bits.rw := UInt<1>("h01") io.smi.req.bits.addr := addr node T_173 = bits(data, 63, 0) io.smi.req.bits.data := T_173 node T_174 = eq(state, UInt<2>("h03")) io.smi.resp.ready := T_174 node T_175 = eq(state, UInt<3>("h04")) io.b.valid := T_175 wire T_181 : {resp : UInt<2>, id : UInt<6>, user : UInt<1>} T_181.user := UInt<1>("h00") T_181.id := UInt<1>("h00") T_181.resp := UInt<1>("h00") T_181.id := id T_181.resp := UInt<1>("h00") T_181.user := UInt<1>("h00") io.b.bits <> T_181 node T_189 = bits(strb, 1, 1) node T_191 = bit(T_189, 0) node T_192 = and(io.aw.ready, io.aw.valid) when T_192 : node T_193 = bits(io.aw.bits.addr, 8, 3) addr := T_193 id := io.aw.bits.id size := io.aw.bits.size last := UInt<1>("h00") state := UInt<1>("h01") skip node T_195 = and(io.w.ready, io.w.valid) when T_195 : last := io.w.bits.last node T_198 = dshl(UInt<1>("h01"), size) node T_199 = dshl(UInt<1>("h01"), T_198) node T_201 = subw(T_199, UInt<1>("h01")) node T_202 = and(T_201, io.w.bits.strb) node T_203 = bit(T_202, 0) node T_204 = bit(T_202, 8) wire T_206 : UInt<1>[2] T_206[0] := T_203 T_206[1] := T_204 node T_210 = cat(T_206[1], T_206[0]) strb := T_210 data := io.w.bits.data state := UInt<2>("h02") skip node T_211 = eq(state, UInt<2>("h02")) when T_211 : node T_213 = eq(strb, UInt<1>("h00")) when T_213 : node T_214 = mux(last, UInt<2>("h03"), UInt<1>("h01")) state := T_214 skip else : node T_215 = bit(strb, 0) node T_217 = eq(T_215, UInt<1>("h00")) node T_218 = or(io.smi.req.ready, T_217) when T_218 : node T_219 = dshr(strb, UInt<1>("h01")) strb := T_219 node T_221 = cat(UInt<1>("h01"), UInt<6>("h00")) node T_222 = dshr(data, T_221) data := T_222 node T_223 = addw(addr, UInt<1>("h01")) addr := T_223 skip skip skip node T_224 = and(io.smi.resp.ready, io.smi.resp.valid) when T_224 : state := UInt<3>("h04") skip node T_225 = and(io.b.ready, io.b.valid) when T_225 : state := UInt<1>("h00") skip module RRArbiter_71 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.bits.rw := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_130 : UInt<1> T_130 := UInt<1>("h00") infer accessor T_132 = io.in[T_130] io.out.valid := T_132.valid infer accessor T_143 = io.in[T_130] io.out.bits <> T_143.bits io.chosen := T_130 infer accessor T_154 = io.in[T_130] T_154.ready := UInt<1>("h00") reg T_168 : UInt<1>, clock, reset onreset T_168 := UInt<1>("h00") node T_169 = gt(UInt<1>("h00"), T_168) node T_170 = and(io.in[0].valid, T_169) node T_172 = gt(UInt<1>("h01"), T_168) node T_173 = and(io.in[1].valid, T_172) node T_176 = or(UInt<1>("h00"), T_170) node T_178 = eq(T_176, UInt<1>("h00")) node T_180 = or(UInt<1>("h00"), T_170) node T_181 = or(T_180, T_173) node T_183 = eq(T_181, UInt<1>("h00")) node T_185 = or(UInt<1>("h00"), T_170) node T_186 = or(T_185, T_173) node T_187 = or(T_186, io.in[0].valid) node T_189 = eq(T_187, UInt<1>("h00")) node T_191 = gt(UInt<1>("h00"), T_168) node T_192 = and(UInt<1>("h01"), T_191) node T_193 = or(T_192, T_183) node T_195 = gt(UInt<1>("h01"), T_168) node T_196 = and(T_178, T_195) node T_197 = or(T_196, T_189) node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_200 = mux(UInt<1>("h00"), T_199, T_193) node T_201 = and(T_200, io.out.ready) io.in[0].ready := T_201 node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_204 = mux(UInt<1>("h00"), T_203, T_197) node T_205 = and(T_204, io.out.ready) io.in[1].ready := T_205 node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_210 = gt(UInt<1>("h01"), T_168) node T_211 = and(io.in[1].valid, T_210) node T_213 = mux(T_211, UInt<1>("h01"), T_208) node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) T_130 := T_214 node T_215 = and(io.out.ready, io.out.valid) when T_215 : T_168 := T_130 skip module SMIArbiter_70 : input clock : Clock input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.out.resp.ready := UInt<1>("h00") io.out.req.bits.data := UInt<1>("h00") io.out.req.bits.addr := UInt<1>("h00") io.out.req.bits.rw := UInt<1>("h00") io.out.req.valid := UInt<1>("h00") io.in[0].resp.bits := UInt<1>("h00") io.in[0].resp.valid := UInt<1>("h00") io.in[0].req.ready := UInt<1>("h00") io.in[1].resp.bits := UInt<1>("h00") io.in[1].resp.valid := UInt<1>("h00") io.in[1].req.ready := UInt<1>("h00") reg wait_resp : UInt<1>, clock, reset onreset wait_resp := UInt<1>("h00") reg choice : UInt<1>, clock, reset inst req_arb of RRArbiter_71 req_arb.io.out.ready := UInt<1>("h00") req_arb.io.in[0].bits.data := UInt<1>("h00") req_arb.io.in[0].bits.addr := UInt<1>("h00") req_arb.io.in[0].bits.rw := UInt<1>("h00") req_arb.io.in[0].valid := UInt<1>("h00") req_arb.io.in[1].bits.data := UInt<1>("h00") req_arb.io.in[1].bits.addr := UInt<1>("h00") req_arb.io.in[1].bits.rw := UInt<1>("h00") req_arb.io.in[1].valid := UInt<1>("h00") req_arb.clock := clock req_arb.reset := reset req_arb.io.in[0] <> io.in[0].req req_arb.io.in[1] <> io.in[1].req node T_322 = eq(wait_resp, UInt<1>("h00")) node T_323 = and(io.out.req.ready, T_322) req_arb.io.out.ready := T_323 io.out.req.bits <> req_arb.io.out.bits node T_325 = eq(wait_resp, UInt<1>("h00")) node T_326 = and(req_arb.io.out.valid, T_325) io.out.req.valid := T_326 node T_327 = and(io.out.req.ready, io.out.req.valid) when T_327 : choice := req_arb.io.chosen wait_resp := UInt<1>("h01") skip node T_329 = and(io.out.resp.ready, io.out.resp.valid) when T_329 : wait_resp := UInt<1>("h00") skip io.in[0].resp.bits := io.out.resp.bits node T_332 = eq(choice, UInt<1>("h00")) node T_333 = and(io.out.resp.valid, T_332) io.in[0].resp.valid := T_333 io.in[1].resp.bits := io.out.resp.bits node T_335 = eq(choice, UInt<1>("h01")) node T_336 = and(io.out.resp.valid, T_335) io.in[1].resp.valid := T_336 infer accessor T_337 = io.in[choice] io.out.resp.ready := T_337.resp.ready module SMIIONASTIIOConverter_67 : input clock : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready := UInt<1>("h00") io.smi.req.bits.data := UInt<1>("h00") io.smi.req.bits.addr := UInt<1>("h00") io.smi.req.bits.rw := UInt<1>("h00") io.smi.req.valid := UInt<1>("h00") io.nasti.r.bits.user := UInt<1>("h00") io.nasti.r.bits.id := UInt<1>("h00") io.nasti.r.bits.last := UInt<1>("h00") io.nasti.r.bits.data := UInt<1>("h00") io.nasti.r.bits.resp := UInt<1>("h00") io.nasti.r.valid := UInt<1>("h00") io.nasti.ar.ready := UInt<1>("h00") io.nasti.b.bits.user := UInt<1>("h00") io.nasti.b.bits.id := UInt<1>("h00") io.nasti.b.bits.resp := UInt<1>("h00") io.nasti.b.valid := UInt<1>("h00") io.nasti.w.ready := UInt<1>("h00") io.nasti.aw.ready := UInt<1>("h00") inst reader of SMIIONASTIReadIOConverter_68 reader.io.smi.resp.bits := UInt<1>("h00") reader.io.smi.resp.valid := UInt<1>("h00") reader.io.smi.req.ready := UInt<1>("h00") reader.io.r.ready := UInt<1>("h00") reader.io.ar.bits.user := UInt<1>("h00") reader.io.ar.bits.id := UInt<1>("h00") reader.io.ar.bits.region := UInt<1>("h00") reader.io.ar.bits.qos := UInt<1>("h00") reader.io.ar.bits.prot := UInt<1>("h00") reader.io.ar.bits.cache := UInt<1>("h00") reader.io.ar.bits.lock := UInt<1>("h00") reader.io.ar.bits.burst := UInt<1>("h00") reader.io.ar.bits.size := UInt<1>("h00") reader.io.ar.bits.len := UInt<1>("h00") reader.io.ar.bits.addr := UInt<1>("h00") reader.io.ar.valid := UInt<1>("h00") reader.clock := clock reader.reset := reset reader.io.ar <> io.nasti.ar io.nasti.r <> reader.io.r inst writer of SMIIONASTIWriteIOConverter_69 writer.io.smi.resp.bits := UInt<1>("h00") writer.io.smi.resp.valid := UInt<1>("h00") writer.io.smi.req.ready := UInt<1>("h00") writer.io.b.ready := UInt<1>("h00") writer.io.w.bits.user := UInt<1>("h00") writer.io.w.bits.strb := UInt<1>("h00") writer.io.w.bits.last := UInt<1>("h00") writer.io.w.bits.data := UInt<1>("h00") writer.io.w.valid := UInt<1>("h00") writer.io.aw.bits.user := UInt<1>("h00") writer.io.aw.bits.id := UInt<1>("h00") writer.io.aw.bits.region := UInt<1>("h00") writer.io.aw.bits.qos := UInt<1>("h00") writer.io.aw.bits.prot := UInt<1>("h00") writer.io.aw.bits.cache := UInt<1>("h00") writer.io.aw.bits.lock := UInt<1>("h00") writer.io.aw.bits.burst := UInt<1>("h00") writer.io.aw.bits.size := UInt<1>("h00") writer.io.aw.bits.len := UInt<1>("h00") writer.io.aw.bits.addr := UInt<1>("h00") writer.io.aw.valid := UInt<1>("h00") writer.clock := clock writer.reset := reset writer.io.aw <> io.nasti.aw writer.io.w <> io.nasti.w io.nasti.b <> writer.io.b inst arb of SMIArbiter_70 arb.io.out.resp.bits := UInt<1>("h00") arb.io.out.resp.valid := UInt<1>("h00") arb.io.out.req.ready := UInt<1>("h00") arb.io.in[0].resp.ready := UInt<1>("h00") arb.io.in[0].req.bits.data := UInt<1>("h00") arb.io.in[0].req.bits.addr := UInt<1>("h00") arb.io.in[0].req.bits.rw := UInt<1>("h00") arb.io.in[0].req.valid := UInt<1>("h00") arb.io.in[1].resp.ready := UInt<1>("h00") arb.io.in[1].req.bits.data := UInt<1>("h00") arb.io.in[1].req.bits.addr := UInt<1>("h00") arb.io.in[1].req.bits.rw := UInt<1>("h00") arb.io.in[1].req.valid := UInt<1>("h00") arb.clock := clock arb.reset := reset arb.io.in[0] <> reader.io.smi arb.io.in[1] <> writer.io.smi io.smi <> arb.io.out module NASTIArbiter_72 : input clock : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[1], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.slave.r.ready := UInt<1>("h00") io.slave.ar.bits.user := UInt<1>("h00") io.slave.ar.bits.id := UInt<1>("h00") io.slave.ar.bits.region := UInt<1>("h00") io.slave.ar.bits.qos := UInt<1>("h00") io.slave.ar.bits.prot := UInt<1>("h00") io.slave.ar.bits.cache := UInt<1>("h00") io.slave.ar.bits.lock := UInt<1>("h00") io.slave.ar.bits.burst := UInt<1>("h00") io.slave.ar.bits.size := UInt<1>("h00") io.slave.ar.bits.len := UInt<1>("h00") io.slave.ar.bits.addr := UInt<1>("h00") io.slave.ar.valid := UInt<1>("h00") io.slave.b.ready := UInt<1>("h00") io.slave.w.bits.user := UInt<1>("h00") io.slave.w.bits.strb := UInt<1>("h00") io.slave.w.bits.last := UInt<1>("h00") io.slave.w.bits.data := UInt<1>("h00") io.slave.w.valid := UInt<1>("h00") io.slave.aw.bits.user := UInt<1>("h00") io.slave.aw.bits.id := UInt<1>("h00") io.slave.aw.bits.region := UInt<1>("h00") io.slave.aw.bits.qos := UInt<1>("h00") io.slave.aw.bits.prot := UInt<1>("h00") io.slave.aw.bits.cache := UInt<1>("h00") io.slave.aw.bits.lock := UInt<1>("h00") io.slave.aw.bits.burst := UInt<1>("h00") io.slave.aw.bits.size := UInt<1>("h00") io.slave.aw.bits.len := UInt<1>("h00") io.slave.aw.bits.addr := UInt<1>("h00") io.slave.aw.valid := UInt<1>("h00") io.master[0].r.bits.user := UInt<1>("h00") io.master[0].r.bits.id := UInt<1>("h00") io.master[0].r.bits.last := UInt<1>("h00") io.master[0].r.bits.data := UInt<1>("h00") io.master[0].r.bits.resp := UInt<1>("h00") io.master[0].r.valid := UInt<1>("h00") io.master[0].ar.ready := UInt<1>("h00") io.master[0].b.bits.user := UInt<1>("h00") io.master[0].b.bits.id := UInt<1>("h00") io.master[0].b.bits.resp := UInt<1>("h00") io.master[0].b.valid := UInt<1>("h00") io.master[0].w.ready := UInt<1>("h00") io.master[0].aw.ready := UInt<1>("h00") io.slave <> io.master[0] module MemIONASTIIOConverter : input clock : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<6>}}}} io.mem.resp.ready := UInt<1>("h00") io.mem.req_data.bits.data := UInt<1>("h00") io.mem.req_data.valid := UInt<1>("h00") io.mem.req_cmd.bits.rw := UInt<1>("h00") io.mem.req_cmd.bits.tag := UInt<1>("h00") io.mem.req_cmd.bits.addr := UInt<1>("h00") io.mem.req_cmd.valid := UInt<1>("h00") io.nasti.r.bits.user := UInt<1>("h00") io.nasti.r.bits.id := UInt<1>("h00") io.nasti.r.bits.last := UInt<1>("h00") io.nasti.r.bits.data := UInt<1>("h00") io.nasti.r.bits.resp := UInt<1>("h00") io.nasti.r.valid := UInt<1>("h00") io.nasti.ar.ready := UInt<1>("h00") io.nasti.b.bits.user := UInt<1>("h00") io.nasti.b.bits.id := UInt<1>("h00") io.nasti.b.bits.resp := UInt<1>("h00") io.nasti.b.valid := UInt<1>("h00") io.nasti.w.ready := UInt<1>("h00") io.nasti.aw.ready := UInt<1>("h00") node T_368 = and(io.mem.resp.ready, io.mem.resp.valid) reg mif_cnt_out : UInt<2>, clock, reset onreset mif_cnt_out := UInt<2>("h00") when T_368 : node T_372 = eq(mif_cnt_out, UInt<2>("h03")) node T_374 = and(UInt<1>("h00"), T_372) node T_377 = addw(mif_cnt_out, UInt<1>("h01")) node T_378 = mux(T_374, UInt<1>("h00"), T_377) mif_cnt_out := T_378 skip node mif_wrap_out = and(T_368, T_372) node T_381 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_383 = eq(io.nasti.aw.bits.size, UInt<3>("h04")) node T_384 = or(T_381, T_383) node T_386 = eq(io.nasti.ar.valid, UInt<1>("h00")) node T_388 = eq(io.nasti.ar.bits.size, UInt<3>("h04")) node T_389 = or(T_386, T_388) node T_391 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_393 = eq(io.nasti.aw.bits.len, UInt<2>("h03")) node T_394 = or(T_391, T_393) node T_396 = eq(io.nasti.ar.valid, UInt<1>("h00")) node T_398 = eq(io.nasti.ar.bits.len, UInt<2>("h03")) node T_399 = or(T_396, T_398) reg b_ok : UInt<1>, clock, reset onreset b_ok := UInt<1>("h01") node T_402 = and(io.nasti.aw.ready, io.nasti.aw.valid) when T_402 : b_ok := UInt<1>("h00") skip node T_404 = and(io.nasti.w.ready, io.nasti.w.valid) node T_405 = and(T_404, io.nasti.w.bits.last) when T_405 : b_ok := UInt<1>("h01") skip inst id_q of Queue_37 id_q.io.deq.ready := UInt<1>("h00") id_q.io.enq.bits := UInt<1>("h00") id_q.io.enq.valid := UInt<1>("h00") id_q.clock := clock id_q.reset := reset id_q.io.enq.valid := io.nasti.aw.valid id_q.io.enq.bits := io.nasti.aw.bits.id node T_412 = and(io.nasti.b.ready, b_ok) id_q.io.deq.ready := T_412 node T_413 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) node T_415 = dshr(T_413, UInt<3>("h06")) io.mem.req_cmd.bits.addr := T_415 node T_416 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) io.mem.req_cmd.bits.tag := T_416 io.mem.req_cmd.bits.rw := io.nasti.aw.valid node T_417 = and(io.nasti.aw.valid, id_q.io.enq.ready) node T_418 = or(T_417, io.nasti.ar.valid) io.mem.req_cmd.valid := T_418 node T_420 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_421 = and(io.mem.req_cmd.ready, T_420) io.nasti.ar.ready := T_421 node T_422 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) io.nasti.aw.ready := T_422 node T_423 = and(id_q.io.deq.valid, b_ok) io.nasti.b.valid := T_423 io.nasti.b.bits.id := id_q.io.deq.bits io.nasti.b.bits.resp := UInt<1>("h00") io.nasti.w.ready := io.mem.req_data.ready io.mem.req_data.valid := io.nasti.w.valid io.mem.req_data.bits.data := io.nasti.w.bits.data node T_426 = eq(io.nasti.w.valid, UInt<1>("h00")) node T_427 = not(io.nasti.w.bits.strb) node T_429 = eq(T_427, UInt<1>("h00")) node T_430 = or(T_426, T_429) io.nasti.r.valid := io.mem.resp.valid io.nasti.r.bits.data := io.mem.resp.bits.data io.nasti.r.bits.last := mif_wrap_out io.nasti.r.bits.id := io.mem.resp.bits.tag io.nasti.r.bits.resp := UInt<1>("h00") io.mem.resp.ready := io.nasti.r.ready module MemSerdes : input clock : Clock input reset : UInt<1> output io : {flip wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<6>}}}, narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}} io.narrow.req.bits := UInt<1>("h00") io.narrow.req.valid := UInt<1>("h00") io.wide.resp.bits.tag := UInt<1>("h00") io.wide.resp.bits.data := UInt<1>("h00") io.wide.resp.valid := UInt<1>("h00") io.wide.req_data.ready := UInt<1>("h00") io.wide.req_cmd.ready := UInt<1>("h00") node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) node T_113 = cat(io.wide.req_cmd.bits.addr, T_112) reg out_buf : UInt, clock, reset reg in_buf : UInt, clock, reset reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg send_cnt : UInt<3>, clock, reset onreset send_cnt := UInt<3>("h00") reg data_send_cnt : UInt<2>, clock, reset onreset data_send_cnt := UInt<2>("h00") node T_130 = eq(send_cnt, UInt<2>("h02")) node adone = and(io.narrow.req.ready, T_130) node T_133 = eq(send_cnt, UInt<3>("h07")) node ddone = and(io.narrow.req.ready, T_133) node T_135 = and(io.narrow.req.valid, io.narrow.req.ready) when T_135 : node T_137 = addw(send_cnt, UInt<1>("h01")) send_cnt := T_137 node T_139 = dshr(out_buf, UInt<5>("h010")) out_buf := T_139 skip node T_140 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) when T_140 : node T_141 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) node T_142 = cat(io.wide.req_cmd.bits.addr, T_141) out_buf := T_142 skip node T_143 = and(io.wide.req_data.valid, io.wide.req_data.ready) when T_143 : out_buf := io.wide.req_data.bits.data skip node T_144 = eq(state, UInt<1>("h00")) io.wide.req_cmd.ready := T_144 node T_145 = eq(state, UInt<2>("h03")) io.wide.req_data.ready := T_145 node T_146 = eq(state, UInt<1>("h01")) node T_147 = eq(state, UInt<2>("h02")) node T_148 = or(T_146, T_147) node T_149 = eq(state, UInt<3>("h04")) node T_150 = or(T_148, T_149) io.narrow.req.valid := T_150 io.narrow.req.bits := out_buf node T_151 = eq(state, UInt<1>("h00")) node T_152 = and(T_151, io.wide.req_cmd.valid) when T_152 : node T_153 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) state := T_153 skip node T_154 = eq(state, UInt<1>("h01")) node T_155 = and(T_154, adone) when T_155 : state := UInt<1>("h00") send_cnt := UInt<1>("h00") skip node T_157 = eq(state, UInt<2>("h02")) node T_158 = and(T_157, adone) when T_158 : state := UInt<2>("h03") send_cnt := UInt<1>("h00") skip node T_160 = eq(state, UInt<2>("h03")) node T_161 = and(T_160, io.wide.req_data.valid) when T_161 : state := UInt<3>("h04") skip node T_162 = eq(state, UInt<3>("h04")) node T_163 = and(T_162, ddone) when T_163 : node T_165 = addw(data_send_cnt, UInt<1>("h01")) data_send_cnt := T_165 node T_167 = eq(data_send_cnt, UInt<2>("h03")) node T_168 = mux(T_167, UInt<1>("h00"), UInt<2>("h03")) state := T_168 send_cnt := UInt<1>("h00") skip reg recv_cnt : UInt<4>, clock, reset onreset recv_cnt := UInt<4>("h00") reg data_recv_cnt : UInt<2>, clock, reset onreset data_recv_cnt := UInt<2>("h00") reg resp_val : UInt<1>, clock, reset onreset resp_val := UInt<1>("h00") resp_val := UInt<1>("h00") when io.narrow.resp.valid : node T_178 = addw(recv_cnt, UInt<1>("h01")) recv_cnt := T_178 node T_180 = eq(recv_cnt, UInt<4>("h08")) when T_180 : recv_cnt := UInt<1>("h00") node T_183 = addw(data_recv_cnt, UInt<1>("h01")) data_recv_cnt := T_183 resp_val := UInt<1>("h01") skip node T_185 = bits(in_buf, 143, 16) node T_186 = cat(io.narrow.resp.bits, T_185) in_buf := T_186 skip io.wide.resp.valid := resp_val wire T_190 : {data : UInt<128>, tag : UInt<6>} T_190.tag := UInt<1>("h00") T_190.data := UInt<1>("h00") node T_195 = bits(in_buf, 5, 0) T_190.tag := T_195 node T_196 = bits(in_buf, 133, 6) T_190.data := T_196 io.wide.resp.bits <> T_190 module OuterMemorySystem : input clock : Clock input reset : UInt<1> output io : {flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1], flip htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, flip incoherent : UInt<1>[1], mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[1], mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.mmio.r.ready := UInt<1>("h00") io.mmio.ar.bits.user := UInt<1>("h00") io.mmio.ar.bits.id := UInt<1>("h00") io.mmio.ar.bits.region := UInt<1>("h00") io.mmio.ar.bits.qos := UInt<1>("h00") io.mmio.ar.bits.prot := UInt<1>("h00") io.mmio.ar.bits.cache := UInt<1>("h00") io.mmio.ar.bits.lock := UInt<1>("h00") io.mmio.ar.bits.burst := UInt<1>("h00") io.mmio.ar.bits.size := UInt<1>("h00") io.mmio.ar.bits.len := UInt<1>("h00") io.mmio.ar.bits.addr := UInt<1>("h00") io.mmio.ar.valid := UInt<1>("h00") io.mmio.b.ready := UInt<1>("h00") io.mmio.w.bits.user := UInt<1>("h00") io.mmio.w.bits.strb := UInt<1>("h00") io.mmio.w.bits.last := UInt<1>("h00") io.mmio.w.bits.data := UInt<1>("h00") io.mmio.w.valid := UInt<1>("h00") io.mmio.aw.bits.user := UInt<1>("h00") io.mmio.aw.bits.id := UInt<1>("h00") io.mmio.aw.bits.region := UInt<1>("h00") io.mmio.aw.bits.qos := UInt<1>("h00") io.mmio.aw.bits.prot := UInt<1>("h00") io.mmio.aw.bits.cache := UInt<1>("h00") io.mmio.aw.bits.lock := UInt<1>("h00") io.mmio.aw.bits.burst := UInt<1>("h00") io.mmio.aw.bits.size := UInt<1>("h00") io.mmio.aw.bits.len := UInt<1>("h00") io.mmio.aw.bits.addr := UInt<1>("h00") io.mmio.aw.valid := UInt<1>("h00") io.scr.resp.ready := UInt<1>("h00") io.scr.req.bits.data := UInt<1>("h00") io.scr.req.bits.addr := UInt<1>("h00") io.scr.req.bits.rw := UInt<1>("h00") io.scr.req.valid := UInt<1>("h00") io.pcr[0].resp.ready := UInt<1>("h00") io.pcr[0].req.bits.data := UInt<1>("h00") io.pcr[0].req.bits.addr := UInt<1>("h00") io.pcr[0].req.bits.rw := UInt<1>("h00") io.pcr[0].req.valid := UInt<1>("h00") io.mem_backup.req.bits := UInt<1>("h00") io.mem_backup.req.valid := UInt<1>("h00") io.mem[0].r.ready := UInt<1>("h00") io.mem[0].ar.bits.user := UInt<1>("h00") io.mem[0].ar.bits.id := UInt<1>("h00") io.mem[0].ar.bits.region := UInt<1>("h00") io.mem[0].ar.bits.qos := UInt<1>("h00") io.mem[0].ar.bits.prot := UInt<1>("h00") io.mem[0].ar.bits.cache := UInt<1>("h00") io.mem[0].ar.bits.lock := UInt<1>("h00") io.mem[0].ar.bits.burst := UInt<1>("h00") io.mem[0].ar.bits.size := UInt<1>("h00") io.mem[0].ar.bits.len := UInt<1>("h00") io.mem[0].ar.bits.addr := UInt<1>("h00") io.mem[0].ar.valid := UInt<1>("h00") io.mem[0].b.ready := UInt<1>("h00") io.mem[0].w.bits.user := UInt<1>("h00") io.mem[0].w.bits.strb := UInt<1>("h00") io.mem[0].w.bits.last := UInt<1>("h00") io.mem[0].w.bits.data := UInt<1>("h00") io.mem[0].w.valid := UInt<1>("h00") io.mem[0].aw.bits.user := UInt<1>("h00") io.mem[0].aw.bits.id := UInt<1>("h00") io.mem[0].aw.bits.region := UInt<1>("h00") io.mem[0].aw.bits.qos := UInt<1>("h00") io.mem[0].aw.bits.prot := UInt<1>("h00") io.mem[0].aw.bits.cache := UInt<1>("h00") io.mem[0].aw.bits.lock := UInt<1>("h00") io.mem[0].aw.bits.burst := UInt<1>("h00") io.mem[0].aw.bits.size := UInt<1>("h00") io.mem[0].aw.bits.len := UInt<1>("h00") io.mem[0].aw.bits.addr := UInt<1>("h00") io.mem[0].aw.valid := UInt<1>("h00") io.htif_uncached.grant.bits.g_type := UInt<1>("h00") io.htif_uncached.grant.bits.is_builtin_type := UInt<1>("h00") io.htif_uncached.grant.bits.manager_xact_id := UInt<1>("h00") io.htif_uncached.grant.bits.client_xact_id := UInt<1>("h00") io.htif_uncached.grant.bits.data := UInt<1>("h00") io.htif_uncached.grant.bits.addr_beat := UInt<1>("h00") io.htif_uncached.grant.valid := UInt<1>("h00") io.htif_uncached.acquire.ready := UInt<1>("h00") io.tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") io.tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") io.tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") io.tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") io.tiles_uncached[0].grant.bits.data := UInt<1>("h00") io.tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") io.tiles_uncached[0].grant.valid := UInt<1>("h00") io.tiles_uncached[0].acquire.ready := UInt<1>("h00") io.tiles_cached[0].release.ready := UInt<1>("h00") io.tiles_cached[0].probe.bits.p_type := UInt<1>("h00") io.tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") io.tiles_cached[0].probe.valid := UInt<1>("h00") io.tiles_cached[0].grant.bits.g_type := UInt<1>("h00") io.tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") io.tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") io.tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") io.tiles_cached[0].grant.bits.data := UInt<1>("h00") io.tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") io.tiles_cached[0].grant.valid := UInt<1>("h00") io.tiles_cached[0].acquire.ready := UInt<1>("h00") inst T_7767 of ClientTileLinkIOWrapper T_7767.io.out.release.ready := UInt<1>("h00") T_7767.io.out.probe.bits.p_type := UInt<1>("h00") T_7767.io.out.probe.bits.addr_block := UInt<1>("h00") T_7767.io.out.probe.valid := UInt<1>("h00") T_7767.io.out.grant.bits.g_type := UInt<1>("h00") T_7767.io.out.grant.bits.is_builtin_type := UInt<1>("h00") T_7767.io.out.grant.bits.manager_xact_id := UInt<1>("h00") T_7767.io.out.grant.bits.client_xact_id := UInt<1>("h00") T_7767.io.out.grant.bits.data := UInt<1>("h00") T_7767.io.out.grant.bits.addr_beat := UInt<1>("h00") T_7767.io.out.grant.valid := UInt<1>("h00") T_7767.io.out.acquire.ready := UInt<1>("h00") T_7767.io.in.grant.ready := UInt<1>("h00") T_7767.io.in.acquire.bits.union := UInt<1>("h00") T_7767.io.in.acquire.bits.a_type := UInt<1>("h00") T_7767.io.in.acquire.bits.is_builtin_type := UInt<1>("h00") T_7767.io.in.acquire.bits.data := UInt<1>("h00") T_7767.io.in.acquire.bits.addr_beat := UInt<1>("h00") T_7767.io.in.acquire.bits.client_xact_id := UInt<1>("h00") T_7767.io.in.acquire.bits.addr_block := UInt<1>("h00") T_7767.io.in.acquire.valid := UInt<1>("h00") T_7767.clock := clock T_7767.reset := reset T_7767.io.in <> io.tiles_uncached[0] inst T_7789 of ClientTileLinkIOWrapper T_7789.io.out.release.ready := UInt<1>("h00") T_7789.io.out.probe.bits.p_type := UInt<1>("h00") T_7789.io.out.probe.bits.addr_block := UInt<1>("h00") T_7789.io.out.probe.valid := UInt<1>("h00") T_7789.io.out.grant.bits.g_type := UInt<1>("h00") T_7789.io.out.grant.bits.is_builtin_type := UInt<1>("h00") T_7789.io.out.grant.bits.manager_xact_id := UInt<1>("h00") T_7789.io.out.grant.bits.client_xact_id := UInt<1>("h00") T_7789.io.out.grant.bits.data := UInt<1>("h00") T_7789.io.out.grant.bits.addr_beat := UInt<1>("h00") T_7789.io.out.grant.valid := UInt<1>("h00") T_7789.io.out.acquire.ready := UInt<1>("h00") T_7789.io.in.grant.ready := UInt<1>("h00") T_7789.io.in.acquire.bits.union := UInt<1>("h00") T_7789.io.in.acquire.bits.a_type := UInt<1>("h00") T_7789.io.in.acquire.bits.is_builtin_type := UInt<1>("h00") T_7789.io.in.acquire.bits.data := UInt<1>("h00") T_7789.io.in.acquire.bits.addr_beat := UInt<1>("h00") T_7789.io.in.acquire.bits.client_xact_id := UInt<1>("h00") T_7789.io.in.acquire.bits.addr_block := UInt<1>("h00") T_7789.io.in.acquire.valid := UInt<1>("h00") T_7789.clock := clock T_7789.reset := reset T_7789.io.in <> io.htif_uncached inst l1tol2net of RocketChipTileLinkArbiter l1tol2net.io.managers[0].release.ready := UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.client_id := UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.p_type := UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.addr_block := UInt<1>("h00") l1tol2net.io.managers[0].probe.valid := UInt<1>("h00") l1tol2net.io.managers[0].finish.ready := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.client_id := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.g_type := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.is_builtin_type := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.manager_xact_id := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.data := UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.addr_beat := UInt<1>("h00") l1tol2net.io.managers[0].grant.valid := UInt<1>("h00") l1tol2net.io.managers[0].acquire.ready := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.voluntary := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.r_type := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.data := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[0].release.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[0].release.valid := UInt<1>("h00") l1tol2net.io.clients[0].probe.ready := UInt<1>("h00") l1tol2net.io.clients[0].grant.ready := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.union := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.a_type := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.is_builtin_type := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.data := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[0].acquire.valid := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.voluntary := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.r_type := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.data := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[1].release.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[1].release.valid := UInt<1>("h00") l1tol2net.io.clients[1].probe.ready := UInt<1>("h00") l1tol2net.io.clients[1].grant.ready := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.union := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.a_type := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.is_builtin_type := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.data := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[1].acquire.valid := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.voluntary := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.r_type := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.data := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[2].release.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[2].release.valid := UInt<1>("h00") l1tol2net.io.clients[2].probe.ready := UInt<1>("h00") l1tol2net.io.clients[2].grant.ready := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.union := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.a_type := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.is_builtin_type := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.data := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.addr_beat := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.client_xact_id := UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.addr_block := UInt<1>("h00") l1tol2net.io.clients[2].acquire.valid := UInt<1>("h00") l1tol2net.clock := clock l1tol2net.reset := reset inst T_7878 of L2BroadcastHub T_7878.io.outer.grant.bits.g_type := UInt<1>("h00") T_7878.io.outer.grant.bits.is_builtin_type := UInt<1>("h00") T_7878.io.outer.grant.bits.manager_xact_id := UInt<1>("h00") T_7878.io.outer.grant.bits.client_xact_id := UInt<1>("h00") T_7878.io.outer.grant.bits.data := UInt<1>("h00") T_7878.io.outer.grant.bits.addr_beat := UInt<1>("h00") T_7878.io.outer.grant.valid := UInt<1>("h00") T_7878.io.outer.acquire.ready := UInt<1>("h00") T_7878.io.incoherent[0] := UInt<1>("h00") T_7878.io.inner.release.bits.client_id := UInt<1>("h00") T_7878.io.inner.release.bits.voluntary := UInt<1>("h00") T_7878.io.inner.release.bits.r_type := UInt<1>("h00") T_7878.io.inner.release.bits.data := UInt<1>("h00") T_7878.io.inner.release.bits.addr_beat := UInt<1>("h00") T_7878.io.inner.release.bits.client_xact_id := UInt<1>("h00") T_7878.io.inner.release.bits.addr_block := UInt<1>("h00") T_7878.io.inner.release.valid := UInt<1>("h00") T_7878.io.inner.probe.ready := UInt<1>("h00") T_7878.io.inner.finish.bits.manager_xact_id := UInt<1>("h00") T_7878.io.inner.finish.valid := UInt<1>("h00") T_7878.io.inner.grant.ready := UInt<1>("h00") T_7878.io.inner.acquire.bits.client_id := UInt<1>("h00") T_7878.io.inner.acquire.bits.union := UInt<1>("h00") T_7878.io.inner.acquire.bits.a_type := UInt<1>("h00") T_7878.io.inner.acquire.bits.is_builtin_type := UInt<1>("h00") T_7878.io.inner.acquire.bits.data := UInt<1>("h00") T_7878.io.inner.acquire.bits.addr_beat := UInt<1>("h00") T_7878.io.inner.acquire.bits.client_xact_id := UInt<1>("h00") T_7878.io.inner.acquire.bits.addr_block := UInt<1>("h00") T_7878.io.inner.acquire.valid := UInt<1>("h00") T_7878.clock := clock T_7878.reset := reset T_7878.io.incoherent := io.incoherent l1tol2net.io.clients[0] <> io.tiles_cached[0] l1tol2net.io.clients[1] <> T_7767.io.out l1tol2net.io.clients[2] <> T_7789.io.out l1tol2net.io.managers[0] <> T_7878.io.inner inst interconnect of NASTITopInterconnect interconnect.io.slaves[0].r.bits.user := UInt<1>("h00") interconnect.io.slaves[0].r.bits.id := UInt<1>("h00") interconnect.io.slaves[0].r.bits.last := UInt<1>("h00") interconnect.io.slaves[0].r.bits.data := UInt<1>("h00") interconnect.io.slaves[0].r.bits.resp := UInt<1>("h00") interconnect.io.slaves[0].r.valid := UInt<1>("h00") interconnect.io.slaves[0].ar.ready := UInt<1>("h00") interconnect.io.slaves[0].b.bits.user := UInt<1>("h00") interconnect.io.slaves[0].b.bits.id := UInt<1>("h00") interconnect.io.slaves[0].b.bits.resp := UInt<1>("h00") interconnect.io.slaves[0].b.valid := UInt<1>("h00") interconnect.io.slaves[0].w.ready := UInt<1>("h00") interconnect.io.slaves[0].aw.ready := UInt<1>("h00") interconnect.io.slaves[1].r.bits.user := UInt<1>("h00") interconnect.io.slaves[1].r.bits.id := UInt<1>("h00") interconnect.io.slaves[1].r.bits.last := UInt<1>("h00") interconnect.io.slaves[1].r.bits.data := UInt<1>("h00") interconnect.io.slaves[1].r.bits.resp := UInt<1>("h00") interconnect.io.slaves[1].r.valid := UInt<1>("h00") interconnect.io.slaves[1].ar.ready := UInt<1>("h00") interconnect.io.slaves[1].b.bits.user := UInt<1>("h00") interconnect.io.slaves[1].b.bits.id := UInt<1>("h00") interconnect.io.slaves[1].b.bits.resp := UInt<1>("h00") interconnect.io.slaves[1].b.valid := UInt<1>("h00") interconnect.io.slaves[1].w.ready := UInt<1>("h00") interconnect.io.slaves[1].aw.ready := UInt<1>("h00") interconnect.io.slaves[2].r.bits.user := UInt<1>("h00") interconnect.io.slaves[2].r.bits.id := UInt<1>("h00") interconnect.io.slaves[2].r.bits.last := UInt<1>("h00") interconnect.io.slaves[2].r.bits.data := UInt<1>("h00") interconnect.io.slaves[2].r.bits.resp := UInt<1>("h00") interconnect.io.slaves[2].r.valid := UInt<1>("h00") interconnect.io.slaves[2].ar.ready := UInt<1>("h00") interconnect.io.slaves[2].b.bits.user := UInt<1>("h00") interconnect.io.slaves[2].b.bits.id := UInt<1>("h00") interconnect.io.slaves[2].b.bits.resp := UInt<1>("h00") interconnect.io.slaves[2].b.valid := UInt<1>("h00") interconnect.io.slaves[2].w.ready := UInt<1>("h00") interconnect.io.slaves[2].aw.ready := UInt<1>("h00") interconnect.io.slaves[3].r.bits.user := UInt<1>("h00") interconnect.io.slaves[3].r.bits.id := UInt<1>("h00") interconnect.io.slaves[3].r.bits.last := UInt<1>("h00") interconnect.io.slaves[3].r.bits.data := UInt<1>("h00") interconnect.io.slaves[3].r.bits.resp := UInt<1>("h00") interconnect.io.slaves[3].r.valid := UInt<1>("h00") interconnect.io.slaves[3].ar.ready := UInt<1>("h00") interconnect.io.slaves[3].b.bits.user := UInt<1>("h00") interconnect.io.slaves[3].b.bits.id := UInt<1>("h00") interconnect.io.slaves[3].b.bits.resp := UInt<1>("h00") interconnect.io.slaves[3].b.valid := UInt<1>("h00") interconnect.io.slaves[3].w.ready := UInt<1>("h00") interconnect.io.slaves[3].aw.ready := UInt<1>("h00") interconnect.io.masters[0].r.ready := UInt<1>("h00") interconnect.io.masters[0].ar.bits.user := UInt<1>("h00") interconnect.io.masters[0].ar.bits.id := UInt<1>("h00") interconnect.io.masters[0].ar.bits.region := UInt<1>("h00") interconnect.io.masters[0].ar.bits.qos := UInt<1>("h00") interconnect.io.masters[0].ar.bits.prot := UInt<1>("h00") interconnect.io.masters[0].ar.bits.cache := UInt<1>("h00") interconnect.io.masters[0].ar.bits.lock := UInt<1>("h00") interconnect.io.masters[0].ar.bits.burst := UInt<1>("h00") interconnect.io.masters[0].ar.bits.size := UInt<1>("h00") interconnect.io.masters[0].ar.bits.len := UInt<1>("h00") interconnect.io.masters[0].ar.bits.addr := UInt<1>("h00") interconnect.io.masters[0].ar.valid := UInt<1>("h00") interconnect.io.masters[0].b.ready := UInt<1>("h00") interconnect.io.masters[0].w.bits.user := UInt<1>("h00") interconnect.io.masters[0].w.bits.strb := UInt<1>("h00") interconnect.io.masters[0].w.bits.last := UInt<1>("h00") interconnect.io.masters[0].w.bits.data := UInt<1>("h00") interconnect.io.masters[0].w.valid := UInt<1>("h00") interconnect.io.masters[0].aw.bits.user := UInt<1>("h00") interconnect.io.masters[0].aw.bits.id := UInt<1>("h00") interconnect.io.masters[0].aw.bits.region := UInt<1>("h00") interconnect.io.masters[0].aw.bits.qos := UInt<1>("h00") interconnect.io.masters[0].aw.bits.prot := UInt<1>("h00") interconnect.io.masters[0].aw.bits.cache := UInt<1>("h00") interconnect.io.masters[0].aw.bits.lock := UInt<1>("h00") interconnect.io.masters[0].aw.bits.burst := UInt<1>("h00") interconnect.io.masters[0].aw.bits.size := UInt<1>("h00") interconnect.io.masters[0].aw.bits.len := UInt<1>("h00") interconnect.io.masters[0].aw.bits.addr := UInt<1>("h00") interconnect.io.masters[0].aw.valid := UInt<1>("h00") interconnect.io.masters[1].r.ready := UInt<1>("h00") interconnect.io.masters[1].ar.bits.user := UInt<1>("h00") interconnect.io.masters[1].ar.bits.id := UInt<1>("h00") interconnect.io.masters[1].ar.bits.region := UInt<1>("h00") interconnect.io.masters[1].ar.bits.qos := UInt<1>("h00") interconnect.io.masters[1].ar.bits.prot := UInt<1>("h00") interconnect.io.masters[1].ar.bits.cache := UInt<1>("h00") interconnect.io.masters[1].ar.bits.lock := UInt<1>("h00") interconnect.io.masters[1].ar.bits.burst := UInt<1>("h00") interconnect.io.masters[1].ar.bits.size := UInt<1>("h00") interconnect.io.masters[1].ar.bits.len := UInt<1>("h00") interconnect.io.masters[1].ar.bits.addr := UInt<1>("h00") interconnect.io.masters[1].ar.valid := UInt<1>("h00") interconnect.io.masters[1].b.ready := UInt<1>("h00") interconnect.io.masters[1].w.bits.user := UInt<1>("h00") interconnect.io.masters[1].w.bits.strb := UInt<1>("h00") interconnect.io.masters[1].w.bits.last := UInt<1>("h00") interconnect.io.masters[1].w.bits.data := UInt<1>("h00") interconnect.io.masters[1].w.valid := UInt<1>("h00") interconnect.io.masters[1].aw.bits.user := UInt<1>("h00") interconnect.io.masters[1].aw.bits.id := UInt<1>("h00") interconnect.io.masters[1].aw.bits.region := UInt<1>("h00") interconnect.io.masters[1].aw.bits.qos := UInt<1>("h00") interconnect.io.masters[1].aw.bits.prot := UInt<1>("h00") interconnect.io.masters[1].aw.bits.cache := UInt<1>("h00") interconnect.io.masters[1].aw.bits.lock := UInt<1>("h00") interconnect.io.masters[1].aw.bits.burst := UInt<1>("h00") interconnect.io.masters[1].aw.bits.size := UInt<1>("h00") interconnect.io.masters[1].aw.bits.len := UInt<1>("h00") interconnect.io.masters[1].aw.bits.addr := UInt<1>("h00") interconnect.io.masters[1].aw.valid := UInt<1>("h00") interconnect.clock := clock interconnect.reset := reset inst T_8024 of ClientTileLinkIOUnwrapper T_8024.io.out.grant.bits.g_type := UInt<1>("h00") T_8024.io.out.grant.bits.is_builtin_type := UInt<1>("h00") T_8024.io.out.grant.bits.manager_xact_id := UInt<1>("h00") T_8024.io.out.grant.bits.client_xact_id := UInt<1>("h00") T_8024.io.out.grant.bits.data := UInt<1>("h00") T_8024.io.out.grant.bits.addr_beat := UInt<1>("h00") T_8024.io.out.grant.valid := UInt<1>("h00") T_8024.io.out.acquire.ready := UInt<1>("h00") T_8024.io.in.release.bits.voluntary := UInt<1>("h00") T_8024.io.in.release.bits.r_type := UInt<1>("h00") T_8024.io.in.release.bits.data := UInt<1>("h00") T_8024.io.in.release.bits.addr_beat := UInt<1>("h00") T_8024.io.in.release.bits.client_xact_id := UInt<1>("h00") T_8024.io.in.release.bits.addr_block := UInt<1>("h00") T_8024.io.in.release.valid := UInt<1>("h00") T_8024.io.in.probe.ready := UInt<1>("h00") T_8024.io.in.grant.ready := UInt<1>("h00") T_8024.io.in.acquire.bits.union := UInt<1>("h00") T_8024.io.in.acquire.bits.a_type := UInt<1>("h00") T_8024.io.in.acquire.bits.is_builtin_type := UInt<1>("h00") T_8024.io.in.acquire.bits.data := UInt<1>("h00") T_8024.io.in.acquire.bits.addr_beat := UInt<1>("h00") T_8024.io.in.acquire.bits.client_xact_id := UInt<1>("h00") T_8024.io.in.acquire.bits.addr_block := UInt<1>("h00") T_8024.io.in.acquire.valid := UInt<1>("h00") T_8024.clock := clock T_8024.reset := reset inst T_8050 of TileLinkIONarrower T_8050.io.out.grant.bits.g_type := UInt<1>("h00") T_8050.io.out.grant.bits.is_builtin_type := UInt<1>("h00") T_8050.io.out.grant.bits.manager_xact_id := UInt<1>("h00") T_8050.io.out.grant.bits.client_xact_id := UInt<1>("h00") T_8050.io.out.grant.bits.data := UInt<1>("h00") T_8050.io.out.grant.bits.addr_beat := UInt<1>("h00") T_8050.io.out.grant.valid := UInt<1>("h00") T_8050.io.out.acquire.ready := UInt<1>("h00") T_8050.io.in.grant.ready := UInt<1>("h00") T_8050.io.in.acquire.bits.union := UInt<1>("h00") T_8050.io.in.acquire.bits.a_type := UInt<1>("h00") T_8050.io.in.acquire.bits.is_builtin_type := UInt<1>("h00") T_8050.io.in.acquire.bits.data := UInt<1>("h00") T_8050.io.in.acquire.bits.addr_beat := UInt<1>("h00") T_8050.io.in.acquire.bits.client_xact_id := UInt<1>("h00") T_8050.io.in.acquire.bits.addr_block := UInt<1>("h00") T_8050.io.in.acquire.valid := UInt<1>("h00") T_8050.clock := clock T_8050.reset := reset inst T_8068 of NASTIIOTileLinkIOConverter T_8068.io.nasti.r.bits.user := UInt<1>("h00") T_8068.io.nasti.r.bits.id := UInt<1>("h00") T_8068.io.nasti.r.bits.last := UInt<1>("h00") T_8068.io.nasti.r.bits.data := UInt<1>("h00") T_8068.io.nasti.r.bits.resp := UInt<1>("h00") T_8068.io.nasti.r.valid := UInt<1>("h00") T_8068.io.nasti.ar.ready := UInt<1>("h00") T_8068.io.nasti.b.bits.user := UInt<1>("h00") T_8068.io.nasti.b.bits.id := UInt<1>("h00") T_8068.io.nasti.b.bits.resp := UInt<1>("h00") T_8068.io.nasti.b.valid := UInt<1>("h00") T_8068.io.nasti.w.ready := UInt<1>("h00") T_8068.io.nasti.aw.ready := UInt<1>("h00") T_8068.io.tl.grant.ready := UInt<1>("h00") T_8068.io.tl.acquire.bits.union := UInt<1>("h00") T_8068.io.tl.acquire.bits.a_type := UInt<1>("h00") T_8068.io.tl.acquire.bits.is_builtin_type := UInt<1>("h00") T_8068.io.tl.acquire.bits.data := UInt<1>("h00") T_8068.io.tl.acquire.bits.addr_beat := UInt<1>("h00") T_8068.io.tl.acquire.bits.client_xact_id := UInt<1>("h00") T_8068.io.tl.acquire.bits.addr_block := UInt<1>("h00") T_8068.io.tl.acquire.valid := UInt<1>("h00") T_8068.clock := clock T_8068.reset := reset inst T_8091 of ClientTileLinkIOWrapper_65 T_8091.io.out.release.ready := UInt<1>("h00") T_8091.io.out.probe.bits.p_type := UInt<1>("h00") T_8091.io.out.probe.bits.addr_block := UInt<1>("h00") T_8091.io.out.probe.valid := UInt<1>("h00") T_8091.io.out.grant.bits.g_type := UInt<1>("h00") T_8091.io.out.grant.bits.is_builtin_type := UInt<1>("h00") T_8091.io.out.grant.bits.manager_xact_id := UInt<1>("h00") T_8091.io.out.grant.bits.client_xact_id := UInt<1>("h00") T_8091.io.out.grant.bits.data := UInt<1>("h00") T_8091.io.out.grant.bits.addr_beat := UInt<1>("h00") T_8091.io.out.grant.valid := UInt<1>("h00") T_8091.io.out.acquire.ready := UInt<1>("h00") T_8091.io.in.grant.ready := UInt<1>("h00") T_8091.io.in.acquire.bits.union := UInt<1>("h00") T_8091.io.in.acquire.bits.a_type := UInt<1>("h00") T_8091.io.in.acquire.bits.is_builtin_type := UInt<1>("h00") T_8091.io.in.acquire.bits.data := UInt<1>("h00") T_8091.io.in.acquire.bits.addr_beat := UInt<1>("h00") T_8091.io.in.acquire.bits.client_xact_id := UInt<1>("h00") T_8091.io.in.acquire.bits.addr_block := UInt<1>("h00") T_8091.io.in.acquire.valid := UInt<1>("h00") T_8091.clock := clock T_8091.reset := reset T_8091.io.in <> T_7878.io.outer T_8024.io.in <> T_8091.io.out T_8050.io.in <> T_8024.io.out T_8068.io.tl <> T_8050.io.out interconnect.io.masters[0] <> T_8068.io.nasti inst rtc of RTC rtc.io.r.bits.user := UInt<1>("h00") rtc.io.r.bits.id := UInt<1>("h00") rtc.io.r.bits.last := UInt<1>("h00") rtc.io.r.bits.data := UInt<1>("h00") rtc.io.r.bits.resp := UInt<1>("h00") rtc.io.r.valid := UInt<1>("h00") rtc.io.ar.ready := UInt<1>("h00") rtc.io.b.bits.user := UInt<1>("h00") rtc.io.b.bits.id := UInt<1>("h00") rtc.io.b.bits.resp := UInt<1>("h00") rtc.io.b.valid := UInt<1>("h00") rtc.io.w.ready := UInt<1>("h00") rtc.io.aw.ready := UInt<1>("h00") rtc.clock := clock rtc.reset := reset interconnect.io.masters[1] <> rtc.io inst T_8127 of SMIIONASTIIOConverter T_8127.io.smi.resp.bits := UInt<1>("h00") T_8127.io.smi.resp.valid := UInt<1>("h00") T_8127.io.smi.req.ready := UInt<1>("h00") T_8127.io.nasti.r.ready := UInt<1>("h00") T_8127.io.nasti.ar.bits.user := UInt<1>("h00") T_8127.io.nasti.ar.bits.id := UInt<1>("h00") T_8127.io.nasti.ar.bits.region := UInt<1>("h00") T_8127.io.nasti.ar.bits.qos := UInt<1>("h00") T_8127.io.nasti.ar.bits.prot := UInt<1>("h00") T_8127.io.nasti.ar.bits.cache := UInt<1>("h00") T_8127.io.nasti.ar.bits.lock := UInt<1>("h00") T_8127.io.nasti.ar.bits.burst := UInt<1>("h00") T_8127.io.nasti.ar.bits.size := UInt<1>("h00") T_8127.io.nasti.ar.bits.len := UInt<1>("h00") T_8127.io.nasti.ar.bits.addr := UInt<1>("h00") T_8127.io.nasti.ar.valid := UInt<1>("h00") T_8127.io.nasti.b.ready := UInt<1>("h00") T_8127.io.nasti.w.bits.user := UInt<1>("h00") T_8127.io.nasti.w.bits.strb := UInt<1>("h00") T_8127.io.nasti.w.bits.last := UInt<1>("h00") T_8127.io.nasti.w.bits.data := UInt<1>("h00") T_8127.io.nasti.w.valid := UInt<1>("h00") T_8127.io.nasti.aw.bits.user := UInt<1>("h00") T_8127.io.nasti.aw.bits.id := UInt<1>("h00") T_8127.io.nasti.aw.bits.region := UInt<1>("h00") T_8127.io.nasti.aw.bits.qos := UInt<1>("h00") T_8127.io.nasti.aw.bits.prot := UInt<1>("h00") T_8127.io.nasti.aw.bits.cache := UInt<1>("h00") T_8127.io.nasti.aw.bits.lock := UInt<1>("h00") T_8127.io.nasti.aw.bits.burst := UInt<1>("h00") T_8127.io.nasti.aw.bits.size := UInt<1>("h00") T_8127.io.nasti.aw.bits.len := UInt<1>("h00") T_8127.io.nasti.aw.bits.addr := UInt<1>("h00") T_8127.io.nasti.aw.valid := UInt<1>("h00") T_8127.clock := clock T_8127.reset := reset T_8127.io.nasti <> interconnect.io.slaves[1] io.pcr[0] <> T_8127.io.smi inst conv of SMIIONASTIIOConverter_67 conv.io.smi.resp.bits := UInt<1>("h00") conv.io.smi.resp.valid := UInt<1>("h00") conv.io.smi.req.ready := UInt<1>("h00") conv.io.nasti.r.ready := UInt<1>("h00") conv.io.nasti.ar.bits.user := UInt<1>("h00") conv.io.nasti.ar.bits.id := UInt<1>("h00") conv.io.nasti.ar.bits.region := UInt<1>("h00") conv.io.nasti.ar.bits.qos := UInt<1>("h00") conv.io.nasti.ar.bits.prot := UInt<1>("h00") conv.io.nasti.ar.bits.cache := UInt<1>("h00") conv.io.nasti.ar.bits.lock := UInt<1>("h00") conv.io.nasti.ar.bits.burst := UInt<1>("h00") conv.io.nasti.ar.bits.size := UInt<1>("h00") conv.io.nasti.ar.bits.len := UInt<1>("h00") conv.io.nasti.ar.bits.addr := UInt<1>("h00") conv.io.nasti.ar.valid := UInt<1>("h00") conv.io.nasti.b.ready := UInt<1>("h00") conv.io.nasti.w.bits.user := UInt<1>("h00") conv.io.nasti.w.bits.strb := UInt<1>("h00") conv.io.nasti.w.bits.last := UInt<1>("h00") conv.io.nasti.w.bits.data := UInt<1>("h00") conv.io.nasti.w.valid := UInt<1>("h00") conv.io.nasti.aw.bits.user := UInt<1>("h00") conv.io.nasti.aw.bits.id := UInt<1>("h00") conv.io.nasti.aw.bits.region := UInt<1>("h00") conv.io.nasti.aw.bits.qos := UInt<1>("h00") conv.io.nasti.aw.bits.prot := UInt<1>("h00") conv.io.nasti.aw.bits.cache := UInt<1>("h00") conv.io.nasti.aw.bits.lock := UInt<1>("h00") conv.io.nasti.aw.bits.burst := UInt<1>("h00") conv.io.nasti.aw.bits.size := UInt<1>("h00") conv.io.nasti.aw.bits.len := UInt<1>("h00") conv.io.nasti.aw.bits.addr := UInt<1>("h00") conv.io.nasti.aw.valid := UInt<1>("h00") conv.clock := clock conv.reset := reset conv.io.nasti <> interconnect.io.slaves[2] io.scr <> conv.io.smi io.mmio <> interconnect.io.slaves[3] inst T_8197 of NASTIArbiter_72 T_8197.io.slave.r.bits.user := UInt<1>("h00") T_8197.io.slave.r.bits.id := UInt<1>("h00") T_8197.io.slave.r.bits.last := UInt<1>("h00") T_8197.io.slave.r.bits.data := UInt<1>("h00") T_8197.io.slave.r.bits.resp := UInt<1>("h00") T_8197.io.slave.r.valid := UInt<1>("h00") T_8197.io.slave.ar.ready := UInt<1>("h00") T_8197.io.slave.b.bits.user := UInt<1>("h00") T_8197.io.slave.b.bits.id := UInt<1>("h00") T_8197.io.slave.b.bits.resp := UInt<1>("h00") T_8197.io.slave.b.valid := UInt<1>("h00") T_8197.io.slave.w.ready := UInt<1>("h00") T_8197.io.slave.aw.ready := UInt<1>("h00") T_8197.io.master[0].r.ready := UInt<1>("h00") T_8197.io.master[0].ar.bits.user := UInt<1>("h00") T_8197.io.master[0].ar.bits.id := UInt<1>("h00") T_8197.io.master[0].ar.bits.region := UInt<1>("h00") T_8197.io.master[0].ar.bits.qos := UInt<1>("h00") T_8197.io.master[0].ar.bits.prot := UInt<1>("h00") T_8197.io.master[0].ar.bits.cache := UInt<1>("h00") T_8197.io.master[0].ar.bits.lock := UInt<1>("h00") T_8197.io.master[0].ar.bits.burst := UInt<1>("h00") T_8197.io.master[0].ar.bits.size := UInt<1>("h00") T_8197.io.master[0].ar.bits.len := UInt<1>("h00") T_8197.io.master[0].ar.bits.addr := UInt<1>("h00") T_8197.io.master[0].ar.valid := UInt<1>("h00") T_8197.io.master[0].b.ready := UInt<1>("h00") T_8197.io.master[0].w.bits.user := UInt<1>("h00") T_8197.io.master[0].w.bits.strb := UInt<1>("h00") T_8197.io.master[0].w.bits.last := UInt<1>("h00") T_8197.io.master[0].w.bits.data := UInt<1>("h00") T_8197.io.master[0].w.valid := UInt<1>("h00") T_8197.io.master[0].aw.bits.user := UInt<1>("h00") T_8197.io.master[0].aw.bits.id := UInt<1>("h00") T_8197.io.master[0].aw.bits.region := UInt<1>("h00") T_8197.io.master[0].aw.bits.qos := UInt<1>("h00") T_8197.io.master[0].aw.bits.prot := UInt<1>("h00") T_8197.io.master[0].aw.bits.cache := UInt<1>("h00") T_8197.io.master[0].aw.bits.lock := UInt<1>("h00") T_8197.io.master[0].aw.bits.burst := UInt<1>("h00") T_8197.io.master[0].aw.bits.size := UInt<1>("h00") T_8197.io.master[0].aw.bits.len := UInt<1>("h00") T_8197.io.master[0].aw.bits.addr := UInt<1>("h00") T_8197.io.master[0].aw.valid := UInt<1>("h00") T_8197.clock := clock T_8197.reset := reset inst T_8242 of MemIONASTIIOConverter T_8242.io.mem.resp.bits.tag := UInt<1>("h00") T_8242.io.mem.resp.bits.data := UInt<1>("h00") T_8242.io.mem.resp.valid := UInt<1>("h00") T_8242.io.mem.req_data.ready := UInt<1>("h00") T_8242.io.mem.req_cmd.ready := UInt<1>("h00") T_8242.io.nasti.r.ready := UInt<1>("h00") T_8242.io.nasti.ar.bits.user := UInt<1>("h00") T_8242.io.nasti.ar.bits.id := UInt<1>("h00") T_8242.io.nasti.ar.bits.region := UInt<1>("h00") T_8242.io.nasti.ar.bits.qos := UInt<1>("h00") T_8242.io.nasti.ar.bits.prot := UInt<1>("h00") T_8242.io.nasti.ar.bits.cache := UInt<1>("h00") T_8242.io.nasti.ar.bits.lock := UInt<1>("h00") T_8242.io.nasti.ar.bits.burst := UInt<1>("h00") T_8242.io.nasti.ar.bits.size := UInt<1>("h00") T_8242.io.nasti.ar.bits.len := UInt<1>("h00") T_8242.io.nasti.ar.bits.addr := UInt<1>("h00") T_8242.io.nasti.ar.valid := UInt<1>("h00") T_8242.io.nasti.b.ready := UInt<1>("h00") T_8242.io.nasti.w.bits.user := UInt<1>("h00") T_8242.io.nasti.w.bits.strb := UInt<1>("h00") T_8242.io.nasti.w.bits.last := UInt<1>("h00") T_8242.io.nasti.w.bits.data := UInt<1>("h00") T_8242.io.nasti.w.valid := UInt<1>("h00") T_8242.io.nasti.aw.bits.user := UInt<1>("h00") T_8242.io.nasti.aw.bits.id := UInt<1>("h00") T_8242.io.nasti.aw.bits.region := UInt<1>("h00") T_8242.io.nasti.aw.bits.qos := UInt<1>("h00") T_8242.io.nasti.aw.bits.prot := UInt<1>("h00") T_8242.io.nasti.aw.bits.cache := UInt<1>("h00") T_8242.io.nasti.aw.bits.lock := UInt<1>("h00") T_8242.io.nasti.aw.bits.burst := UInt<1>("h00") T_8242.io.nasti.aw.bits.size := UInt<1>("h00") T_8242.io.nasti.aw.bits.len := UInt<1>("h00") T_8242.io.nasti.aw.bits.addr := UInt<1>("h00") T_8242.io.nasti.aw.valid := UInt<1>("h00") T_8242.clock := clock T_8242.reset := reset inst T_8279 of MemSerdes T_8279.io.narrow.resp.bits := UInt<1>("h00") T_8279.io.narrow.resp.valid := UInt<1>("h00") T_8279.io.narrow.req.ready := UInt<1>("h00") T_8279.io.wide.resp.ready := UInt<1>("h00") T_8279.io.wide.req_data.bits.data := UInt<1>("h00") T_8279.io.wide.req_data.valid := UInt<1>("h00") T_8279.io.wide.req_cmd.bits.rw := UInt<1>("h00") T_8279.io.wide.req_cmd.bits.tag := UInt<1>("h00") T_8279.io.wide.req_cmd.bits.addr := UInt<1>("h00") T_8279.io.wide.req_cmd.valid := UInt<1>("h00") T_8279.clock := clock T_8279.reset := reset T_8242.io.nasti <> T_8197.io.slave T_8279.io.wide <> T_8242.io.mem io.mem_backup <> T_8279.io.narrow node T_8290 = mux(io.mem_backup_en, T_8197.io.master[0].ar.ready, io.mem[0].ar.ready) interconnect.io.slaves[0].ar.ready := T_8290 node T_8292 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8293 = and(interconnect.io.slaves[0].ar.valid, T_8292) io.mem[0].ar.valid := T_8293 io.mem[0].ar.bits <> interconnect.io.slaves[0].ar.bits node T_8294 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) T_8197.io.master[0].ar.valid := T_8294 T_8197.io.master[0].ar.bits <> interconnect.io.slaves[0].ar.bits node T_8295 = mux(io.mem_backup_en, T_8197.io.master[0].aw.ready, io.mem[0].aw.ready) interconnect.io.slaves[0].aw.ready := T_8295 node T_8297 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8298 = and(interconnect.io.slaves[0].aw.valid, T_8297) io.mem[0].aw.valid := T_8298 io.mem[0].aw.bits <> interconnect.io.slaves[0].aw.bits node T_8299 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) T_8197.io.master[0].aw.valid := T_8299 T_8197.io.master[0].aw.bits <> interconnect.io.slaves[0].aw.bits node T_8300 = mux(io.mem_backup_en, T_8197.io.master[0].w.ready, io.mem[0].w.ready) interconnect.io.slaves[0].w.ready := T_8300 node T_8302 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8303 = and(interconnect.io.slaves[0].w.valid, T_8302) io.mem[0].w.valid := T_8303 io.mem[0].w.bits <> interconnect.io.slaves[0].w.bits node T_8304 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) T_8197.io.master[0].w.valid := T_8304 T_8197.io.master[0].w.bits <> interconnect.io.slaves[0].w.bits node T_8305 = mux(io.mem_backup_en, T_8197.io.master[0].b.valid, io.mem[0].b.valid) interconnect.io.slaves[0].b.valid := T_8305 wire T_8310 : {resp : UInt<2>, id : UInt<6>, user : UInt<1>} T_8310 <> io.mem[0].b.bits when io.mem_backup_en : T_8310 <> T_8197.io.master[0].b.bits skip interconnect.io.slaves[0].b.bits <> T_8310 node T_8315 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8316 = and(interconnect.io.slaves[0].b.ready, T_8315) io.mem[0].b.ready := T_8316 node T_8317 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) T_8197.io.master[0].b.ready := T_8317 node T_8318 = mux(io.mem_backup_en, T_8197.io.master[0].r.valid, io.mem[0].r.valid) interconnect.io.slaves[0].r.valid := T_8318 wire T_8325 : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>} T_8325 <> io.mem[0].r.bits when io.mem_backup_en : T_8325 <> T_8197.io.master[0].r.bits skip interconnect.io.slaves[0].r.bits <> T_8325 node T_8332 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8333 = and(interconnect.io.slaves[0].r.ready, T_8332) io.mem[0].r.ready := T_8333 node T_8334 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) T_8197.io.master[0].r.ready := T_8334 module SCRFile : input clock : Clock input reset : UInt<1> output io : {flip smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}} io.scr.wdata := UInt<1>("h00") io.scr.waddr := UInt<1>("h00") io.scr.wen := UInt<1>("h00") io.smi.resp.bits := UInt<1>("h00") io.smi.resp.valid := UInt<1>("h00") io.smi.req.ready := UInt<1>("h00") wire scr_rdata : UInt<64>[64] scr_rdata[0] := UInt<1>("h00") scr_rdata[1] := UInt<1>("h00") scr_rdata[2] := UInt<1>("h00") scr_rdata[3] := UInt<1>("h00") scr_rdata[4] := UInt<1>("h00") scr_rdata[5] := UInt<1>("h00") scr_rdata[6] := UInt<1>("h00") scr_rdata[7] := UInt<1>("h00") scr_rdata[8] := UInt<1>("h00") scr_rdata[9] := UInt<1>("h00") scr_rdata[10] := UInt<1>("h00") scr_rdata[11] := UInt<1>("h00") scr_rdata[12] := UInt<1>("h00") scr_rdata[13] := UInt<1>("h00") scr_rdata[14] := UInt<1>("h00") scr_rdata[15] := UInt<1>("h00") scr_rdata[16] := UInt<1>("h00") scr_rdata[17] := UInt<1>("h00") scr_rdata[18] := UInt<1>("h00") scr_rdata[19] := UInt<1>("h00") scr_rdata[20] := UInt<1>("h00") scr_rdata[21] := UInt<1>("h00") scr_rdata[22] := UInt<1>("h00") scr_rdata[23] := UInt<1>("h00") scr_rdata[24] := UInt<1>("h00") scr_rdata[25] := UInt<1>("h00") scr_rdata[26] := UInt<1>("h00") scr_rdata[27] := UInt<1>("h00") scr_rdata[28] := UInt<1>("h00") scr_rdata[29] := UInt<1>("h00") scr_rdata[30] := UInt<1>("h00") scr_rdata[31] := UInt<1>("h00") scr_rdata[32] := UInt<1>("h00") scr_rdata[33] := UInt<1>("h00") scr_rdata[34] := UInt<1>("h00") scr_rdata[35] := UInt<1>("h00") scr_rdata[36] := UInt<1>("h00") scr_rdata[37] := UInt<1>("h00") scr_rdata[38] := UInt<1>("h00") scr_rdata[39] := UInt<1>("h00") scr_rdata[40] := UInt<1>("h00") scr_rdata[41] := UInt<1>("h00") scr_rdata[42] := UInt<1>("h00") scr_rdata[43] := UInt<1>("h00") scr_rdata[44] := UInt<1>("h00") scr_rdata[45] := UInt<1>("h00") scr_rdata[46] := UInt<1>("h00") scr_rdata[47] := UInt<1>("h00") scr_rdata[48] := UInt<1>("h00") scr_rdata[49] := UInt<1>("h00") scr_rdata[50] := UInt<1>("h00") scr_rdata[51] := UInt<1>("h00") scr_rdata[52] := UInt<1>("h00") scr_rdata[53] := UInt<1>("h00") scr_rdata[54] := UInt<1>("h00") scr_rdata[55] := UInt<1>("h00") scr_rdata[56] := UInt<1>("h00") scr_rdata[57] := UInt<1>("h00") scr_rdata[58] := UInt<1>("h00") scr_rdata[59] := UInt<1>("h00") scr_rdata[60] := UInt<1>("h00") scr_rdata[61] := UInt<1>("h00") scr_rdata[62] := UInt<1>("h00") scr_rdata[63] := UInt<1>("h00") scr_rdata[0] := io.scr.rdata[0] scr_rdata[1] := io.scr.rdata[1] scr_rdata[2] := io.scr.rdata[2] scr_rdata[3] := io.scr.rdata[3] scr_rdata[4] := io.scr.rdata[4] scr_rdata[5] := io.scr.rdata[5] scr_rdata[6] := io.scr.rdata[6] scr_rdata[7] := io.scr.rdata[7] scr_rdata[8] := io.scr.rdata[8] scr_rdata[9] := io.scr.rdata[9] scr_rdata[10] := io.scr.rdata[10] scr_rdata[11] := io.scr.rdata[11] scr_rdata[12] := io.scr.rdata[12] scr_rdata[13] := io.scr.rdata[13] scr_rdata[14] := io.scr.rdata[14] scr_rdata[15] := io.scr.rdata[15] scr_rdata[16] := io.scr.rdata[16] scr_rdata[17] := io.scr.rdata[17] scr_rdata[18] := io.scr.rdata[18] scr_rdata[19] := io.scr.rdata[19] scr_rdata[20] := io.scr.rdata[20] scr_rdata[21] := io.scr.rdata[21] scr_rdata[22] := io.scr.rdata[22] scr_rdata[23] := io.scr.rdata[23] scr_rdata[24] := io.scr.rdata[24] scr_rdata[25] := io.scr.rdata[25] scr_rdata[26] := io.scr.rdata[26] scr_rdata[27] := io.scr.rdata[27] scr_rdata[28] := io.scr.rdata[28] scr_rdata[29] := io.scr.rdata[29] scr_rdata[30] := io.scr.rdata[30] scr_rdata[31] := io.scr.rdata[31] scr_rdata[32] := io.scr.rdata[32] scr_rdata[33] := io.scr.rdata[33] scr_rdata[34] := io.scr.rdata[34] scr_rdata[35] := io.scr.rdata[35] scr_rdata[36] := io.scr.rdata[36] scr_rdata[37] := io.scr.rdata[37] scr_rdata[38] := io.scr.rdata[38] scr_rdata[39] := io.scr.rdata[39] scr_rdata[40] := io.scr.rdata[40] scr_rdata[41] := io.scr.rdata[41] scr_rdata[42] := io.scr.rdata[42] scr_rdata[43] := io.scr.rdata[43] scr_rdata[44] := io.scr.rdata[44] scr_rdata[45] := io.scr.rdata[45] scr_rdata[46] := io.scr.rdata[46] scr_rdata[47] := io.scr.rdata[47] scr_rdata[48] := io.scr.rdata[48] scr_rdata[49] := io.scr.rdata[49] scr_rdata[50] := io.scr.rdata[50] scr_rdata[51] := io.scr.rdata[51] scr_rdata[52] := io.scr.rdata[52] scr_rdata[53] := io.scr.rdata[53] scr_rdata[54] := io.scr.rdata[54] scr_rdata[55] := io.scr.rdata[55] scr_rdata[56] := io.scr.rdata[56] scr_rdata[57] := io.scr.rdata[57] scr_rdata[58] := io.scr.rdata[58] scr_rdata[59] := io.scr.rdata[59] scr_rdata[60] := io.scr.rdata[60] scr_rdata[61] := io.scr.rdata[61] scr_rdata[62] := io.scr.rdata[62] scr_rdata[63] := io.scr.rdata[63] scr_rdata[0] := UInt<1>("h01") scr_rdata[1] := UInt<11>("h0400") reg read_addr : UInt<6>, clock, reset onreset read_addr := UInt<6>("h00") reg resp_valid : UInt<1>, clock, reset onreset resp_valid := UInt<1>("h00") node T_337 = eq(resp_valid, UInt<1>("h00")) io.smi.req.ready := T_337 io.smi.resp.valid := resp_valid infer accessor T_338 = scr_rdata[read_addr] io.smi.resp.bits := T_338 node T_339 = and(io.smi.req.ready, io.smi.req.valid) node T_340 = and(T_339, io.smi.req.bits.rw) io.scr.wen := T_340 io.scr.wdata := io.smi.req.bits.data io.scr.waddr := io.smi.req.bits.addr node T_341 = and(io.smi.req.ready, io.smi.req.valid) when T_341 : read_addr := io.smi.req.bits.addr resp_valid := UInt<1>("h01") skip node T_343 = and(io.smi.resp.ready, io.smi.resp.valid) when T_343 : resp_valid := UInt<1>("h00") skip module Queue_78 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>} io.count := UInt<1>("h00") io.deq.bits := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : UInt<17>[1], clock reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_31 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_31) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_37 = and(io.enq.ready, io.enq.valid) node T_39 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_37, T_39) node T_41 = and(io.deq.ready, io.deq.valid) node T_43 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_41, T_43) when do_enq : infer accessor T_45 = ram[UInt<1>("h00")] T_45 := io.enq.bits skip when do_deq : skip node T_48 = neq(do_enq, do_deq) when T_48 : maybe_full := do_enq skip node T_50 = eq(empty, UInt<1>("h00")) node T_52 = and(UInt<1>("h00"), io.enq.valid) node T_53 = or(T_50, T_52) io.deq.valid := T_53 node T_55 = eq(full, UInt<1>("h00")) node T_57 = and(UInt<1>("h00"), io.deq.ready) node T_58 = or(T_55, T_57) io.enq.ready := T_58 infer accessor T_59 = ram[UInt<1>("h00")] node T_60 = mux(maybe_flow, io.enq.bits, T_59) io.deq.bits := T_60 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_62 = and(maybe_full, ptr_match) node T_63 = cat(T_62, ptr_diff) io.count := T_63 module SlowIO : input clock : Clock input reset : UInt<1> output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>} io.divisor := UInt<1>("h00") io.clk_slow := UInt<1>("h00") io.in_slow.ready := UInt<1>("h00") io.in_fast.bits := UInt<1>("h00") io.in_fast.valid := UInt<1>("h00") io.out_slow.bits := UInt<1>("h00") io.out_slow.valid := UInt<1>("h00") io.out_fast.ready := UInt<1>("h00") reg divisor : UInt, clock, reset onreset divisor := UInt<9>("h01ff") reg d_shadow : UInt, clock, reset onreset d_shadow := UInt<9>("h01ff") reg hold : UInt, clock, reset onreset hold := UInt<7>("h07f") reg h_shadow : UInt, clock, reset onreset h_shadow := UInt<7>("h07f") when io.set_divisor.valid : node T_57 = bits(io.set_divisor.bits, 8, 0) d_shadow := T_57 node T_58 = bits(io.set_divisor.bits, 24, 16) h_shadow := T_58 skip node T_59 = shl(hold, 16) node T_60 = or(T_59, divisor) io.divisor := T_60 reg count : UInt<9>, clock, reset reg myclock : UInt<1>, clock, reset node T_66 = addw(count, UInt<1>("h01")) count := T_66 node T_67 = shr(divisor, 1) node rising = eq(count, T_67) node falling = eq(count, divisor) node T_70 = shr(divisor, 1) node T_71 = addw(T_70, hold) node held = eq(count, T_71) when falling : divisor := d_shadow hold := h_shadow count := UInt<1>("h00") myclock := UInt<1>("h00") skip when rising : myclock := UInt<1>("h01") skip reg in_slow_rdy : UInt<1>, clock, reset onreset in_slow_rdy := UInt<1>("h00") reg out_slow_val : UInt<1>, clock, reset onreset out_slow_val := UInt<1>("h00") reg out_slow_bits : UInt<17>, clock, reset inst fromhost_q of Queue_78 fromhost_q.io.deq.ready := UInt<1>("h00") fromhost_q.io.enq.bits := UInt<1>("h00") fromhost_q.io.enq.valid := UInt<1>("h00") fromhost_q.clock := clock fromhost_q.reset := reset node T_87 = and(io.in_slow.valid, in_slow_rdy) node T_88 = or(T_87, reset) node T_89 = and(rising, T_88) fromhost_q.io.enq.valid := T_89 fromhost_q.io.enq.bits := io.in_slow.bits io.in_fast <> fromhost_q.io.deq inst tohost_q of Queue_78 tohost_q.io.deq.ready := UInt<1>("h00") tohost_q.io.enq.bits := UInt<1>("h00") tohost_q.io.enq.valid := UInt<1>("h00") tohost_q.clock := clock tohost_q.reset := reset tohost_q.io.enq <> io.out_fast node T_95 = and(rising, io.out_slow.ready) node T_96 = and(T_95, out_slow_val) tohost_q.io.deq.ready := T_96 when held : in_slow_rdy := fromhost_q.io.enq.ready out_slow_val := tohost_q.io.deq.valid node T_97 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) out_slow_bits := T_97 skip io.in_slow.ready := in_slow_rdy io.out_slow.valid := out_slow_val io.out_slow.bits := out_slow_bits io.clk_slow := myclock module Uncore : input clock : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[1], flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.mmio.r.ready := UInt<1>("h00") io.mmio.ar.bits.user := UInt<1>("h00") io.mmio.ar.bits.id := UInt<1>("h00") io.mmio.ar.bits.region := UInt<1>("h00") io.mmio.ar.bits.qos := UInt<1>("h00") io.mmio.ar.bits.prot := UInt<1>("h00") io.mmio.ar.bits.cache := UInt<1>("h00") io.mmio.ar.bits.lock := UInt<1>("h00") io.mmio.ar.bits.burst := UInt<1>("h00") io.mmio.ar.bits.size := UInt<1>("h00") io.mmio.ar.bits.len := UInt<1>("h00") io.mmio.ar.bits.addr := UInt<1>("h00") io.mmio.ar.valid := UInt<1>("h00") io.mmio.b.ready := UInt<1>("h00") io.mmio.w.bits.user := UInt<1>("h00") io.mmio.w.bits.strb := UInt<1>("h00") io.mmio.w.bits.last := UInt<1>("h00") io.mmio.w.bits.data := UInt<1>("h00") io.mmio.w.valid := UInt<1>("h00") io.mmio.aw.bits.user := UInt<1>("h00") io.mmio.aw.bits.id := UInt<1>("h00") io.mmio.aw.bits.region := UInt<1>("h00") io.mmio.aw.bits.qos := UInt<1>("h00") io.mmio.aw.bits.prot := UInt<1>("h00") io.mmio.aw.bits.cache := UInt<1>("h00") io.mmio.aw.bits.lock := UInt<1>("h00") io.mmio.aw.bits.burst := UInt<1>("h00") io.mmio.aw.bits.size := UInt<1>("h00") io.mmio.aw.bits.len := UInt<1>("h00") io.mmio.aw.bits.addr := UInt<1>("h00") io.mmio.aw.valid := UInt<1>("h00") io.mem_backup_ctrl.out_valid := UInt<1>("h00") io.htif[0].ipi_rep.bits := UInt<1>("h00") io.htif[0].ipi_rep.valid := UInt<1>("h00") io.htif[0].ipi_req.ready := UInt<1>("h00") io.htif[0].pcr.resp.ready := UInt<1>("h00") io.htif[0].pcr.req.bits.data := UInt<1>("h00") io.htif[0].pcr.req.bits.addr := UInt<1>("h00") io.htif[0].pcr.req.bits.rw := UInt<1>("h00") io.htif[0].pcr.req.valid := UInt<1>("h00") io.htif[0].id := UInt<1>("h00") io.htif[0].reset := UInt<1>("h00") io.tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") io.tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") io.tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") io.tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") io.tiles_uncached[0].grant.bits.data := UInt<1>("h00") io.tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") io.tiles_uncached[0].grant.valid := UInt<1>("h00") io.tiles_uncached[0].acquire.ready := UInt<1>("h00") io.tiles_cached[0].release.ready := UInt<1>("h00") io.tiles_cached[0].probe.bits.p_type := UInt<1>("h00") io.tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") io.tiles_cached[0].probe.valid := UInt<1>("h00") io.tiles_cached[0].grant.bits.g_type := UInt<1>("h00") io.tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") io.tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") io.tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") io.tiles_cached[0].grant.bits.data := UInt<1>("h00") io.tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") io.tiles_cached[0].grant.valid := UInt<1>("h00") io.tiles_cached[0].acquire.ready := UInt<1>("h00") io.mem[0].r.ready := UInt<1>("h00") io.mem[0].ar.bits.user := UInt<1>("h00") io.mem[0].ar.bits.id := UInt<1>("h00") io.mem[0].ar.bits.region := UInt<1>("h00") io.mem[0].ar.bits.qos := UInt<1>("h00") io.mem[0].ar.bits.prot := UInt<1>("h00") io.mem[0].ar.bits.cache := UInt<1>("h00") io.mem[0].ar.bits.lock := UInt<1>("h00") io.mem[0].ar.bits.burst := UInt<1>("h00") io.mem[0].ar.bits.size := UInt<1>("h00") io.mem[0].ar.bits.len := UInt<1>("h00") io.mem[0].ar.bits.addr := UInt<1>("h00") io.mem[0].ar.valid := UInt<1>("h00") io.mem[0].b.ready := UInt<1>("h00") io.mem[0].w.bits.user := UInt<1>("h00") io.mem[0].w.bits.strb := UInt<1>("h00") io.mem[0].w.bits.last := UInt<1>("h00") io.mem[0].w.bits.data := UInt<1>("h00") io.mem[0].w.valid := UInt<1>("h00") io.mem[0].aw.bits.user := UInt<1>("h00") io.mem[0].aw.bits.id := UInt<1>("h00") io.mem[0].aw.bits.region := UInt<1>("h00") io.mem[0].aw.bits.qos := UInt<1>("h00") io.mem[0].aw.bits.prot := UInt<1>("h00") io.mem[0].aw.bits.cache := UInt<1>("h00") io.mem[0].aw.bits.lock := UInt<1>("h00") io.mem[0].aw.bits.burst := UInt<1>("h00") io.mem[0].aw.bits.size := UInt<1>("h00") io.mem[0].aw.bits.len := UInt<1>("h00") io.mem[0].aw.bits.addr := UInt<1>("h00") io.mem[0].aw.valid := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.out.bits := UInt<1>("h00") io.host.out.valid := UInt<1>("h00") io.host.in.ready := UInt<1>("h00") io.host.clk_edge := UInt<1>("h00") io.host.clk := UInt<1>("h00") inst htif of HTIF htif.io.scr.resp.bits := UInt<1>("h00") htif.io.scr.resp.valid := UInt<1>("h00") htif.io.scr.req.ready := UInt<1>("h00") htif.io.mem.grant.bits.g_type := UInt<1>("h00") htif.io.mem.grant.bits.is_builtin_type := UInt<1>("h00") htif.io.mem.grant.bits.manager_xact_id := UInt<1>("h00") htif.io.mem.grant.bits.client_xact_id := UInt<1>("h00") htif.io.mem.grant.bits.data := UInt<1>("h00") htif.io.mem.grant.bits.addr_beat := UInt<1>("h00") htif.io.mem.grant.valid := UInt<1>("h00") htif.io.mem.acquire.ready := UInt<1>("h00") htif.io.cpu[0].debug_stats_pcr := UInt<1>("h00") htif.io.cpu[0].ipi_rep.ready := UInt<1>("h00") htif.io.cpu[0].ipi_req.bits := UInt<1>("h00") htif.io.cpu[0].ipi_req.valid := UInt<1>("h00") htif.io.cpu[0].pcr.resp.bits := UInt<1>("h00") htif.io.cpu[0].pcr.resp.valid := UInt<1>("h00") htif.io.cpu[0].pcr.req.ready := UInt<1>("h00") htif.io.host.out.ready := UInt<1>("h00") htif.io.host.in.bits := UInt<1>("h00") htif.io.host.in.valid := UInt<1>("h00") htif.clock := clock htif.reset := reset inst outmemsys of OuterMemorySystem outmemsys.io.mmio.r.bits.user := UInt<1>("h00") outmemsys.io.mmio.r.bits.id := UInt<1>("h00") outmemsys.io.mmio.r.bits.last := UInt<1>("h00") outmemsys.io.mmio.r.bits.data := UInt<1>("h00") outmemsys.io.mmio.r.bits.resp := UInt<1>("h00") outmemsys.io.mmio.r.valid := UInt<1>("h00") outmemsys.io.mmio.ar.ready := UInt<1>("h00") outmemsys.io.mmio.b.bits.user := UInt<1>("h00") outmemsys.io.mmio.b.bits.id := UInt<1>("h00") outmemsys.io.mmio.b.bits.resp := UInt<1>("h00") outmemsys.io.mmio.b.valid := UInt<1>("h00") outmemsys.io.mmio.w.ready := UInt<1>("h00") outmemsys.io.mmio.aw.ready := UInt<1>("h00") outmemsys.io.scr.resp.bits := UInt<1>("h00") outmemsys.io.scr.resp.valid := UInt<1>("h00") outmemsys.io.scr.req.ready := UInt<1>("h00") outmemsys.io.pcr[0].resp.bits := UInt<1>("h00") outmemsys.io.pcr[0].resp.valid := UInt<1>("h00") outmemsys.io.pcr[0].req.ready := UInt<1>("h00") outmemsys.io.mem_backup_en := UInt<1>("h00") outmemsys.io.mem_backup.resp.bits := UInt<1>("h00") outmemsys.io.mem_backup.resp.valid := UInt<1>("h00") outmemsys.io.mem_backup.req.ready := UInt<1>("h00") outmemsys.io.mem[0].r.bits.user := UInt<1>("h00") outmemsys.io.mem[0].r.bits.id := UInt<1>("h00") outmemsys.io.mem[0].r.bits.last := UInt<1>("h00") outmemsys.io.mem[0].r.bits.data := UInt<1>("h00") outmemsys.io.mem[0].r.bits.resp := UInt<1>("h00") outmemsys.io.mem[0].r.valid := UInt<1>("h00") outmemsys.io.mem[0].ar.ready := UInt<1>("h00") outmemsys.io.mem[0].b.bits.user := UInt<1>("h00") outmemsys.io.mem[0].b.bits.id := UInt<1>("h00") outmemsys.io.mem[0].b.bits.resp := UInt<1>("h00") outmemsys.io.mem[0].b.valid := UInt<1>("h00") outmemsys.io.mem[0].w.ready := UInt<1>("h00") outmemsys.io.mem[0].aw.ready := UInt<1>("h00") outmemsys.io.incoherent[0] := UInt<1>("h00") outmemsys.io.htif_uncached.grant.ready := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.union := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.a_type := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.is_builtin_type := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.data := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.addr_beat := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.client_xact_id := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.addr_block := UInt<1>("h00") outmemsys.io.htif_uncached.acquire.valid := UInt<1>("h00") outmemsys.io.tiles_uncached[0].grant.ready := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.valid := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.r_type := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.data := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") outmemsys.io.tiles_cached[0].release.valid := UInt<1>("h00") outmemsys.io.tiles_cached[0].probe.ready := UInt<1>("h00") outmemsys.io.tiles_cached[0].grant.ready := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.union := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.data := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.valid := UInt<1>("h00") outmemsys.clock := clock outmemsys.reset := reset outmemsys.io.incoherent[0] := htif.io.cpu[0].reset outmemsys.io.htif_uncached <> htif.io.mem outmemsys.io.tiles_uncached <> io.tiles_uncached outmemsys.io.tiles_cached <> io.tiles_cached io.htif[0].reset := htif.io.cpu[0].reset io.htif[0].id := htif.io.cpu[0].id htif.io.cpu[0].ipi_req <> io.htif[0].ipi_req io.htif[0].ipi_rep <> htif.io.cpu[0].ipi_rep htif.io.cpu[0].debug_stats_pcr := io.htif[0].debug_stats_pcr inst T_7802 of SMIArbiter T_7802.io.out.resp.bits := UInt<1>("h00") T_7802.io.out.resp.valid := UInt<1>("h00") T_7802.io.out.req.ready := UInt<1>("h00") T_7802.io.in[0].resp.ready := UInt<1>("h00") T_7802.io.in[0].req.bits.data := UInt<1>("h00") T_7802.io.in[0].req.bits.addr := UInt<1>("h00") T_7802.io.in[0].req.bits.rw := UInt<1>("h00") T_7802.io.in[0].req.valid := UInt<1>("h00") T_7802.io.in[1].resp.ready := UInt<1>("h00") T_7802.io.in[1].req.bits.data := UInt<1>("h00") T_7802.io.in[1].req.bits.addr := UInt<1>("h00") T_7802.io.in[1].req.bits.rw := UInt<1>("h00") T_7802.io.in[1].req.valid := UInt<1>("h00") T_7802.clock := clock T_7802.reset := reset T_7802.io.in[0] <> htif.io.cpu[0].pcr T_7802.io.in[1] <> outmemsys.io.pcr[0] io.htif[0].pcr <> T_7802.io.out inst scrArb of SMIArbiter_70 scrArb.io.out.resp.bits := UInt<1>("h00") scrArb.io.out.resp.valid := UInt<1>("h00") scrArb.io.out.req.ready := UInt<1>("h00") scrArb.io.in[0].resp.ready := UInt<1>("h00") scrArb.io.in[0].req.bits.data := UInt<1>("h00") scrArb.io.in[0].req.bits.addr := UInt<1>("h00") scrArb.io.in[0].req.bits.rw := UInt<1>("h00") scrArb.io.in[0].req.valid := UInt<1>("h00") scrArb.io.in[1].resp.ready := UInt<1>("h00") scrArb.io.in[1].req.bits.data := UInt<1>("h00") scrArb.io.in[1].req.bits.addr := UInt<1>("h00") scrArb.io.in[1].req.bits.rw := UInt<1>("h00") scrArb.io.in[1].req.valid := UInt<1>("h00") scrArb.clock := clock scrArb.reset := reset inst scrFile of SCRFile scrFile.io.scr.rdata[0] := UInt<1>("h00") scrFile.io.scr.rdata[1] := UInt<1>("h00") scrFile.io.scr.rdata[2] := UInt<1>("h00") scrFile.io.scr.rdata[3] := UInt<1>("h00") scrFile.io.scr.rdata[4] := UInt<1>("h00") scrFile.io.scr.rdata[5] := UInt<1>("h00") scrFile.io.scr.rdata[6] := UInt<1>("h00") scrFile.io.scr.rdata[7] := UInt<1>("h00") scrFile.io.scr.rdata[8] := UInt<1>("h00") scrFile.io.scr.rdata[9] := UInt<1>("h00") scrFile.io.scr.rdata[10] := UInt<1>("h00") scrFile.io.scr.rdata[11] := UInt<1>("h00") scrFile.io.scr.rdata[12] := UInt<1>("h00") scrFile.io.scr.rdata[13] := UInt<1>("h00") scrFile.io.scr.rdata[14] := UInt<1>("h00") scrFile.io.scr.rdata[15] := UInt<1>("h00") scrFile.io.scr.rdata[16] := UInt<1>("h00") scrFile.io.scr.rdata[17] := UInt<1>("h00") scrFile.io.scr.rdata[18] := UInt<1>("h00") scrFile.io.scr.rdata[19] := UInt<1>("h00") scrFile.io.scr.rdata[20] := UInt<1>("h00") scrFile.io.scr.rdata[21] := UInt<1>("h00") scrFile.io.scr.rdata[22] := UInt<1>("h00") scrFile.io.scr.rdata[23] := UInt<1>("h00") scrFile.io.scr.rdata[24] := UInt<1>("h00") scrFile.io.scr.rdata[25] := UInt<1>("h00") scrFile.io.scr.rdata[26] := UInt<1>("h00") scrFile.io.scr.rdata[27] := UInt<1>("h00") scrFile.io.scr.rdata[28] := UInt<1>("h00") scrFile.io.scr.rdata[29] := UInt<1>("h00") scrFile.io.scr.rdata[30] := UInt<1>("h00") scrFile.io.scr.rdata[31] := UInt<1>("h00") scrFile.io.scr.rdata[32] := UInt<1>("h00") scrFile.io.scr.rdata[33] := UInt<1>("h00") scrFile.io.scr.rdata[34] := UInt<1>("h00") scrFile.io.scr.rdata[35] := UInt<1>("h00") scrFile.io.scr.rdata[36] := UInt<1>("h00") scrFile.io.scr.rdata[37] := UInt<1>("h00") scrFile.io.scr.rdata[38] := UInt<1>("h00") scrFile.io.scr.rdata[39] := UInt<1>("h00") scrFile.io.scr.rdata[40] := UInt<1>("h00") scrFile.io.scr.rdata[41] := UInt<1>("h00") scrFile.io.scr.rdata[42] := UInt<1>("h00") scrFile.io.scr.rdata[43] := UInt<1>("h00") scrFile.io.scr.rdata[44] := UInt<1>("h00") scrFile.io.scr.rdata[45] := UInt<1>("h00") scrFile.io.scr.rdata[46] := UInt<1>("h00") scrFile.io.scr.rdata[47] := UInt<1>("h00") scrFile.io.scr.rdata[48] := UInt<1>("h00") scrFile.io.scr.rdata[49] := UInt<1>("h00") scrFile.io.scr.rdata[50] := UInt<1>("h00") scrFile.io.scr.rdata[51] := UInt<1>("h00") scrFile.io.scr.rdata[52] := UInt<1>("h00") scrFile.io.scr.rdata[53] := UInt<1>("h00") scrFile.io.scr.rdata[54] := UInt<1>("h00") scrFile.io.scr.rdata[55] := UInt<1>("h00") scrFile.io.scr.rdata[56] := UInt<1>("h00") scrFile.io.scr.rdata[57] := UInt<1>("h00") scrFile.io.scr.rdata[58] := UInt<1>("h00") scrFile.io.scr.rdata[59] := UInt<1>("h00") scrFile.io.scr.rdata[60] := UInt<1>("h00") scrFile.io.scr.rdata[61] := UInt<1>("h00") scrFile.io.scr.rdata[62] := UInt<1>("h00") scrFile.io.scr.rdata[63] := UInt<1>("h00") scrFile.io.smi.resp.ready := UInt<1>("h00") scrFile.io.smi.req.bits.data := UInt<1>("h00") scrFile.io.smi.req.bits.addr := UInt<1>("h00") scrFile.io.smi.req.bits.rw := UInt<1>("h00") scrFile.io.smi.req.valid := UInt<1>("h00") scrFile.clock := clock scrFile.reset := reset scrArb.io.in[0] <> htif.io.scr scrArb.io.in[1] <> outmemsys.io.scr scrFile.io.smi <> scrArb.io.out io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr io.mem <> outmemsys.io.mem io.mmio <> outmemsys.io.mmio outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en inst T_7900 of SlowIO T_7900.io.set_divisor.bits := UInt<1>("h00") T_7900.io.set_divisor.valid := UInt<1>("h00") T_7900.io.in_slow.bits := UInt<1>("h00") T_7900.io.in_slow.valid := UInt<1>("h00") T_7900.io.in_fast.ready := UInt<1>("h00") T_7900.io.out_slow.ready := UInt<1>("h00") T_7900.io.out_fast.bits := UInt<1>("h00") T_7900.io.out_fast.valid := UInt<1>("h00") T_7900.clock := clock T_7900.reset := reset node T_7910 = eq(scrFile.io.scr.waddr, UInt<6>("h03f")) node T_7911 = and(scrFile.io.scr.wen, T_7910) T_7900.io.set_divisor.valid := T_7911 T_7900.io.set_divisor.bits := scrFile.io.scr.wdata scrFile.io.scr.rdata[63] := T_7900.io.divisor node T_7912 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) T_7900.io.out_fast.valid := T_7912 node T_7913 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) node T_7914 = cat(htif.io.host.out.valid, T_7913) T_7900.io.out_fast.bits := T_7914 htif.io.host.out.ready := T_7900.io.out_fast.ready node T_7916 = eq(htif.io.host.out.valid, UInt<1>("h00")) node T_7917 = and(T_7900.io.out_fast.ready, T_7916) outmemsys.io.mem_backup.req.ready := T_7917 node T_7918 = bit(T_7900.io.out_slow.bits, 16) node T_7919 = and(T_7900.io.out_slow.valid, T_7918) io.host.out.valid := T_7919 io.host.out.bits := T_7900.io.out_slow.bits node T_7920 = bit(T_7900.io.out_slow.bits, 16) node T_7922 = eq(T_7920, UInt<1>("h00")) node T_7923 = and(T_7900.io.out_slow.valid, T_7922) io.mem_backup_ctrl.out_valid := T_7923 node T_7924 = bit(T_7900.io.out_slow.bits, 16) node T_7925 = mux(T_7924, io.host.out.ready, io.mem_backup_ctrl.out_ready) T_7900.io.out_slow.ready := T_7925 node T_7926 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) node T_7927 = or(T_7926, io.host.in.valid) T_7900.io.in_slow.valid := T_7927 node T_7928 = cat(T_7926, io.host.in.bits) T_7900.io.in_slow.bits := T_7928 io.host.in.ready := T_7900.io.in_slow.ready node T_7929 = bit(T_7900.io.in_fast.bits, 16) node T_7930 = and(T_7900.io.in_fast.valid, T_7929) outmemsys.io.mem_backup.resp.valid := T_7930 outmemsys.io.mem_backup.resp.bits := T_7900.io.in_fast.bits node T_7931 = bit(T_7900.io.in_fast.bits, 16) node T_7933 = eq(T_7931, UInt<1>("h00")) node T_7934 = and(T_7900.io.in_fast.valid, T_7933) htif.io.host.in.valid := T_7934 htif.io.host.in.bits := T_7900.io.in_fast.bits node T_7935 = bit(T_7900.io.in_fast.bits, 16) node T_7937 = mux(T_7935, UInt<1>("h01"), htif.io.host.in.ready) T_7900.io.in_fast.ready := T_7937 io.host.clk := T_7900.io.clk_slow reg T_7938 : UInt<1>, clock, reset T_7938 := io.host.clk node T_7940 = eq(T_7938, UInt<1>("h00")) node T_7941 = and(io.host.clk, T_7940) reg T_7942 : UInt<1>, clock, reset T_7942 := T_7941 io.host.clk_edge := T_7942 module BTB : input clock : Clock input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>} io.resp.bits.bht.value := UInt<1>("h00") io.resp.bits.bht.history := UInt<1>("h00") io.resp.bits.entry := UInt<1>("h00") io.resp.bits.target := UInt<1>("h00") io.resp.bits.bridx := UInt<1>("h00") io.resp.bits.mask := UInt<1>("h00") io.resp.bits.taken := UInt<1>("h00") io.resp.valid := UInt<1>("h00") reg idxValid : UInt<62>, clock, reset onreset idxValid := UInt<62>("h00") cmem idxs : UInt<12>[62], clock cmem idxPages : UInt<3>[62], clock cmem tgts : UInt<12>[62], clock cmem tgtPages : UInt<3>[62], clock cmem pages : UInt<27>[6], clock reg pageValid : UInt<6>, clock, reset onreset pageValid := UInt<6>("h00") infer accessor T_590 = idxPages[UInt<1>("h00")] node T_592 = dshl(UInt<1>("h01"), T_590) node T_593 = bits(T_592, 5, 0) infer accessor T_595 = idxPages[UInt<1>("h01")] node T_597 = dshl(UInt<1>("h01"), T_595) node T_598 = bits(T_597, 5, 0) infer accessor T_600 = idxPages[UInt<2>("h02")] node T_602 = dshl(UInt<1>("h01"), T_600) node T_603 = bits(T_602, 5, 0) infer accessor T_605 = idxPages[UInt<2>("h03")] node T_607 = dshl(UInt<1>("h01"), T_605) node T_608 = bits(T_607, 5, 0) infer accessor T_610 = idxPages[UInt<3>("h04")] node T_612 = dshl(UInt<1>("h01"), T_610) node T_613 = bits(T_612, 5, 0) infer accessor T_615 = idxPages[UInt<3>("h05")] node T_617 = dshl(UInt<1>("h01"), T_615) node T_618 = bits(T_617, 5, 0) infer accessor T_620 = idxPages[UInt<3>("h06")] node T_622 = dshl(UInt<1>("h01"), T_620) node T_623 = bits(T_622, 5, 0) infer accessor T_625 = idxPages[UInt<3>("h07")] node T_627 = dshl(UInt<1>("h01"), T_625) node T_628 = bits(T_627, 5, 0) infer accessor T_630 = idxPages[UInt<4>("h08")] node T_632 = dshl(UInt<1>("h01"), T_630) node T_633 = bits(T_632, 5, 0) infer accessor T_635 = idxPages[UInt<4>("h09")] node T_637 = dshl(UInt<1>("h01"), T_635) node T_638 = bits(T_637, 5, 0) infer accessor T_640 = idxPages[UInt<4>("h0a")] node T_642 = dshl(UInt<1>("h01"), T_640) node T_643 = bits(T_642, 5, 0) infer accessor T_645 = idxPages[UInt<4>("h0b")] node T_647 = dshl(UInt<1>("h01"), T_645) node T_648 = bits(T_647, 5, 0) infer accessor T_650 = idxPages[UInt<4>("h0c")] node T_652 = dshl(UInt<1>("h01"), T_650) node T_653 = bits(T_652, 5, 0) infer accessor T_655 = idxPages[UInt<4>("h0d")] node T_657 = dshl(UInt<1>("h01"), T_655) node T_658 = bits(T_657, 5, 0) infer accessor T_660 = idxPages[UInt<4>("h0e")] node T_662 = dshl(UInt<1>("h01"), T_660) node T_663 = bits(T_662, 5, 0) infer accessor T_665 = idxPages[UInt<4>("h0f")] node T_667 = dshl(UInt<1>("h01"), T_665) node T_668 = bits(T_667, 5, 0) infer accessor T_670 = idxPages[UInt<5>("h010")] node T_672 = dshl(UInt<1>("h01"), T_670) node T_673 = bits(T_672, 5, 0) infer accessor T_675 = idxPages[UInt<5>("h011")] node T_677 = dshl(UInt<1>("h01"), T_675) node T_678 = bits(T_677, 5, 0) infer accessor T_680 = idxPages[UInt<5>("h012")] node T_682 = dshl(UInt<1>("h01"), T_680) node T_683 = bits(T_682, 5, 0) infer accessor T_685 = idxPages[UInt<5>("h013")] node T_687 = dshl(UInt<1>("h01"), T_685) node T_688 = bits(T_687, 5, 0) infer accessor T_690 = idxPages[UInt<5>("h014")] node T_692 = dshl(UInt<1>("h01"), T_690) node T_693 = bits(T_692, 5, 0) infer accessor T_695 = idxPages[UInt<5>("h015")] node T_697 = dshl(UInt<1>("h01"), T_695) node T_698 = bits(T_697, 5, 0) infer accessor T_700 = idxPages[UInt<5>("h016")] node T_702 = dshl(UInt<1>("h01"), T_700) node T_703 = bits(T_702, 5, 0) infer accessor T_705 = idxPages[UInt<5>("h017")] node T_707 = dshl(UInt<1>("h01"), T_705) node T_708 = bits(T_707, 5, 0) infer accessor T_710 = idxPages[UInt<5>("h018")] node T_712 = dshl(UInt<1>("h01"), T_710) node T_713 = bits(T_712, 5, 0) infer accessor T_715 = idxPages[UInt<5>("h019")] node T_717 = dshl(UInt<1>("h01"), T_715) node T_718 = bits(T_717, 5, 0) infer accessor T_720 = idxPages[UInt<5>("h01a")] node T_722 = dshl(UInt<1>("h01"), T_720) node T_723 = bits(T_722, 5, 0) infer accessor T_725 = idxPages[UInt<5>("h01b")] node T_727 = dshl(UInt<1>("h01"), T_725) node T_728 = bits(T_727, 5, 0) infer accessor T_730 = idxPages[UInt<5>("h01c")] node T_732 = dshl(UInt<1>("h01"), T_730) node T_733 = bits(T_732, 5, 0) infer accessor T_735 = idxPages[UInt<5>("h01d")] node T_737 = dshl(UInt<1>("h01"), T_735) node T_738 = bits(T_737, 5, 0) infer accessor T_740 = idxPages[UInt<5>("h01e")] node T_742 = dshl(UInt<1>("h01"), T_740) node T_743 = bits(T_742, 5, 0) infer accessor T_745 = idxPages[UInt<5>("h01f")] node T_747 = dshl(UInt<1>("h01"), T_745) node T_748 = bits(T_747, 5, 0) infer accessor T_750 = idxPages[UInt<6>("h020")] node T_752 = dshl(UInt<1>("h01"), T_750) node T_753 = bits(T_752, 5, 0) infer accessor T_755 = idxPages[UInt<6>("h021")] node T_757 = dshl(UInt<1>("h01"), T_755) node T_758 = bits(T_757, 5, 0) infer accessor T_760 = idxPages[UInt<6>("h022")] node T_762 = dshl(UInt<1>("h01"), T_760) node T_763 = bits(T_762, 5, 0) infer accessor T_765 = idxPages[UInt<6>("h023")] node T_767 = dshl(UInt<1>("h01"), T_765) node T_768 = bits(T_767, 5, 0) infer accessor T_770 = idxPages[UInt<6>("h024")] node T_772 = dshl(UInt<1>("h01"), T_770) node T_773 = bits(T_772, 5, 0) infer accessor T_775 = idxPages[UInt<6>("h025")] node T_777 = dshl(UInt<1>("h01"), T_775) node T_778 = bits(T_777, 5, 0) infer accessor T_780 = idxPages[UInt<6>("h026")] node T_782 = dshl(UInt<1>("h01"), T_780) node T_783 = bits(T_782, 5, 0) infer accessor T_785 = idxPages[UInt<6>("h027")] node T_787 = dshl(UInt<1>("h01"), T_785) node T_788 = bits(T_787, 5, 0) infer accessor T_790 = idxPages[UInt<6>("h028")] node T_792 = dshl(UInt<1>("h01"), T_790) node T_793 = bits(T_792, 5, 0) infer accessor T_795 = idxPages[UInt<6>("h029")] node T_797 = dshl(UInt<1>("h01"), T_795) node T_798 = bits(T_797, 5, 0) infer accessor T_800 = idxPages[UInt<6>("h02a")] node T_802 = dshl(UInt<1>("h01"), T_800) node T_803 = bits(T_802, 5, 0) infer accessor T_805 = idxPages[UInt<6>("h02b")] node T_807 = dshl(UInt<1>("h01"), T_805) node T_808 = bits(T_807, 5, 0) infer accessor T_810 = idxPages[UInt<6>("h02c")] node T_812 = dshl(UInt<1>("h01"), T_810) node T_813 = bits(T_812, 5, 0) infer accessor T_815 = idxPages[UInt<6>("h02d")] node T_817 = dshl(UInt<1>("h01"), T_815) node T_818 = bits(T_817, 5, 0) infer accessor T_820 = idxPages[UInt<6>("h02e")] node T_822 = dshl(UInt<1>("h01"), T_820) node T_823 = bits(T_822, 5, 0) infer accessor T_825 = idxPages[UInt<6>("h02f")] node T_827 = dshl(UInt<1>("h01"), T_825) node T_828 = bits(T_827, 5, 0) infer accessor T_830 = idxPages[UInt<6>("h030")] node T_832 = dshl(UInt<1>("h01"), T_830) node T_833 = bits(T_832, 5, 0) infer accessor T_835 = idxPages[UInt<6>("h031")] node T_837 = dshl(UInt<1>("h01"), T_835) node T_838 = bits(T_837, 5, 0) infer accessor T_840 = idxPages[UInt<6>("h032")] node T_842 = dshl(UInt<1>("h01"), T_840) node T_843 = bits(T_842, 5, 0) infer accessor T_845 = idxPages[UInt<6>("h033")] node T_847 = dshl(UInt<1>("h01"), T_845) node T_848 = bits(T_847, 5, 0) infer accessor T_850 = idxPages[UInt<6>("h034")] node T_852 = dshl(UInt<1>("h01"), T_850) node T_853 = bits(T_852, 5, 0) infer accessor T_855 = idxPages[UInt<6>("h035")] node T_857 = dshl(UInt<1>("h01"), T_855) node T_858 = bits(T_857, 5, 0) infer accessor T_860 = idxPages[UInt<6>("h036")] node T_862 = dshl(UInt<1>("h01"), T_860) node T_863 = bits(T_862, 5, 0) infer accessor T_865 = idxPages[UInt<6>("h037")] node T_867 = dshl(UInt<1>("h01"), T_865) node T_868 = bits(T_867, 5, 0) infer accessor T_870 = idxPages[UInt<6>("h038")] node T_872 = dshl(UInt<1>("h01"), T_870) node T_873 = bits(T_872, 5, 0) infer accessor T_875 = idxPages[UInt<6>("h039")] node T_877 = dshl(UInt<1>("h01"), T_875) node T_878 = bits(T_877, 5, 0) infer accessor T_880 = idxPages[UInt<6>("h03a")] node T_882 = dshl(UInt<1>("h01"), T_880) node T_883 = bits(T_882, 5, 0) infer accessor T_885 = idxPages[UInt<6>("h03b")] node T_887 = dshl(UInt<1>("h01"), T_885) node T_888 = bits(T_887, 5, 0) infer accessor T_890 = idxPages[UInt<6>("h03c")] node T_892 = dshl(UInt<1>("h01"), T_890) node T_893 = bits(T_892, 5, 0) infer accessor T_895 = idxPages[UInt<6>("h03d")] node T_897 = dshl(UInt<1>("h01"), T_895) node T_898 = bits(T_897, 5, 0) infer accessor T_900 = tgtPages[UInt<1>("h00")] node T_902 = dshl(UInt<1>("h01"), T_900) node T_903 = bits(T_902, 5, 0) infer accessor T_905 = tgtPages[UInt<1>("h01")] node T_907 = dshl(UInt<1>("h01"), T_905) node T_908 = bits(T_907, 5, 0) infer accessor T_910 = tgtPages[UInt<2>("h02")] node T_912 = dshl(UInt<1>("h01"), T_910) node T_913 = bits(T_912, 5, 0) infer accessor T_915 = tgtPages[UInt<2>("h03")] node T_917 = dshl(UInt<1>("h01"), T_915) node T_918 = bits(T_917, 5, 0) infer accessor T_920 = tgtPages[UInt<3>("h04")] node T_922 = dshl(UInt<1>("h01"), T_920) node T_923 = bits(T_922, 5, 0) infer accessor T_925 = tgtPages[UInt<3>("h05")] node T_927 = dshl(UInt<1>("h01"), T_925) node T_928 = bits(T_927, 5, 0) infer accessor T_930 = tgtPages[UInt<3>("h06")] node T_932 = dshl(UInt<1>("h01"), T_930) node T_933 = bits(T_932, 5, 0) infer accessor T_935 = tgtPages[UInt<3>("h07")] node T_937 = dshl(UInt<1>("h01"), T_935) node T_938 = bits(T_937, 5, 0) infer accessor T_940 = tgtPages[UInt<4>("h08")] node T_942 = dshl(UInt<1>("h01"), T_940) node T_943 = bits(T_942, 5, 0) infer accessor T_945 = tgtPages[UInt<4>("h09")] node T_947 = dshl(UInt<1>("h01"), T_945) node T_948 = bits(T_947, 5, 0) infer accessor T_950 = tgtPages[UInt<4>("h0a")] node T_952 = dshl(UInt<1>("h01"), T_950) node T_953 = bits(T_952, 5, 0) infer accessor T_955 = tgtPages[UInt<4>("h0b")] node T_957 = dshl(UInt<1>("h01"), T_955) node T_958 = bits(T_957, 5, 0) infer accessor T_960 = tgtPages[UInt<4>("h0c")] node T_962 = dshl(UInt<1>("h01"), T_960) node T_963 = bits(T_962, 5, 0) infer accessor T_965 = tgtPages[UInt<4>("h0d")] node T_967 = dshl(UInt<1>("h01"), T_965) node T_968 = bits(T_967, 5, 0) infer accessor T_970 = tgtPages[UInt<4>("h0e")] node T_972 = dshl(UInt<1>("h01"), T_970) node T_973 = bits(T_972, 5, 0) infer accessor T_975 = tgtPages[UInt<4>("h0f")] node T_977 = dshl(UInt<1>("h01"), T_975) node T_978 = bits(T_977, 5, 0) infer accessor T_980 = tgtPages[UInt<5>("h010")] node T_982 = dshl(UInt<1>("h01"), T_980) node T_983 = bits(T_982, 5, 0) infer accessor T_985 = tgtPages[UInt<5>("h011")] node T_987 = dshl(UInt<1>("h01"), T_985) node T_988 = bits(T_987, 5, 0) infer accessor T_990 = tgtPages[UInt<5>("h012")] node T_992 = dshl(UInt<1>("h01"), T_990) node T_993 = bits(T_992, 5, 0) infer accessor T_995 = tgtPages[UInt<5>("h013")] node T_997 = dshl(UInt<1>("h01"), T_995) node T_998 = bits(T_997, 5, 0) infer accessor T_1000 = tgtPages[UInt<5>("h014")] node T_1002 = dshl(UInt<1>("h01"), T_1000) node T_1003 = bits(T_1002, 5, 0) infer accessor T_1005 = tgtPages[UInt<5>("h015")] node T_1007 = dshl(UInt<1>("h01"), T_1005) node T_1008 = bits(T_1007, 5, 0) infer accessor T_1010 = tgtPages[UInt<5>("h016")] node T_1012 = dshl(UInt<1>("h01"), T_1010) node T_1013 = bits(T_1012, 5, 0) infer accessor T_1015 = tgtPages[UInt<5>("h017")] node T_1017 = dshl(UInt<1>("h01"), T_1015) node T_1018 = bits(T_1017, 5, 0) infer accessor T_1020 = tgtPages[UInt<5>("h018")] node T_1022 = dshl(UInt<1>("h01"), T_1020) node T_1023 = bits(T_1022, 5, 0) infer accessor T_1025 = tgtPages[UInt<5>("h019")] node T_1027 = dshl(UInt<1>("h01"), T_1025) node T_1028 = bits(T_1027, 5, 0) infer accessor T_1030 = tgtPages[UInt<5>("h01a")] node T_1032 = dshl(UInt<1>("h01"), T_1030) node T_1033 = bits(T_1032, 5, 0) infer accessor T_1035 = tgtPages[UInt<5>("h01b")] node T_1037 = dshl(UInt<1>("h01"), T_1035) node T_1038 = bits(T_1037, 5, 0) infer accessor T_1040 = tgtPages[UInt<5>("h01c")] node T_1042 = dshl(UInt<1>("h01"), T_1040) node T_1043 = bits(T_1042, 5, 0) infer accessor T_1045 = tgtPages[UInt<5>("h01d")] node T_1047 = dshl(UInt<1>("h01"), T_1045) node T_1048 = bits(T_1047, 5, 0) infer accessor T_1050 = tgtPages[UInt<5>("h01e")] node T_1052 = dshl(UInt<1>("h01"), T_1050) node T_1053 = bits(T_1052, 5, 0) infer accessor T_1055 = tgtPages[UInt<5>("h01f")] node T_1057 = dshl(UInt<1>("h01"), T_1055) node T_1058 = bits(T_1057, 5, 0) infer accessor T_1060 = tgtPages[UInt<6>("h020")] node T_1062 = dshl(UInt<1>("h01"), T_1060) node T_1063 = bits(T_1062, 5, 0) infer accessor T_1065 = tgtPages[UInt<6>("h021")] node T_1067 = dshl(UInt<1>("h01"), T_1065) node T_1068 = bits(T_1067, 5, 0) infer accessor T_1070 = tgtPages[UInt<6>("h022")] node T_1072 = dshl(UInt<1>("h01"), T_1070) node T_1073 = bits(T_1072, 5, 0) infer accessor T_1075 = tgtPages[UInt<6>("h023")] node T_1077 = dshl(UInt<1>("h01"), T_1075) node T_1078 = bits(T_1077, 5, 0) infer accessor T_1080 = tgtPages[UInt<6>("h024")] node T_1082 = dshl(UInt<1>("h01"), T_1080) node T_1083 = bits(T_1082, 5, 0) infer accessor T_1085 = tgtPages[UInt<6>("h025")] node T_1087 = dshl(UInt<1>("h01"), T_1085) node T_1088 = bits(T_1087, 5, 0) infer accessor T_1090 = tgtPages[UInt<6>("h026")] node T_1092 = dshl(UInt<1>("h01"), T_1090) node T_1093 = bits(T_1092, 5, 0) infer accessor T_1095 = tgtPages[UInt<6>("h027")] node T_1097 = dshl(UInt<1>("h01"), T_1095) node T_1098 = bits(T_1097, 5, 0) infer accessor T_1100 = tgtPages[UInt<6>("h028")] node T_1102 = dshl(UInt<1>("h01"), T_1100) node T_1103 = bits(T_1102, 5, 0) infer accessor T_1105 = tgtPages[UInt<6>("h029")] node T_1107 = dshl(UInt<1>("h01"), T_1105) node T_1108 = bits(T_1107, 5, 0) infer accessor T_1110 = tgtPages[UInt<6>("h02a")] node T_1112 = dshl(UInt<1>("h01"), T_1110) node T_1113 = bits(T_1112, 5, 0) infer accessor T_1115 = tgtPages[UInt<6>("h02b")] node T_1117 = dshl(UInt<1>("h01"), T_1115) node T_1118 = bits(T_1117, 5, 0) infer accessor T_1120 = tgtPages[UInt<6>("h02c")] node T_1122 = dshl(UInt<1>("h01"), T_1120) node T_1123 = bits(T_1122, 5, 0) infer accessor T_1125 = tgtPages[UInt<6>("h02d")] node T_1127 = dshl(UInt<1>("h01"), T_1125) node T_1128 = bits(T_1127, 5, 0) infer accessor T_1130 = tgtPages[UInt<6>("h02e")] node T_1132 = dshl(UInt<1>("h01"), T_1130) node T_1133 = bits(T_1132, 5, 0) infer accessor T_1135 = tgtPages[UInt<6>("h02f")] node T_1137 = dshl(UInt<1>("h01"), T_1135) node T_1138 = bits(T_1137, 5, 0) infer accessor T_1140 = tgtPages[UInt<6>("h030")] node T_1142 = dshl(UInt<1>("h01"), T_1140) node T_1143 = bits(T_1142, 5, 0) infer accessor T_1145 = tgtPages[UInt<6>("h031")] node T_1147 = dshl(UInt<1>("h01"), T_1145) node T_1148 = bits(T_1147, 5, 0) infer accessor T_1150 = tgtPages[UInt<6>("h032")] node T_1152 = dshl(UInt<1>("h01"), T_1150) node T_1153 = bits(T_1152, 5, 0) infer accessor T_1155 = tgtPages[UInt<6>("h033")] node T_1157 = dshl(UInt<1>("h01"), T_1155) node T_1158 = bits(T_1157, 5, 0) infer accessor T_1160 = tgtPages[UInt<6>("h034")] node T_1162 = dshl(UInt<1>("h01"), T_1160) node T_1163 = bits(T_1162, 5, 0) infer accessor T_1165 = tgtPages[UInt<6>("h035")] node T_1167 = dshl(UInt<1>("h01"), T_1165) node T_1168 = bits(T_1167, 5, 0) infer accessor T_1170 = tgtPages[UInt<6>("h036")] node T_1172 = dshl(UInt<1>("h01"), T_1170) node T_1173 = bits(T_1172, 5, 0) infer accessor T_1175 = tgtPages[UInt<6>("h037")] node T_1177 = dshl(UInt<1>("h01"), T_1175) node T_1178 = bits(T_1177, 5, 0) infer accessor T_1180 = tgtPages[UInt<6>("h038")] node T_1182 = dshl(UInt<1>("h01"), T_1180) node T_1183 = bits(T_1182, 5, 0) infer accessor T_1185 = tgtPages[UInt<6>("h039")] node T_1187 = dshl(UInt<1>("h01"), T_1185) node T_1188 = bits(T_1187, 5, 0) infer accessor T_1190 = tgtPages[UInt<6>("h03a")] node T_1192 = dshl(UInt<1>("h01"), T_1190) node T_1193 = bits(T_1192, 5, 0) infer accessor T_1195 = tgtPages[UInt<6>("h03b")] node T_1197 = dshl(UInt<1>("h01"), T_1195) node T_1198 = bits(T_1197, 5, 0) infer accessor T_1200 = tgtPages[UInt<6>("h03c")] node T_1202 = dshl(UInt<1>("h01"), T_1200) node T_1203 = bits(T_1202, 5, 0) infer accessor T_1205 = tgtPages[UInt<6>("h03d")] node T_1207 = dshl(UInt<1>("h01"), T_1205) node T_1208 = bits(T_1207, 5, 0) reg useRAS : UInt<1>[62], clock, reset reg isJump : UInt<1>[62], clock, reset cmem brIdx : UInt<1>[62], clock reg T_1478 : UInt<1>, clock, reset onreset T_1478 := UInt<1>("h00") T_1478 := io.btb_update.valid reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clock, reset when io.btb_update.valid : T_1479 <> io.btb_update.bits skip wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} r_btb_update.bits.br_pc := UInt<1>("h00") r_btb_update.bits.isReturn := UInt<1>("h00") r_btb_update.bits.isJump := UInt<1>("h00") r_btb_update.bits.taken := UInt<1>("h00") r_btb_update.bits.target := UInt<1>("h00") r_btb_update.bits.pc := UInt<1>("h00") r_btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") r_btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") r_btb_update.bits.prediction.bits.entry := UInt<1>("h00") r_btb_update.bits.prediction.bits.target := UInt<1>("h00") r_btb_update.bits.prediction.bits.bridx := UInt<1>("h00") r_btb_update.bits.prediction.bits.mask := UInt<1>("h00") r_btb_update.bits.prediction.bits.taken := UInt<1>("h00") r_btb_update.bits.prediction.valid := UInt<1>("h00") r_btb_update.valid := UInt<1>("h00") r_btb_update.valid := T_1478 r_btb_update.bits <> T_1479 node T_1678 = shr(io.req.bits.addr, 12) infer accessor T_1680 = pages[UInt<1>("h00")] node T_1681 = eq(T_1680, T_1678) infer accessor T_1683 = pages[UInt<1>("h01")] node T_1684 = eq(T_1683, T_1678) infer accessor T_1686 = pages[UInt<2>("h02")] node T_1687 = eq(T_1686, T_1678) infer accessor T_1689 = pages[UInt<2>("h03")] node T_1690 = eq(T_1689, T_1678) infer accessor T_1692 = pages[UInt<3>("h04")] node T_1693 = eq(T_1692, T_1678) infer accessor T_1695 = pages[UInt<3>("h05")] node T_1696 = eq(T_1695, T_1678) wire T_1698 : UInt<1>[6] T_1698[0] := T_1681 T_1698[1] := T_1684 T_1698[2] := T_1687 T_1698[3] := T_1690 T_1698[4] := T_1693 T_1698[5] := T_1696 node T_1706 = cat(T_1698[4], T_1698[3]) node T_1707 = cat(T_1698[5], T_1706) node T_1708 = cat(T_1698[1], T_1698[0]) node T_1709 = cat(T_1698[2], T_1708) node T_1710 = cat(T_1707, T_1709) node pageHit = and(T_1710, pageValid) node T_1712 = bits(io.req.bits.addr, 11, 0) infer accessor T_1714 = idxs[UInt<1>("h00")] node T_1715 = eq(T_1714, T_1712) infer accessor T_1717 = idxs[UInt<1>("h01")] node T_1718 = eq(T_1717, T_1712) infer accessor T_1720 = idxs[UInt<2>("h02")] node T_1721 = eq(T_1720, T_1712) infer accessor T_1723 = idxs[UInt<2>("h03")] node T_1724 = eq(T_1723, T_1712) infer accessor T_1726 = idxs[UInt<3>("h04")] node T_1727 = eq(T_1726, T_1712) infer accessor T_1729 = idxs[UInt<3>("h05")] node T_1730 = eq(T_1729, T_1712) infer accessor T_1732 = idxs[UInt<3>("h06")] node T_1733 = eq(T_1732, T_1712) infer accessor T_1735 = idxs[UInt<3>("h07")] node T_1736 = eq(T_1735, T_1712) infer accessor T_1738 = idxs[UInt<4>("h08")] node T_1739 = eq(T_1738, T_1712) infer accessor T_1741 = idxs[UInt<4>("h09")] node T_1742 = eq(T_1741, T_1712) infer accessor T_1744 = idxs[UInt<4>("h0a")] node T_1745 = eq(T_1744, T_1712) infer accessor T_1747 = idxs[UInt<4>("h0b")] node T_1748 = eq(T_1747, T_1712) infer accessor T_1750 = idxs[UInt<4>("h0c")] node T_1751 = eq(T_1750, T_1712) infer accessor T_1753 = idxs[UInt<4>("h0d")] node T_1754 = eq(T_1753, T_1712) infer accessor T_1756 = idxs[UInt<4>("h0e")] node T_1757 = eq(T_1756, T_1712) infer accessor T_1759 = idxs[UInt<4>("h0f")] node T_1760 = eq(T_1759, T_1712) infer accessor T_1762 = idxs[UInt<5>("h010")] node T_1763 = eq(T_1762, T_1712) infer accessor T_1765 = idxs[UInt<5>("h011")] node T_1766 = eq(T_1765, T_1712) infer accessor T_1768 = idxs[UInt<5>("h012")] node T_1769 = eq(T_1768, T_1712) infer accessor T_1771 = idxs[UInt<5>("h013")] node T_1772 = eq(T_1771, T_1712) infer accessor T_1774 = idxs[UInt<5>("h014")] node T_1775 = eq(T_1774, T_1712) infer accessor T_1777 = idxs[UInt<5>("h015")] node T_1778 = eq(T_1777, T_1712) infer accessor T_1780 = idxs[UInt<5>("h016")] node T_1781 = eq(T_1780, T_1712) infer accessor T_1783 = idxs[UInt<5>("h017")] node T_1784 = eq(T_1783, T_1712) infer accessor T_1786 = idxs[UInt<5>("h018")] node T_1787 = eq(T_1786, T_1712) infer accessor T_1789 = idxs[UInt<5>("h019")] node T_1790 = eq(T_1789, T_1712) infer accessor T_1792 = idxs[UInt<5>("h01a")] node T_1793 = eq(T_1792, T_1712) infer accessor T_1795 = idxs[UInt<5>("h01b")] node T_1796 = eq(T_1795, T_1712) infer accessor T_1798 = idxs[UInt<5>("h01c")] node T_1799 = eq(T_1798, T_1712) infer accessor T_1801 = idxs[UInt<5>("h01d")] node T_1802 = eq(T_1801, T_1712) infer accessor T_1804 = idxs[UInt<5>("h01e")] node T_1805 = eq(T_1804, T_1712) infer accessor T_1807 = idxs[UInt<5>("h01f")] node T_1808 = eq(T_1807, T_1712) infer accessor T_1810 = idxs[UInt<6>("h020")] node T_1811 = eq(T_1810, T_1712) infer accessor T_1813 = idxs[UInt<6>("h021")] node T_1814 = eq(T_1813, T_1712) infer accessor T_1816 = idxs[UInt<6>("h022")] node T_1817 = eq(T_1816, T_1712) infer accessor T_1819 = idxs[UInt<6>("h023")] node T_1820 = eq(T_1819, T_1712) infer accessor T_1822 = idxs[UInt<6>("h024")] node T_1823 = eq(T_1822, T_1712) infer accessor T_1825 = idxs[UInt<6>("h025")] node T_1826 = eq(T_1825, T_1712) infer accessor T_1828 = idxs[UInt<6>("h026")] node T_1829 = eq(T_1828, T_1712) infer accessor T_1831 = idxs[UInt<6>("h027")] node T_1832 = eq(T_1831, T_1712) infer accessor T_1834 = idxs[UInt<6>("h028")] node T_1835 = eq(T_1834, T_1712) infer accessor T_1837 = idxs[UInt<6>("h029")] node T_1838 = eq(T_1837, T_1712) infer accessor T_1840 = idxs[UInt<6>("h02a")] node T_1841 = eq(T_1840, T_1712) infer accessor T_1843 = idxs[UInt<6>("h02b")] node T_1844 = eq(T_1843, T_1712) infer accessor T_1846 = idxs[UInt<6>("h02c")] node T_1847 = eq(T_1846, T_1712) infer accessor T_1849 = idxs[UInt<6>("h02d")] node T_1850 = eq(T_1849, T_1712) infer accessor T_1852 = idxs[UInt<6>("h02e")] node T_1853 = eq(T_1852, T_1712) infer accessor T_1855 = idxs[UInt<6>("h02f")] node T_1856 = eq(T_1855, T_1712) infer accessor T_1858 = idxs[UInt<6>("h030")] node T_1859 = eq(T_1858, T_1712) infer accessor T_1861 = idxs[UInt<6>("h031")] node T_1862 = eq(T_1861, T_1712) infer accessor T_1864 = idxs[UInt<6>("h032")] node T_1865 = eq(T_1864, T_1712) infer accessor T_1867 = idxs[UInt<6>("h033")] node T_1868 = eq(T_1867, T_1712) infer accessor T_1870 = idxs[UInt<6>("h034")] node T_1871 = eq(T_1870, T_1712) infer accessor T_1873 = idxs[UInt<6>("h035")] node T_1874 = eq(T_1873, T_1712) infer accessor T_1876 = idxs[UInt<6>("h036")] node T_1877 = eq(T_1876, T_1712) infer accessor T_1879 = idxs[UInt<6>("h037")] node T_1880 = eq(T_1879, T_1712) infer accessor T_1882 = idxs[UInt<6>("h038")] node T_1883 = eq(T_1882, T_1712) infer accessor T_1885 = idxs[UInt<6>("h039")] node T_1886 = eq(T_1885, T_1712) infer accessor T_1888 = idxs[UInt<6>("h03a")] node T_1889 = eq(T_1888, T_1712) infer accessor T_1891 = idxs[UInt<6>("h03b")] node T_1892 = eq(T_1891, T_1712) infer accessor T_1894 = idxs[UInt<6>("h03c")] node T_1895 = eq(T_1894, T_1712) infer accessor T_1897 = idxs[UInt<6>("h03d")] node T_1898 = eq(T_1897, T_1712) wire T_1900 : UInt<1>[62] T_1900[0] := T_1715 T_1900[1] := T_1718 T_1900[2] := T_1721 T_1900[3] := T_1724 T_1900[4] := T_1727 T_1900[5] := T_1730 T_1900[6] := T_1733 T_1900[7] := T_1736 T_1900[8] := T_1739 T_1900[9] := T_1742 T_1900[10] := T_1745 T_1900[11] := T_1748 T_1900[12] := T_1751 T_1900[13] := T_1754 T_1900[14] := T_1757 T_1900[15] := T_1760 T_1900[16] := T_1763 T_1900[17] := T_1766 T_1900[18] := T_1769 T_1900[19] := T_1772 T_1900[20] := T_1775 T_1900[21] := T_1778 T_1900[22] := T_1781 T_1900[23] := T_1784 T_1900[24] := T_1787 T_1900[25] := T_1790 T_1900[26] := T_1793 T_1900[27] := T_1796 T_1900[28] := T_1799 T_1900[29] := T_1802 T_1900[30] := T_1805 T_1900[31] := T_1808 T_1900[32] := T_1811 T_1900[33] := T_1814 T_1900[34] := T_1817 T_1900[35] := T_1820 T_1900[36] := T_1823 T_1900[37] := T_1826 T_1900[38] := T_1829 T_1900[39] := T_1832 T_1900[40] := T_1835 T_1900[41] := T_1838 T_1900[42] := T_1841 T_1900[43] := T_1844 T_1900[44] := T_1847 T_1900[45] := T_1850 T_1900[46] := T_1853 T_1900[47] := T_1856 T_1900[48] := T_1859 T_1900[49] := T_1862 T_1900[50] := T_1865 T_1900[51] := T_1868 T_1900[52] := T_1871 T_1900[53] := T_1874 T_1900[54] := T_1877 T_1900[55] := T_1880 T_1900[56] := T_1883 T_1900[57] := T_1886 T_1900[58] := T_1889 T_1900[59] := T_1892 T_1900[60] := T_1895 T_1900[61] := T_1898 node T_1964 = cat(T_1900[60], T_1900[59]) node T_1965 = cat(T_1900[61], T_1964) node T_1966 = cat(T_1900[58], T_1900[57]) node T_1967 = cat(T_1900[56], T_1900[55]) node T_1968 = cat(T_1966, T_1967) node T_1969 = cat(T_1965, T_1968) node T_1970 = cat(T_1900[54], T_1900[53]) node T_1971 = cat(T_1900[52], T_1900[51]) node T_1972 = cat(T_1970, T_1971) node T_1973 = cat(T_1900[50], T_1900[49]) node T_1974 = cat(T_1900[48], T_1900[47]) node T_1975 = cat(T_1973, T_1974) node T_1976 = cat(T_1972, T_1975) node T_1977 = cat(T_1969, T_1976) node T_1978 = cat(T_1900[46], T_1900[45]) node T_1979 = cat(T_1900[44], T_1900[43]) node T_1980 = cat(T_1978, T_1979) node T_1981 = cat(T_1900[42], T_1900[41]) node T_1982 = cat(T_1900[40], T_1900[39]) node T_1983 = cat(T_1981, T_1982) node T_1984 = cat(T_1980, T_1983) node T_1985 = cat(T_1900[38], T_1900[37]) node T_1986 = cat(T_1900[36], T_1900[35]) node T_1987 = cat(T_1985, T_1986) node T_1988 = cat(T_1900[34], T_1900[33]) node T_1989 = cat(T_1900[32], T_1900[31]) node T_1990 = cat(T_1988, T_1989) node T_1991 = cat(T_1987, T_1990) node T_1992 = cat(T_1984, T_1991) node T_1993 = cat(T_1977, T_1992) node T_1994 = cat(T_1900[29], T_1900[28]) node T_1995 = cat(T_1900[30], T_1994) node T_1996 = cat(T_1900[27], T_1900[26]) node T_1997 = cat(T_1900[25], T_1900[24]) node T_1998 = cat(T_1996, T_1997) node T_1999 = cat(T_1995, T_1998) node T_2000 = cat(T_1900[23], T_1900[22]) node T_2001 = cat(T_1900[21], T_1900[20]) node T_2002 = cat(T_2000, T_2001) node T_2003 = cat(T_1900[19], T_1900[18]) node T_2004 = cat(T_1900[17], T_1900[16]) node T_2005 = cat(T_2003, T_2004) node T_2006 = cat(T_2002, T_2005) node T_2007 = cat(T_1999, T_2006) node T_2008 = cat(T_1900[15], T_1900[14]) node T_2009 = cat(T_1900[13], T_1900[12]) node T_2010 = cat(T_2008, T_2009) node T_2011 = cat(T_1900[11], T_1900[10]) node T_2012 = cat(T_1900[9], T_1900[8]) node T_2013 = cat(T_2011, T_2012) node T_2014 = cat(T_2010, T_2013) node T_2015 = cat(T_1900[7], T_1900[6]) node T_2016 = cat(T_1900[5], T_1900[4]) node T_2017 = cat(T_2015, T_2016) node T_2018 = cat(T_1900[3], T_1900[2]) node T_2019 = cat(T_1900[1], T_1900[0]) node T_2020 = cat(T_2018, T_2019) node T_2021 = cat(T_2017, T_2020) node T_2022 = cat(T_2014, T_2021) node T_2023 = cat(T_2007, T_2022) node T_2024 = cat(T_1993, T_2023) node T_2025 = and(T_593, pageHit) node T_2026 = and(T_598, pageHit) node T_2027 = and(T_603, pageHit) node T_2028 = and(T_608, pageHit) node T_2029 = and(T_613, pageHit) node T_2030 = and(T_618, pageHit) node T_2031 = and(T_623, pageHit) node T_2032 = and(T_628, pageHit) node T_2033 = and(T_633, pageHit) node T_2034 = and(T_638, pageHit) node T_2035 = and(T_643, pageHit) node T_2036 = and(T_648, pageHit) node T_2037 = and(T_653, pageHit) node T_2038 = and(T_658, pageHit) node T_2039 = and(T_663, pageHit) node T_2040 = and(T_668, pageHit) node T_2041 = and(T_673, pageHit) node T_2042 = and(T_678, pageHit) node T_2043 = and(T_683, pageHit) node T_2044 = and(T_688, pageHit) node T_2045 = and(T_693, pageHit) node T_2046 = and(T_698, pageHit) node T_2047 = and(T_703, pageHit) node T_2048 = and(T_708, pageHit) node T_2049 = and(T_713, pageHit) node T_2050 = and(T_718, pageHit) node T_2051 = and(T_723, pageHit) node T_2052 = and(T_728, pageHit) node T_2053 = and(T_733, pageHit) node T_2054 = and(T_738, pageHit) node T_2055 = and(T_743, pageHit) node T_2056 = and(T_748, pageHit) node T_2057 = and(T_753, pageHit) node T_2058 = and(T_758, pageHit) node T_2059 = and(T_763, pageHit) node T_2060 = and(T_768, pageHit) node T_2061 = and(T_773, pageHit) node T_2062 = and(T_778, pageHit) node T_2063 = and(T_783, pageHit) node T_2064 = and(T_788, pageHit) node T_2065 = and(T_793, pageHit) node T_2066 = and(T_798, pageHit) node T_2067 = and(T_803, pageHit) node T_2068 = and(T_808, pageHit) node T_2069 = and(T_813, pageHit) node T_2070 = and(T_818, pageHit) node T_2071 = and(T_823, pageHit) node T_2072 = and(T_828, pageHit) node T_2073 = and(T_833, pageHit) node T_2074 = and(T_838, pageHit) node T_2075 = and(T_843, pageHit) node T_2076 = and(T_848, pageHit) node T_2077 = and(T_853, pageHit) node T_2078 = and(T_858, pageHit) node T_2079 = and(T_863, pageHit) node T_2080 = and(T_868, pageHit) node T_2081 = and(T_873, pageHit) node T_2082 = and(T_878, pageHit) node T_2083 = and(T_883, pageHit) node T_2084 = and(T_888, pageHit) node T_2085 = and(T_893, pageHit) node T_2086 = and(T_898, pageHit) node T_2088 = neq(T_2025, UInt<1>("h00")) node T_2090 = neq(T_2026, UInt<1>("h00")) node T_2092 = neq(T_2027, UInt<1>("h00")) node T_2094 = neq(T_2028, UInt<1>("h00")) node T_2096 = neq(T_2029, UInt<1>("h00")) node T_2098 = neq(T_2030, UInt<1>("h00")) node T_2100 = neq(T_2031, UInt<1>("h00")) node T_2102 = neq(T_2032, UInt<1>("h00")) node T_2104 = neq(T_2033, UInt<1>("h00")) node T_2106 = neq(T_2034, UInt<1>("h00")) node T_2108 = neq(T_2035, UInt<1>("h00")) node T_2110 = neq(T_2036, UInt<1>("h00")) node T_2112 = neq(T_2037, UInt<1>("h00")) node T_2114 = neq(T_2038, UInt<1>("h00")) node T_2116 = neq(T_2039, UInt<1>("h00")) node T_2118 = neq(T_2040, UInt<1>("h00")) node T_2120 = neq(T_2041, UInt<1>("h00")) node T_2122 = neq(T_2042, UInt<1>("h00")) node T_2124 = neq(T_2043, UInt<1>("h00")) node T_2126 = neq(T_2044, UInt<1>("h00")) node T_2128 = neq(T_2045, UInt<1>("h00")) node T_2130 = neq(T_2046, UInt<1>("h00")) node T_2132 = neq(T_2047, UInt<1>("h00")) node T_2134 = neq(T_2048, UInt<1>("h00")) node T_2136 = neq(T_2049, UInt<1>("h00")) node T_2138 = neq(T_2050, UInt<1>("h00")) node T_2140 = neq(T_2051, UInt<1>("h00")) node T_2142 = neq(T_2052, UInt<1>("h00")) node T_2144 = neq(T_2053, UInt<1>("h00")) node T_2146 = neq(T_2054, UInt<1>("h00")) node T_2148 = neq(T_2055, UInt<1>("h00")) node T_2150 = neq(T_2056, UInt<1>("h00")) node T_2152 = neq(T_2057, UInt<1>("h00")) node T_2154 = neq(T_2058, UInt<1>("h00")) node T_2156 = neq(T_2059, UInt<1>("h00")) node T_2158 = neq(T_2060, UInt<1>("h00")) node T_2160 = neq(T_2061, UInt<1>("h00")) node T_2162 = neq(T_2062, UInt<1>("h00")) node T_2164 = neq(T_2063, UInt<1>("h00")) node T_2166 = neq(T_2064, UInt<1>("h00")) node T_2168 = neq(T_2065, UInt<1>("h00")) node T_2170 = neq(T_2066, UInt<1>("h00")) node T_2172 = neq(T_2067, UInt<1>("h00")) node T_2174 = neq(T_2068, UInt<1>("h00")) node T_2176 = neq(T_2069, UInt<1>("h00")) node T_2178 = neq(T_2070, UInt<1>("h00")) node T_2180 = neq(T_2071, UInt<1>("h00")) node T_2182 = neq(T_2072, UInt<1>("h00")) node T_2184 = neq(T_2073, UInt<1>("h00")) node T_2186 = neq(T_2074, UInt<1>("h00")) node T_2188 = neq(T_2075, UInt<1>("h00")) node T_2190 = neq(T_2076, UInt<1>("h00")) node T_2192 = neq(T_2077, UInt<1>("h00")) node T_2194 = neq(T_2078, UInt<1>("h00")) node T_2196 = neq(T_2079, UInt<1>("h00")) node T_2198 = neq(T_2080, UInt<1>("h00")) node T_2200 = neq(T_2081, UInt<1>("h00")) node T_2202 = neq(T_2082, UInt<1>("h00")) node T_2204 = neq(T_2083, UInt<1>("h00")) node T_2206 = neq(T_2084, UInt<1>("h00")) node T_2208 = neq(T_2085, UInt<1>("h00")) node T_2210 = neq(T_2086, UInt<1>("h00")) wire T_2212 : UInt<1>[62] T_2212[0] := T_2088 T_2212[1] := T_2090 T_2212[2] := T_2092 T_2212[3] := T_2094 T_2212[4] := T_2096 T_2212[5] := T_2098 T_2212[6] := T_2100 T_2212[7] := T_2102 T_2212[8] := T_2104 T_2212[9] := T_2106 T_2212[10] := T_2108 T_2212[11] := T_2110 T_2212[12] := T_2112 T_2212[13] := T_2114 T_2212[14] := T_2116 T_2212[15] := T_2118 T_2212[16] := T_2120 T_2212[17] := T_2122 T_2212[18] := T_2124 T_2212[19] := T_2126 T_2212[20] := T_2128 T_2212[21] := T_2130 T_2212[22] := T_2132 T_2212[23] := T_2134 T_2212[24] := T_2136 T_2212[25] := T_2138 T_2212[26] := T_2140 T_2212[27] := T_2142 T_2212[28] := T_2144 T_2212[29] := T_2146 T_2212[30] := T_2148 T_2212[31] := T_2150 T_2212[32] := T_2152 T_2212[33] := T_2154 T_2212[34] := T_2156 T_2212[35] := T_2158 T_2212[36] := T_2160 T_2212[37] := T_2162 T_2212[38] := T_2164 T_2212[39] := T_2166 T_2212[40] := T_2168 T_2212[41] := T_2170 T_2212[42] := T_2172 T_2212[43] := T_2174 T_2212[44] := T_2176 T_2212[45] := T_2178 T_2212[46] := T_2180 T_2212[47] := T_2182 T_2212[48] := T_2184 T_2212[49] := T_2186 T_2212[50] := T_2188 T_2212[51] := T_2190 T_2212[52] := T_2192 T_2212[53] := T_2194 T_2212[54] := T_2196 T_2212[55] := T_2198 T_2212[56] := T_2200 T_2212[57] := T_2202 T_2212[58] := T_2204 T_2212[59] := T_2206 T_2212[60] := T_2208 T_2212[61] := T_2210 node T_2276 = cat(T_2212[60], T_2212[59]) node T_2277 = cat(T_2212[61], T_2276) node T_2278 = cat(T_2212[58], T_2212[57]) node T_2279 = cat(T_2212[56], T_2212[55]) node T_2280 = cat(T_2278, T_2279) node T_2281 = cat(T_2277, T_2280) node T_2282 = cat(T_2212[54], T_2212[53]) node T_2283 = cat(T_2212[52], T_2212[51]) node T_2284 = cat(T_2282, T_2283) node T_2285 = cat(T_2212[50], T_2212[49]) node T_2286 = cat(T_2212[48], T_2212[47]) node T_2287 = cat(T_2285, T_2286) node T_2288 = cat(T_2284, T_2287) node T_2289 = cat(T_2281, T_2288) node T_2290 = cat(T_2212[46], T_2212[45]) node T_2291 = cat(T_2212[44], T_2212[43]) node T_2292 = cat(T_2290, T_2291) node T_2293 = cat(T_2212[42], T_2212[41]) node T_2294 = cat(T_2212[40], T_2212[39]) node T_2295 = cat(T_2293, T_2294) node T_2296 = cat(T_2292, T_2295) node T_2297 = cat(T_2212[38], T_2212[37]) node T_2298 = cat(T_2212[36], T_2212[35]) node T_2299 = cat(T_2297, T_2298) node T_2300 = cat(T_2212[34], T_2212[33]) node T_2301 = cat(T_2212[32], T_2212[31]) node T_2302 = cat(T_2300, T_2301) node T_2303 = cat(T_2299, T_2302) node T_2304 = cat(T_2296, T_2303) node T_2305 = cat(T_2289, T_2304) node T_2306 = cat(T_2212[29], T_2212[28]) node T_2307 = cat(T_2212[30], T_2306) node T_2308 = cat(T_2212[27], T_2212[26]) node T_2309 = cat(T_2212[25], T_2212[24]) node T_2310 = cat(T_2308, T_2309) node T_2311 = cat(T_2307, T_2310) node T_2312 = cat(T_2212[23], T_2212[22]) node T_2313 = cat(T_2212[21], T_2212[20]) node T_2314 = cat(T_2312, T_2313) node T_2315 = cat(T_2212[19], T_2212[18]) node T_2316 = cat(T_2212[17], T_2212[16]) node T_2317 = cat(T_2315, T_2316) node T_2318 = cat(T_2314, T_2317) node T_2319 = cat(T_2311, T_2318) node T_2320 = cat(T_2212[15], T_2212[14]) node T_2321 = cat(T_2212[13], T_2212[12]) node T_2322 = cat(T_2320, T_2321) node T_2323 = cat(T_2212[11], T_2212[10]) node T_2324 = cat(T_2212[9], T_2212[8]) node T_2325 = cat(T_2323, T_2324) node T_2326 = cat(T_2322, T_2325) node T_2327 = cat(T_2212[7], T_2212[6]) node T_2328 = cat(T_2212[5], T_2212[4]) node T_2329 = cat(T_2327, T_2328) node T_2330 = cat(T_2212[3], T_2212[2]) node T_2331 = cat(T_2212[1], T_2212[0]) node T_2332 = cat(T_2330, T_2331) node T_2333 = cat(T_2329, T_2332) node T_2334 = cat(T_2326, T_2333) node T_2335 = cat(T_2319, T_2334) node T_2336 = cat(T_2305, T_2335) node T_2337 = and(idxValid, T_2024) node hits = and(T_2337, T_2336) node T_2339 = shr(r_btb_update.bits.pc, 12) infer accessor T_2341 = pages[UInt<1>("h00")] node T_2342 = eq(T_2341, T_2339) infer accessor T_2344 = pages[UInt<1>("h01")] node T_2345 = eq(T_2344, T_2339) infer accessor T_2347 = pages[UInt<2>("h02")] node T_2348 = eq(T_2347, T_2339) infer accessor T_2350 = pages[UInt<2>("h03")] node T_2351 = eq(T_2350, T_2339) infer accessor T_2353 = pages[UInt<3>("h04")] node T_2354 = eq(T_2353, T_2339) infer accessor T_2356 = pages[UInt<3>("h05")] node T_2357 = eq(T_2356, T_2339) wire T_2359 : UInt<1>[6] T_2359[0] := T_2342 T_2359[1] := T_2345 T_2359[2] := T_2348 T_2359[3] := T_2351 T_2359[4] := T_2354 T_2359[5] := T_2357 node T_2367 = cat(T_2359[4], T_2359[3]) node T_2368 = cat(T_2359[5], T_2367) node T_2369 = cat(T_2359[1], T_2359[0]) node T_2370 = cat(T_2359[2], T_2369) node T_2371 = cat(T_2368, T_2370) node updatePageHit = and(T_2371, pageValid) node T_2373 = bits(r_btb_update.bits.pc, 11, 0) infer accessor T_2375 = idxs[UInt<1>("h00")] node T_2376 = eq(T_2375, T_2373) infer accessor T_2378 = idxs[UInt<1>("h01")] node T_2379 = eq(T_2378, T_2373) infer accessor T_2381 = idxs[UInt<2>("h02")] node T_2382 = eq(T_2381, T_2373) infer accessor T_2384 = idxs[UInt<2>("h03")] node T_2385 = eq(T_2384, T_2373) infer accessor T_2387 = idxs[UInt<3>("h04")] node T_2388 = eq(T_2387, T_2373) infer accessor T_2390 = idxs[UInt<3>("h05")] node T_2391 = eq(T_2390, T_2373) infer accessor T_2393 = idxs[UInt<3>("h06")] node T_2394 = eq(T_2393, T_2373) infer accessor T_2396 = idxs[UInt<3>("h07")] node T_2397 = eq(T_2396, T_2373) infer accessor T_2399 = idxs[UInt<4>("h08")] node T_2400 = eq(T_2399, T_2373) infer accessor T_2402 = idxs[UInt<4>("h09")] node T_2403 = eq(T_2402, T_2373) infer accessor T_2405 = idxs[UInt<4>("h0a")] node T_2406 = eq(T_2405, T_2373) infer accessor T_2408 = idxs[UInt<4>("h0b")] node T_2409 = eq(T_2408, T_2373) infer accessor T_2411 = idxs[UInt<4>("h0c")] node T_2412 = eq(T_2411, T_2373) infer accessor T_2414 = idxs[UInt<4>("h0d")] node T_2415 = eq(T_2414, T_2373) infer accessor T_2417 = idxs[UInt<4>("h0e")] node T_2418 = eq(T_2417, T_2373) infer accessor T_2420 = idxs[UInt<4>("h0f")] node T_2421 = eq(T_2420, T_2373) infer accessor T_2423 = idxs[UInt<5>("h010")] node T_2424 = eq(T_2423, T_2373) infer accessor T_2426 = idxs[UInt<5>("h011")] node T_2427 = eq(T_2426, T_2373) infer accessor T_2429 = idxs[UInt<5>("h012")] node T_2430 = eq(T_2429, T_2373) infer accessor T_2432 = idxs[UInt<5>("h013")] node T_2433 = eq(T_2432, T_2373) infer accessor T_2435 = idxs[UInt<5>("h014")] node T_2436 = eq(T_2435, T_2373) infer accessor T_2438 = idxs[UInt<5>("h015")] node T_2439 = eq(T_2438, T_2373) infer accessor T_2441 = idxs[UInt<5>("h016")] node T_2442 = eq(T_2441, T_2373) infer accessor T_2444 = idxs[UInt<5>("h017")] node T_2445 = eq(T_2444, T_2373) infer accessor T_2447 = idxs[UInt<5>("h018")] node T_2448 = eq(T_2447, T_2373) infer accessor T_2450 = idxs[UInt<5>("h019")] node T_2451 = eq(T_2450, T_2373) infer accessor T_2453 = idxs[UInt<5>("h01a")] node T_2454 = eq(T_2453, T_2373) infer accessor T_2456 = idxs[UInt<5>("h01b")] node T_2457 = eq(T_2456, T_2373) infer accessor T_2459 = idxs[UInt<5>("h01c")] node T_2460 = eq(T_2459, T_2373) infer accessor T_2462 = idxs[UInt<5>("h01d")] node T_2463 = eq(T_2462, T_2373) infer accessor T_2465 = idxs[UInt<5>("h01e")] node T_2466 = eq(T_2465, T_2373) infer accessor T_2468 = idxs[UInt<5>("h01f")] node T_2469 = eq(T_2468, T_2373) infer accessor T_2471 = idxs[UInt<6>("h020")] node T_2472 = eq(T_2471, T_2373) infer accessor T_2474 = idxs[UInt<6>("h021")] node T_2475 = eq(T_2474, T_2373) infer accessor T_2477 = idxs[UInt<6>("h022")] node T_2478 = eq(T_2477, T_2373) infer accessor T_2480 = idxs[UInt<6>("h023")] node T_2481 = eq(T_2480, T_2373) infer accessor T_2483 = idxs[UInt<6>("h024")] node T_2484 = eq(T_2483, T_2373) infer accessor T_2486 = idxs[UInt<6>("h025")] node T_2487 = eq(T_2486, T_2373) infer accessor T_2489 = idxs[UInt<6>("h026")] node T_2490 = eq(T_2489, T_2373) infer accessor T_2492 = idxs[UInt<6>("h027")] node T_2493 = eq(T_2492, T_2373) infer accessor T_2495 = idxs[UInt<6>("h028")] node T_2496 = eq(T_2495, T_2373) infer accessor T_2498 = idxs[UInt<6>("h029")] node T_2499 = eq(T_2498, T_2373) infer accessor T_2501 = idxs[UInt<6>("h02a")] node T_2502 = eq(T_2501, T_2373) infer accessor T_2504 = idxs[UInt<6>("h02b")] node T_2505 = eq(T_2504, T_2373) infer accessor T_2507 = idxs[UInt<6>("h02c")] node T_2508 = eq(T_2507, T_2373) infer accessor T_2510 = idxs[UInt<6>("h02d")] node T_2511 = eq(T_2510, T_2373) infer accessor T_2513 = idxs[UInt<6>("h02e")] node T_2514 = eq(T_2513, T_2373) infer accessor T_2516 = idxs[UInt<6>("h02f")] node T_2517 = eq(T_2516, T_2373) infer accessor T_2519 = idxs[UInt<6>("h030")] node T_2520 = eq(T_2519, T_2373) infer accessor T_2522 = idxs[UInt<6>("h031")] node T_2523 = eq(T_2522, T_2373) infer accessor T_2525 = idxs[UInt<6>("h032")] node T_2526 = eq(T_2525, T_2373) infer accessor T_2528 = idxs[UInt<6>("h033")] node T_2529 = eq(T_2528, T_2373) infer accessor T_2531 = idxs[UInt<6>("h034")] node T_2532 = eq(T_2531, T_2373) infer accessor T_2534 = idxs[UInt<6>("h035")] node T_2535 = eq(T_2534, T_2373) infer accessor T_2537 = idxs[UInt<6>("h036")] node T_2538 = eq(T_2537, T_2373) infer accessor T_2540 = idxs[UInt<6>("h037")] node T_2541 = eq(T_2540, T_2373) infer accessor T_2543 = idxs[UInt<6>("h038")] node T_2544 = eq(T_2543, T_2373) infer accessor T_2546 = idxs[UInt<6>("h039")] node T_2547 = eq(T_2546, T_2373) infer accessor T_2549 = idxs[UInt<6>("h03a")] node T_2550 = eq(T_2549, T_2373) infer accessor T_2552 = idxs[UInt<6>("h03b")] node T_2553 = eq(T_2552, T_2373) infer accessor T_2555 = idxs[UInt<6>("h03c")] node T_2556 = eq(T_2555, T_2373) infer accessor T_2558 = idxs[UInt<6>("h03d")] node T_2559 = eq(T_2558, T_2373) wire T_2561 : UInt<1>[62] T_2561[0] := T_2376 T_2561[1] := T_2379 T_2561[2] := T_2382 T_2561[3] := T_2385 T_2561[4] := T_2388 T_2561[5] := T_2391 T_2561[6] := T_2394 T_2561[7] := T_2397 T_2561[8] := T_2400 T_2561[9] := T_2403 T_2561[10] := T_2406 T_2561[11] := T_2409 T_2561[12] := T_2412 T_2561[13] := T_2415 T_2561[14] := T_2418 T_2561[15] := T_2421 T_2561[16] := T_2424 T_2561[17] := T_2427 T_2561[18] := T_2430 T_2561[19] := T_2433 T_2561[20] := T_2436 T_2561[21] := T_2439 T_2561[22] := T_2442 T_2561[23] := T_2445 T_2561[24] := T_2448 T_2561[25] := T_2451 T_2561[26] := T_2454 T_2561[27] := T_2457 T_2561[28] := T_2460 T_2561[29] := T_2463 T_2561[30] := T_2466 T_2561[31] := T_2469 T_2561[32] := T_2472 T_2561[33] := T_2475 T_2561[34] := T_2478 T_2561[35] := T_2481 T_2561[36] := T_2484 T_2561[37] := T_2487 T_2561[38] := T_2490 T_2561[39] := T_2493 T_2561[40] := T_2496 T_2561[41] := T_2499 T_2561[42] := T_2502 T_2561[43] := T_2505 T_2561[44] := T_2508 T_2561[45] := T_2511 T_2561[46] := T_2514 T_2561[47] := T_2517 T_2561[48] := T_2520 T_2561[49] := T_2523 T_2561[50] := T_2526 T_2561[51] := T_2529 T_2561[52] := T_2532 T_2561[53] := T_2535 T_2561[54] := T_2538 T_2561[55] := T_2541 T_2561[56] := T_2544 T_2561[57] := T_2547 T_2561[58] := T_2550 T_2561[59] := T_2553 T_2561[60] := T_2556 T_2561[61] := T_2559 node T_2625 = cat(T_2561[60], T_2561[59]) node T_2626 = cat(T_2561[61], T_2625) node T_2627 = cat(T_2561[58], T_2561[57]) node T_2628 = cat(T_2561[56], T_2561[55]) node T_2629 = cat(T_2627, T_2628) node T_2630 = cat(T_2626, T_2629) node T_2631 = cat(T_2561[54], T_2561[53]) node T_2632 = cat(T_2561[52], T_2561[51]) node T_2633 = cat(T_2631, T_2632) node T_2634 = cat(T_2561[50], T_2561[49]) node T_2635 = cat(T_2561[48], T_2561[47]) node T_2636 = cat(T_2634, T_2635) node T_2637 = cat(T_2633, T_2636) node T_2638 = cat(T_2630, T_2637) node T_2639 = cat(T_2561[46], T_2561[45]) node T_2640 = cat(T_2561[44], T_2561[43]) node T_2641 = cat(T_2639, T_2640) node T_2642 = cat(T_2561[42], T_2561[41]) node T_2643 = cat(T_2561[40], T_2561[39]) node T_2644 = cat(T_2642, T_2643) node T_2645 = cat(T_2641, T_2644) node T_2646 = cat(T_2561[38], T_2561[37]) node T_2647 = cat(T_2561[36], T_2561[35]) node T_2648 = cat(T_2646, T_2647) node T_2649 = cat(T_2561[34], T_2561[33]) node T_2650 = cat(T_2561[32], T_2561[31]) node T_2651 = cat(T_2649, T_2650) node T_2652 = cat(T_2648, T_2651) node T_2653 = cat(T_2645, T_2652) node T_2654 = cat(T_2638, T_2653) node T_2655 = cat(T_2561[29], T_2561[28]) node T_2656 = cat(T_2561[30], T_2655) node T_2657 = cat(T_2561[27], T_2561[26]) node T_2658 = cat(T_2561[25], T_2561[24]) node T_2659 = cat(T_2657, T_2658) node T_2660 = cat(T_2656, T_2659) node T_2661 = cat(T_2561[23], T_2561[22]) node T_2662 = cat(T_2561[21], T_2561[20]) node T_2663 = cat(T_2661, T_2662) node T_2664 = cat(T_2561[19], T_2561[18]) node T_2665 = cat(T_2561[17], T_2561[16]) node T_2666 = cat(T_2664, T_2665) node T_2667 = cat(T_2663, T_2666) node T_2668 = cat(T_2660, T_2667) node T_2669 = cat(T_2561[15], T_2561[14]) node T_2670 = cat(T_2561[13], T_2561[12]) node T_2671 = cat(T_2669, T_2670) node T_2672 = cat(T_2561[11], T_2561[10]) node T_2673 = cat(T_2561[9], T_2561[8]) node T_2674 = cat(T_2672, T_2673) node T_2675 = cat(T_2671, T_2674) node T_2676 = cat(T_2561[7], T_2561[6]) node T_2677 = cat(T_2561[5], T_2561[4]) node T_2678 = cat(T_2676, T_2677) node T_2679 = cat(T_2561[3], T_2561[2]) node T_2680 = cat(T_2561[1], T_2561[0]) node T_2681 = cat(T_2679, T_2680) node T_2682 = cat(T_2678, T_2681) node T_2683 = cat(T_2675, T_2682) node T_2684 = cat(T_2668, T_2683) node T_2685 = cat(T_2654, T_2684) node T_2686 = and(T_593, updatePageHit) node T_2687 = and(T_598, updatePageHit) node T_2688 = and(T_603, updatePageHit) node T_2689 = and(T_608, updatePageHit) node T_2690 = and(T_613, updatePageHit) node T_2691 = and(T_618, updatePageHit) node T_2692 = and(T_623, updatePageHit) node T_2693 = and(T_628, updatePageHit) node T_2694 = and(T_633, updatePageHit) node T_2695 = and(T_638, updatePageHit) node T_2696 = and(T_643, updatePageHit) node T_2697 = and(T_648, updatePageHit) node T_2698 = and(T_653, updatePageHit) node T_2699 = and(T_658, updatePageHit) node T_2700 = and(T_663, updatePageHit) node T_2701 = and(T_668, updatePageHit) node T_2702 = and(T_673, updatePageHit) node T_2703 = and(T_678, updatePageHit) node T_2704 = and(T_683, updatePageHit) node T_2705 = and(T_688, updatePageHit) node T_2706 = and(T_693, updatePageHit) node T_2707 = and(T_698, updatePageHit) node T_2708 = and(T_703, updatePageHit) node T_2709 = and(T_708, updatePageHit) node T_2710 = and(T_713, updatePageHit) node T_2711 = and(T_718, updatePageHit) node T_2712 = and(T_723, updatePageHit) node T_2713 = and(T_728, updatePageHit) node T_2714 = and(T_733, updatePageHit) node T_2715 = and(T_738, updatePageHit) node T_2716 = and(T_743, updatePageHit) node T_2717 = and(T_748, updatePageHit) node T_2718 = and(T_753, updatePageHit) node T_2719 = and(T_758, updatePageHit) node T_2720 = and(T_763, updatePageHit) node T_2721 = and(T_768, updatePageHit) node T_2722 = and(T_773, updatePageHit) node T_2723 = and(T_778, updatePageHit) node T_2724 = and(T_783, updatePageHit) node T_2725 = and(T_788, updatePageHit) node T_2726 = and(T_793, updatePageHit) node T_2727 = and(T_798, updatePageHit) node T_2728 = and(T_803, updatePageHit) node T_2729 = and(T_808, updatePageHit) node T_2730 = and(T_813, updatePageHit) node T_2731 = and(T_818, updatePageHit) node T_2732 = and(T_823, updatePageHit) node T_2733 = and(T_828, updatePageHit) node T_2734 = and(T_833, updatePageHit) node T_2735 = and(T_838, updatePageHit) node T_2736 = and(T_843, updatePageHit) node T_2737 = and(T_848, updatePageHit) node T_2738 = and(T_853, updatePageHit) node T_2739 = and(T_858, updatePageHit) node T_2740 = and(T_863, updatePageHit) node T_2741 = and(T_868, updatePageHit) node T_2742 = and(T_873, updatePageHit) node T_2743 = and(T_878, updatePageHit) node T_2744 = and(T_883, updatePageHit) node T_2745 = and(T_888, updatePageHit) node T_2746 = and(T_893, updatePageHit) node T_2747 = and(T_898, updatePageHit) node T_2749 = neq(T_2686, UInt<1>("h00")) node T_2751 = neq(T_2687, UInt<1>("h00")) node T_2753 = neq(T_2688, UInt<1>("h00")) node T_2755 = neq(T_2689, UInt<1>("h00")) node T_2757 = neq(T_2690, UInt<1>("h00")) node T_2759 = neq(T_2691, UInt<1>("h00")) node T_2761 = neq(T_2692, UInt<1>("h00")) node T_2763 = neq(T_2693, UInt<1>("h00")) node T_2765 = neq(T_2694, UInt<1>("h00")) node T_2767 = neq(T_2695, UInt<1>("h00")) node T_2769 = neq(T_2696, UInt<1>("h00")) node T_2771 = neq(T_2697, UInt<1>("h00")) node T_2773 = neq(T_2698, UInt<1>("h00")) node T_2775 = neq(T_2699, UInt<1>("h00")) node T_2777 = neq(T_2700, UInt<1>("h00")) node T_2779 = neq(T_2701, UInt<1>("h00")) node T_2781 = neq(T_2702, UInt<1>("h00")) node T_2783 = neq(T_2703, UInt<1>("h00")) node T_2785 = neq(T_2704, UInt<1>("h00")) node T_2787 = neq(T_2705, UInt<1>("h00")) node T_2789 = neq(T_2706, UInt<1>("h00")) node T_2791 = neq(T_2707, UInt<1>("h00")) node T_2793 = neq(T_2708, UInt<1>("h00")) node T_2795 = neq(T_2709, UInt<1>("h00")) node T_2797 = neq(T_2710, UInt<1>("h00")) node T_2799 = neq(T_2711, UInt<1>("h00")) node T_2801 = neq(T_2712, UInt<1>("h00")) node T_2803 = neq(T_2713, UInt<1>("h00")) node T_2805 = neq(T_2714, UInt<1>("h00")) node T_2807 = neq(T_2715, UInt<1>("h00")) node T_2809 = neq(T_2716, UInt<1>("h00")) node T_2811 = neq(T_2717, UInt<1>("h00")) node T_2813 = neq(T_2718, UInt<1>("h00")) node T_2815 = neq(T_2719, UInt<1>("h00")) node T_2817 = neq(T_2720, UInt<1>("h00")) node T_2819 = neq(T_2721, UInt<1>("h00")) node T_2821 = neq(T_2722, UInt<1>("h00")) node T_2823 = neq(T_2723, UInt<1>("h00")) node T_2825 = neq(T_2724, UInt<1>("h00")) node T_2827 = neq(T_2725, UInt<1>("h00")) node T_2829 = neq(T_2726, UInt<1>("h00")) node T_2831 = neq(T_2727, UInt<1>("h00")) node T_2833 = neq(T_2728, UInt<1>("h00")) node T_2835 = neq(T_2729, UInt<1>("h00")) node T_2837 = neq(T_2730, UInt<1>("h00")) node T_2839 = neq(T_2731, UInt<1>("h00")) node T_2841 = neq(T_2732, UInt<1>("h00")) node T_2843 = neq(T_2733, UInt<1>("h00")) node T_2845 = neq(T_2734, UInt<1>("h00")) node T_2847 = neq(T_2735, UInt<1>("h00")) node T_2849 = neq(T_2736, UInt<1>("h00")) node T_2851 = neq(T_2737, UInt<1>("h00")) node T_2853 = neq(T_2738, UInt<1>("h00")) node T_2855 = neq(T_2739, UInt<1>("h00")) node T_2857 = neq(T_2740, UInt<1>("h00")) node T_2859 = neq(T_2741, UInt<1>("h00")) node T_2861 = neq(T_2742, UInt<1>("h00")) node T_2863 = neq(T_2743, UInt<1>("h00")) node T_2865 = neq(T_2744, UInt<1>("h00")) node T_2867 = neq(T_2745, UInt<1>("h00")) node T_2869 = neq(T_2746, UInt<1>("h00")) node T_2871 = neq(T_2747, UInt<1>("h00")) wire T_2873 : UInt<1>[62] T_2873[0] := T_2749 T_2873[1] := T_2751 T_2873[2] := T_2753 T_2873[3] := T_2755 T_2873[4] := T_2757 T_2873[5] := T_2759 T_2873[6] := T_2761 T_2873[7] := T_2763 T_2873[8] := T_2765 T_2873[9] := T_2767 T_2873[10] := T_2769 T_2873[11] := T_2771 T_2873[12] := T_2773 T_2873[13] := T_2775 T_2873[14] := T_2777 T_2873[15] := T_2779 T_2873[16] := T_2781 T_2873[17] := T_2783 T_2873[18] := T_2785 T_2873[19] := T_2787 T_2873[20] := T_2789 T_2873[21] := T_2791 T_2873[22] := T_2793 T_2873[23] := T_2795 T_2873[24] := T_2797 T_2873[25] := T_2799 T_2873[26] := T_2801 T_2873[27] := T_2803 T_2873[28] := T_2805 T_2873[29] := T_2807 T_2873[30] := T_2809 T_2873[31] := T_2811 T_2873[32] := T_2813 T_2873[33] := T_2815 T_2873[34] := T_2817 T_2873[35] := T_2819 T_2873[36] := T_2821 T_2873[37] := T_2823 T_2873[38] := T_2825 T_2873[39] := T_2827 T_2873[40] := T_2829 T_2873[41] := T_2831 T_2873[42] := T_2833 T_2873[43] := T_2835 T_2873[44] := T_2837 T_2873[45] := T_2839 T_2873[46] := T_2841 T_2873[47] := T_2843 T_2873[48] := T_2845 T_2873[49] := T_2847 T_2873[50] := T_2849 T_2873[51] := T_2851 T_2873[52] := T_2853 T_2873[53] := T_2855 T_2873[54] := T_2857 T_2873[55] := T_2859 T_2873[56] := T_2861 T_2873[57] := T_2863 T_2873[58] := T_2865 T_2873[59] := T_2867 T_2873[60] := T_2869 T_2873[61] := T_2871 node T_2937 = cat(T_2873[60], T_2873[59]) node T_2938 = cat(T_2873[61], T_2937) node T_2939 = cat(T_2873[58], T_2873[57]) node T_2940 = cat(T_2873[56], T_2873[55]) node T_2941 = cat(T_2939, T_2940) node T_2942 = cat(T_2938, T_2941) node T_2943 = cat(T_2873[54], T_2873[53]) node T_2944 = cat(T_2873[52], T_2873[51]) node T_2945 = cat(T_2943, T_2944) node T_2946 = cat(T_2873[50], T_2873[49]) node T_2947 = cat(T_2873[48], T_2873[47]) node T_2948 = cat(T_2946, T_2947) node T_2949 = cat(T_2945, T_2948) node T_2950 = cat(T_2942, T_2949) node T_2951 = cat(T_2873[46], T_2873[45]) node T_2952 = cat(T_2873[44], T_2873[43]) node T_2953 = cat(T_2951, T_2952) node T_2954 = cat(T_2873[42], T_2873[41]) node T_2955 = cat(T_2873[40], T_2873[39]) node T_2956 = cat(T_2954, T_2955) node T_2957 = cat(T_2953, T_2956) node T_2958 = cat(T_2873[38], T_2873[37]) node T_2959 = cat(T_2873[36], T_2873[35]) node T_2960 = cat(T_2958, T_2959) node T_2961 = cat(T_2873[34], T_2873[33]) node T_2962 = cat(T_2873[32], T_2873[31]) node T_2963 = cat(T_2961, T_2962) node T_2964 = cat(T_2960, T_2963) node T_2965 = cat(T_2957, T_2964) node T_2966 = cat(T_2950, T_2965) node T_2967 = cat(T_2873[29], T_2873[28]) node T_2968 = cat(T_2873[30], T_2967) node T_2969 = cat(T_2873[27], T_2873[26]) node T_2970 = cat(T_2873[25], T_2873[24]) node T_2971 = cat(T_2969, T_2970) node T_2972 = cat(T_2968, T_2971) node T_2973 = cat(T_2873[23], T_2873[22]) node T_2974 = cat(T_2873[21], T_2873[20]) node T_2975 = cat(T_2973, T_2974) node T_2976 = cat(T_2873[19], T_2873[18]) node T_2977 = cat(T_2873[17], T_2873[16]) node T_2978 = cat(T_2976, T_2977) node T_2979 = cat(T_2975, T_2978) node T_2980 = cat(T_2972, T_2979) node T_2981 = cat(T_2873[15], T_2873[14]) node T_2982 = cat(T_2873[13], T_2873[12]) node T_2983 = cat(T_2981, T_2982) node T_2984 = cat(T_2873[11], T_2873[10]) node T_2985 = cat(T_2873[9], T_2873[8]) node T_2986 = cat(T_2984, T_2985) node T_2987 = cat(T_2983, T_2986) node T_2988 = cat(T_2873[7], T_2873[6]) node T_2989 = cat(T_2873[5], T_2873[4]) node T_2990 = cat(T_2988, T_2989) node T_2991 = cat(T_2873[3], T_2873[2]) node T_2992 = cat(T_2873[1], T_2873[0]) node T_2993 = cat(T_2991, T_2992) node T_2994 = cat(T_2990, T_2993) node T_2995 = cat(T_2987, T_2994) node T_2996 = cat(T_2980, T_2995) node T_2997 = cat(T_2966, T_2996) node T_2998 = and(idxValid, T_2685) node updateHits = and(T_2998, T_2997) reg T_3001 : UInt<16>, clock, reset onreset T_3001 := UInt<16>("h01") when r_btb_update.valid : node T_3002 = bit(T_3001, 0) node T_3003 = bit(T_3001, 2) node T_3004 = xor(T_3002, T_3003) node T_3005 = bit(T_3001, 3) node T_3006 = xor(T_3004, T_3005) node T_3007 = bit(T_3001, 5) node T_3008 = xor(T_3006, T_3007) node T_3009 = bits(T_3001, 15, 1) node T_3010 = cat(T_3008, T_3009) T_3001 := T_3010 skip node T_3012 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) node T_3013 = and(r_btb_update.valid, T_3012) reg nextRepl : UInt<6>, clock, reset onreset nextRepl := UInt<6>("h00") when T_3013 : node T_3017 = eq(nextRepl, UInt<6>("h03d")) node T_3019 = and(UInt<1>("h01"), T_3017) node T_3022 = addw(nextRepl, UInt<1>("h01")) node T_3023 = mux(T_3019, UInt<1>("h00"), T_3022) nextRepl := T_3023 skip node T_3024 = and(T_3013, T_3017) node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) wire idxPageRepl : UInt<6> idxPageRepl := UInt<1>("h00") node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) node T_3033 = bits(idxPageUpdateOH, 5, 4) node T_3034 = bits(idxPageUpdateOH, 3, 0) node T_3036 = neq(T_3033, UInt<1>("h00")) node T_3037 = or(T_3033, T_3034) node T_3038 = bits(T_3037, 3, 2) node T_3039 = bits(T_3037, 1, 0) node T_3041 = neq(T_3038, UInt<1>("h00")) node T_3042 = or(T_3038, T_3039) node T_3043 = bit(T_3042, 1) node T_3044 = cat(T_3041, T_3043) node idxPageUpdate = cat(T_3036, T_3044) node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) node T_3048 = shr(r_btb_update.bits.pc, 12) node T_3049 = shr(io.req.bits.addr, 12) node samePage = eq(T_3048, T_3049) node T_3051 = not(idxPageReplEn) node T_3052 = and(pageHit, T_3051) node usePageHit = neq(T_3052, UInt<1>("h00")) node T_3056 = eq(samePage, UInt<1>("h00")) node T_3058 = eq(usePageHit, UInt<1>("h00")) node doTgtPageRepl = and(T_3056, T_3058) node T_3060 = bits(idxPageUpdateOH, 4, 0) node T_3061 = shl(T_3060, 1) node T_3062 = bit(idxPageUpdateOH, 5) node T_3063 = or(T_3061, T_3062) node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3063) node T_3065 = mux(usePageHit, pageHit, tgtPageRepl) node T_3066 = bits(T_3065, 5, 4) node T_3067 = bits(T_3065, 3, 0) node T_3069 = neq(T_3066, UInt<1>("h00")) node T_3070 = or(T_3066, T_3067) node T_3071 = bits(T_3070, 3, 2) node T_3072 = bits(T_3070, 1, 0) node T_3074 = neq(T_3071, UInt<1>("h00")) node T_3075 = or(T_3071, T_3072) node T_3076 = bit(T_3075, 1) node T_3077 = cat(T_3074, T_3076) node tgtPageUpdate = cat(T_3069, T_3077) node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) node pageReplEn = or(idxPageReplEn, tgtPageReplEn) node T_3083 = and(r_btb_update.valid, doPageRepl) reg T_3085 : UInt<3>, clock, reset onreset T_3085 := UInt<3>("h00") when T_3083 : node T_3087 = eq(T_3085, UInt<3>("h05")) node T_3089 = and(UInt<1>("h01"), T_3087) node T_3092 = addw(T_3085, UInt<1>("h01")) node T_3093 = mux(T_3089, UInt<1>("h00"), T_3092) T_3085 := T_3093 skip node T_3094 = and(T_3083, T_3087) node T_3096 = dshl(UInt<1>("h01"), T_3085) idxPageRepl := T_3096 when r_btb_update.valid : node T_3097 = eq(io.req.bits.addr, r_btb_update.bits.target) node T_3098 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) node T_3099 = or(T_593, T_903) node T_3100 = and(pageReplEn, T_3099) node T_3102 = neq(T_3100, UInt<1>("h00")) node T_3103 = or(T_598, T_908) node T_3104 = and(pageReplEn, T_3103) node T_3106 = neq(T_3104, UInt<1>("h00")) node T_3107 = or(T_603, T_913) node T_3108 = and(pageReplEn, T_3107) node T_3110 = neq(T_3108, UInt<1>("h00")) node T_3111 = or(T_608, T_918) node T_3112 = and(pageReplEn, T_3111) node T_3114 = neq(T_3112, UInt<1>("h00")) node T_3115 = or(T_613, T_923) node T_3116 = and(pageReplEn, T_3115) node T_3118 = neq(T_3116, UInt<1>("h00")) node T_3119 = or(T_618, T_928) node T_3120 = and(pageReplEn, T_3119) node T_3122 = neq(T_3120, UInt<1>("h00")) node T_3123 = or(T_623, T_933) node T_3124 = and(pageReplEn, T_3123) node T_3126 = neq(T_3124, UInt<1>("h00")) node T_3127 = or(T_628, T_938) node T_3128 = and(pageReplEn, T_3127) node T_3130 = neq(T_3128, UInt<1>("h00")) node T_3131 = or(T_633, T_943) node T_3132 = and(pageReplEn, T_3131) node T_3134 = neq(T_3132, UInt<1>("h00")) node T_3135 = or(T_638, T_948) node T_3136 = and(pageReplEn, T_3135) node T_3138 = neq(T_3136, UInt<1>("h00")) node T_3139 = or(T_643, T_953) node T_3140 = and(pageReplEn, T_3139) node T_3142 = neq(T_3140, UInt<1>("h00")) node T_3143 = or(T_648, T_958) node T_3144 = and(pageReplEn, T_3143) node T_3146 = neq(T_3144, UInt<1>("h00")) node T_3147 = or(T_653, T_963) node T_3148 = and(pageReplEn, T_3147) node T_3150 = neq(T_3148, UInt<1>("h00")) node T_3151 = or(T_658, T_968) node T_3152 = and(pageReplEn, T_3151) node T_3154 = neq(T_3152, UInt<1>("h00")) node T_3155 = or(T_663, T_973) node T_3156 = and(pageReplEn, T_3155) node T_3158 = neq(T_3156, UInt<1>("h00")) node T_3159 = or(T_668, T_978) node T_3160 = and(pageReplEn, T_3159) node T_3162 = neq(T_3160, UInt<1>("h00")) node T_3163 = or(T_673, T_983) node T_3164 = and(pageReplEn, T_3163) node T_3166 = neq(T_3164, UInt<1>("h00")) node T_3167 = or(T_678, T_988) node T_3168 = and(pageReplEn, T_3167) node T_3170 = neq(T_3168, UInt<1>("h00")) node T_3171 = or(T_683, T_993) node T_3172 = and(pageReplEn, T_3171) node T_3174 = neq(T_3172, UInt<1>("h00")) node T_3175 = or(T_688, T_998) node T_3176 = and(pageReplEn, T_3175) node T_3178 = neq(T_3176, UInt<1>("h00")) node T_3179 = or(T_693, T_1003) node T_3180 = and(pageReplEn, T_3179) node T_3182 = neq(T_3180, UInt<1>("h00")) node T_3183 = or(T_698, T_1008) node T_3184 = and(pageReplEn, T_3183) node T_3186 = neq(T_3184, UInt<1>("h00")) node T_3187 = or(T_703, T_1013) node T_3188 = and(pageReplEn, T_3187) node T_3190 = neq(T_3188, UInt<1>("h00")) node T_3191 = or(T_708, T_1018) node T_3192 = and(pageReplEn, T_3191) node T_3194 = neq(T_3192, UInt<1>("h00")) node T_3195 = or(T_713, T_1023) node T_3196 = and(pageReplEn, T_3195) node T_3198 = neq(T_3196, UInt<1>("h00")) node T_3199 = or(T_718, T_1028) node T_3200 = and(pageReplEn, T_3199) node T_3202 = neq(T_3200, UInt<1>("h00")) node T_3203 = or(T_723, T_1033) node T_3204 = and(pageReplEn, T_3203) node T_3206 = neq(T_3204, UInt<1>("h00")) node T_3207 = or(T_728, T_1038) node T_3208 = and(pageReplEn, T_3207) node T_3210 = neq(T_3208, UInt<1>("h00")) node T_3211 = or(T_733, T_1043) node T_3212 = and(pageReplEn, T_3211) node T_3214 = neq(T_3212, UInt<1>("h00")) node T_3215 = or(T_738, T_1048) node T_3216 = and(pageReplEn, T_3215) node T_3218 = neq(T_3216, UInt<1>("h00")) node T_3219 = or(T_743, T_1053) node T_3220 = and(pageReplEn, T_3219) node T_3222 = neq(T_3220, UInt<1>("h00")) node T_3223 = or(T_748, T_1058) node T_3224 = and(pageReplEn, T_3223) node T_3226 = neq(T_3224, UInt<1>("h00")) node T_3227 = or(T_753, T_1063) node T_3228 = and(pageReplEn, T_3227) node T_3230 = neq(T_3228, UInt<1>("h00")) node T_3231 = or(T_758, T_1068) node T_3232 = and(pageReplEn, T_3231) node T_3234 = neq(T_3232, UInt<1>("h00")) node T_3235 = or(T_763, T_1073) node T_3236 = and(pageReplEn, T_3235) node T_3238 = neq(T_3236, UInt<1>("h00")) node T_3239 = or(T_768, T_1078) node T_3240 = and(pageReplEn, T_3239) node T_3242 = neq(T_3240, UInt<1>("h00")) node T_3243 = or(T_773, T_1083) node T_3244 = and(pageReplEn, T_3243) node T_3246 = neq(T_3244, UInt<1>("h00")) node T_3247 = or(T_778, T_1088) node T_3248 = and(pageReplEn, T_3247) node T_3250 = neq(T_3248, UInt<1>("h00")) node T_3251 = or(T_783, T_1093) node T_3252 = and(pageReplEn, T_3251) node T_3254 = neq(T_3252, UInt<1>("h00")) node T_3255 = or(T_788, T_1098) node T_3256 = and(pageReplEn, T_3255) node T_3258 = neq(T_3256, UInt<1>("h00")) node T_3259 = or(T_793, T_1103) node T_3260 = and(pageReplEn, T_3259) node T_3262 = neq(T_3260, UInt<1>("h00")) node T_3263 = or(T_798, T_1108) node T_3264 = and(pageReplEn, T_3263) node T_3266 = neq(T_3264, UInt<1>("h00")) node T_3267 = or(T_803, T_1113) node T_3268 = and(pageReplEn, T_3267) node T_3270 = neq(T_3268, UInt<1>("h00")) node T_3271 = or(T_808, T_1118) node T_3272 = and(pageReplEn, T_3271) node T_3274 = neq(T_3272, UInt<1>("h00")) node T_3275 = or(T_813, T_1123) node T_3276 = and(pageReplEn, T_3275) node T_3278 = neq(T_3276, UInt<1>("h00")) node T_3279 = or(T_818, T_1128) node T_3280 = and(pageReplEn, T_3279) node T_3282 = neq(T_3280, UInt<1>("h00")) node T_3283 = or(T_823, T_1133) node T_3284 = and(pageReplEn, T_3283) node T_3286 = neq(T_3284, UInt<1>("h00")) node T_3287 = or(T_828, T_1138) node T_3288 = and(pageReplEn, T_3287) node T_3290 = neq(T_3288, UInt<1>("h00")) node T_3291 = or(T_833, T_1143) node T_3292 = and(pageReplEn, T_3291) node T_3294 = neq(T_3292, UInt<1>("h00")) node T_3295 = or(T_838, T_1148) node T_3296 = and(pageReplEn, T_3295) node T_3298 = neq(T_3296, UInt<1>("h00")) node T_3299 = or(T_843, T_1153) node T_3300 = and(pageReplEn, T_3299) node T_3302 = neq(T_3300, UInt<1>("h00")) node T_3303 = or(T_848, T_1158) node T_3304 = and(pageReplEn, T_3303) node T_3306 = neq(T_3304, UInt<1>("h00")) node T_3307 = or(T_853, T_1163) node T_3308 = and(pageReplEn, T_3307) node T_3310 = neq(T_3308, UInt<1>("h00")) node T_3311 = or(T_858, T_1168) node T_3312 = and(pageReplEn, T_3311) node T_3314 = neq(T_3312, UInt<1>("h00")) node T_3315 = or(T_863, T_1173) node T_3316 = and(pageReplEn, T_3315) node T_3318 = neq(T_3316, UInt<1>("h00")) node T_3319 = or(T_868, T_1178) node T_3320 = and(pageReplEn, T_3319) node T_3322 = neq(T_3320, UInt<1>("h00")) node T_3323 = or(T_873, T_1183) node T_3324 = and(pageReplEn, T_3323) node T_3326 = neq(T_3324, UInt<1>("h00")) node T_3327 = or(T_878, T_1188) node T_3328 = and(pageReplEn, T_3327) node T_3330 = neq(T_3328, UInt<1>("h00")) node T_3331 = or(T_883, T_1193) node T_3332 = and(pageReplEn, T_3331) node T_3334 = neq(T_3332, UInt<1>("h00")) node T_3335 = or(T_888, T_1198) node T_3336 = and(pageReplEn, T_3335) node T_3338 = neq(T_3336, UInt<1>("h00")) node T_3339 = or(T_893, T_1203) node T_3340 = and(pageReplEn, T_3339) node T_3342 = neq(T_3340, UInt<1>("h00")) node T_3343 = or(T_898, T_1208) node T_3344 = and(pageReplEn, T_3343) node T_3346 = neq(T_3344, UInt<1>("h00")) wire T_3348 : UInt<1>[62] T_3348[0] := T_3102 T_3348[1] := T_3106 T_3348[2] := T_3110 T_3348[3] := T_3114 T_3348[4] := T_3118 T_3348[5] := T_3122 T_3348[6] := T_3126 T_3348[7] := T_3130 T_3348[8] := T_3134 T_3348[9] := T_3138 T_3348[10] := T_3142 T_3348[11] := T_3146 T_3348[12] := T_3150 T_3348[13] := T_3154 T_3348[14] := T_3158 T_3348[15] := T_3162 T_3348[16] := T_3166 T_3348[17] := T_3170 T_3348[18] := T_3174 T_3348[19] := T_3178 T_3348[20] := T_3182 T_3348[21] := T_3186 T_3348[22] := T_3190 T_3348[23] := T_3194 T_3348[24] := T_3198 T_3348[25] := T_3202 T_3348[26] := T_3206 T_3348[27] := T_3210 T_3348[28] := T_3214 T_3348[29] := T_3218 T_3348[30] := T_3222 T_3348[31] := T_3226 T_3348[32] := T_3230 T_3348[33] := T_3234 T_3348[34] := T_3238 T_3348[35] := T_3242 T_3348[36] := T_3246 T_3348[37] := T_3250 T_3348[38] := T_3254 T_3348[39] := T_3258 T_3348[40] := T_3262 T_3348[41] := T_3266 T_3348[42] := T_3270 T_3348[43] := T_3274 T_3348[44] := T_3278 T_3348[45] := T_3282 T_3348[46] := T_3286 T_3348[47] := T_3290 T_3348[48] := T_3294 T_3348[49] := T_3298 T_3348[50] := T_3302 T_3348[51] := T_3306 T_3348[52] := T_3310 T_3348[53] := T_3314 T_3348[54] := T_3318 T_3348[55] := T_3322 T_3348[56] := T_3326 T_3348[57] := T_3330 T_3348[58] := T_3334 T_3348[59] := T_3338 T_3348[60] := T_3342 T_3348[61] := T_3346 node T_3412 = cat(T_3348[60], T_3348[59]) node T_3413 = cat(T_3348[61], T_3412) node T_3414 = cat(T_3348[58], T_3348[57]) node T_3415 = cat(T_3348[56], T_3348[55]) node T_3416 = cat(T_3414, T_3415) node T_3417 = cat(T_3413, T_3416) node T_3418 = cat(T_3348[54], T_3348[53]) node T_3419 = cat(T_3348[52], T_3348[51]) node T_3420 = cat(T_3418, T_3419) node T_3421 = cat(T_3348[50], T_3348[49]) node T_3422 = cat(T_3348[48], T_3348[47]) node T_3423 = cat(T_3421, T_3422) node T_3424 = cat(T_3420, T_3423) node T_3425 = cat(T_3417, T_3424) node T_3426 = cat(T_3348[46], T_3348[45]) node T_3427 = cat(T_3348[44], T_3348[43]) node T_3428 = cat(T_3426, T_3427) node T_3429 = cat(T_3348[42], T_3348[41]) node T_3430 = cat(T_3348[40], T_3348[39]) node T_3431 = cat(T_3429, T_3430) node T_3432 = cat(T_3428, T_3431) node T_3433 = cat(T_3348[38], T_3348[37]) node T_3434 = cat(T_3348[36], T_3348[35]) node T_3435 = cat(T_3433, T_3434) node T_3436 = cat(T_3348[34], T_3348[33]) node T_3437 = cat(T_3348[32], T_3348[31]) node T_3438 = cat(T_3436, T_3437) node T_3439 = cat(T_3435, T_3438) node T_3440 = cat(T_3432, T_3439) node T_3441 = cat(T_3425, T_3440) node T_3442 = cat(T_3348[29], T_3348[28]) node T_3443 = cat(T_3348[30], T_3442) node T_3444 = cat(T_3348[27], T_3348[26]) node T_3445 = cat(T_3348[25], T_3348[24]) node T_3446 = cat(T_3444, T_3445) node T_3447 = cat(T_3443, T_3446) node T_3448 = cat(T_3348[23], T_3348[22]) node T_3449 = cat(T_3348[21], T_3348[20]) node T_3450 = cat(T_3448, T_3449) node T_3451 = cat(T_3348[19], T_3348[18]) node T_3452 = cat(T_3348[17], T_3348[16]) node T_3453 = cat(T_3451, T_3452) node T_3454 = cat(T_3450, T_3453) node T_3455 = cat(T_3447, T_3454) node T_3456 = cat(T_3348[15], T_3348[14]) node T_3457 = cat(T_3348[13], T_3348[12]) node T_3458 = cat(T_3456, T_3457) node T_3459 = cat(T_3348[11], T_3348[10]) node T_3460 = cat(T_3348[9], T_3348[8]) node T_3461 = cat(T_3459, T_3460) node T_3462 = cat(T_3458, T_3461) node T_3463 = cat(T_3348[7], T_3348[6]) node T_3464 = cat(T_3348[5], T_3348[4]) node T_3465 = cat(T_3463, T_3464) node T_3466 = cat(T_3348[3], T_3348[2]) node T_3467 = cat(T_3348[1], T_3348[0]) node T_3468 = cat(T_3466, T_3467) node T_3469 = cat(T_3465, T_3468) node T_3470 = cat(T_3462, T_3469) node T_3471 = cat(T_3455, T_3470) node T_3472 = cat(T_3441, T_3471) node T_3474 = dshl(UInt<1>("h01"), T_3098) node T_3475 = not(T_3472) node T_3476 = and(idxValid, T_3475) node T_3477 = or(T_3476, T_3474) idxValid := T_3477 infer accessor T_3478 = idxs[T_3098] T_3478 := r_btb_update.bits.pc infer accessor T_3479 = tgts[T_3098] T_3479 := io.req.bits.addr infer accessor T_3480 = idxPages[T_3098] T_3480 := idxPageUpdate infer accessor T_3481 = tgtPages[T_3098] T_3481 := tgtPageUpdate infer accessor T_3482 = useRAS[T_3098] T_3482 := r_btb_update.bits.isReturn infer accessor T_3483 = isJump[T_3098] T_3483 := r_btb_update.bits.isJump infer accessor T_3484 = brIdx[T_3098] T_3484 := UInt<1>("h00") node T_3487 = cat(UInt<2>("h01"), UInt<2>("h01")) node T_3488 = cat(UInt<2>("h01"), T_3487) node T_3489 = and(idxPageUpdateOH, T_3488) node T_3491 = neq(T_3489, UInt<1>("h00")) node T_3492 = mux(T_3491, doIdxPageRepl, doTgtPageRepl) node T_3493 = shr(r_btb_update.bits.pc, 12) node T_3494 = shr(io.req.bits.addr, 12) node T_3495 = mux(T_3491, T_3493, T_3494) node T_3496 = bit(pageReplEn, 0) node T_3497 = and(T_3492, T_3496) when T_3497 : infer accessor T_3499 = pages[UInt<1>("h00")] T_3499 := T_3495 skip node T_3500 = bit(pageReplEn, 2) node T_3501 = and(T_3492, T_3500) when T_3501 : infer accessor T_3503 = pages[UInt<2>("h02")] T_3503 := T_3495 skip node T_3504 = bit(pageReplEn, 4) node T_3505 = and(T_3492, T_3504) when T_3505 : infer accessor T_3507 = pages[UInt<3>("h04")] T_3507 := T_3495 skip node T_3508 = mux(T_3491, doTgtPageRepl, doIdxPageRepl) node T_3509 = shr(io.req.bits.addr, 12) node T_3510 = shr(r_btb_update.bits.pc, 12) node T_3511 = mux(T_3491, T_3509, T_3510) node T_3512 = bit(pageReplEn, 1) node T_3513 = and(T_3508, T_3512) when T_3513 : infer accessor T_3515 = pages[UInt<1>("h01")] T_3515 := T_3511 skip node T_3516 = bit(pageReplEn, 3) node T_3517 = and(T_3508, T_3516) when T_3517 : infer accessor T_3519 = pages[UInt<2>("h03")] T_3519 := T_3511 skip node T_3520 = bit(pageReplEn, 5) node T_3521 = and(T_3508, T_3520) when T_3521 : infer accessor T_3523 = pages[UInt<3>("h05")] T_3523 := T_3511 skip when doPageRepl : node T_3524 = or(pageValid, pageReplEn) pageValid := T_3524 skip skip when io.invalidate : idxValid := UInt<1>("h00") pageValid := UInt<1>("h00") skip node T_3528 = neq(hits, UInt<1>("h00")) io.resp.valid := T_3528 io.resp.bits.taken := io.resp.valid node T_3529 = bit(hits, 0) node T_3530 = bit(hits, 1) node T_3531 = bit(hits, 2) node T_3532 = bit(hits, 3) node T_3533 = bit(hits, 4) node T_3534 = bit(hits, 5) node T_3535 = bit(hits, 6) node T_3536 = bit(hits, 7) node T_3537 = bit(hits, 8) node T_3538 = bit(hits, 9) node T_3539 = bit(hits, 10) node T_3540 = bit(hits, 11) node T_3541 = bit(hits, 12) node T_3542 = bit(hits, 13) node T_3543 = bit(hits, 14) node T_3544 = bit(hits, 15) node T_3545 = bit(hits, 16) node T_3546 = bit(hits, 17) node T_3547 = bit(hits, 18) node T_3548 = bit(hits, 19) node T_3549 = bit(hits, 20) node T_3550 = bit(hits, 21) node T_3551 = bit(hits, 22) node T_3552 = bit(hits, 23) node T_3553 = bit(hits, 24) node T_3554 = bit(hits, 25) node T_3555 = bit(hits, 26) node T_3556 = bit(hits, 27) node T_3557 = bit(hits, 28) node T_3558 = bit(hits, 29) node T_3559 = bit(hits, 30) node T_3560 = bit(hits, 31) node T_3561 = bit(hits, 32) node T_3562 = bit(hits, 33) node T_3563 = bit(hits, 34) node T_3564 = bit(hits, 35) node T_3565 = bit(hits, 36) node T_3566 = bit(hits, 37) node T_3567 = bit(hits, 38) node T_3568 = bit(hits, 39) node T_3569 = bit(hits, 40) node T_3570 = bit(hits, 41) node T_3571 = bit(hits, 42) node T_3572 = bit(hits, 43) node T_3573 = bit(hits, 44) node T_3574 = bit(hits, 45) node T_3575 = bit(hits, 46) node T_3576 = bit(hits, 47) node T_3577 = bit(hits, 48) node T_3578 = bit(hits, 49) node T_3579 = bit(hits, 50) node T_3580 = bit(hits, 51) node T_3581 = bit(hits, 52) node T_3582 = bit(hits, 53) node T_3583 = bit(hits, 54) node T_3584 = bit(hits, 55) node T_3585 = bit(hits, 56) node T_3586 = bit(hits, 57) node T_3587 = bit(hits, 58) node T_3588 = bit(hits, 59) node T_3589 = bit(hits, 60) node T_3590 = bit(hits, 61) node T_3592 = mux(T_3529, T_903, UInt<1>("h00")) node T_3594 = mux(T_3530, T_908, UInt<1>("h00")) node T_3596 = mux(T_3531, T_913, UInt<1>("h00")) node T_3598 = mux(T_3532, T_918, UInt<1>("h00")) node T_3600 = mux(T_3533, T_923, UInt<1>("h00")) node T_3602 = mux(T_3534, T_928, UInt<1>("h00")) node T_3604 = mux(T_3535, T_933, UInt<1>("h00")) node T_3606 = mux(T_3536, T_938, UInt<1>("h00")) node T_3608 = mux(T_3537, T_943, UInt<1>("h00")) node T_3610 = mux(T_3538, T_948, UInt<1>("h00")) node T_3612 = mux(T_3539, T_953, UInt<1>("h00")) node T_3614 = mux(T_3540, T_958, UInt<1>("h00")) node T_3616 = mux(T_3541, T_963, UInt<1>("h00")) node T_3618 = mux(T_3542, T_968, UInt<1>("h00")) node T_3620 = mux(T_3543, T_973, UInt<1>("h00")) node T_3622 = mux(T_3544, T_978, UInt<1>("h00")) node T_3624 = mux(T_3545, T_983, UInt<1>("h00")) node T_3626 = mux(T_3546, T_988, UInt<1>("h00")) node T_3628 = mux(T_3547, T_993, UInt<1>("h00")) node T_3630 = mux(T_3548, T_998, UInt<1>("h00")) node T_3632 = mux(T_3549, T_1003, UInt<1>("h00")) node T_3634 = mux(T_3550, T_1008, UInt<1>("h00")) node T_3636 = mux(T_3551, T_1013, UInt<1>("h00")) node T_3638 = mux(T_3552, T_1018, UInt<1>("h00")) node T_3640 = mux(T_3553, T_1023, UInt<1>("h00")) node T_3642 = mux(T_3554, T_1028, UInt<1>("h00")) node T_3644 = mux(T_3555, T_1033, UInt<1>("h00")) node T_3646 = mux(T_3556, T_1038, UInt<1>("h00")) node T_3648 = mux(T_3557, T_1043, UInt<1>("h00")) node T_3650 = mux(T_3558, T_1048, UInt<1>("h00")) node T_3652 = mux(T_3559, T_1053, UInt<1>("h00")) node T_3654 = mux(T_3560, T_1058, UInt<1>("h00")) node T_3656 = mux(T_3561, T_1063, UInt<1>("h00")) node T_3658 = mux(T_3562, T_1068, UInt<1>("h00")) node T_3660 = mux(T_3563, T_1073, UInt<1>("h00")) node T_3662 = mux(T_3564, T_1078, UInt<1>("h00")) node T_3664 = mux(T_3565, T_1083, UInt<1>("h00")) node T_3666 = mux(T_3566, T_1088, UInt<1>("h00")) node T_3668 = mux(T_3567, T_1093, UInt<1>("h00")) node T_3670 = mux(T_3568, T_1098, UInt<1>("h00")) node T_3672 = mux(T_3569, T_1103, UInt<1>("h00")) node T_3674 = mux(T_3570, T_1108, UInt<1>("h00")) node T_3676 = mux(T_3571, T_1113, UInt<1>("h00")) node T_3678 = mux(T_3572, T_1118, UInt<1>("h00")) node T_3680 = mux(T_3573, T_1123, UInt<1>("h00")) node T_3682 = mux(T_3574, T_1128, UInt<1>("h00")) node T_3684 = mux(T_3575, T_1133, UInt<1>("h00")) node T_3686 = mux(T_3576, T_1138, UInt<1>("h00")) node T_3688 = mux(T_3577, T_1143, UInt<1>("h00")) node T_3690 = mux(T_3578, T_1148, UInt<1>("h00")) node T_3692 = mux(T_3579, T_1153, UInt<1>("h00")) node T_3694 = mux(T_3580, T_1158, UInt<1>("h00")) node T_3696 = mux(T_3581, T_1163, UInt<1>("h00")) node T_3698 = mux(T_3582, T_1168, UInt<1>("h00")) node T_3700 = mux(T_3583, T_1173, UInt<1>("h00")) node T_3702 = mux(T_3584, T_1178, UInt<1>("h00")) node T_3704 = mux(T_3585, T_1183, UInt<1>("h00")) node T_3706 = mux(T_3586, T_1188, UInt<1>("h00")) node T_3708 = mux(T_3587, T_1193, UInt<1>("h00")) node T_3710 = mux(T_3588, T_1198, UInt<1>("h00")) node T_3712 = mux(T_3589, T_1203, UInt<1>("h00")) node T_3714 = mux(T_3590, T_1208, UInt<1>("h00")) node T_3716 = or(T_3592, T_3594) node T_3717 = or(T_3716, T_3596) node T_3718 = or(T_3717, T_3598) node T_3719 = or(T_3718, T_3600) node T_3720 = or(T_3719, T_3602) node T_3721 = or(T_3720, T_3604) node T_3722 = or(T_3721, T_3606) node T_3723 = or(T_3722, T_3608) node T_3724 = or(T_3723, T_3610) node T_3725 = or(T_3724, T_3612) node T_3726 = or(T_3725, T_3614) node T_3727 = or(T_3726, T_3616) node T_3728 = or(T_3727, T_3618) node T_3729 = or(T_3728, T_3620) node T_3730 = or(T_3729, T_3622) node T_3731 = or(T_3730, T_3624) node T_3732 = or(T_3731, T_3626) node T_3733 = or(T_3732, T_3628) node T_3734 = or(T_3733, T_3630) node T_3735 = or(T_3734, T_3632) node T_3736 = or(T_3735, T_3634) node T_3737 = or(T_3736, T_3636) node T_3738 = or(T_3737, T_3638) node T_3739 = or(T_3738, T_3640) node T_3740 = or(T_3739, T_3642) node T_3741 = or(T_3740, T_3644) node T_3742 = or(T_3741, T_3646) node T_3743 = or(T_3742, T_3648) node T_3744 = or(T_3743, T_3650) node T_3745 = or(T_3744, T_3652) node T_3746 = or(T_3745, T_3654) node T_3747 = or(T_3746, T_3656) node T_3748 = or(T_3747, T_3658) node T_3749 = or(T_3748, T_3660) node T_3750 = or(T_3749, T_3662) node T_3751 = or(T_3750, T_3664) node T_3752 = or(T_3751, T_3666) node T_3753 = or(T_3752, T_3668) node T_3754 = or(T_3753, T_3670) node T_3755 = or(T_3754, T_3672) node T_3756 = or(T_3755, T_3674) node T_3757 = or(T_3756, T_3676) node T_3758 = or(T_3757, T_3678) node T_3759 = or(T_3758, T_3680) node T_3760 = or(T_3759, T_3682) node T_3761 = or(T_3760, T_3684) node T_3762 = or(T_3761, T_3686) node T_3763 = or(T_3762, T_3688) node T_3764 = or(T_3763, T_3690) node T_3765 = or(T_3764, T_3692) node T_3766 = or(T_3765, T_3694) node T_3767 = or(T_3766, T_3696) node T_3768 = or(T_3767, T_3698) node T_3769 = or(T_3768, T_3700) node T_3770 = or(T_3769, T_3702) node T_3771 = or(T_3770, T_3704) node T_3772 = or(T_3771, T_3706) node T_3773 = or(T_3772, T_3708) node T_3774 = or(T_3773, T_3710) node T_3775 = or(T_3774, T_3712) node T_3776 = or(T_3775, T_3714) wire T_3777 : UInt<6> T_3777 := UInt<1>("h00") T_3777 := T_3776 node T_3779 = bit(T_3777, 0) node T_3780 = bit(T_3777, 1) node T_3781 = bit(T_3777, 2) node T_3782 = bit(T_3777, 3) node T_3783 = bit(T_3777, 4) node T_3784 = bit(T_3777, 5) infer accessor T_3786 = pages[UInt<1>("h00")] infer accessor T_3788 = pages[UInt<1>("h01")] infer accessor T_3790 = pages[UInt<2>("h02")] infer accessor T_3792 = pages[UInt<2>("h03")] infer accessor T_3794 = pages[UInt<3>("h04")] infer accessor T_3796 = pages[UInt<3>("h05")] node T_3798 = mux(T_3779, T_3786, UInt<1>("h00")) node T_3800 = mux(T_3780, T_3788, UInt<1>("h00")) node T_3802 = mux(T_3781, T_3790, UInt<1>("h00")) node T_3804 = mux(T_3782, T_3792, UInt<1>("h00")) node T_3806 = mux(T_3783, T_3794, UInt<1>("h00")) node T_3808 = mux(T_3784, T_3796, UInt<1>("h00")) node T_3810 = or(T_3798, T_3800) node T_3811 = or(T_3810, T_3802) node T_3812 = or(T_3811, T_3804) node T_3813 = or(T_3812, T_3806) node T_3814 = or(T_3813, T_3808) wire T_3815 : UInt<27> T_3815 := UInt<1>("h00") T_3815 := T_3814 node T_3817 = bit(hits, 0) node T_3818 = bit(hits, 1) node T_3819 = bit(hits, 2) node T_3820 = bit(hits, 3) node T_3821 = bit(hits, 4) node T_3822 = bit(hits, 5) node T_3823 = bit(hits, 6) node T_3824 = bit(hits, 7) node T_3825 = bit(hits, 8) node T_3826 = bit(hits, 9) node T_3827 = bit(hits, 10) node T_3828 = bit(hits, 11) node T_3829 = bit(hits, 12) node T_3830 = bit(hits, 13) node T_3831 = bit(hits, 14) node T_3832 = bit(hits, 15) node T_3833 = bit(hits, 16) node T_3834 = bit(hits, 17) node T_3835 = bit(hits, 18) node T_3836 = bit(hits, 19) node T_3837 = bit(hits, 20) node T_3838 = bit(hits, 21) node T_3839 = bit(hits, 22) node T_3840 = bit(hits, 23) node T_3841 = bit(hits, 24) node T_3842 = bit(hits, 25) node T_3843 = bit(hits, 26) node T_3844 = bit(hits, 27) node T_3845 = bit(hits, 28) node T_3846 = bit(hits, 29) node T_3847 = bit(hits, 30) node T_3848 = bit(hits, 31) node T_3849 = bit(hits, 32) node T_3850 = bit(hits, 33) node T_3851 = bit(hits, 34) node T_3852 = bit(hits, 35) node T_3853 = bit(hits, 36) node T_3854 = bit(hits, 37) node T_3855 = bit(hits, 38) node T_3856 = bit(hits, 39) node T_3857 = bit(hits, 40) node T_3858 = bit(hits, 41) node T_3859 = bit(hits, 42) node T_3860 = bit(hits, 43) node T_3861 = bit(hits, 44) node T_3862 = bit(hits, 45) node T_3863 = bit(hits, 46) node T_3864 = bit(hits, 47) node T_3865 = bit(hits, 48) node T_3866 = bit(hits, 49) node T_3867 = bit(hits, 50) node T_3868 = bit(hits, 51) node T_3869 = bit(hits, 52) node T_3870 = bit(hits, 53) node T_3871 = bit(hits, 54) node T_3872 = bit(hits, 55) node T_3873 = bit(hits, 56) node T_3874 = bit(hits, 57) node T_3875 = bit(hits, 58) node T_3876 = bit(hits, 59) node T_3877 = bit(hits, 60) node T_3878 = bit(hits, 61) infer accessor T_3880 = tgts[UInt<1>("h00")] infer accessor T_3882 = tgts[UInt<1>("h01")] infer accessor T_3884 = tgts[UInt<2>("h02")] infer accessor T_3886 = tgts[UInt<2>("h03")] infer accessor T_3888 = tgts[UInt<3>("h04")] infer accessor T_3890 = tgts[UInt<3>("h05")] infer accessor T_3892 = tgts[UInt<3>("h06")] infer accessor T_3894 = tgts[UInt<3>("h07")] infer accessor T_3896 = tgts[UInt<4>("h08")] infer accessor T_3898 = tgts[UInt<4>("h09")] infer accessor T_3900 = tgts[UInt<4>("h0a")] infer accessor T_3902 = tgts[UInt<4>("h0b")] infer accessor T_3904 = tgts[UInt<4>("h0c")] infer accessor T_3906 = tgts[UInt<4>("h0d")] infer accessor T_3908 = tgts[UInt<4>("h0e")] infer accessor T_3910 = tgts[UInt<4>("h0f")] infer accessor T_3912 = tgts[UInt<5>("h010")] infer accessor T_3914 = tgts[UInt<5>("h011")] infer accessor T_3916 = tgts[UInt<5>("h012")] infer accessor T_3918 = tgts[UInt<5>("h013")] infer accessor T_3920 = tgts[UInt<5>("h014")] infer accessor T_3922 = tgts[UInt<5>("h015")] infer accessor T_3924 = tgts[UInt<5>("h016")] infer accessor T_3926 = tgts[UInt<5>("h017")] infer accessor T_3928 = tgts[UInt<5>("h018")] infer accessor T_3930 = tgts[UInt<5>("h019")] infer accessor T_3932 = tgts[UInt<5>("h01a")] infer accessor T_3934 = tgts[UInt<5>("h01b")] infer accessor T_3936 = tgts[UInt<5>("h01c")] infer accessor T_3938 = tgts[UInt<5>("h01d")] infer accessor T_3940 = tgts[UInt<5>("h01e")] infer accessor T_3942 = tgts[UInt<5>("h01f")] infer accessor T_3944 = tgts[UInt<6>("h020")] infer accessor T_3946 = tgts[UInt<6>("h021")] infer accessor T_3948 = tgts[UInt<6>("h022")] infer accessor T_3950 = tgts[UInt<6>("h023")] infer accessor T_3952 = tgts[UInt<6>("h024")] infer accessor T_3954 = tgts[UInt<6>("h025")] infer accessor T_3956 = tgts[UInt<6>("h026")] infer accessor T_3958 = tgts[UInt<6>("h027")] infer accessor T_3960 = tgts[UInt<6>("h028")] infer accessor T_3962 = tgts[UInt<6>("h029")] infer accessor T_3964 = tgts[UInt<6>("h02a")] infer accessor T_3966 = tgts[UInt<6>("h02b")] infer accessor T_3968 = tgts[UInt<6>("h02c")] infer accessor T_3970 = tgts[UInt<6>("h02d")] infer accessor T_3972 = tgts[UInt<6>("h02e")] infer accessor T_3974 = tgts[UInt<6>("h02f")] infer accessor T_3976 = tgts[UInt<6>("h030")] infer accessor T_3978 = tgts[UInt<6>("h031")] infer accessor T_3980 = tgts[UInt<6>("h032")] infer accessor T_3982 = tgts[UInt<6>("h033")] infer accessor T_3984 = tgts[UInt<6>("h034")] infer accessor T_3986 = tgts[UInt<6>("h035")] infer accessor T_3988 = tgts[UInt<6>("h036")] infer accessor T_3990 = tgts[UInt<6>("h037")] infer accessor T_3992 = tgts[UInt<6>("h038")] infer accessor T_3994 = tgts[UInt<6>("h039")] infer accessor T_3996 = tgts[UInt<6>("h03a")] infer accessor T_3998 = tgts[UInt<6>("h03b")] infer accessor T_4000 = tgts[UInt<6>("h03c")] infer accessor T_4002 = tgts[UInt<6>("h03d")] node T_4004 = mux(T_3817, T_3880, UInt<1>("h00")) node T_4006 = mux(T_3818, T_3882, UInt<1>("h00")) node T_4008 = mux(T_3819, T_3884, UInt<1>("h00")) node T_4010 = mux(T_3820, T_3886, UInt<1>("h00")) node T_4012 = mux(T_3821, T_3888, UInt<1>("h00")) node T_4014 = mux(T_3822, T_3890, UInt<1>("h00")) node T_4016 = mux(T_3823, T_3892, UInt<1>("h00")) node T_4018 = mux(T_3824, T_3894, UInt<1>("h00")) node T_4020 = mux(T_3825, T_3896, UInt<1>("h00")) node T_4022 = mux(T_3826, T_3898, UInt<1>("h00")) node T_4024 = mux(T_3827, T_3900, UInt<1>("h00")) node T_4026 = mux(T_3828, T_3902, UInt<1>("h00")) node T_4028 = mux(T_3829, T_3904, UInt<1>("h00")) node T_4030 = mux(T_3830, T_3906, UInt<1>("h00")) node T_4032 = mux(T_3831, T_3908, UInt<1>("h00")) node T_4034 = mux(T_3832, T_3910, UInt<1>("h00")) node T_4036 = mux(T_3833, T_3912, UInt<1>("h00")) node T_4038 = mux(T_3834, T_3914, UInt<1>("h00")) node T_4040 = mux(T_3835, T_3916, UInt<1>("h00")) node T_4042 = mux(T_3836, T_3918, UInt<1>("h00")) node T_4044 = mux(T_3837, T_3920, UInt<1>("h00")) node T_4046 = mux(T_3838, T_3922, UInt<1>("h00")) node T_4048 = mux(T_3839, T_3924, UInt<1>("h00")) node T_4050 = mux(T_3840, T_3926, UInt<1>("h00")) node T_4052 = mux(T_3841, T_3928, UInt<1>("h00")) node T_4054 = mux(T_3842, T_3930, UInt<1>("h00")) node T_4056 = mux(T_3843, T_3932, UInt<1>("h00")) node T_4058 = mux(T_3844, T_3934, UInt<1>("h00")) node T_4060 = mux(T_3845, T_3936, UInt<1>("h00")) node T_4062 = mux(T_3846, T_3938, UInt<1>("h00")) node T_4064 = mux(T_3847, T_3940, UInt<1>("h00")) node T_4066 = mux(T_3848, T_3942, UInt<1>("h00")) node T_4068 = mux(T_3849, T_3944, UInt<1>("h00")) node T_4070 = mux(T_3850, T_3946, UInt<1>("h00")) node T_4072 = mux(T_3851, T_3948, UInt<1>("h00")) node T_4074 = mux(T_3852, T_3950, UInt<1>("h00")) node T_4076 = mux(T_3853, T_3952, UInt<1>("h00")) node T_4078 = mux(T_3854, T_3954, UInt<1>("h00")) node T_4080 = mux(T_3855, T_3956, UInt<1>("h00")) node T_4082 = mux(T_3856, T_3958, UInt<1>("h00")) node T_4084 = mux(T_3857, T_3960, UInt<1>("h00")) node T_4086 = mux(T_3858, T_3962, UInt<1>("h00")) node T_4088 = mux(T_3859, T_3964, UInt<1>("h00")) node T_4090 = mux(T_3860, T_3966, UInt<1>("h00")) node T_4092 = mux(T_3861, T_3968, UInt<1>("h00")) node T_4094 = mux(T_3862, T_3970, UInt<1>("h00")) node T_4096 = mux(T_3863, T_3972, UInt<1>("h00")) node T_4098 = mux(T_3864, T_3974, UInt<1>("h00")) node T_4100 = mux(T_3865, T_3976, UInt<1>("h00")) node T_4102 = mux(T_3866, T_3978, UInt<1>("h00")) node T_4104 = mux(T_3867, T_3980, UInt<1>("h00")) node T_4106 = mux(T_3868, T_3982, UInt<1>("h00")) node T_4108 = mux(T_3869, T_3984, UInt<1>("h00")) node T_4110 = mux(T_3870, T_3986, UInt<1>("h00")) node T_4112 = mux(T_3871, T_3988, UInt<1>("h00")) node T_4114 = mux(T_3872, T_3990, UInt<1>("h00")) node T_4116 = mux(T_3873, T_3992, UInt<1>("h00")) node T_4118 = mux(T_3874, T_3994, UInt<1>("h00")) node T_4120 = mux(T_3875, T_3996, UInt<1>("h00")) node T_4122 = mux(T_3876, T_3998, UInt<1>("h00")) node T_4124 = mux(T_3877, T_4000, UInt<1>("h00")) node T_4126 = mux(T_3878, T_4002, UInt<1>("h00")) node T_4128 = or(T_4004, T_4006) node T_4129 = or(T_4128, T_4008) node T_4130 = or(T_4129, T_4010) node T_4131 = or(T_4130, T_4012) node T_4132 = or(T_4131, T_4014) node T_4133 = or(T_4132, T_4016) node T_4134 = or(T_4133, T_4018) node T_4135 = or(T_4134, T_4020) node T_4136 = or(T_4135, T_4022) node T_4137 = or(T_4136, T_4024) node T_4138 = or(T_4137, T_4026) node T_4139 = or(T_4138, T_4028) node T_4140 = or(T_4139, T_4030) node T_4141 = or(T_4140, T_4032) node T_4142 = or(T_4141, T_4034) node T_4143 = or(T_4142, T_4036) node T_4144 = or(T_4143, T_4038) node T_4145 = or(T_4144, T_4040) node T_4146 = or(T_4145, T_4042) node T_4147 = or(T_4146, T_4044) node T_4148 = or(T_4147, T_4046) node T_4149 = or(T_4148, T_4048) node T_4150 = or(T_4149, T_4050) node T_4151 = or(T_4150, T_4052) node T_4152 = or(T_4151, T_4054) node T_4153 = or(T_4152, T_4056) node T_4154 = or(T_4153, T_4058) node T_4155 = or(T_4154, T_4060) node T_4156 = or(T_4155, T_4062) node T_4157 = or(T_4156, T_4064) node T_4158 = or(T_4157, T_4066) node T_4159 = or(T_4158, T_4068) node T_4160 = or(T_4159, T_4070) node T_4161 = or(T_4160, T_4072) node T_4162 = or(T_4161, T_4074) node T_4163 = or(T_4162, T_4076) node T_4164 = or(T_4163, T_4078) node T_4165 = or(T_4164, T_4080) node T_4166 = or(T_4165, T_4082) node T_4167 = or(T_4166, T_4084) node T_4168 = or(T_4167, T_4086) node T_4169 = or(T_4168, T_4088) node T_4170 = or(T_4169, T_4090) node T_4171 = or(T_4170, T_4092) node T_4172 = or(T_4171, T_4094) node T_4173 = or(T_4172, T_4096) node T_4174 = or(T_4173, T_4098) node T_4175 = or(T_4174, T_4100) node T_4176 = or(T_4175, T_4102) node T_4177 = or(T_4176, T_4104) node T_4178 = or(T_4177, T_4106) node T_4179 = or(T_4178, T_4108) node T_4180 = or(T_4179, T_4110) node T_4181 = or(T_4180, T_4112) node T_4182 = or(T_4181, T_4114) node T_4183 = or(T_4182, T_4116) node T_4184 = or(T_4183, T_4118) node T_4185 = or(T_4184, T_4120) node T_4186 = or(T_4185, T_4122) node T_4187 = or(T_4186, T_4124) node T_4188 = or(T_4187, T_4126) wire T_4189 : UInt<12> T_4189 := UInt<1>("h00") T_4189 := T_4188 node T_4191 = cat(T_3815, T_4189) io.resp.bits.target := T_4191 node T_4192 = bits(hits, 61, 32) node T_4193 = bits(hits, 31, 0) node T_4195 = neq(T_4192, UInt<1>("h00")) node T_4196 = or(T_4192, T_4193) node T_4197 = bits(T_4196, 31, 16) node T_4198 = bits(T_4196, 15, 0) node T_4200 = neq(T_4197, UInt<1>("h00")) node T_4201 = or(T_4197, T_4198) node T_4202 = bits(T_4201, 15, 8) node T_4203 = bits(T_4201, 7, 0) node T_4205 = neq(T_4202, UInt<1>("h00")) node T_4206 = or(T_4202, T_4203) node T_4207 = bits(T_4206, 7, 4) node T_4208 = bits(T_4206, 3, 0) node T_4210 = neq(T_4207, UInt<1>("h00")) node T_4211 = or(T_4207, T_4208) node T_4212 = bits(T_4211, 3, 2) node T_4213 = bits(T_4211, 1, 0) node T_4215 = neq(T_4212, UInt<1>("h00")) node T_4216 = or(T_4212, T_4213) node T_4217 = bit(T_4216, 1) node T_4218 = cat(T_4215, T_4217) node T_4219 = cat(T_4210, T_4218) node T_4220 = cat(T_4205, T_4219) node T_4221 = cat(T_4200, T_4220) node T_4222 = cat(T_4195, T_4221) io.resp.bits.entry := T_4222 infer accessor T_4223 = brIdx[io.resp.bits.entry] io.resp.bits.bridx := T_4223 io.resp.bits.mask := UInt<1>("h01") cmem T_4227 : UInt<2>[128], clock reg T_4229 : UInt<7>, clock, reset node T_4230 = bit(hits, 0) node T_4231 = bit(hits, 1) node T_4232 = bit(hits, 2) node T_4233 = bit(hits, 3) node T_4234 = bit(hits, 4) node T_4235 = bit(hits, 5) node T_4236 = bit(hits, 6) node T_4237 = bit(hits, 7) node T_4238 = bit(hits, 8) node T_4239 = bit(hits, 9) node T_4240 = bit(hits, 10) node T_4241 = bit(hits, 11) node T_4242 = bit(hits, 12) node T_4243 = bit(hits, 13) node T_4244 = bit(hits, 14) node T_4245 = bit(hits, 15) node T_4246 = bit(hits, 16) node T_4247 = bit(hits, 17) node T_4248 = bit(hits, 18) node T_4249 = bit(hits, 19) node T_4250 = bit(hits, 20) node T_4251 = bit(hits, 21) node T_4252 = bit(hits, 22) node T_4253 = bit(hits, 23) node T_4254 = bit(hits, 24) node T_4255 = bit(hits, 25) node T_4256 = bit(hits, 26) node T_4257 = bit(hits, 27) node T_4258 = bit(hits, 28) node T_4259 = bit(hits, 29) node T_4260 = bit(hits, 30) node T_4261 = bit(hits, 31) node T_4262 = bit(hits, 32) node T_4263 = bit(hits, 33) node T_4264 = bit(hits, 34) node T_4265 = bit(hits, 35) node T_4266 = bit(hits, 36) node T_4267 = bit(hits, 37) node T_4268 = bit(hits, 38) node T_4269 = bit(hits, 39) node T_4270 = bit(hits, 40) node T_4271 = bit(hits, 41) node T_4272 = bit(hits, 42) node T_4273 = bit(hits, 43) node T_4274 = bit(hits, 44) node T_4275 = bit(hits, 45) node T_4276 = bit(hits, 46) node T_4277 = bit(hits, 47) node T_4278 = bit(hits, 48) node T_4279 = bit(hits, 49) node T_4280 = bit(hits, 50) node T_4281 = bit(hits, 51) node T_4282 = bit(hits, 52) node T_4283 = bit(hits, 53) node T_4284 = bit(hits, 54) node T_4285 = bit(hits, 55) node T_4286 = bit(hits, 56) node T_4287 = bit(hits, 57) node T_4288 = bit(hits, 58) node T_4289 = bit(hits, 59) node T_4290 = bit(hits, 60) node T_4291 = bit(hits, 61) node T_4293 = shl(isJump[0], 0) node T_4294 = mux(T_4230, T_4293, UInt<1>("h00")) node T_4296 = shl(isJump[1], 0) node T_4297 = mux(T_4231, T_4296, UInt<1>("h00")) node T_4299 = shl(isJump[2], 0) node T_4300 = mux(T_4232, T_4299, UInt<1>("h00")) node T_4302 = shl(isJump[3], 0) node T_4303 = mux(T_4233, T_4302, UInt<1>("h00")) node T_4305 = shl(isJump[4], 0) node T_4306 = mux(T_4234, T_4305, UInt<1>("h00")) node T_4308 = shl(isJump[5], 0) node T_4309 = mux(T_4235, T_4308, UInt<1>("h00")) node T_4311 = shl(isJump[6], 0) node T_4312 = mux(T_4236, T_4311, UInt<1>("h00")) node T_4314 = shl(isJump[7], 0) node T_4315 = mux(T_4237, T_4314, UInt<1>("h00")) node T_4317 = shl(isJump[8], 0) node T_4318 = mux(T_4238, T_4317, UInt<1>("h00")) node T_4320 = shl(isJump[9], 0) node T_4321 = mux(T_4239, T_4320, UInt<1>("h00")) node T_4323 = shl(isJump[10], 0) node T_4324 = mux(T_4240, T_4323, UInt<1>("h00")) node T_4326 = shl(isJump[11], 0) node T_4327 = mux(T_4241, T_4326, UInt<1>("h00")) node T_4329 = shl(isJump[12], 0) node T_4330 = mux(T_4242, T_4329, UInt<1>("h00")) node T_4332 = shl(isJump[13], 0) node T_4333 = mux(T_4243, T_4332, UInt<1>("h00")) node T_4335 = shl(isJump[14], 0) node T_4336 = mux(T_4244, T_4335, UInt<1>("h00")) node T_4338 = shl(isJump[15], 0) node T_4339 = mux(T_4245, T_4338, UInt<1>("h00")) node T_4341 = shl(isJump[16], 0) node T_4342 = mux(T_4246, T_4341, UInt<1>("h00")) node T_4344 = shl(isJump[17], 0) node T_4345 = mux(T_4247, T_4344, UInt<1>("h00")) node T_4347 = shl(isJump[18], 0) node T_4348 = mux(T_4248, T_4347, UInt<1>("h00")) node T_4350 = shl(isJump[19], 0) node T_4351 = mux(T_4249, T_4350, UInt<1>("h00")) node T_4353 = shl(isJump[20], 0) node T_4354 = mux(T_4250, T_4353, UInt<1>("h00")) node T_4356 = shl(isJump[21], 0) node T_4357 = mux(T_4251, T_4356, UInt<1>("h00")) node T_4359 = shl(isJump[22], 0) node T_4360 = mux(T_4252, T_4359, UInt<1>("h00")) node T_4362 = shl(isJump[23], 0) node T_4363 = mux(T_4253, T_4362, UInt<1>("h00")) node T_4365 = shl(isJump[24], 0) node T_4366 = mux(T_4254, T_4365, UInt<1>("h00")) node T_4368 = shl(isJump[25], 0) node T_4369 = mux(T_4255, T_4368, UInt<1>("h00")) node T_4371 = shl(isJump[26], 0) node T_4372 = mux(T_4256, T_4371, UInt<1>("h00")) node T_4374 = shl(isJump[27], 0) node T_4375 = mux(T_4257, T_4374, UInt<1>("h00")) node T_4377 = shl(isJump[28], 0) node T_4378 = mux(T_4258, T_4377, UInt<1>("h00")) node T_4380 = shl(isJump[29], 0) node T_4381 = mux(T_4259, T_4380, UInt<1>("h00")) node T_4383 = shl(isJump[30], 0) node T_4384 = mux(T_4260, T_4383, UInt<1>("h00")) node T_4386 = shl(isJump[31], 0) node T_4387 = mux(T_4261, T_4386, UInt<1>("h00")) node T_4389 = shl(isJump[32], 0) node T_4390 = mux(T_4262, T_4389, UInt<1>("h00")) node T_4392 = shl(isJump[33], 0) node T_4393 = mux(T_4263, T_4392, UInt<1>("h00")) node T_4395 = shl(isJump[34], 0) node T_4396 = mux(T_4264, T_4395, UInt<1>("h00")) node T_4398 = shl(isJump[35], 0) node T_4399 = mux(T_4265, T_4398, UInt<1>("h00")) node T_4401 = shl(isJump[36], 0) node T_4402 = mux(T_4266, T_4401, UInt<1>("h00")) node T_4404 = shl(isJump[37], 0) node T_4405 = mux(T_4267, T_4404, UInt<1>("h00")) node T_4407 = shl(isJump[38], 0) node T_4408 = mux(T_4268, T_4407, UInt<1>("h00")) node T_4410 = shl(isJump[39], 0) node T_4411 = mux(T_4269, T_4410, UInt<1>("h00")) node T_4413 = shl(isJump[40], 0) node T_4414 = mux(T_4270, T_4413, UInt<1>("h00")) node T_4416 = shl(isJump[41], 0) node T_4417 = mux(T_4271, T_4416, UInt<1>("h00")) node T_4419 = shl(isJump[42], 0) node T_4420 = mux(T_4272, T_4419, UInt<1>("h00")) node T_4422 = shl(isJump[43], 0) node T_4423 = mux(T_4273, T_4422, UInt<1>("h00")) node T_4425 = shl(isJump[44], 0) node T_4426 = mux(T_4274, T_4425, UInt<1>("h00")) node T_4428 = shl(isJump[45], 0) node T_4429 = mux(T_4275, T_4428, UInt<1>("h00")) node T_4431 = shl(isJump[46], 0) node T_4432 = mux(T_4276, T_4431, UInt<1>("h00")) node T_4434 = shl(isJump[47], 0) node T_4435 = mux(T_4277, T_4434, UInt<1>("h00")) node T_4437 = shl(isJump[48], 0) node T_4438 = mux(T_4278, T_4437, UInt<1>("h00")) node T_4440 = shl(isJump[49], 0) node T_4441 = mux(T_4279, T_4440, UInt<1>("h00")) node T_4443 = shl(isJump[50], 0) node T_4444 = mux(T_4280, T_4443, UInt<1>("h00")) node T_4446 = shl(isJump[51], 0) node T_4447 = mux(T_4281, T_4446, UInt<1>("h00")) node T_4449 = shl(isJump[52], 0) node T_4450 = mux(T_4282, T_4449, UInt<1>("h00")) node T_4452 = shl(isJump[53], 0) node T_4453 = mux(T_4283, T_4452, UInt<1>("h00")) node T_4455 = shl(isJump[54], 0) node T_4456 = mux(T_4284, T_4455, UInt<1>("h00")) node T_4458 = shl(isJump[55], 0) node T_4459 = mux(T_4285, T_4458, UInt<1>("h00")) node T_4461 = shl(isJump[56], 0) node T_4462 = mux(T_4286, T_4461, UInt<1>("h00")) node T_4464 = shl(isJump[57], 0) node T_4465 = mux(T_4287, T_4464, UInt<1>("h00")) node T_4467 = shl(isJump[58], 0) node T_4468 = mux(T_4288, T_4467, UInt<1>("h00")) node T_4470 = shl(isJump[59], 0) node T_4471 = mux(T_4289, T_4470, UInt<1>("h00")) node T_4473 = shl(isJump[60], 0) node T_4474 = mux(T_4290, T_4473, UInt<1>("h00")) node T_4476 = shl(isJump[61], 0) node T_4477 = mux(T_4291, T_4476, UInt<1>("h00")) node T_4479 = or(T_4294, T_4297) node T_4480 = or(T_4479, T_4300) node T_4481 = or(T_4480, T_4303) node T_4482 = or(T_4481, T_4306) node T_4483 = or(T_4482, T_4309) node T_4484 = or(T_4483, T_4312) node T_4485 = or(T_4484, T_4315) node T_4486 = or(T_4485, T_4318) node T_4487 = or(T_4486, T_4321) node T_4488 = or(T_4487, T_4324) node T_4489 = or(T_4488, T_4327) node T_4490 = or(T_4489, T_4330) node T_4491 = or(T_4490, T_4333) node T_4492 = or(T_4491, T_4336) node T_4493 = or(T_4492, T_4339) node T_4494 = or(T_4493, T_4342) node T_4495 = or(T_4494, T_4345) node T_4496 = or(T_4495, T_4348) node T_4497 = or(T_4496, T_4351) node T_4498 = or(T_4497, T_4354) node T_4499 = or(T_4498, T_4357) node T_4500 = or(T_4499, T_4360) node T_4501 = or(T_4500, T_4363) node T_4502 = or(T_4501, T_4366) node T_4503 = or(T_4502, T_4369) node T_4504 = or(T_4503, T_4372) node T_4505 = or(T_4504, T_4375) node T_4506 = or(T_4505, T_4378) node T_4507 = or(T_4506, T_4381) node T_4508 = or(T_4507, T_4384) node T_4509 = or(T_4508, T_4387) node T_4510 = or(T_4509, T_4390) node T_4511 = or(T_4510, T_4393) node T_4512 = or(T_4511, T_4396) node T_4513 = or(T_4512, T_4399) node T_4514 = or(T_4513, T_4402) node T_4515 = or(T_4514, T_4405) node T_4516 = or(T_4515, T_4408) node T_4517 = or(T_4516, T_4411) node T_4518 = or(T_4517, T_4414) node T_4519 = or(T_4518, T_4417) node T_4520 = or(T_4519, T_4420) node T_4521 = or(T_4520, T_4423) node T_4522 = or(T_4521, T_4426) node T_4523 = or(T_4522, T_4429) node T_4524 = or(T_4523, T_4432) node T_4525 = or(T_4524, T_4435) node T_4526 = or(T_4525, T_4438) node T_4527 = or(T_4526, T_4441) node T_4528 = or(T_4527, T_4444) node T_4529 = or(T_4528, T_4447) node T_4530 = or(T_4529, T_4450) node T_4531 = or(T_4530, T_4453) node T_4532 = or(T_4531, T_4456) node T_4533 = or(T_4532, T_4459) node T_4534 = or(T_4533, T_4462) node T_4535 = or(T_4534, T_4465) node T_4536 = or(T_4535, T_4468) node T_4537 = or(T_4536, T_4471) node T_4538 = or(T_4537, T_4474) node T_4539 = or(T_4538, T_4477) wire T_4540 : UInt<1> T_4540 := UInt<1>("h00") T_4540 := T_4539 node T_4543 = eq(T_4540, UInt<1>("h00")) node T_4544 = and(io.req.valid, io.resp.valid) node T_4545 = and(T_4544, T_4543) wire T_4549 : {history : UInt<7>, value : UInt<2>} T_4549.value := UInt<1>("h00") T_4549.history := UInt<1>("h00") node T_4554 = bits(io.req.bits.addr, 8, 2) node T_4555 = xor(T_4554, T_4229) infer accessor T_4556 = T_4227[T_4555] T_4549.value := T_4556 T_4549.history := T_4229 node T_4557 = bit(T_4549.value, 0) when T_4545 : node T_4558 = bits(T_4229, 6, 1) node T_4559 = cat(T_4557, T_4558) T_4229 := T_4559 skip node T_4560 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) when T_4560 : node T_4561 = bits(io.bht_update.bits.pc, 8, 2) node T_4562 = xor(T_4561, io.bht_update.bits.prediction.bits.bht.history) infer accessor T_4563 = T_4227[T_4562] node T_4564 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) node T_4565 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) node T_4566 = and(T_4564, T_4565) node T_4567 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) node T_4568 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) node T_4569 = or(T_4567, T_4568) node T_4570 = and(T_4569, io.bht_update.bits.taken) node T_4571 = or(T_4566, T_4570) node T_4572 = cat(io.bht_update.bits.taken, T_4571) T_4563 := T_4572 when io.bht_update.bits.mispredict : node T_4573 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) node T_4574 = cat(io.bht_update.bits.taken, T_4573) T_4229 := T_4574 skip skip node T_4575 = bit(T_4549.value, 0) node T_4577 = eq(T_4575, UInt<1>("h00")) node T_4578 = and(T_4577, T_4543) when T_4578 : io.resp.bits.taken := UInt<1>("h00") skip io.resp.bits.bht <> T_4549 reg T_4581 : UInt<2>, clock, reset onreset T_4581 := UInt<2>("h00") reg T_4583 : UInt<1>, clock, reset onreset T_4583 := UInt<1>("h00") reg T_4592 : UInt[2], clock, reset node T_4596 = bit(hits, 0) node T_4597 = bit(hits, 1) node T_4598 = bit(hits, 2) node T_4599 = bit(hits, 3) node T_4600 = bit(hits, 4) node T_4601 = bit(hits, 5) node T_4602 = bit(hits, 6) node T_4603 = bit(hits, 7) node T_4604 = bit(hits, 8) node T_4605 = bit(hits, 9) node T_4606 = bit(hits, 10) node T_4607 = bit(hits, 11) node T_4608 = bit(hits, 12) node T_4609 = bit(hits, 13) node T_4610 = bit(hits, 14) node T_4611 = bit(hits, 15) node T_4612 = bit(hits, 16) node T_4613 = bit(hits, 17) node T_4614 = bit(hits, 18) node T_4615 = bit(hits, 19) node T_4616 = bit(hits, 20) node T_4617 = bit(hits, 21) node T_4618 = bit(hits, 22) node T_4619 = bit(hits, 23) node T_4620 = bit(hits, 24) node T_4621 = bit(hits, 25) node T_4622 = bit(hits, 26) node T_4623 = bit(hits, 27) node T_4624 = bit(hits, 28) node T_4625 = bit(hits, 29) node T_4626 = bit(hits, 30) node T_4627 = bit(hits, 31) node T_4628 = bit(hits, 32) node T_4629 = bit(hits, 33) node T_4630 = bit(hits, 34) node T_4631 = bit(hits, 35) node T_4632 = bit(hits, 36) node T_4633 = bit(hits, 37) node T_4634 = bit(hits, 38) node T_4635 = bit(hits, 39) node T_4636 = bit(hits, 40) node T_4637 = bit(hits, 41) node T_4638 = bit(hits, 42) node T_4639 = bit(hits, 43) node T_4640 = bit(hits, 44) node T_4641 = bit(hits, 45) node T_4642 = bit(hits, 46) node T_4643 = bit(hits, 47) node T_4644 = bit(hits, 48) node T_4645 = bit(hits, 49) node T_4646 = bit(hits, 50) node T_4647 = bit(hits, 51) node T_4648 = bit(hits, 52) node T_4649 = bit(hits, 53) node T_4650 = bit(hits, 54) node T_4651 = bit(hits, 55) node T_4652 = bit(hits, 56) node T_4653 = bit(hits, 57) node T_4654 = bit(hits, 58) node T_4655 = bit(hits, 59) node T_4656 = bit(hits, 60) node T_4657 = bit(hits, 61) node T_4659 = shl(useRAS[0], 0) node T_4660 = mux(T_4596, T_4659, UInt<1>("h00")) node T_4662 = shl(useRAS[1], 0) node T_4663 = mux(T_4597, T_4662, UInt<1>("h00")) node T_4665 = shl(useRAS[2], 0) node T_4666 = mux(T_4598, T_4665, UInt<1>("h00")) node T_4668 = shl(useRAS[3], 0) node T_4669 = mux(T_4599, T_4668, UInt<1>("h00")) node T_4671 = shl(useRAS[4], 0) node T_4672 = mux(T_4600, T_4671, UInt<1>("h00")) node T_4674 = shl(useRAS[5], 0) node T_4675 = mux(T_4601, T_4674, UInt<1>("h00")) node T_4677 = shl(useRAS[6], 0) node T_4678 = mux(T_4602, T_4677, UInt<1>("h00")) node T_4680 = shl(useRAS[7], 0) node T_4681 = mux(T_4603, T_4680, UInt<1>("h00")) node T_4683 = shl(useRAS[8], 0) node T_4684 = mux(T_4604, T_4683, UInt<1>("h00")) node T_4686 = shl(useRAS[9], 0) node T_4687 = mux(T_4605, T_4686, UInt<1>("h00")) node T_4689 = shl(useRAS[10], 0) node T_4690 = mux(T_4606, T_4689, UInt<1>("h00")) node T_4692 = shl(useRAS[11], 0) node T_4693 = mux(T_4607, T_4692, UInt<1>("h00")) node T_4695 = shl(useRAS[12], 0) node T_4696 = mux(T_4608, T_4695, UInt<1>("h00")) node T_4698 = shl(useRAS[13], 0) node T_4699 = mux(T_4609, T_4698, UInt<1>("h00")) node T_4701 = shl(useRAS[14], 0) node T_4702 = mux(T_4610, T_4701, UInt<1>("h00")) node T_4704 = shl(useRAS[15], 0) node T_4705 = mux(T_4611, T_4704, UInt<1>("h00")) node T_4707 = shl(useRAS[16], 0) node T_4708 = mux(T_4612, T_4707, UInt<1>("h00")) node T_4710 = shl(useRAS[17], 0) node T_4711 = mux(T_4613, T_4710, UInt<1>("h00")) node T_4713 = shl(useRAS[18], 0) node T_4714 = mux(T_4614, T_4713, UInt<1>("h00")) node T_4716 = shl(useRAS[19], 0) node T_4717 = mux(T_4615, T_4716, UInt<1>("h00")) node T_4719 = shl(useRAS[20], 0) node T_4720 = mux(T_4616, T_4719, UInt<1>("h00")) node T_4722 = shl(useRAS[21], 0) node T_4723 = mux(T_4617, T_4722, UInt<1>("h00")) node T_4725 = shl(useRAS[22], 0) node T_4726 = mux(T_4618, T_4725, UInt<1>("h00")) node T_4728 = shl(useRAS[23], 0) node T_4729 = mux(T_4619, T_4728, UInt<1>("h00")) node T_4731 = shl(useRAS[24], 0) node T_4732 = mux(T_4620, T_4731, UInt<1>("h00")) node T_4734 = shl(useRAS[25], 0) node T_4735 = mux(T_4621, T_4734, UInt<1>("h00")) node T_4737 = shl(useRAS[26], 0) node T_4738 = mux(T_4622, T_4737, UInt<1>("h00")) node T_4740 = shl(useRAS[27], 0) node T_4741 = mux(T_4623, T_4740, UInt<1>("h00")) node T_4743 = shl(useRAS[28], 0) node T_4744 = mux(T_4624, T_4743, UInt<1>("h00")) node T_4746 = shl(useRAS[29], 0) node T_4747 = mux(T_4625, T_4746, UInt<1>("h00")) node T_4749 = shl(useRAS[30], 0) node T_4750 = mux(T_4626, T_4749, UInt<1>("h00")) node T_4752 = shl(useRAS[31], 0) node T_4753 = mux(T_4627, T_4752, UInt<1>("h00")) node T_4755 = shl(useRAS[32], 0) node T_4756 = mux(T_4628, T_4755, UInt<1>("h00")) node T_4758 = shl(useRAS[33], 0) node T_4759 = mux(T_4629, T_4758, UInt<1>("h00")) node T_4761 = shl(useRAS[34], 0) node T_4762 = mux(T_4630, T_4761, UInt<1>("h00")) node T_4764 = shl(useRAS[35], 0) node T_4765 = mux(T_4631, T_4764, UInt<1>("h00")) node T_4767 = shl(useRAS[36], 0) node T_4768 = mux(T_4632, T_4767, UInt<1>("h00")) node T_4770 = shl(useRAS[37], 0) node T_4771 = mux(T_4633, T_4770, UInt<1>("h00")) node T_4773 = shl(useRAS[38], 0) node T_4774 = mux(T_4634, T_4773, UInt<1>("h00")) node T_4776 = shl(useRAS[39], 0) node T_4777 = mux(T_4635, T_4776, UInt<1>("h00")) node T_4779 = shl(useRAS[40], 0) node T_4780 = mux(T_4636, T_4779, UInt<1>("h00")) node T_4782 = shl(useRAS[41], 0) node T_4783 = mux(T_4637, T_4782, UInt<1>("h00")) node T_4785 = shl(useRAS[42], 0) node T_4786 = mux(T_4638, T_4785, UInt<1>("h00")) node T_4788 = shl(useRAS[43], 0) node T_4789 = mux(T_4639, T_4788, UInt<1>("h00")) node T_4791 = shl(useRAS[44], 0) node T_4792 = mux(T_4640, T_4791, UInt<1>("h00")) node T_4794 = shl(useRAS[45], 0) node T_4795 = mux(T_4641, T_4794, UInt<1>("h00")) node T_4797 = shl(useRAS[46], 0) node T_4798 = mux(T_4642, T_4797, UInt<1>("h00")) node T_4800 = shl(useRAS[47], 0) node T_4801 = mux(T_4643, T_4800, UInt<1>("h00")) node T_4803 = shl(useRAS[48], 0) node T_4804 = mux(T_4644, T_4803, UInt<1>("h00")) node T_4806 = shl(useRAS[49], 0) node T_4807 = mux(T_4645, T_4806, UInt<1>("h00")) node T_4809 = shl(useRAS[50], 0) node T_4810 = mux(T_4646, T_4809, UInt<1>("h00")) node T_4812 = shl(useRAS[51], 0) node T_4813 = mux(T_4647, T_4812, UInt<1>("h00")) node T_4815 = shl(useRAS[52], 0) node T_4816 = mux(T_4648, T_4815, UInt<1>("h00")) node T_4818 = shl(useRAS[53], 0) node T_4819 = mux(T_4649, T_4818, UInt<1>("h00")) node T_4821 = shl(useRAS[54], 0) node T_4822 = mux(T_4650, T_4821, UInt<1>("h00")) node T_4824 = shl(useRAS[55], 0) node T_4825 = mux(T_4651, T_4824, UInt<1>("h00")) node T_4827 = shl(useRAS[56], 0) node T_4828 = mux(T_4652, T_4827, UInt<1>("h00")) node T_4830 = shl(useRAS[57], 0) node T_4831 = mux(T_4653, T_4830, UInt<1>("h00")) node T_4833 = shl(useRAS[58], 0) node T_4834 = mux(T_4654, T_4833, UInt<1>("h00")) node T_4836 = shl(useRAS[59], 0) node T_4837 = mux(T_4655, T_4836, UInt<1>("h00")) node T_4839 = shl(useRAS[60], 0) node T_4840 = mux(T_4656, T_4839, UInt<1>("h00")) node T_4842 = shl(useRAS[61], 0) node T_4843 = mux(T_4657, T_4842, UInt<1>("h00")) node T_4845 = or(T_4660, T_4663) node T_4846 = or(T_4845, T_4666) node T_4847 = or(T_4846, T_4669) node T_4848 = or(T_4847, T_4672) node T_4849 = or(T_4848, T_4675) node T_4850 = or(T_4849, T_4678) node T_4851 = or(T_4850, T_4681) node T_4852 = or(T_4851, T_4684) node T_4853 = or(T_4852, T_4687) node T_4854 = or(T_4853, T_4690) node T_4855 = or(T_4854, T_4693) node T_4856 = or(T_4855, T_4696) node T_4857 = or(T_4856, T_4699) node T_4858 = or(T_4857, T_4702) node T_4859 = or(T_4858, T_4705) node T_4860 = or(T_4859, T_4708) node T_4861 = or(T_4860, T_4711) node T_4862 = or(T_4861, T_4714) node T_4863 = or(T_4862, T_4717) node T_4864 = or(T_4863, T_4720) node T_4865 = or(T_4864, T_4723) node T_4866 = or(T_4865, T_4726) node T_4867 = or(T_4866, T_4729) node T_4868 = or(T_4867, T_4732) node T_4869 = or(T_4868, T_4735) node T_4870 = or(T_4869, T_4738) node T_4871 = or(T_4870, T_4741) node T_4872 = or(T_4871, T_4744) node T_4873 = or(T_4872, T_4747) node T_4874 = or(T_4873, T_4750) node T_4875 = or(T_4874, T_4753) node T_4876 = or(T_4875, T_4756) node T_4877 = or(T_4876, T_4759) node T_4878 = or(T_4877, T_4762) node T_4879 = or(T_4878, T_4765) node T_4880 = or(T_4879, T_4768) node T_4881 = or(T_4880, T_4771) node T_4882 = or(T_4881, T_4774) node T_4883 = or(T_4882, T_4777) node T_4884 = or(T_4883, T_4780) node T_4885 = or(T_4884, T_4783) node T_4886 = or(T_4885, T_4786) node T_4887 = or(T_4886, T_4789) node T_4888 = or(T_4887, T_4792) node T_4889 = or(T_4888, T_4795) node T_4890 = or(T_4889, T_4798) node T_4891 = or(T_4890, T_4801) node T_4892 = or(T_4891, T_4804) node T_4893 = or(T_4892, T_4807) node T_4894 = or(T_4893, T_4810) node T_4895 = or(T_4894, T_4813) node T_4896 = or(T_4895, T_4816) node T_4897 = or(T_4896, T_4819) node T_4898 = or(T_4897, T_4822) node T_4899 = or(T_4898, T_4825) node T_4900 = or(T_4899, T_4828) node T_4901 = or(T_4900, T_4831) node T_4902 = or(T_4901, T_4834) node T_4903 = or(T_4902, T_4837) node T_4904 = or(T_4903, T_4840) node T_4905 = or(T_4904, T_4843) wire T_4906 : UInt<1> T_4906 := UInt<1>("h00") T_4906 := T_4905 node T_4909 = eq(T_4581, UInt<1>("h00")) node T_4911 = eq(T_4909, UInt<1>("h00")) node T_4912 = and(T_4911, T_4906) when T_4912 : infer accessor T_4913 = T_4592[T_4583] io.resp.bits.target := T_4913 skip when io.ras_update.valid : when io.ras_update.bits.isCall : node T_4915 = lt(T_4581, UInt<2>("h02")) when T_4915 : node T_4917 = addw(T_4581, UInt<1>("h01")) T_4581 := T_4917 skip node T_4920 = lt(T_4583, UInt<1>("h01")) node T_4921 = or(UInt<1>("h01"), T_4920) node T_4923 = addw(T_4583, UInt<1>("h01")) node T_4925 = mux(T_4921, T_4923, UInt<1>("h00")) infer accessor T_4926 = T_4592[T_4925] T_4926 := io.ras_update.bits.returnAddr T_4583 := T_4925 when T_4906 : io.resp.bits.target := io.ras_update.bits.returnAddr skip skip else : node T_4927 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) when T_4927 : node T_4929 = eq(T_4581, UInt<1>("h00")) node T_4931 = eq(T_4929, UInt<1>("h00")) when T_4931 : node T_4933 = subw(T_4581, UInt<1>("h01")) T_4581 := T_4933 node T_4936 = gt(T_4583, UInt<1>("h00")) node T_4937 = or(UInt<1>("h01"), T_4936) node T_4939 = subw(T_4583, UInt<1>("h01")) node T_4941 = mux(T_4937, T_4939, UInt<1>("h01")) T_4583 := T_4941 skip skip skip skip when io.invalidate : T_4581 := UInt<1>("h00") skip module FlowThroughSerializer : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, cnt : UInt<1>, done : UInt<1>} io.done := UInt<1>("h00") io.cnt := UInt<1>("h00") io.out.bits.g_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.manager_xact_id := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in.ready := UInt<1>("h00") io.out <> io.in io.cnt := UInt<1>("h00") io.done := UInt<1>("h01") module ICache : input clock : Clock input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.mem.grant.ready := UInt<1>("h00") io.mem.acquire.bits.union := UInt<1>("h00") io.mem.acquire.bits.a_type := UInt<1>("h00") io.mem.acquire.bits.is_builtin_type := UInt<1>("h00") io.mem.acquire.bits.data := UInt<1>("h00") io.mem.acquire.bits.addr_beat := UInt<1>("h00") io.mem.acquire.bits.client_xact_id := UInt<1>("h00") io.mem.acquire.bits.addr_block := UInt<1>("h00") io.mem.acquire.valid := UInt<1>("h00") io.resp.bits.datablock := UInt<1>("h00") io.resp.bits.data := UInt<1>("h00") io.resp.valid := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg invalidated : UInt<1>, clock, reset node stall = eq(io.resp.ready, UInt<1>("h00")) wire rdy : UInt<1> rdy := UInt<1>("h00") reg s2_valid : UInt<1>, clock, reset onreset s2_valid := UInt<1>("h00") reg s2_addr : UInt<32>, clock, reset wire s2_any_tag_hit : UInt<1> s2_any_tag_hit := UInt<1>("h00") reg s1_valid : UInt<1>, clock, reset onreset s1_valid := UInt<1>("h00") reg s1_pgoff : UInt<12>, clock, reset node s1_addr = cat(io.req.bits.ppn, s1_pgoff) node s1_tag = bits(s1_addr, 31, 12) node T_343 = and(s1_valid, stall) node s0_valid = or(io.req.valid, T_343) node T_345 = and(s1_valid, stall) node s0_pgoff = mux(T_345, s1_pgoff, io.req.bits.idx) node T_347 = and(io.req.valid, rdy) node T_348 = and(s1_valid, stall) node T_350 = eq(io.req.bits.kill, UInt<1>("h00")) node T_351 = and(T_348, T_350) node T_352 = or(T_347, T_351) s1_valid := T_352 node T_353 = and(io.req.valid, rdy) when T_353 : s1_pgoff := io.req.bits.idx skip node T_354 = and(s1_valid, rdy) node T_356 = eq(io.req.bits.kill, UInt<1>("h00")) node T_357 = and(T_354, T_356) node T_358 = and(io.resp.valid, stall) node T_359 = or(T_357, T_358) s2_valid := T_359 node T_360 = and(s1_valid, rdy) node T_362 = eq(stall, UInt<1>("h00")) node T_363 = and(T_360, T_362) when T_363 : s2_addr := s1_addr skip node s2_tag = bits(s2_addr, 31, 12) node s2_idx = bits(s2_addr, 11, 6) node s2_offset = bits(s2_addr, 5, 0) node s2_hit = and(s2_valid, s2_any_tag_hit) node T_369 = eq(s2_any_tag_hit, UInt<1>("h00")) node s2_miss = and(s2_valid, T_369) node T_371 = eq(state, UInt<1>("h00")) node T_373 = eq(s2_miss, UInt<1>("h00")) node T_374 = and(T_371, T_373) rdy := T_374 inst T_375 of FlowThroughSerializer T_375.io.out.ready := UInt<1>("h00") T_375.io.in.bits.g_type := UInt<1>("h00") T_375.io.in.bits.is_builtin_type := UInt<1>("h00") T_375.io.in.bits.manager_xact_id := UInt<1>("h00") T_375.io.in.bits.client_xact_id := UInt<1>("h00") T_375.io.in.bits.data := UInt<1>("h00") T_375.io.in.bits.addr_beat := UInt<1>("h00") T_375.io.in.valid := UInt<1>("h00") T_375.clock := clock T_375.reset := reset T_375.io.in.valid := io.mem.grant.valid T_375.io.in.bits <> io.mem.grant.bits io.mem.grant.ready := T_375.io.in.ready node T_384 = and(T_375.io.out.ready, T_375.io.out.valid) reg refill_cnt : UInt<2>, clock, reset onreset refill_cnt := UInt<2>("h00") when T_384 : node T_388 = eq(refill_cnt, UInt<2>("h03")) node T_390 = and(UInt<1>("h00"), T_388) node T_393 = addw(refill_cnt, UInt<1>("h01")) node T_394 = mux(T_390, UInt<1>("h00"), T_393) refill_cnt := T_394 skip node refill_wrap = and(T_384, T_388) node T_396 = eq(state, UInt<2>("h03")) node refill_done = and(T_396, refill_wrap) T_375.io.out.ready := UInt<1>("h01") reg T_400 : UInt<16>, clock, reset onreset T_400 := UInt<16>("h01") when s2_miss : node T_401 = bit(T_400, 0) node T_402 = bit(T_400, 2) node T_403 = xor(T_401, T_402) node T_404 = bit(T_400, 3) node T_405 = xor(T_403, T_404) node T_406 = bit(T_400, 5) node T_407 = xor(T_405, T_406) node T_408 = bits(T_400, 15, 1) node T_409 = cat(T_407, T_408) T_400 := T_409 skip node repl_way = bits(T_400, 1, 0) smem tag_array : UInt<20>[4][64], clock node T_428 = bits(s0_pgoff, 11, 6) node T_430 = eq(refill_done, UInt<1>("h00")) node T_431 = and(T_430, s0_valid) poison T_432 : UInt<6> node T_433 = mux(T_431, T_428, T_432) infer accessor tag_rdata = tag_array[T_433] when refill_done : wire T_443 : UInt<20>[4] T_443[0] := s2_tag T_443[1] := s2_tag T_443[2] := s2_tag T_443[3] := s2_tag node T_450 = eq(repl_way, UInt<1>("h00")) node T_452 = eq(repl_way, UInt<1>("h01")) node T_454 = eq(repl_way, UInt<2>("h02")) node T_456 = eq(repl_way, UInt<2>("h03")) wire T_458 : UInt<1>[4] T_458[0] := T_450 T_458[1] := T_452 T_458[2] := T_454 T_458[3] := T_456 infer accessor T_466 = tag_array[s2_idx] when T_458[0] : T_466[0] := T_443[0] skip when T_458[1] : T_466[1] := T_443[1] skip when T_458[2] : T_466[2] := T_443[2] skip when T_458[3] : T_466[3] := T_443[3] skip skip reg vb_array : UInt<256>, clock, reset onreset vb_array := UInt<256>("h00") node T_475 = eq(invalidated, UInt<1>("h00")) node T_476 = and(refill_done, T_475) when T_476 : node T_477 = cat(repl_way, s2_idx) node T_480 = dshl(UInt<1>("h01"), T_477) node T_481 = or(vb_array, T_480) node T_482 = not(vb_array) node T_483 = or(T_482, T_480) node T_484 = not(T_483) node T_485 = mux(UInt<1>("h01"), T_481, T_484) vb_array := T_485 skip when io.invalidate : vb_array := UInt<1>("h00") invalidated := UInt<1>("h01") skip wire s2_disparity : UInt<1>[4] s2_disparity[0] := UInt<1>("h00") s2_disparity[1] := UInt<1>("h00") s2_disparity[2] := UInt<1>("h00") s2_disparity[3] := UInt<1>("h00") node T_508 = and(s2_valid, s2_disparity[0]) when T_508 : node T_510 = cat(UInt<1>("h00"), s2_idx) node T_513 = dshl(UInt<1>("h01"), T_510) node T_514 = or(vb_array, T_513) node T_515 = not(vb_array) node T_516 = or(T_515, T_513) node T_517 = not(T_516) node T_518 = mux(UInt<1>("h00"), T_514, T_517) vb_array := T_518 skip node T_519 = and(s2_valid, s2_disparity[1]) when T_519 : node T_521 = cat(UInt<1>("h01"), s2_idx) node T_524 = dshl(UInt<1>("h01"), T_521) node T_525 = or(vb_array, T_524) node T_526 = not(vb_array) node T_527 = or(T_526, T_524) node T_528 = not(T_527) node T_529 = mux(UInt<1>("h00"), T_525, T_528) vb_array := T_529 skip node T_530 = and(s2_valid, s2_disparity[2]) when T_530 : node T_532 = cat(UInt<2>("h02"), s2_idx) node T_535 = dshl(UInt<1>("h01"), T_532) node T_536 = or(vb_array, T_535) node T_537 = not(vb_array) node T_538 = or(T_537, T_535) node T_539 = not(T_538) node T_540 = mux(UInt<1>("h00"), T_536, T_539) vb_array := T_540 skip node T_541 = and(s2_valid, s2_disparity[3]) when T_541 : node T_543 = cat(UInt<2>("h03"), s2_idx) node T_546 = dshl(UInt<1>("h01"), T_543) node T_547 = or(vb_array, T_546) node T_548 = not(vb_array) node T_549 = or(T_548, T_546) node T_550 = not(T_549) node T_551 = mux(UInt<1>("h00"), T_547, T_550) vb_array := T_551 skip wire s1_tag_match : UInt<1>[4] s1_tag_match[0] := UInt<1>("h00") s1_tag_match[1] := UInt<1>("h00") s1_tag_match[2] := UInt<1>("h00") s1_tag_match[3] := UInt<1>("h00") wire s2_tag_hit : UInt<1>[4] s2_tag_hit[0] := UInt<1>("h00") s2_tag_hit[1] := UInt<1>("h00") s2_tag_hit[2] := UInt<1>("h00") s2_tag_hit[3] := UInt<1>("h00") reg s2_dout : UInt<128>[4], clock, reset node T_609 = eq(io.invalidate, UInt<1>("h00")) node T_611 = bits(s1_pgoff, 11, 6) node T_612 = cat(UInt<1>("h00"), T_611) node T_613 = dshr(vb_array, T_612) node T_614 = bit(T_613, 0) node T_615 = bit(T_614, 0) node T_616 = and(T_609, T_615) reg T_618 : UInt<1>, clock, reset reg T_620 : UInt<1>, clock, reset reg T_622 : UInt<1>, clock, reset node T_623 = and(s1_valid, rdy) node T_625 = eq(stall, UInt<1>("h00")) node T_626 = and(T_623, T_625) when T_626 : T_618 := T_616 node T_629 = or(UInt<1>("h00"), UInt<1>("h00")) T_620 := T_629 T_622 := s1_tag_match[0] skip node T_630 = bits(tag_rdata[0], 19, 0) node T_631 = eq(T_630, s1_tag) s1_tag_match[0] := T_631 node T_632 = and(T_618, T_622) s2_tag_hit[0] := T_632 node T_635 = or(UInt<1>("h00"), UInt<1>("h00")) node T_636 = or(T_620, T_635) node T_637 = and(T_618, T_636) s2_disparity[0] := T_637 node T_639 = eq(io.invalidate, UInt<1>("h00")) node T_641 = bits(s1_pgoff, 11, 6) node T_642 = cat(UInt<1>("h01"), T_641) node T_643 = dshr(vb_array, T_642) node T_644 = bit(T_643, 0) node T_645 = bit(T_644, 0) node T_646 = and(T_639, T_645) reg T_648 : UInt<1>, clock, reset reg T_650 : UInt<1>, clock, reset reg T_652 : UInt<1>, clock, reset node T_653 = and(s1_valid, rdy) node T_655 = eq(stall, UInt<1>("h00")) node T_656 = and(T_653, T_655) when T_656 : T_648 := T_646 node T_659 = or(UInt<1>("h00"), UInt<1>("h00")) T_650 := T_659 T_652 := s1_tag_match[1] skip node T_660 = bits(tag_rdata[1], 19, 0) node T_661 = eq(T_660, s1_tag) s1_tag_match[1] := T_661 node T_662 = and(T_648, T_652) s2_tag_hit[1] := T_662 node T_665 = or(UInt<1>("h00"), UInt<1>("h00")) node T_666 = or(T_650, T_665) node T_667 = and(T_648, T_666) s2_disparity[1] := T_667 node T_669 = eq(io.invalidate, UInt<1>("h00")) node T_671 = bits(s1_pgoff, 11, 6) node T_672 = cat(UInt<2>("h02"), T_671) node T_673 = dshr(vb_array, T_672) node T_674 = bit(T_673, 0) node T_675 = bit(T_674, 0) node T_676 = and(T_669, T_675) reg T_678 : UInt<1>, clock, reset reg T_680 : UInt<1>, clock, reset reg T_682 : UInt<1>, clock, reset node T_683 = and(s1_valid, rdy) node T_685 = eq(stall, UInt<1>("h00")) node T_686 = and(T_683, T_685) when T_686 : T_678 := T_676 node T_689 = or(UInt<1>("h00"), UInt<1>("h00")) T_680 := T_689 T_682 := s1_tag_match[2] skip node T_690 = bits(tag_rdata[2], 19, 0) node T_691 = eq(T_690, s1_tag) s1_tag_match[2] := T_691 node T_692 = and(T_678, T_682) s2_tag_hit[2] := T_692 node T_695 = or(UInt<1>("h00"), UInt<1>("h00")) node T_696 = or(T_680, T_695) node T_697 = and(T_678, T_696) s2_disparity[2] := T_697 node T_699 = eq(io.invalidate, UInt<1>("h00")) node T_701 = bits(s1_pgoff, 11, 6) node T_702 = cat(UInt<2>("h03"), T_701) node T_703 = dshr(vb_array, T_702) node T_704 = bit(T_703, 0) node T_705 = bit(T_704, 0) node T_706 = and(T_699, T_705) reg T_708 : UInt<1>, clock, reset reg T_710 : UInt<1>, clock, reset reg T_712 : UInt<1>, clock, reset node T_713 = and(s1_valid, rdy) node T_715 = eq(stall, UInt<1>("h00")) node T_716 = and(T_713, T_715) when T_716 : T_708 := T_706 node T_719 = or(UInt<1>("h00"), UInt<1>("h00")) T_710 := T_719 T_712 := s1_tag_match[3] skip node T_720 = bits(tag_rdata[3], 19, 0) node T_721 = eq(T_720, s1_tag) s1_tag_match[3] := T_721 node T_722 = and(T_708, T_712) s2_tag_hit[3] := T_722 node T_725 = or(UInt<1>("h00"), UInt<1>("h00")) node T_726 = or(T_710, T_725) node T_727 = and(T_708, T_726) s2_disparity[3] := T_727 node T_728 = or(s2_tag_hit[0], s2_tag_hit[1]) node T_729 = or(T_728, s2_tag_hit[2]) node T_730 = or(T_729, s2_tag_hit[3]) node T_731 = or(s2_disparity[0], s2_disparity[1]) node T_732 = or(T_731, s2_disparity[2]) node T_733 = or(T_732, s2_disparity[3]) node T_735 = eq(T_733, UInt<1>("h00")) node T_736 = and(T_730, T_735) s2_any_tag_hit := T_736 smem T_739 : UInt<128>[256], clock node T_741 = eq(repl_way, UInt<1>("h00")) node T_742 = and(T_375.io.out.valid, T_741) when T_742 : node T_743 = cat(s2_idx, refill_cnt) infer accessor T_744 = T_739[T_743] T_744 := T_375.io.out.bits.data skip node T_745 = bits(s0_pgoff, 11, 4) node T_747 = eq(T_742, UInt<1>("h00")) node T_748 = and(T_747, s0_valid) poison T_749 : UInt<8> node T_750 = mux(T_748, T_745, T_749) infer accessor T_751 = T_739[T_750] node T_752 = and(s1_valid, rdy) node T_754 = eq(stall, UInt<1>("h00")) node T_755 = and(T_752, T_754) node T_757 = or(UInt<1>("h00"), s1_tag_match[0]) node T_758 = and(T_755, T_757) when T_758 : s2_dout[0] := T_751 skip smem T_761 : UInt<128>[256], clock node T_763 = eq(repl_way, UInt<1>("h01")) node T_764 = and(T_375.io.out.valid, T_763) when T_764 : node T_765 = cat(s2_idx, refill_cnt) infer accessor T_766 = T_761[T_765] T_766 := T_375.io.out.bits.data skip node T_767 = bits(s0_pgoff, 11, 4) node T_769 = eq(T_764, UInt<1>("h00")) node T_770 = and(T_769, s0_valid) poison T_771 : UInt<8> node T_772 = mux(T_770, T_767, T_771) infer accessor T_773 = T_761[T_772] node T_774 = and(s1_valid, rdy) node T_776 = eq(stall, UInt<1>("h00")) node T_777 = and(T_774, T_776) node T_779 = or(UInt<1>("h00"), s1_tag_match[1]) node T_780 = and(T_777, T_779) when T_780 : s2_dout[1] := T_773 skip smem T_783 : UInt<128>[256], clock node T_785 = eq(repl_way, UInt<2>("h02")) node T_786 = and(T_375.io.out.valid, T_785) when T_786 : node T_787 = cat(s2_idx, refill_cnt) infer accessor T_788 = T_783[T_787] T_788 := T_375.io.out.bits.data skip node T_789 = bits(s0_pgoff, 11, 4) node T_791 = eq(T_786, UInt<1>("h00")) node T_792 = and(T_791, s0_valid) poison T_793 : UInt<8> node T_794 = mux(T_792, T_789, T_793) infer accessor T_795 = T_783[T_794] node T_796 = and(s1_valid, rdy) node T_798 = eq(stall, UInt<1>("h00")) node T_799 = and(T_796, T_798) node T_801 = or(UInt<1>("h00"), s1_tag_match[2]) node T_802 = and(T_799, T_801) when T_802 : s2_dout[2] := T_795 skip smem T_805 : UInt<128>[256], clock node T_807 = eq(repl_way, UInt<2>("h03")) node T_808 = and(T_375.io.out.valid, T_807) when T_808 : node T_809 = cat(s2_idx, refill_cnt) infer accessor T_810 = T_805[T_809] T_810 := T_375.io.out.bits.data skip node T_811 = bits(s0_pgoff, 11, 4) node T_813 = eq(T_808, UInt<1>("h00")) node T_814 = and(T_813, s0_valid) poison T_815 : UInt<8> node T_816 = mux(T_814, T_811, T_815) infer accessor T_817 = T_805[T_816] node T_818 = and(s1_valid, rdy) node T_820 = eq(stall, UInt<1>("h00")) node T_821 = and(T_818, T_820) node T_823 = or(UInt<1>("h00"), s1_tag_match[3]) node T_824 = and(T_821, T_823) when T_824 : s2_dout[3] := T_817 skip node T_825 = bits(s2_offset, 3, 2) node T_826 = shl(T_825, 5) node T_827 = dshr(s2_dout[0], T_826) node T_828 = bits(T_827, 31, 0) node T_829 = bits(s2_offset, 3, 2) node T_830 = shl(T_829, 5) node T_831 = dshr(s2_dout[1], T_830) node T_832 = bits(T_831, 31, 0) node T_833 = bits(s2_offset, 3, 2) node T_834 = shl(T_833, 5) node T_835 = dshr(s2_dout[2], T_834) node T_836 = bits(T_835, 31, 0) node T_837 = bits(s2_offset, 3, 2) node T_838 = shl(T_837, 5) node T_839 = dshr(s2_dout[3], T_838) node T_840 = bits(T_839, 31, 0) node T_842 = mux(s2_tag_hit[0], T_828, UInt<1>("h00")) node T_844 = mux(s2_tag_hit[1], T_832, UInt<1>("h00")) node T_846 = mux(s2_tag_hit[2], T_836, UInt<1>("h00")) node T_848 = mux(s2_tag_hit[3], T_840, UInt<1>("h00")) node T_850 = or(T_842, T_844) node T_851 = or(T_850, T_846) node T_852 = or(T_851, T_848) wire T_853 : UInt<32> T_853 := UInt<1>("h00") T_853 := T_852 io.resp.bits.data := T_853 node T_856 = mux(s2_tag_hit[0], s2_dout[0], UInt<1>("h00")) node T_858 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>("h00")) node T_860 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>("h00")) node T_862 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>("h00")) node T_864 = or(T_856, T_858) node T_865 = or(T_864, T_860) node T_866 = or(T_865, T_862) wire T_867 : UInt<128> T_867 := UInt<1>("h00") T_867 := T_866 io.resp.bits.datablock := T_867 io.resp.valid := s2_hit node T_869 = eq(state, UInt<1>("h01")) io.mem.acquire.valid := T_869 node T_870 = shr(s2_addr, 6) node T_875 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_876 = cat(UInt<3>("h07"), T_875) wire T_910 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_910.union := UInt<1>("h00") T_910.a_type := UInt<1>("h00") T_910.is_builtin_type := UInt<1>("h00") T_910.data := UInt<1>("h00") T_910.addr_beat := UInt<1>("h00") T_910.client_xact_id := UInt<1>("h00") T_910.addr_block := UInt<1>("h00") T_910.is_builtin_type := UInt<1>("h01") T_910.a_type := UInt<3>("h01") T_910.client_xact_id := UInt<1>("h00") T_910.addr_block := T_870 T_910.addr_beat := UInt<1>("h00") T_910.data := UInt<1>("h00") T_910.union := T_876 io.mem.acquire.bits <> T_910 node T_948 = eq(UInt<1>("h00"), state) when T_948 : when s2_miss : state := UInt<1>("h01") skip invalidated := UInt<1>("h00") skip node T_950 = eq(UInt<1>("h01"), state) when T_950 : when io.mem.acquire.ready : state := UInt<2>("h02") skip skip node T_951 = eq(UInt<2>("h02"), state) when T_951 : when io.mem.grant.valid : state := UInt<2>("h03") skip skip node T_952 = eq(UInt<2>("h03"), state) when T_952 : when refill_done : state := UInt<1>("h00") skip skip module RocketCAM : input clock : Clock input reset : UInt<1> output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>} io.valid_bits := UInt<1>("h00") io.hits := UInt<1>("h00") io.hit := UInt<1>("h00") cmem cam_tags : UInt<34>[8], clock reg vb_array : UInt<8>, clock, reset onreset vb_array := UInt<8>("h00") when io.write : node T_21 = dshl(UInt<1>("h01"), io.write_addr) node T_22 = or(vb_array, T_21) node T_23 = not(vb_array) node T_24 = or(T_23, T_21) node T_25 = not(T_24) node T_26 = mux(UInt<1>("h01"), T_22, T_25) vb_array := T_26 infer accessor T_27 = cam_tags[io.write_addr] T_27 := io.write_tag skip when io.clear : node T_28 = not(io.clear_mask) node T_29 = and(vb_array, T_28) vb_array := T_29 skip node T_30 = bit(vb_array, 0) infer accessor T_32 = cam_tags[UInt<1>("h00")] node T_33 = eq(T_32, io.tag) node T_34 = and(T_30, T_33) node T_35 = bit(vb_array, 1) infer accessor T_37 = cam_tags[UInt<1>("h01")] node T_38 = eq(T_37, io.tag) node T_39 = and(T_35, T_38) node T_40 = bit(vb_array, 2) infer accessor T_42 = cam_tags[UInt<2>("h02")] node T_43 = eq(T_42, io.tag) node T_44 = and(T_40, T_43) node T_45 = bit(vb_array, 3) infer accessor T_47 = cam_tags[UInt<2>("h03")] node T_48 = eq(T_47, io.tag) node T_49 = and(T_45, T_48) node T_50 = bit(vb_array, 4) infer accessor T_52 = cam_tags[UInt<3>("h04")] node T_53 = eq(T_52, io.tag) node T_54 = and(T_50, T_53) node T_55 = bit(vb_array, 5) infer accessor T_57 = cam_tags[UInt<3>("h05")] node T_58 = eq(T_57, io.tag) node T_59 = and(T_55, T_58) node T_60 = bit(vb_array, 6) infer accessor T_62 = cam_tags[UInt<3>("h06")] node T_63 = eq(T_62, io.tag) node T_64 = and(T_60, T_63) node T_65 = bit(vb_array, 7) infer accessor T_67 = cam_tags[UInt<3>("h07")] node T_68 = eq(T_67, io.tag) node T_69 = and(T_65, T_68) io.valid_bits := vb_array wire T_71 : UInt<1>[8] T_71[0] := T_34 T_71[1] := T_39 T_71[2] := T_44 T_71[3] := T_49 T_71[4] := T_54 T_71[5] := T_59 T_71[6] := T_64 T_71[7] := T_69 node T_81 = cat(T_71[7], T_71[6]) node T_82 = cat(T_71[5], T_71[4]) node T_83 = cat(T_81, T_82) node T_84 = cat(T_71[3], T_71[2]) node T_85 = cat(T_71[1], T_71[0]) node T_86 = cat(T_84, T_85) node T_87 = cat(T_83, T_86) io.hits := T_87 node T_89 = neq(io.hits, UInt<1>("h00")) io.hit := T_89 module TLB : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} io.ptw.req.bits.fetch := UInt<1>("h00") io.ptw.req.bits.store := UInt<1>("h00") io.ptw.req.bits.prv := UInt<1>("h00") io.ptw.req.bits.addr := UInt<1>("h00") io.ptw.req.valid := UInt<1>("h00") io.resp.hit_idx := UInt<1>("h00") io.resp.xcpt_if := UInt<1>("h00") io.resp.xcpt_st := UInt<1>("h00") io.resp.xcpt_ld := UInt<1>("h00") io.resp.ppn := UInt<1>("h00") io.resp.miss := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg r_refill_tag : UInt, clock, reset reg r_refill_waddr : UInt, clock, reset reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset inst tag_cam of RocketCAM tag_cam.io.write_addr := UInt<1>("h00") tag_cam.io.write_tag := UInt<1>("h00") tag_cam.io.write := UInt<1>("h00") tag_cam.io.tag := UInt<1>("h00") tag_cam.io.clear_mask := UInt<1>("h00") tag_cam.io.clear := UInt<1>("h00") tag_cam.clock := clock tag_cam.reset := reset cmem tag_ram : UInt<20>[8], clock node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) tag_cam.io.tag := lookup_tag node T_182 = eq(state, UInt<2>("h02")) node T_183 = and(T_182, io.ptw.resp.valid) tag_cam.io.write := T_183 tag_cam.io.write_tag := r_refill_tag tag_cam.io.write_addr := r_refill_waddr node T_184 = bits(tag_cam.io.hits, 7, 4) node T_185 = bits(tag_cam.io.hits, 3, 0) node T_187 = neq(T_184, UInt<1>("h00")) node T_188 = or(T_184, T_185) node T_189 = bits(T_188, 3, 2) node T_190 = bits(T_188, 1, 0) node T_192 = neq(T_189, UInt<1>("h00")) node T_193 = or(T_189, T_190) node T_194 = bit(T_193, 1) node T_195 = cat(T_192, T_194) node tag_hit_addr = cat(T_187, T_195) reg valid_array : UInt<1>[8], clock, reset reg ur_array : UInt<1>[8], clock, reset reg uw_array : UInt<1>[8], clock, reset reg ux_array : UInt<1>[8], clock, reset reg sr_array : UInt<1>[8], clock, reset reg sw_array : UInt<1>[8], clock, reset reg sx_array : UInt<1>[8], clock, reset reg dirty_array : UInt<1>[8], clock, reset when io.ptw.resp.valid : infer accessor T_389 = tag_ram[r_refill_waddr] T_389 := io.ptw.resp.bits.pte.ppn infer accessor T_390 = valid_array[r_refill_waddr] node T_392 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) T_390 := T_392 infer accessor T_393 = ur_array[r_refill_waddr] node T_395 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_396 = and(io.ptw.resp.bits.pte.v, T_395) node T_398 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_399 = and(T_396, T_398) node T_401 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_402 = and(T_399, T_401) T_393 := T_402 infer accessor T_403 = uw_array[r_refill_waddr] node T_405 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_406 = and(io.ptw.resp.bits.pte.v, T_405) node T_408 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_409 = and(T_406, T_408) node T_410 = bit(io.ptw.resp.bits.pte.typ, 0) node T_411 = and(T_409, T_410) node T_413 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_414 = and(T_411, T_413) T_403 := T_414 infer accessor T_415 = ux_array[r_refill_waddr] node T_417 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_418 = and(io.ptw.resp.bits.pte.v, T_417) node T_420 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_421 = and(T_418, T_420) node T_422 = bit(io.ptw.resp.bits.pte.typ, 1) node T_423 = and(T_421, T_422) node T_425 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_426 = and(T_423, T_425) T_415 := T_426 infer accessor T_427 = sr_array[r_refill_waddr] node T_429 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_430 = and(io.ptw.resp.bits.pte.v, T_429) node T_432 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_433 = and(T_430, T_432) T_427 := T_433 infer accessor T_434 = sw_array[r_refill_waddr] node T_436 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_437 = and(io.ptw.resp.bits.pte.v, T_436) node T_438 = bit(io.ptw.resp.bits.pte.typ, 0) node T_439 = and(T_437, T_438) node T_441 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_442 = and(T_439, T_441) T_434 := T_442 infer accessor T_443 = sx_array[r_refill_waddr] node T_445 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) node T_446 = and(io.ptw.resp.bits.pte.v, T_445) node T_447 = bit(io.ptw.resp.bits.pte.typ, 1) node T_448 = and(T_446, T_447) node T_450 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_451 = and(T_448, T_450) T_443 := T_451 infer accessor T_452 = dirty_array[r_refill_waddr] T_452 := io.ptw.resp.bits.pte.d skip node T_453 = not(tag_cam.io.valid_bits) node T_455 = eq(T_453, UInt<1>("h00")) node has_invalid_entry = eq(T_455, UInt<1>("h00")) node T_458 = not(tag_cam.io.valid_bits) node T_459 = bit(T_458, 0) node T_460 = bit(T_458, 1) node T_461 = bit(T_458, 2) node T_462 = bit(T_458, 3) node T_463 = bit(T_458, 4) node T_464 = bit(T_458, 5) node T_465 = bit(T_458, 6) node T_466 = bit(T_458, 7) wire T_468 : UInt<1>[8] T_468[0] := T_459 T_468[1] := T_460 T_468[2] := T_461 T_468[3] := T_462 T_468[4] := T_463 T_468[5] := T_464 T_468[6] := T_465 T_468[7] := T_466 node T_486 = mux(T_468[6], UInt<3>("h06"), UInt<3>("h07")) node T_487 = mux(T_468[5], UInt<3>("h05"), T_486) node T_488 = mux(T_468[4], UInt<3>("h04"), T_487) node T_489 = mux(T_468[3], UInt<2>("h03"), T_488) node T_490 = mux(T_468[2], UInt<2>("h02"), T_489) node T_491 = mux(T_468[1], UInt<1>("h01"), T_490) node invalid_entry = mux(T_468[0], UInt<1>("h00"), T_491) reg T_494 : UInt<8>, clock, reset node T_496 = dshr(T_494, UInt<1>("h01")) node T_497 = bit(T_496, 0) node T_498 = cat(UInt<1>("h01"), T_497) node T_499 = dshr(T_494, T_498) node T_500 = bit(T_499, 0) node T_501 = cat(T_498, T_500) node T_502 = dshr(T_494, T_501) node T_503 = bit(T_502, 0) node T_504 = cat(T_501, T_503) node T_505 = bits(T_504, 2, 0) node repl_waddr = mux(has_invalid_entry, invalid_entry, T_505) node T_508 = eq(io.req.bits.instruction, UInt<1>("h00")) node T_509 = and(io.ptw.status.mprv, T_508) node priv = mux(T_509, io.ptw.status.prv1, io.ptw.status.prv) node priv_s = eq(priv, UInt<1>("h01")) node priv_uses_vm = leq(priv, UInt<1>("h01")) node T_537 = eq(r_req.store, UInt<1>("h00")) node T_538 = or(r_req.instruction, r_req.store) node T_540 = eq(T_538, UInt<1>("h00")) node T_541 = cat(r_req.store, T_540) node req_xwr = cat(T_537, T_541) node T_543 = cat(sr_array[7], sr_array[6]) node T_544 = cat(sr_array[5], sr_array[4]) node T_545 = cat(T_543, T_544) node T_546 = cat(sr_array[3], sr_array[2]) node T_547 = cat(sr_array[1], sr_array[0]) node T_548 = cat(T_546, T_547) node T_549 = cat(T_545, T_548) node T_550 = cat(ur_array[7], ur_array[6]) node T_551 = cat(ur_array[5], ur_array[4]) node T_552 = cat(T_550, T_551) node T_553 = cat(ur_array[3], ur_array[2]) node T_554 = cat(ur_array[1], ur_array[0]) node T_555 = cat(T_553, T_554) node T_556 = cat(T_552, T_555) node r_array = mux(priv_s, T_549, T_556) node T_558 = cat(sw_array[7], sw_array[6]) node T_559 = cat(sw_array[5], sw_array[4]) node T_560 = cat(T_558, T_559) node T_561 = cat(sw_array[3], sw_array[2]) node T_562 = cat(sw_array[1], sw_array[0]) node T_563 = cat(T_561, T_562) node T_564 = cat(T_560, T_563) node T_565 = cat(uw_array[7], uw_array[6]) node T_566 = cat(uw_array[5], uw_array[4]) node T_567 = cat(T_565, T_566) node T_568 = cat(uw_array[3], uw_array[2]) node T_569 = cat(uw_array[1], uw_array[0]) node T_570 = cat(T_568, T_569) node T_571 = cat(T_567, T_570) node w_array = mux(priv_s, T_564, T_571) node T_573 = cat(sx_array[7], sx_array[6]) node T_574 = cat(sx_array[5], sx_array[4]) node T_575 = cat(T_573, T_574) node T_576 = cat(sx_array[3], sx_array[2]) node T_577 = cat(sx_array[1], sx_array[0]) node T_578 = cat(T_576, T_577) node T_579 = cat(T_575, T_578) node T_580 = cat(ux_array[7], ux_array[6]) node T_581 = cat(ux_array[5], ux_array[4]) node T_582 = cat(T_580, T_581) node T_583 = cat(ux_array[3], ux_array[2]) node T_584 = cat(ux_array[1], ux_array[0]) node T_585 = cat(T_583, T_584) node T_586 = cat(T_582, T_585) node x_array = mux(priv_s, T_579, T_586) node T_588 = bit(io.ptw.status.vm, 3) node T_589 = and(T_588, priv_uses_vm) node T_591 = eq(io.req.bits.passthrough, UInt<1>("h00")) node vm_enabled = and(T_589, T_591) node T_593 = bit(io.req.bits.vpn, 27) node T_594 = bit(io.req.bits.vpn, 26) node bad_va = neq(T_593, T_594) node T_596 = cat(dirty_array[7], dirty_array[6]) node T_597 = cat(dirty_array[5], dirty_array[4]) node T_598 = cat(T_596, T_597) node T_599 = cat(dirty_array[3], dirty_array[2]) node T_600 = cat(dirty_array[1], dirty_array[0]) node T_601 = cat(T_599, T_600) node T_602 = cat(T_598, T_601) node T_604 = mux(io.req.bits.store, w_array, UInt<1>("h00")) node T_605 = not(T_604) node T_606 = or(T_602, T_605) node tag_hits = and(tag_cam.io.hits, T_606) node tag_hit = neq(tag_hits, UInt<1>("h00")) node tlb_hit = and(vm_enabled, tag_hit) node T_612 = eq(tag_hit, UInt<1>("h00")) node T_613 = and(vm_enabled, T_612) node T_615 = eq(bad_va, UInt<1>("h00")) node tlb_miss = and(T_613, T_615) node T_617 = and(io.req.valid, tlb_hit) when T_617 : node T_618 = bits(tag_cam.io.hits, 7, 4) node T_619 = bits(tag_cam.io.hits, 3, 0) node T_621 = neq(T_618, UInt<1>("h00")) node T_622 = or(T_618, T_619) node T_623 = bits(T_622, 3, 2) node T_624 = bits(T_622, 1, 0) node T_626 = neq(T_623, UInt<1>("h00")) node T_627 = or(T_623, T_624) node T_628 = bit(T_627, 1) node T_629 = cat(T_626, T_628) node T_630 = cat(T_621, T_629) node T_632 = bit(T_630, 2) node T_634 = dshl(UInt<8>("h01"), UInt<1>("h01")) node T_635 = bits(T_634, 7, 0) node T_636 = not(T_635) node T_637 = and(T_494, T_636) node T_639 = mux(T_632, UInt<1>("h00"), T_635) node T_640 = or(T_637, T_639) node T_641 = cat(UInt<1>("h01"), T_632) node T_642 = bit(T_630, 1) node T_644 = dshl(UInt<8>("h01"), T_641) node T_645 = bits(T_644, 7, 0) node T_646 = not(T_645) node T_647 = and(T_640, T_646) node T_649 = mux(T_642, UInt<1>("h00"), T_645) node T_650 = or(T_647, T_649) node T_651 = cat(T_641, T_642) node T_652 = bit(T_630, 0) node T_654 = dshl(UInt<8>("h01"), T_651) node T_655 = bits(T_654, 7, 0) node T_656 = not(T_655) node T_657 = and(T_650, T_656) node T_659 = mux(T_652, UInt<1>("h00"), T_655) node T_660 = or(T_657, T_659) node T_661 = cat(T_651, T_652) T_494 := T_660 skip node paddr = cat(io.resp.ppn, UInt<12>("h00")) node T_665 = geq(paddr, UInt<1>("h00")) node T_667 = lt(paddr, UInt<31>("h040000000")) node T_668 = and(T_665, T_667) node T_670 = geq(paddr, UInt<31>("h040000000")) node T_672 = lt(paddr, UInt<31>("h040008000")) node T_673 = and(T_670, T_672) node T_675 = geq(paddr, UInt<31>("h040008000")) node T_677 = lt(paddr, UInt<31>("h040008200")) node T_678 = and(T_675, T_677) node T_680 = geq(paddr, UInt<32>("h080000000")) node T_682 = lt(paddr, UInt<33>("h0100000000")) node T_683 = and(T_680, T_682) node T_684 = or(T_668, T_673) node T_685 = or(T_684, T_678) node addr_ok = or(T_685, T_683) node T_688 = geq(paddr, UInt<1>("h00")) node T_690 = lt(paddr, UInt<31>("h040000000")) node T_691 = and(T_688, T_690) wire T_701 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_701.x := UInt<1>("h00") T_701.w := UInt<1>("h00") T_701.r := UInt<1>("h00") T_701.x := UInt<1>("h01") T_701.w := UInt<1>("h01") T_701.r := UInt<1>("h01") node T_712 = geq(paddr, UInt<31>("h040000000")) node T_714 = lt(paddr, UInt<31>("h040008000")) node T_715 = and(T_712, T_714) wire T_725 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_725.x := UInt<1>("h00") T_725.w := UInt<1>("h00") T_725.r := UInt<1>("h00") T_725.x := UInt<1>("h00") T_725.w := UInt<1>("h01") T_725.r := UInt<1>("h01") node T_736 = geq(paddr, UInt<31>("h040008000")) node T_738 = lt(paddr, UInt<31>("h040008200")) node T_739 = and(T_736, T_738) wire T_749 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_749.x := UInt<1>("h00") T_749.w := UInt<1>("h00") T_749.r := UInt<1>("h00") T_749.x := UInt<1>("h00") T_749.w := UInt<1>("h01") T_749.r := UInt<1>("h01") node T_760 = geq(paddr, UInt<32>("h080000000")) node T_762 = lt(paddr, UInt<33>("h0100000000")) node T_763 = and(T_760, T_762) wire T_773 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_773.x := UInt<1>("h00") T_773.w := UInt<1>("h00") T_773.r := UInt<1>("h00") T_773.x := UInt<1>("h00") T_773.w := UInt<1>("h01") T_773.r := UInt<1>("h01") node T_783 = cat(T_701.w, T_701.x) node T_784 = cat(T_701.r, T_783) node T_786 = mux(T_691, T_784, UInt<1>("h00")) node T_787 = cat(T_725.w, T_725.x) node T_788 = cat(T_725.r, T_787) node T_790 = mux(T_715, T_788, UInt<1>("h00")) node T_791 = cat(T_749.w, T_749.x) node T_792 = cat(T_749.r, T_791) node T_794 = mux(T_739, T_792, UInt<1>("h00")) node T_795 = cat(T_773.w, T_773.x) node T_796 = cat(T_773.r, T_795) node T_798 = mux(T_763, T_796, UInt<1>("h00")) node T_803 = or(T_786, T_790) node T_804 = or(T_803, T_794) node T_805 = or(T_804, T_798) wire addr_prot : {r : UInt<1>, w : UInt<1>, x : UInt<1>} addr_prot.x := UInt<1>("h00") addr_prot.w := UInt<1>("h00") addr_prot.r := UInt<1>("h00") node T_817 = bits(T_805, 0, 0) addr_prot.x := T_817 node T_818 = bits(T_805, 1, 1) addr_prot.w := T_818 node T_819 = bits(T_805, 2, 2) addr_prot.r := T_819 node T_820 = eq(state, UInt<1>("h00")) io.req.ready := T_820 node T_822 = eq(addr_ok, UInt<1>("h00")) node T_824 = eq(addr_prot.r, UInt<1>("h00")) node T_825 = or(T_822, T_824) node T_826 = or(T_825, bad_va) node T_827 = and(r_array, tag_cam.io.hits) node T_829 = neq(T_827, UInt<1>("h00")) node T_831 = eq(T_829, UInt<1>("h00")) node T_832 = and(tlb_hit, T_831) node T_833 = or(T_826, T_832) io.resp.xcpt_ld := T_833 node T_835 = eq(addr_ok, UInt<1>("h00")) node T_837 = eq(addr_prot.w, UInt<1>("h00")) node T_838 = or(T_835, T_837) node T_839 = or(T_838, bad_va) node T_840 = and(w_array, tag_cam.io.hits) node T_842 = neq(T_840, UInt<1>("h00")) node T_844 = eq(T_842, UInt<1>("h00")) node T_845 = and(tlb_hit, T_844) node T_846 = or(T_839, T_845) io.resp.xcpt_st := T_846 node T_848 = eq(addr_ok, UInt<1>("h00")) node T_850 = eq(addr_prot.x, UInt<1>("h00")) node T_851 = or(T_848, T_850) node T_852 = or(T_851, bad_va) node T_853 = and(x_array, tag_cam.io.hits) node T_855 = neq(T_853, UInt<1>("h00")) node T_857 = eq(T_855, UInt<1>("h00")) node T_858 = and(tlb_hit, T_857) node T_859 = or(T_852, T_858) io.resp.xcpt_if := T_859 io.resp.miss := tlb_miss node T_860 = bit(tag_cam.io.hits, 0) node T_861 = bit(tag_cam.io.hits, 1) node T_862 = bit(tag_cam.io.hits, 2) node T_863 = bit(tag_cam.io.hits, 3) node T_864 = bit(tag_cam.io.hits, 4) node T_865 = bit(tag_cam.io.hits, 5) node T_866 = bit(tag_cam.io.hits, 6) node T_867 = bit(tag_cam.io.hits, 7) infer accessor T_869 = tag_ram[UInt<1>("h00")] infer accessor T_871 = tag_ram[UInt<1>("h01")] infer accessor T_873 = tag_ram[UInt<2>("h02")] infer accessor T_875 = tag_ram[UInt<2>("h03")] infer accessor T_877 = tag_ram[UInt<3>("h04")] infer accessor T_879 = tag_ram[UInt<3>("h05")] infer accessor T_881 = tag_ram[UInt<3>("h06")] infer accessor T_883 = tag_ram[UInt<3>("h07")] node T_885 = mux(T_860, T_869, UInt<1>("h00")) node T_887 = mux(T_861, T_871, UInt<1>("h00")) node T_889 = mux(T_862, T_873, UInt<1>("h00")) node T_891 = mux(T_863, T_875, UInt<1>("h00")) node T_893 = mux(T_864, T_877, UInt<1>("h00")) node T_895 = mux(T_865, T_879, UInt<1>("h00")) node T_897 = mux(T_866, T_881, UInt<1>("h00")) node T_899 = mux(T_867, T_883, UInt<1>("h00")) node T_901 = or(T_885, T_887) node T_902 = or(T_901, T_889) node T_903 = or(T_902, T_891) node T_904 = or(T_903, T_893) node T_905 = or(T_904, T_895) node T_906 = or(T_905, T_897) node T_907 = or(T_906, T_899) wire T_908 : UInt<20> T_908 := UInt<1>("h00") T_908 := T_907 node T_910 = bits(io.req.bits.vpn, 19, 0) node T_911 = mux(vm_enabled, T_908, T_910) io.resp.ppn := T_911 io.resp.hit_idx := tag_cam.io.hits node T_912 = and(io.req.ready, io.req.valid) node T_913 = or(io.ptw.invalidate, T_912) tag_cam.io.clear := T_913 node T_914 = cat(valid_array[7], valid_array[6]) node T_915 = cat(valid_array[5], valid_array[4]) node T_916 = cat(T_914, T_915) node T_917 = cat(valid_array[3], valid_array[2]) node T_918 = cat(valid_array[1], valid_array[0]) node T_919 = cat(T_917, T_918) node T_920 = cat(T_916, T_919) node T_921 = not(T_920) node T_922 = not(tag_hits) node T_923 = and(tag_cam.io.hits, T_922) node T_924 = or(T_921, T_923) tag_cam.io.clear_mask := T_924 when io.ptw.invalidate : node T_926 = not(UInt<8>("h00")) tag_cam.io.clear_mask := T_926 skip node T_927 = eq(state, UInt<1>("h01")) io.ptw.req.valid := T_927 io.ptw.req.bits.addr := r_refill_tag io.ptw.req.bits.prv := io.ptw.status.prv io.ptw.req.bits.store := r_req.store io.ptw.req.bits.fetch := r_req.instruction node T_928 = and(io.req.ready, io.req.valid) node T_929 = and(T_928, tlb_miss) when T_929 : state := UInt<1>("h01") r_refill_tag := lookup_tag r_refill_waddr := repl_waddr r_req <> io.req.bits skip node T_930 = eq(state, UInt<1>("h01")) when T_930 : when io.ptw.invalidate : state := UInt<1>("h00") skip when io.ptw.req.ready : state := UInt<2>("h02") when io.ptw.invalidate : state := UInt<2>("h03") skip skip skip node T_931 = eq(state, UInt<2>("h02")) node T_932 = and(T_931, io.ptw.invalidate) when T_932 : state := UInt<2>("h03") skip when io.ptw.resp.valid : state := UInt<1>("h00") skip module Frontend : input clock : Clock input reset : UInt<1> output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}} io.mem.grant.ready := UInt<1>("h00") io.mem.acquire.bits.union := UInt<1>("h00") io.mem.acquire.bits.a_type := UInt<1>("h00") io.mem.acquire.bits.is_builtin_type := UInt<1>("h00") io.mem.acquire.bits.data := UInt<1>("h00") io.mem.acquire.bits.addr_beat := UInt<1>("h00") io.mem.acquire.bits.client_xact_id := UInt<1>("h00") io.mem.acquire.bits.addr_block := UInt<1>("h00") io.mem.acquire.valid := UInt<1>("h00") io.ptw.req.bits.fetch := UInt<1>("h00") io.ptw.req.bits.store := UInt<1>("h00") io.ptw.req.bits.prv := UInt<1>("h00") io.ptw.req.bits.addr := UInt<1>("h00") io.ptw.req.valid := UInt<1>("h00") io.cpu.npc := UInt<1>("h00") io.cpu.btb_resp.bits.bht.value := UInt<1>("h00") io.cpu.btb_resp.bits.bht.history := UInt<1>("h00") io.cpu.btb_resp.bits.entry := UInt<1>("h00") io.cpu.btb_resp.bits.target := UInt<1>("h00") io.cpu.btb_resp.bits.bridx := UInt<1>("h00") io.cpu.btb_resp.bits.mask := UInt<1>("h00") io.cpu.btb_resp.bits.taken := UInt<1>("h00") io.cpu.btb_resp.valid := UInt<1>("h00") io.cpu.resp.bits.xcpt_if := UInt<1>("h00") io.cpu.resp.bits.mask := UInt<1>("h00") io.cpu.resp.bits.data[0] := UInt<1>("h00") io.cpu.resp.bits.pc := UInt<1>("h00") io.cpu.resp.valid := UInt<1>("h00") inst btb of BTB btb.io.invalidate := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.entry := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.target := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.mask := UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.taken := UInt<1>("h00") btb.io.ras_update.bits.prediction.valid := UInt<1>("h00") btb.io.ras_update.bits.returnAddr := UInt<1>("h00") btb.io.ras_update.bits.isReturn := UInt<1>("h00") btb.io.ras_update.bits.isCall := UInt<1>("h00") btb.io.ras_update.valid := UInt<1>("h00") btb.io.bht_update.bits.mispredict := UInt<1>("h00") btb.io.bht_update.bits.taken := UInt<1>("h00") btb.io.bht_update.bits.pc := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.entry := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.target := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.mask := UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.taken := UInt<1>("h00") btb.io.bht_update.bits.prediction.valid := UInt<1>("h00") btb.io.bht_update.valid := UInt<1>("h00") btb.io.btb_update.bits.br_pc := UInt<1>("h00") btb.io.btb_update.bits.isReturn := UInt<1>("h00") btb.io.btb_update.bits.isJump := UInt<1>("h00") btb.io.btb_update.bits.taken := UInt<1>("h00") btb.io.btb_update.bits.target := UInt<1>("h00") btb.io.btb_update.bits.pc := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.entry := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.target := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.mask := UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.taken := UInt<1>("h00") btb.io.btb_update.bits.prediction.valid := UInt<1>("h00") btb.io.btb_update.valid := UInt<1>("h00") btb.io.req.bits.addr := UInt<1>("h00") btb.io.req.valid := UInt<1>("h00") btb.clock := clock btb.reset := reset inst icache of ICache icache.io.mem.grant.bits.g_type := UInt<1>("h00") icache.io.mem.grant.bits.is_builtin_type := UInt<1>("h00") icache.io.mem.grant.bits.manager_xact_id := UInt<1>("h00") icache.io.mem.grant.bits.client_xact_id := UInt<1>("h00") icache.io.mem.grant.bits.data := UInt<1>("h00") icache.io.mem.grant.bits.addr_beat := UInt<1>("h00") icache.io.mem.grant.valid := UInt<1>("h00") icache.io.mem.acquire.ready := UInt<1>("h00") icache.io.invalidate := UInt<1>("h00") icache.io.resp.ready := UInt<1>("h00") icache.io.req.bits.kill := UInt<1>("h00") icache.io.req.bits.ppn := UInt<1>("h00") icache.io.req.bits.idx := UInt<1>("h00") icache.io.req.valid := UInt<1>("h00") icache.clock := clock icache.reset := reset inst tlb of TLB tlb.io.ptw.invalidate := UInt<1>("h00") tlb.io.ptw.status.ie := UInt<1>("h00") tlb.io.ptw.status.prv := UInt<1>("h00") tlb.io.ptw.status.ie1 := UInt<1>("h00") tlb.io.ptw.status.prv1 := UInt<1>("h00") tlb.io.ptw.status.ie2 := UInt<1>("h00") tlb.io.ptw.status.prv2 := UInt<1>("h00") tlb.io.ptw.status.ie3 := UInt<1>("h00") tlb.io.ptw.status.prv3 := UInt<1>("h00") tlb.io.ptw.status.fs := UInt<1>("h00") tlb.io.ptw.status.xs := UInt<1>("h00") tlb.io.ptw.status.mprv := UInt<1>("h00") tlb.io.ptw.status.vm := UInt<1>("h00") tlb.io.ptw.status.zero1 := UInt<1>("h00") tlb.io.ptw.status.sd_rv32 := UInt<1>("h00") tlb.io.ptw.status.zero2 := UInt<1>("h00") tlb.io.ptw.status.sd := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.v := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.typ := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.r := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.d := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") tlb.io.ptw.resp.bits.pte.ppn := UInt<1>("h00") tlb.io.ptw.resp.bits.error := UInt<1>("h00") tlb.io.ptw.resp.valid := UInt<1>("h00") tlb.io.ptw.req.ready := UInt<1>("h00") tlb.io.req.bits.store := UInt<1>("h00") tlb.io.req.bits.instruction := UInt<1>("h00") tlb.io.req.bits.passthrough := UInt<1>("h00") tlb.io.req.bits.vpn := UInt<1>("h00") tlb.io.req.bits.asid := UInt<1>("h00") tlb.io.req.valid := UInt<1>("h00") tlb.clock := clock tlb.reset := reset reg s1_pc_ : UInt, clock, reset node T_1322 = not(s1_pc_) node T_1324 = or(T_1322, UInt<2>("h03")) node s1_pc = not(T_1324) reg s1_same_block : UInt<1>, clock, reset reg s2_valid : UInt<1>, clock, reset onreset s2_valid := UInt<1>("h01") reg s2_pc : UInt, clock, reset onreset s2_pc := UInt<10>("h0200") reg s2_btb_resp_valid : UInt<1>, clock, reset onreset s2_btb_resp_valid := UInt<1>("h00") reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset reg s2_xcpt_if : UInt<1>, clock, reset onreset s2_xcpt_if := UInt<1>("h00") node T_1345 = bit(btb.io.resp.bits.target, 38) node btbTarget = cat(T_1345, btb.io.resp.bits.target) node ntpc_0 = addw(s1_pc, UInt<3>("h04")) node T_1349 = bit(s1_pc, 38) node T_1350 = bit(ntpc_0, 38) node T_1351 = and(T_1349, T_1350) node T_1352 = bits(ntpc_0, 38, 2) node T_1354 = cat(T_1352, UInt<2>("h00")) node ntpc = cat(T_1351, T_1354) node T_1357 = eq(icache.io.resp.valid, UInt<1>("h00")) node icmiss = and(s2_valid, T_1357) node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc) node npc = mux(icmiss, s2_pc, predicted_npc) node T_1362 = eq(icmiss, UInt<1>("h00")) node T_1364 = eq(io.cpu.req.valid, UInt<1>("h00")) node T_1365 = and(T_1362, T_1364) node T_1367 = eq(btb.io.resp.bits.taken, UInt<1>("h00")) node T_1368 = and(T_1365, T_1367) node T_1370 = and(ntpc, UInt<5>("h010")) node T_1372 = and(s1_pc, UInt<5>("h010")) node T_1373 = eq(T_1370, T_1372) node s0_same_block = and(T_1368, T_1373) node T_1376 = eq(io.cpu.resp.ready, UInt<1>("h00")) node stall = and(io.cpu.resp.valid, T_1376) node T_1379 = eq(stall, UInt<1>("h00")) when T_1379 : node T_1381 = eq(tlb.io.resp.miss, UInt<1>("h00")) node T_1382 = and(s0_same_block, T_1381) s1_same_block := T_1382 s1_pc_ := npc node T_1384 = eq(icmiss, UInt<1>("h00")) s2_valid := T_1384 node T_1386 = eq(icmiss, UInt<1>("h00")) when T_1386 : s2_pc := s1_pc s2_btb_resp_valid := btb.io.resp.valid when btb.io.resp.valid : s2_btb_resp_bits <> btb.io.resp.bits skip s2_xcpt_if := tlb.io.resp.xcpt_if skip skip when io.cpu.req.valid : s1_same_block := UInt<1>("h00") s1_pc_ := io.cpu.req.bits.pc s2_valid := UInt<1>("h00") skip node T_1390 = eq(stall, UInt<1>("h00")) node T_1392 = eq(icmiss, UInt<1>("h00")) node T_1393 = and(T_1390, T_1392) btb.io.req.valid := T_1393 btb.io.req.bits.addr := s1_pc btb.io.btb_update <> io.cpu.btb_update btb.io.bht_update <> io.cpu.bht_update btb.io.ras_update <> io.cpu.ras_update node T_1394 = or(io.cpu.invalidate, io.ptw.invalidate) btb.io.invalidate := T_1394 io.ptw <> tlb.io.ptw node T_1396 = eq(stall, UInt<1>("h00")) node T_1398 = eq(icmiss, UInt<1>("h00")) node T_1399 = and(T_1396, T_1398) tlb.io.req.valid := T_1399 node T_1400 = shr(s1_pc, 12) tlb.io.req.bits.vpn := T_1400 tlb.io.req.bits.asid := UInt<1>("h00") tlb.io.req.bits.passthrough := UInt<1>("h00") tlb.io.req.bits.instruction := UInt<1>("h01") tlb.io.req.bits.store := UInt<1>("h00") io.mem <> icache.io.mem node T_1406 = eq(stall, UInt<1>("h00")) node T_1408 = eq(s0_same_block, UInt<1>("h00")) node T_1409 = and(T_1406, T_1408) icache.io.req.valid := T_1409 icache.io.req.bits.idx := io.cpu.npc icache.io.invalidate := io.cpu.invalidate icache.io.req.bits.ppn := tlb.io.resp.ppn node T_1410 = or(io.cpu.req.valid, tlb.io.resp.miss) node T_1411 = or(T_1410, tlb.io.resp.xcpt_if) node T_1412 = or(T_1411, icmiss) node T_1413 = or(T_1412, io.ptw.invalidate) icache.io.req.bits.kill := T_1413 node T_1415 = eq(stall, UInt<1>("h00")) node T_1417 = eq(s1_same_block, UInt<1>("h00")) node T_1418 = and(T_1415, T_1417) icache.io.resp.ready := T_1418 node T_1419 = or(s2_xcpt_if, icache.io.resp.valid) node T_1420 = and(s2_valid, T_1419) io.cpu.resp.valid := T_1420 io.cpu.resp.bits.pc := s2_pc node T_1421 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) io.cpu.npc := T_1421 node T_1422 = bits(s2_pc, 3, 2) node T_1423 = shl(T_1422, 5) node fetch_data = dshr(icache.io.resp.bits.datablock, T_1423) node T_1425 = bits(fetch_data, 31, 0) io.cpu.resp.bits.data[0] := T_1425 node T_1427 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) node T_1428 = mux(s2_btb_resp_valid, T_1427, UInt<2>("h03")) io.cpu.resp.bits.mask := T_1428 io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.btb_resp.valid := s2_btb_resp_valid io.cpu.btb_resp.bits <> s2_btb_resp_bits module WritebackUnit : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} io.release.bits.voluntary := UInt<1>("h00") io.release.bits.r_type := UInt<1>("h00") io.release.bits.data := UInt<1>("h00") io.release.bits.addr_beat := UInt<1>("h00") io.release.bits.client_xact_id := UInt<1>("h00") io.release.bits.addr_block := UInt<1>("h00") io.release.valid := UInt<1>("h00") io.data_req.bits.addr := UInt<1>("h00") io.data_req.bits.way_en := UInt<1>("h00") io.data_req.valid := UInt<1>("h00") io.meta_read.bits.tag := UInt<1>("h00") io.meta_read.bits.idx := UInt<1>("h00") io.meta_read.valid := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg active : UInt<1>, clock, reset onreset active := UInt<1>("h00") reg r1_data_req_fired : UInt<1>, clock, reset onreset r1_data_req_fired := UInt<1>("h00") reg r2_data_req_fired : UInt<1>, clock, reset onreset r2_data_req_fired := UInt<1>("h00") reg data_req_cnt : UInt<3>, clock, reset onreset data_req_cnt := UInt<3>("h00") node T_292 = not(UInt<1>("h01")) node beat_done = eq(T_292, UInt<1>("h00")) node T_295 = and(io.release.ready, io.release.valid) reg beat_cnt : UInt<2>, clock, reset onreset beat_cnt := UInt<2>("h00") when T_295 : node T_299 = eq(beat_cnt, UInt<2>("h03")) node T_301 = and(UInt<1>("h00"), T_299) node T_304 = addw(beat_cnt, UInt<1>("h01")) node T_305 = mux(T_301, UInt<1>("h00"), T_304) beat_cnt := T_305 skip node all_beats_done = and(T_295, T_299) reg req : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}, clock, reset io.release.valid := UInt<1>("h00") when active : r1_data_req_fired := UInt<1>("h00") r2_data_req_fired := r1_data_req_fired node T_371 = and(io.data_req.ready, io.data_req.valid) node T_372 = and(io.meta_read.ready, io.meta_read.valid) node T_373 = and(T_371, T_372) when T_373 : r1_data_req_fired := UInt<1>("h01") node T_376 = addw(data_req_cnt, UInt<1>("h01")) data_req_cnt := T_376 skip when r2_data_req_fired : io.release.valid := beat_done when beat_done : node T_378 = eq(io.release.ready, UInt<1>("h00")) when T_378 : r1_data_req_fired := UInt<1>("h00") r2_data_req_fired := UInt<1>("h00") node T_382 = and(UInt<1>("h01"), r1_data_req_fired) node T_385 = mux(T_382, UInt<2>("h02"), UInt<1>("h01")) node T_386 = subw(data_req_cnt, T_385) data_req_cnt := T_386 skip else : skip skip node T_388 = eq(r1_data_req_fired, UInt<1>("h00")) when T_388 : node T_390 = lt(data_req_cnt, UInt<3>("h04")) node T_392 = eq(io.release.ready, UInt<1>("h00")) node T_393 = or(T_390, T_392) active := T_393 skip skip skip node T_394 = and(io.req.ready, io.req.valid) when T_394 : active := UInt<1>("h01") data_req_cnt := UInt<1>("h00") req <> io.req.bits skip node T_398 = eq(active, UInt<1>("h00")) io.req.ready := T_398 node req_idx = bits(req.addr_block, 5, 0) node T_401 = lt(data_req_cnt, UInt<3>("h04")) node fire = and(active, T_401) io.meta_read.valid := fire io.meta_read.bits.idx := req_idx node T_403 = shr(req.addr_block, 6) io.meta_read.bits.tag := T_403 io.data_req.valid := fire io.data_req.bits.way_en := req.way_en node T_404 = bits(data_req_cnt, 1, 0) node T_405 = cat(req_idx, T_404) node T_406 = shl(T_405, 4) io.data_req.bits.addr := T_406 io.release.bits <> req io.release.bits.addr_beat := beat_cnt io.release.bits.data := io.data_resp module ProbeUnit : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}} io.wb_req.bits.way_en := UInt<1>("h00") io.wb_req.bits.voluntary := UInt<1>("h00") io.wb_req.bits.r_type := UInt<1>("h00") io.wb_req.bits.data := UInt<1>("h00") io.wb_req.bits.addr_beat := UInt<1>("h00") io.wb_req.bits.client_xact_id := UInt<1>("h00") io.wb_req.bits.addr_block := UInt<1>("h00") io.wb_req.valid := UInt<1>("h00") io.meta_write.bits.data.coh.state := UInt<1>("h00") io.meta_write.bits.data.tag := UInt<1>("h00") io.meta_write.bits.way_en := UInt<1>("h00") io.meta_write.bits.idx := UInt<1>("h00") io.meta_write.valid := UInt<1>("h00") io.meta_read.bits.tag := UInt<1>("h00") io.meta_read.bits.idx := UInt<1>("h00") io.meta_read.valid := UInt<1>("h00") io.rep.bits.voluntary := UInt<1>("h00") io.rep.bits.r_type := UInt<1>("h00") io.rep.bits.data := UInt<1>("h00") io.rep.bits.addr_beat := UInt<1>("h00") io.rep.bits.client_xact_id := UInt<1>("h00") io.rep.bits.addr_block := UInt<1>("h00") io.rep.valid := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg old_coh : {state : UInt<2>}, clock, reset reg way_en : UInt, clock, reset reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clock, reset node tag_matches = neq(way_en, UInt<1>("h00")) node T_636 = eq(state, UInt<3>("h07")) node T_637 = and(T_636, io.meta_write.ready) when T_637 : state := UInt<1>("h00") skip node T_638 = eq(state, UInt<3>("h06")) node T_639 = and(T_638, io.wb_req.ready) when T_639 : state := UInt<3>("h07") skip node T_640 = eq(state, UInt<3>("h05")) node T_641 = and(T_640, io.wb_req.ready) when T_641 : state := UInt<3>("h06") skip node T_642 = eq(state, UInt<3>("h04")) node T_643 = and(T_642, io.rep.ready) when T_643 : state := UInt<1>("h00") when tag_matches : wire T_645 : UInt<2>[1] T_645[0] := UInt<2>("h03") node T_648 = eq(T_645[0], old_coh.state) node T_650 = or(UInt<1>("h00"), T_648) node T_651 = mux(T_650, UInt<3>("h05"), UInt<3>("h07")) state := T_651 skip skip node T_652 = eq(state, UInt<2>("h03")) when T_652 : state := UInt<3>("h04") old_coh <> io.block_state way_en := io.way_en node T_654 = eq(io.mshr_rdy, UInt<1>("h00")) when T_654 : state := UInt<1>("h01") skip skip node T_655 = eq(state, UInt<2>("h02")) when T_655 : state := UInt<2>("h03") skip node T_656 = eq(state, UInt<1>("h01")) node T_657 = and(T_656, io.meta_read.ready) when T_657 : state := UInt<2>("h02") skip node T_658 = eq(state, UInt<1>("h00")) node T_659 = and(T_658, io.req.valid) when T_659 : state := UInt<1>("h01") req <> io.req.bits skip wire miss_coh : {state : UInt<2>} miss_coh.state := UInt<1>("h00") miss_coh.state := UInt<1>("h00") wire reply_coh : {state : UInt<2>} reply_coh <> miss_coh when tag_matches : reply_coh <> old_coh skip wire T_790 : UInt<2>[1] T_790[0] := UInt<2>("h03") node T_793 = eq(T_790[0], reply_coh.state) node T_795 = or(UInt<1>("h00"), T_793) node T_796 = mux(T_795, UInt<1>("h00"), UInt<2>("h03")) node T_797 = mux(T_795, UInt<1>("h01"), UInt<3>("h04")) node T_798 = mux(T_795, UInt<2>("h02"), UInt<3>("h05")) node T_799 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_800 = mux(T_799, T_798, UInt<3>("h05")) node T_801 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_802 = mux(T_801, T_797, T_800) node T_803 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_804 = mux(T_803, T_796, T_802) wire T_806 : UInt<2>[1] T_806[0] := UInt<2>("h03") node T_809 = eq(T_806[0], reply_coh.state) node T_811 = or(UInt<1>("h00"), T_809) node T_812 = mux(T_811, UInt<1>("h00"), UInt<2>("h03")) node T_813 = mux(T_811, UInt<1>("h01"), UInt<3>("h04")) node T_814 = mux(T_811, UInt<2>("h02"), UInt<3>("h05")) node T_815 = eq(UInt<5>("h013"), UInt<5>("h011")) node T_816 = mux(T_815, T_814, UInt<3>("h05")) node T_817 = eq(UInt<5>("h011"), UInt<5>("h011")) node T_818 = mux(T_817, T_813, T_816) node T_819 = eq(UInt<5>("h010"), UInt<5>("h011")) node T_820 = mux(T_819, T_812, T_818) wire T_822 : UInt<2>[1] T_822[0] := UInt<2>("h03") node T_825 = eq(T_822[0], reply_coh.state) node T_827 = or(UInt<1>("h00"), T_825) node T_828 = mux(T_827, UInt<1>("h00"), UInt<2>("h03")) node T_829 = mux(T_827, UInt<1>("h01"), UInt<3>("h04")) node T_830 = mux(T_827, UInt<2>("h02"), UInt<3>("h05")) node T_831 = eq(UInt<5>("h013"), UInt<5>("h013")) node T_832 = mux(T_831, T_830, UInt<3>("h05")) node T_833 = eq(UInt<5>("h011"), UInt<5>("h013")) node T_834 = mux(T_833, T_829, T_832) node T_835 = eq(UInt<5>("h010"), UInt<5>("h013")) node T_836 = mux(T_835, T_828, T_834) node T_837 = eq(UInt<2>("h02"), req.p_type) node T_838 = mux(T_837, T_836, UInt<2>("h03")) node T_839 = eq(UInt<1>("h01"), req.p_type) node T_840 = mux(T_839, T_820, T_838) node T_841 = eq(UInt<1>("h00"), req.p_type) node T_842 = mux(T_841, T_804, T_840) wire reply : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} reply.voluntary := UInt<1>("h00") reply.r_type := UInt<1>("h00") reply.data := UInt<1>("h00") reply.addr_beat := UInt<1>("h00") reply.client_xact_id := UInt<1>("h00") reply.addr_block := UInt<1>("h00") reply.r_type := T_842 reply.client_xact_id := UInt<1>("h00") reply.addr_block := req.addr_block reply.addr_beat := UInt<1>("h00") reply.data := UInt<1>("h00") reply.voluntary := UInt<1>("h00") node T_910 = eq(state, UInt<1>("h00")) io.req.ready := T_910 node T_911 = eq(state, UInt<3>("h04")) wire T_913 : UInt<2>[1] T_913[0] := UInt<2>("h03") node T_916 = eq(T_913[0], old_coh.state) node T_918 = or(UInt<1>("h00"), T_916) node T_919 = and(tag_matches, T_918) node T_921 = eq(T_919, UInt<1>("h00")) node T_922 = and(T_911, T_921) io.rep.valid := T_922 io.rep.bits <> reply node T_923 = eq(state, UInt<1>("h01")) io.meta_read.valid := T_923 io.meta_read.bits.idx := req.addr_block node T_924 = shr(req.addr_block, 6) io.meta_read.bits.tag := T_924 node T_925 = eq(state, UInt<3>("h07")) io.meta_write.valid := T_925 io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req.addr_block node T_926 = shr(req.addr_block, 6) io.meta_write.bits.data.tag := T_926 node T_927 = eq(UInt<2>("h02"), req.p_type) node T_928 = mux(T_927, old_coh.state, old_coh.state) node T_929 = eq(UInt<1>("h01"), req.p_type) node T_930 = mux(T_929, UInt<1>("h01"), T_928) node T_931 = eq(UInt<1>("h00"), req.p_type) node T_932 = mux(T_931, UInt<1>("h00"), T_930) wire T_958 : {state : UInt<2>} T_958.state := UInt<1>("h00") T_958.state := T_932 io.meta_write.bits.data.coh <> T_958 node T_984 = eq(state, UInt<3>("h05")) io.wb_req.valid := T_984 io.wb_req.bits <> reply io.wb_req.bits.way_en := way_en module Arbiter_80 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.tag := UInt<1>("h00") io.out.bits.idx := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_108 : UInt<1> T_108 := UInt<1>("h00") infer accessor T_110 = io.in[T_108] io.out.valid := T_110.valid infer accessor T_119 = io.in[T_108] io.out.bits <> T_119.bits io.chosen := T_108 infer accessor T_128 = io.in[T_108] T_128.ready := UInt<1>("h00") node T_140 = or(UInt<1>("h00"), io.in[0].valid) node T_142 = eq(T_140, UInt<1>("h00")) node T_144 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_145 = mux(UInt<1>("h00"), T_144, UInt<1>("h01")) node T_146 = and(T_145, io.out.ready) io.in[0].ready := T_146 node T_148 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_149 = mux(UInt<1>("h00"), T_148, T_142) node T_150 = and(T_149, io.out.ready) io.in[1].ready := T_150 node T_153 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_154 = mux(UInt<1>("h00"), UInt<1>("h01"), T_153) T_108 := T_154 module Arbiter_81 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.data.coh.state := UInt<1>("h00") io.out.bits.data.tag := UInt<1>("h00") io.out.bits.way_en := UInt<1>("h00") io.out.bits.idx := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_702 : UInt<1> T_702 := UInt<1>("h00") infer accessor T_704 = io.in[T_702] io.out.valid := T_704.valid infer accessor T_767 = io.in[T_702] io.out.bits <> T_767.bits io.chosen := T_702 infer accessor T_830 = io.in[T_702] T_830.ready := UInt<1>("h00") node T_896 = or(UInt<1>("h00"), io.in[0].valid) node T_898 = eq(T_896, UInt<1>("h00")) node T_900 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_901 = mux(UInt<1>("h00"), T_900, UInt<1>("h01")) node T_902 = and(T_901, io.out.ready) io.in[0].ready := T_902 node T_904 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_905 = mux(UInt<1>("h00"), T_904, T_898) node T_906 = and(T_905, io.out.ready) io.in[1].ready := T_906 node T_909 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_910 = mux(UInt<1>("h00"), UInt<1>("h01"), T_909) T_702 := T_910 module LockingArbiter : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.union := UInt<1>("h00") io.out.bits.a_type := UInt<1>("h00") io.out.bits.is_builtin_type := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") reg T_852 : UInt<1>, clock, reset onreset T_852 := UInt<1>("h00") reg T_854 : UInt, clock, reset onreset T_854 := UInt<2>("h02") wire T_856 : UInt<2> T_856 := UInt<1>("h00") infer accessor T_858 = io.in[T_856] io.out.valid := T_858.valid infer accessor T_923 = io.in[T_856] io.out.bits <> T_923.bits io.chosen := T_856 infer accessor T_988 = io.in[T_856] T_988.ready := UInt<1>("h00") node T_1056 = or(UInt<1>("h00"), io.in[0].valid) node T_1058 = eq(T_1056, UInt<1>("h00")) node T_1060 = or(UInt<1>("h00"), io.in[0].valid) node T_1061 = or(T_1060, io.in[1].valid) node T_1063 = eq(T_1061, UInt<1>("h00")) node T_1065 = eq(T_854, UInt<1>("h00")) node T_1066 = mux(T_852, T_1065, UInt<1>("h01")) node T_1067 = and(T_1066, io.out.ready) io.in[0].ready := T_1067 node T_1069 = eq(T_854, UInt<1>("h01")) node T_1070 = mux(T_852, T_1069, T_1058) node T_1071 = and(T_1070, io.out.ready) io.in[1].ready := T_1071 node T_1073 = eq(T_854, UInt<2>("h02")) node T_1074 = mux(T_852, T_1073, T_1063) node T_1075 = and(T_1074, io.out.ready) io.in[2].ready := T_1075 reg T_1077 : UInt<2>, clock, reset onreset T_1077 := UInt<2>("h00") node T_1079 = addw(T_1077, UInt<1>("h01")) node T_1080 = and(io.out.ready, io.out.valid) when T_1080 : node T_1082 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_1085 : UInt<3>[1] T_1085[0] := UInt<3>("h03") node T_1088 = eq(T_1085[0], io.out.bits.a_type) node T_1090 = or(UInt<1>("h00"), T_1088) node T_1091 = and(T_1082, T_1090) when T_1091 : T_1077 := T_1079 node T_1093 = eq(T_852, UInt<1>("h00")) when T_1093 : T_852 := UInt<1>("h01") node T_1095 = and(io.in[0].ready, io.in[0].valid) node T_1096 = and(io.in[1].ready, io.in[1].valid) node T_1097 = and(io.in[2].ready, io.in[2].valid) wire T_1099 : UInt<1>[3] T_1099[0] := T_1095 T_1099[1] := T_1096 T_1099[2] := T_1097 node T_1107 = mux(T_1099[1], UInt<1>("h01"), UInt<2>("h02")) node T_1108 = mux(T_1099[0], UInt<1>("h00"), T_1107) T_854 := T_1108 skip skip node T_1110 = eq(T_1079, UInt<1>("h00")) when T_1110 : T_852 := UInt<1>("h00") skip skip node T_1114 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node choose = mux(io.in[0].valid, UInt<1>("h00"), T_1114) node T_1117 = mux(T_852, T_854, choose) T_856 := T_1117 module Arbiter_82 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.way_en := UInt<1>("h00") io.out.bits.voluntary := UInt<1>("h00") io.out.bits.r_type := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_724 : UInt<1> T_724 := UInt<1>("h00") infer accessor T_726 = io.in[T_724] io.out.valid := T_726.valid infer accessor T_791 = io.in[T_724] io.out.bits <> T_791.bits io.chosen := T_724 infer accessor T_856 = io.in[T_724] T_856.ready := UInt<1>("h00") node T_924 = or(UInt<1>("h00"), io.in[0].valid) node T_926 = eq(T_924, UInt<1>("h00")) node T_928 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_929 = mux(UInt<1>("h00"), T_928, UInt<1>("h01")) node T_930 = and(T_929, io.out.ready) io.in[0].ready := T_930 node T_932 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_933 = mux(UInt<1>("h00"), T_932, T_926) node T_934 = and(T_933, io.out.ready) io.in[1].ready := T_934 node T_937 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_938 = mux(UInt<1>("h00"), UInt<1>("h01"), T_937) T_724 := T_938 module Arbiter_83 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.sdq_id := UInt<1>("h00") io.out.bits.phys := UInt<1>("h00") io.out.bits.kill := UInt<1>("h00") io.out.bits.typ := UInt<1>("h00") io.out.bits.cmd := UInt<1>("h00") io.out.bits.tag := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_218 : UInt<1> T_218 := UInt<1>("h00") infer accessor T_220 = io.in[T_218] io.out.valid := T_220.valid infer accessor T_239 = io.in[T_218] io.out.bits <> T_239.bits io.chosen := T_218 infer accessor T_258 = io.in[T_218] T_258.ready := UInt<1>("h00") node T_280 = or(UInt<1>("h00"), io.in[0].valid) node T_282 = eq(T_280, UInt<1>("h00")) node T_284 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_285 = mux(UInt<1>("h00"), T_284, UInt<1>("h01")) node T_286 = and(T_285, io.out.ready) io.in[0].ready := T_286 node T_288 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_289 = mux(UInt<1>("h00"), T_288, T_282) node T_290 = and(T_289, io.out.ready) io.in[1].ready := T_290 node T_293 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_294 = mux(UInt<1>("h00"), UInt<1>("h01"), T_293) T_218 := T_294 module Arbiter_84 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_64 : UInt<1> T_64 := UInt<1>("h00") infer accessor T_66 = io.in[T_64] io.out.valid := T_66.valid infer accessor T_71 = io.in[T_64] io.out.bits := T_71.bits io.chosen := T_64 infer accessor T_76 = io.in[T_64] T_76.ready := UInt<1>("h00") node T_84 = or(UInt<1>("h00"), io.in[0].valid) node T_86 = eq(T_84, UInt<1>("h00")) node T_88 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_89 = mux(UInt<1>("h00"), T_88, UInt<1>("h01")) node T_90 = and(T_89, io.out.ready) io.in[0].ready := T_90 node T_92 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_93 = mux(UInt<1>("h00"), T_92, T_86) node T_94 = and(T_93, io.out.ready) io.in[1].ready := T_94 node T_97 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_98 = mux(UInt<1>("h00"), UInt<1>("h01"), T_97) T_64 := T_98 module Queue_85 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>} io.count := UInt<1>("h00") io.deq.bits.sdq_id := UInt<1>("h00") io.deq.bits.phys := UInt<1>("h00") io.deq.bits.kill := UInt<1>("h00") io.deq.bits.typ := UInt<1>("h00") io.deq.bits.cmd := UInt<1>("h00") io.deq.bits.tag := UInt<1>("h00") io.deq.bits.addr := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16], clock reg T_89 : UInt<4>, clock, reset onreset T_89 := UInt<4>("h00") reg T_91 : UInt<4>, clock, reset onreset T_91 := UInt<4>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_89, T_91) node T_96 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_96) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_102 = and(io.enq.ready, io.enq.valid) node T_104 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_102, T_104) node T_106 = and(io.deq.ready, io.deq.valid) node T_108 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_106, T_108) when do_enq : infer accessor T_110 = ram[T_89] T_110 <> io.enq.bits node T_119 = eq(T_89, UInt<4>("h0f")) node T_121 = and(UInt<1>("h00"), T_119) node T_124 = addw(T_89, UInt<1>("h01")) node T_125 = mux(T_121, UInt<1>("h00"), T_124) T_89 := T_125 skip when do_deq : node T_127 = eq(T_91, UInt<4>("h0f")) node T_129 = and(UInt<1>("h00"), T_127) node T_132 = addw(T_91, UInt<1>("h01")) node T_133 = mux(T_129, UInt<1>("h00"), T_132) T_91 := T_133 skip node T_134 = neq(do_enq, do_deq) when T_134 : maybe_full := do_enq skip node T_136 = eq(empty, UInt<1>("h00")) node T_138 = and(UInt<1>("h00"), io.enq.valid) node T_139 = or(T_136, T_138) io.deq.valid := T_139 node T_141 = eq(full, UInt<1>("h00")) node T_143 = and(UInt<1>("h00"), io.deq.ready) node T_144 = or(T_141, T_143) io.enq.ready := T_144 infer accessor T_145 = ram[T_91] wire T_161 : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} T_161 <> T_145 when maybe_flow : T_161 <> io.enq.bits skip io.deq.bits <> T_161 node ptr_diff = subw(T_89, T_91) node T_170 = and(maybe_full, ptr_match) node T_171 = cat(T_170, ptr_diff) io.count := T_171 module MSHR : input clock : Clock input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, probe_rdy : UInt<1>} io.probe_rdy := UInt<1>("h00") io.wb_req.bits.way_en := UInt<1>("h00") io.wb_req.bits.voluntary := UInt<1>("h00") io.wb_req.bits.r_type := UInt<1>("h00") io.wb_req.bits.data := UInt<1>("h00") io.wb_req.bits.addr_beat := UInt<1>("h00") io.wb_req.bits.client_xact_id := UInt<1>("h00") io.wb_req.bits.addr_block := UInt<1>("h00") io.wb_req.valid := UInt<1>("h00") io.replay.bits.sdq_id := UInt<1>("h00") io.replay.bits.phys := UInt<1>("h00") io.replay.bits.kill := UInt<1>("h00") io.replay.bits.typ := UInt<1>("h00") io.replay.bits.cmd := UInt<1>("h00") io.replay.bits.tag := UInt<1>("h00") io.replay.bits.addr := UInt<1>("h00") io.replay.valid := UInt<1>("h00") io.meta_write.bits.data.coh.state := UInt<1>("h00") io.meta_write.bits.data.tag := UInt<1>("h00") io.meta_write.bits.way_en := UInt<1>("h00") io.meta_write.bits.idx := UInt<1>("h00") io.meta_write.valid := UInt<1>("h00") io.meta_read.bits.tag := UInt<1>("h00") io.meta_read.bits.idx := UInt<1>("h00") io.meta_read.valid := UInt<1>("h00") io.refill.addr := UInt<1>("h00") io.refill.way_en := UInt<1>("h00") io.mem_req.bits.union := UInt<1>("h00") io.mem_req.bits.a_type := UInt<1>("h00") io.mem_req.bits.is_builtin_type := UInt<1>("h00") io.mem_req.bits.data := UInt<1>("h00") io.mem_req.bits.addr_beat := UInt<1>("h00") io.mem_req.bits.client_xact_id := UInt<1>("h00") io.mem_req.bits.addr_block := UInt<1>("h00") io.mem_req.valid := UInt<1>("h00") io.tag := UInt<1>("h00") io.idx_match := UInt<1>("h00") io.req_sec_rdy := UInt<1>("h00") io.req_pri_rdy := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") wire T_657 : {state : UInt<2>} T_657.state := UInt<1>("h00") T_657.state := UInt<1>("h00") reg new_coh_state : {state : UInt<2>}, clock, reset onreset new_coh_state := T_657 reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset node req_idx = bits(req.addr, 11, 6) node T_783 = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, T_783) node T_785 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_786 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_787 = or(T_785, T_786) node T_788 = bit(io.req_bits.cmd, 3) node T_789 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_790 = or(T_788, T_789) node T_791 = or(T_787, T_790) node T_792 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_793 = or(T_791, T_792) node T_794 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_795 = or(T_793, T_794) node T_796 = eq(req.cmd, UInt<5>("h01")) node T_797 = eq(req.cmd, UInt<5>("h07")) node T_798 = or(T_796, T_797) node T_799 = bit(req.cmd, 3) node T_800 = eq(req.cmd, UInt<5>("h04")) node T_801 = or(T_799, T_800) node T_802 = or(T_798, T_801) node T_803 = eq(req.cmd, UInt<5>("h03")) node T_804 = or(T_802, T_803) node T_805 = eq(req.cmd, UInt<5>("h06")) node T_806 = or(T_804, T_805) node T_808 = eq(T_806, UInt<1>("h00")) node cmd_requires_second_acquire = and(T_795, T_808) wire states_before_refill : UInt<2>[3] states_before_refill[0] := UInt<1>("h01") states_before_refill[1] := UInt<2>("h02") states_before_refill[2] := UInt<2>("h03") node T_816 = eq(states_before_refill[0], state) node T_817 = eq(states_before_refill[1], state) node T_818 = eq(states_before_refill[2], state) node T_820 = or(UInt<1>("h00"), T_816) node T_821 = or(T_820, T_817) node T_822 = or(T_821, T_818) wire T_824 : UInt<3>[2] T_824[0] := UInt<3>("h04") T_824[1] := UInt<3>("h05") node T_828 = eq(T_824[0], state) node T_829 = eq(T_824[1], state) node T_831 = or(UInt<1>("h00"), T_828) node T_832 = or(T_831, T_829) node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) node T_835 = and(T_832, T_834) node T_836 = or(T_822, T_835) node sec_rdy = and(idx_match, T_836) wire T_841 : UInt<3>[1] T_841[0] := UInt<3>("h05") node T_844 = eq(T_841[0], io.mem_grant.bits.g_type) node T_846 = or(UInt<1>("h00"), T_844) wire T_848 : UInt<1>[2] T_848[0] := UInt<1>("h00") T_848[1] := UInt<1>("h01") node T_852 = eq(T_848[0], io.mem_grant.bits.g_type) node T_853 = eq(T_848[1], io.mem_grant.bits.g_type) node T_855 = or(UInt<1>("h00"), T_852) node T_856 = or(T_855, T_853) node T_857 = mux(io.mem_grant.bits.is_builtin_type, T_846, T_856) node gnt_multi_data = and(UInt<1>("h01"), T_857) node T_859 = and(io.mem_grant.valid, gnt_multi_data) reg refill_cnt : UInt<2>, clock, reset onreset refill_cnt := UInt<2>("h00") when T_859 : node T_863 = eq(refill_cnt, UInt<2>("h03")) node T_865 = and(UInt<1>("h00"), T_863) node T_868 = addw(refill_cnt, UInt<1>("h01")) node T_869 = mux(T_865, UInt<1>("h00"), T_868) refill_cnt := T_869 skip node refill_count_done = and(T_859, T_863) node T_872 = eq(gnt_multi_data, UInt<1>("h00")) node T_873 = or(T_872, refill_count_done) node refill_done = and(io.mem_grant.valid, T_873) inst rpq of Queue_85 rpq.io.deq.ready := UInt<1>("h00") rpq.io.enq.bits.sdq_id := UInt<1>("h00") rpq.io.enq.bits.phys := UInt<1>("h00") rpq.io.enq.bits.kill := UInt<1>("h00") rpq.io.enq.bits.typ := UInt<1>("h00") rpq.io.enq.bits.cmd := UInt<1>("h00") rpq.io.enq.bits.tag := UInt<1>("h00") rpq.io.enq.bits.addr := UInt<1>("h00") rpq.io.enq.valid := UInt<1>("h00") rpq.clock := clock rpq.reset := reset node T_893 = and(io.req_pri_val, io.req_pri_rdy) node T_894 = and(io.req_sec_val, sec_rdy) node T_895 = or(T_893, T_894) node T_896 = eq(io.req_bits.cmd, UInt<5>("h02")) node T_897 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_898 = or(T_896, T_897) node T_900 = eq(T_898, UInt<1>("h00")) node T_901 = and(T_895, T_900) rpq.io.enq.valid := T_901 rpq.io.enq.bits <> io.req_bits node T_902 = eq(state, UInt<4>("h08")) node T_903 = and(io.replay.ready, T_902) node T_904 = eq(state, UInt<1>("h00")) node T_905 = or(T_903, T_904) rpq.io.deq.ready := T_905 node T_906 = eq(req.cmd, UInt<5>("h01")) node T_907 = eq(req.cmd, UInt<5>("h07")) node T_908 = or(T_906, T_907) node T_909 = bit(req.cmd, 3) node T_910 = eq(req.cmd, UInt<5>("h04")) node T_911 = or(T_909, T_910) node T_912 = or(T_908, T_911) node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) node T_914 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) node T_916 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) node T_917 = mux(T_916, T_913, T_915) node T_918 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) node T_919 = mux(T_918, UInt<1>("h01"), T_917) node T_920 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) wire coh_on_grant : {state : UInt<2>} coh_on_grant.state := UInt<1>("h00") coh_on_grant.state := T_920 node T_972 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_973 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_974 = or(T_972, T_973) node T_975 = bit(io.req_bits.cmd, 3) node T_976 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_977 = or(T_975, T_976) node T_978 = or(T_974, T_977) node T_979 = mux(T_978, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} coh_on_hit.state := UInt<1>("h00") coh_on_hit.state := T_979 node T_1031 = eq(state, UInt<4>("h08")) node T_1033 = eq(rpq.io.deq.valid, UInt<1>("h00")) node T_1034 = and(T_1031, T_1033) when T_1034 : state := UInt<1>("h00") skip node T_1035 = eq(state, UInt<3>("h07")) when T_1035 : state := UInt<4>("h08") skip node T_1036 = eq(state, UInt<3>("h06")) node T_1037 = and(T_1036, io.meta_write.ready) when T_1037 : state := UInt<3>("h07") skip node T_1038 = eq(state, UInt<3>("h05")) when T_1038 : when io.mem_grant.valid : new_coh_state <> coh_on_grant skip when refill_done : state := UInt<3>("h06") skip skip node T_1039 = and(io.mem_req.ready, io.mem_req.valid) when T_1039 : state := UInt<3>("h05") skip node T_1040 = eq(state, UInt<2>("h03")) node T_1041 = and(T_1040, io.meta_write.ready) when T_1041 : state := UInt<3>("h04") skip node T_1042 = eq(state, UInt<2>("h02")) node T_1043 = and(T_1042, io.mem_grant.valid) when T_1043 : state := UInt<2>("h03") skip node T_1044 = and(io.wb_req.ready, io.wb_req.valid) when T_1044 : node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) state := T_1048 skip node T_1049 = and(io.req_sec_val, io.req_sec_rdy) when T_1049 : when cmd_requires_second_acquire : req.cmd := io.req_bits.cmd skip skip node T_1050 = and(io.req_pri_val, io.req_pri_rdy) when T_1050 : req <> io.req_bits when io.req_bits.tag_match : node T_1051 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1052 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1053 = or(T_1051, T_1052) node T_1054 = bit(io.req_bits.cmd, 3) node T_1055 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1056 = or(T_1054, T_1055) node T_1057 = or(T_1053, T_1056) node T_1058 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1059 = or(T_1057, T_1058) node T_1060 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1061 = or(T_1059, T_1060) wire T_1063 : UInt<2>[2] T_1063[0] := UInt<2>("h02") T_1063[1] := UInt<2>("h03") node T_1067 = eq(T_1063[0], io.req_bits.old_meta.coh.state) node T_1068 = eq(T_1063[1], io.req_bits.old_meta.coh.state) node T_1070 = or(UInt<1>("h00"), T_1067) node T_1071 = or(T_1070, T_1068) wire T_1073 : UInt<2>[3] T_1073[0] := UInt<1>("h01") T_1073[1] := UInt<2>("h02") T_1073[2] := UInt<2>("h03") node T_1078 = eq(T_1073[0], io.req_bits.old_meta.coh.state) node T_1079 = eq(T_1073[1], io.req_bits.old_meta.coh.state) node T_1080 = eq(T_1073[2], io.req_bits.old_meta.coh.state) node T_1082 = or(UInt<1>("h00"), T_1078) node T_1083 = or(T_1082, T_1079) node T_1084 = or(T_1083, T_1080) node T_1085 = mux(T_1061, T_1071, T_1084) when T_1085 : state := UInt<3>("h06") new_coh_state <> coh_on_hit skip else : state := UInt<3>("h04") skip skip else : wire T_1087 : UInt<2>[1] T_1087[0] := UInt<2>("h03") node T_1090 = eq(T_1087[0], io.req_bits.old_meta.coh.state) node T_1092 = or(UInt<1>("h00"), T_1090) node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) state := T_1093 skip skip node T_1094 = neq(state, UInt<1>("h00")) node T_1095 = and(T_1094, idx_match) io.idx_match := T_1095 io.refill.way_en := req.way_en node T_1096 = cat(req_idx, refill_cnt) node T_1097 = shl(T_1096, 4) io.refill.addr := T_1097 node T_1098 = shr(req.addr, 12) io.tag := T_1098 node T_1099 = eq(state, UInt<1>("h00")) io.req_pri_rdy := T_1099 node T_1100 = and(sec_rdy, rpq.io.enq.ready) io.req_sec_rdy := T_1100 reg meta_hazard : UInt<2>, clock, reset onreset meta_hazard := UInt<2>("h00") node T_1104 = neq(meta_hazard, UInt<1>("h00")) when T_1104 : node T_1106 = addw(meta_hazard, UInt<1>("h01")) meta_hazard := T_1106 skip node T_1107 = and(io.meta_write.ready, io.meta_write.valid) when T_1107 : meta_hazard := UInt<1>("h01") skip node T_1110 = eq(idx_match, UInt<1>("h00")) node T_1111 = eq(states_before_refill[0], state) node T_1112 = eq(states_before_refill[1], state) node T_1113 = eq(states_before_refill[2], state) node T_1115 = or(UInt<1>("h00"), T_1111) node T_1116 = or(T_1115, T_1112) node T_1117 = or(T_1116, T_1113) node T_1119 = eq(T_1117, UInt<1>("h00")) node T_1121 = eq(meta_hazard, UInt<1>("h00")) node T_1122 = and(T_1119, T_1121) node T_1123 = or(T_1110, T_1122) io.probe_rdy := T_1123 node T_1124 = eq(state, UInt<3>("h06")) node T_1125 = eq(state, UInt<2>("h03")) node T_1126 = or(T_1124, T_1125) io.meta_write.valid := T_1126 io.meta_write.bits.idx := req_idx node T_1127 = eq(state, UInt<2>("h03")) wire T_1129 : UInt<2>[2] T_1129[0] := UInt<2>("h02") T_1129[1] := UInt<2>("h03") node T_1133 = eq(T_1129[0], req.old_meta.coh.state) node T_1134 = eq(T_1129[1], req.old_meta.coh.state) node T_1136 = or(UInt<1>("h00"), T_1133) node T_1137 = or(T_1136, T_1134) node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1144 = mux(T_1143, T_1138, T_1142) node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) wire T_1172 : {state : UInt<2>} T_1172.state := UInt<1>("h00") T_1172.state := T_1146 wire T_1223 : {state : UInt<2>} T_1223 <> new_coh_state when T_1127 : T_1223 <> T_1172 skip io.meta_write.bits.data.coh <> T_1223 io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en node T_1248 = eq(state, UInt<1>("h01")) io.wb_req.valid := T_1248 node T_1250 = cat(req.old_meta.tag, req_idx) wire T_1255 : UInt<2>[1] T_1255[0] := UInt<2>("h03") node T_1258 = eq(T_1255[0], req.old_meta.coh.state) node T_1260 = or(UInt<1>("h00"), T_1258) node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1267 = mux(T_1266, T_1262, T_1265) node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_1269 = mux(T_1268, T_1261, T_1267) wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} T_1300.voluntary := UInt<1>("h00") T_1300.r_type := UInt<1>("h00") T_1300.data := UInt<1>("h00") T_1300.addr_beat := UInt<1>("h00") T_1300.client_xact_id := UInt<1>("h00") T_1300.addr_block := UInt<1>("h00") T_1300.r_type := T_1269 T_1300.client_xact_id := UInt<1>("h00") T_1300.addr_block := T_1250 T_1300.addr_beat := UInt<1>("h00") T_1300.data := UInt<1>("h00") T_1300.voluntary := UInt<1>("h01") io.wb_req.bits <> T_1300 io.wb_req.bits.way_en := req.way_en node T_1336 = eq(state, UInt<3>("h04")) io.mem_req.valid := T_1336 node T_1337 = cat(io.tag, req_idx) node T_1340 = eq(req.cmd, UInt<5>("h01")) node T_1341 = eq(req.cmd, UInt<5>("h07")) node T_1342 = or(T_1340, T_1341) node T_1343 = bit(req.cmd, 3) node T_1344 = eq(req.cmd, UInt<5>("h04")) node T_1345 = or(T_1343, T_1344) node T_1346 = or(T_1342, T_1345) node T_1347 = eq(req.cmd, UInt<5>("h03")) node T_1348 = or(T_1346, T_1347) node T_1349 = eq(req.cmd, UInt<5>("h06")) node T_1350 = or(T_1348, T_1349) node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) node T_1353 = cat(req.cmd, UInt<1>("h01")) wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1387.union := UInt<1>("h00") T_1387.a_type := UInt<1>("h00") T_1387.is_builtin_type := UInt<1>("h00") T_1387.data := UInt<1>("h00") T_1387.addr_beat := UInt<1>("h00") T_1387.client_xact_id := UInt<1>("h00") T_1387.addr_block := UInt<1>("h00") T_1387.is_builtin_type := UInt<1>("h00") T_1387.a_type := T_1351 T_1387.client_xact_id := UInt<1>("h00") T_1387.addr_block := T_1337 T_1387.addr_beat := UInt<1>("h00") T_1387.data := UInt<1>("h00") T_1387.union := T_1353 io.mem_req.bits <> T_1387 node T_1425 = eq(state, UInt<4>("h08")) io.meta_read.valid := T_1425 io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := io.tag node T_1426 = eq(state, UInt<4>("h08")) node T_1427 = and(T_1426, rpq.io.deq.valid) io.replay.valid := T_1427 io.replay.bits <> rpq.io.deq.bits io.replay.bits.phys := UInt<1>("h01") node T_1429 = bits(rpq.io.deq.bits.addr, 5, 0) node T_1430 = cat(req_idx, T_1429) node T_1431 = cat(io.tag, T_1430) io.replay.bits.addr := T_1431 node T_1433 = eq(io.meta_read.ready, UInt<1>("h00")) when T_1433 : rpq.io.deq.ready := UInt<1>("h00") io.replay.bits.cmd := UInt<5>("h05") skip module MSHR_86 : input clock : Clock input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, probe_rdy : UInt<1>} io.probe_rdy := UInt<1>("h00") io.wb_req.bits.way_en := UInt<1>("h00") io.wb_req.bits.voluntary := UInt<1>("h00") io.wb_req.bits.r_type := UInt<1>("h00") io.wb_req.bits.data := UInt<1>("h00") io.wb_req.bits.addr_beat := UInt<1>("h00") io.wb_req.bits.client_xact_id := UInt<1>("h00") io.wb_req.bits.addr_block := UInt<1>("h00") io.wb_req.valid := UInt<1>("h00") io.replay.bits.sdq_id := UInt<1>("h00") io.replay.bits.phys := UInt<1>("h00") io.replay.bits.kill := UInt<1>("h00") io.replay.bits.typ := UInt<1>("h00") io.replay.bits.cmd := UInt<1>("h00") io.replay.bits.tag := UInt<1>("h00") io.replay.bits.addr := UInt<1>("h00") io.replay.valid := UInt<1>("h00") io.meta_write.bits.data.coh.state := UInt<1>("h00") io.meta_write.bits.data.tag := UInt<1>("h00") io.meta_write.bits.way_en := UInt<1>("h00") io.meta_write.bits.idx := UInt<1>("h00") io.meta_write.valid := UInt<1>("h00") io.meta_read.bits.tag := UInt<1>("h00") io.meta_read.bits.idx := UInt<1>("h00") io.meta_read.valid := UInt<1>("h00") io.refill.addr := UInt<1>("h00") io.refill.way_en := UInt<1>("h00") io.mem_req.bits.union := UInt<1>("h00") io.mem_req.bits.a_type := UInt<1>("h00") io.mem_req.bits.is_builtin_type := UInt<1>("h00") io.mem_req.bits.data := UInt<1>("h00") io.mem_req.bits.addr_beat := UInt<1>("h00") io.mem_req.bits.client_xact_id := UInt<1>("h00") io.mem_req.bits.addr_block := UInt<1>("h00") io.mem_req.valid := UInt<1>("h00") io.tag := UInt<1>("h00") io.idx_match := UInt<1>("h00") io.req_sec_rdy := UInt<1>("h00") io.req_pri_rdy := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") wire T_657 : {state : UInt<2>} T_657.state := UInt<1>("h00") T_657.state := UInt<1>("h00") reg new_coh_state : {state : UInt<2>}, clock, reset onreset new_coh_state := T_657 reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset node req_idx = bits(req.addr, 11, 6) node T_783 = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, T_783) node T_785 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_786 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_787 = or(T_785, T_786) node T_788 = bit(io.req_bits.cmd, 3) node T_789 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_790 = or(T_788, T_789) node T_791 = or(T_787, T_790) node T_792 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_793 = or(T_791, T_792) node T_794 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_795 = or(T_793, T_794) node T_796 = eq(req.cmd, UInt<5>("h01")) node T_797 = eq(req.cmd, UInt<5>("h07")) node T_798 = or(T_796, T_797) node T_799 = bit(req.cmd, 3) node T_800 = eq(req.cmd, UInt<5>("h04")) node T_801 = or(T_799, T_800) node T_802 = or(T_798, T_801) node T_803 = eq(req.cmd, UInt<5>("h03")) node T_804 = or(T_802, T_803) node T_805 = eq(req.cmd, UInt<5>("h06")) node T_806 = or(T_804, T_805) node T_808 = eq(T_806, UInt<1>("h00")) node cmd_requires_second_acquire = and(T_795, T_808) wire states_before_refill : UInt<2>[3] states_before_refill[0] := UInt<1>("h01") states_before_refill[1] := UInt<2>("h02") states_before_refill[2] := UInt<2>("h03") node T_816 = eq(states_before_refill[0], state) node T_817 = eq(states_before_refill[1], state) node T_818 = eq(states_before_refill[2], state) node T_820 = or(UInt<1>("h00"), T_816) node T_821 = or(T_820, T_817) node T_822 = or(T_821, T_818) wire T_824 : UInt<3>[2] T_824[0] := UInt<3>("h04") T_824[1] := UInt<3>("h05") node T_828 = eq(T_824[0], state) node T_829 = eq(T_824[1], state) node T_831 = or(UInt<1>("h00"), T_828) node T_832 = or(T_831, T_829) node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) node T_835 = and(T_832, T_834) node T_836 = or(T_822, T_835) node sec_rdy = and(idx_match, T_836) wire T_841 : UInt<3>[1] T_841[0] := UInt<3>("h05") node T_844 = eq(T_841[0], io.mem_grant.bits.g_type) node T_846 = or(UInt<1>("h00"), T_844) wire T_848 : UInt<1>[2] T_848[0] := UInt<1>("h00") T_848[1] := UInt<1>("h01") node T_852 = eq(T_848[0], io.mem_grant.bits.g_type) node T_853 = eq(T_848[1], io.mem_grant.bits.g_type) node T_855 = or(UInt<1>("h00"), T_852) node T_856 = or(T_855, T_853) node T_857 = mux(io.mem_grant.bits.is_builtin_type, T_846, T_856) node gnt_multi_data = and(UInt<1>("h01"), T_857) node T_859 = and(io.mem_grant.valid, gnt_multi_data) reg refill_cnt : UInt<2>, clock, reset onreset refill_cnt := UInt<2>("h00") when T_859 : node T_863 = eq(refill_cnt, UInt<2>("h03")) node T_865 = and(UInt<1>("h00"), T_863) node T_868 = addw(refill_cnt, UInt<1>("h01")) node T_869 = mux(T_865, UInt<1>("h00"), T_868) refill_cnt := T_869 skip node refill_count_done = and(T_859, T_863) node T_872 = eq(gnt_multi_data, UInt<1>("h00")) node T_873 = or(T_872, refill_count_done) node refill_done = and(io.mem_grant.valid, T_873) inst rpq of Queue_85 rpq.io.deq.ready := UInt<1>("h00") rpq.io.enq.bits.sdq_id := UInt<1>("h00") rpq.io.enq.bits.phys := UInt<1>("h00") rpq.io.enq.bits.kill := UInt<1>("h00") rpq.io.enq.bits.typ := UInt<1>("h00") rpq.io.enq.bits.cmd := UInt<1>("h00") rpq.io.enq.bits.tag := UInt<1>("h00") rpq.io.enq.bits.addr := UInt<1>("h00") rpq.io.enq.valid := UInt<1>("h00") rpq.clock := clock rpq.reset := reset node T_893 = and(io.req_pri_val, io.req_pri_rdy) node T_894 = and(io.req_sec_val, sec_rdy) node T_895 = or(T_893, T_894) node T_896 = eq(io.req_bits.cmd, UInt<5>("h02")) node T_897 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_898 = or(T_896, T_897) node T_900 = eq(T_898, UInt<1>("h00")) node T_901 = and(T_895, T_900) rpq.io.enq.valid := T_901 rpq.io.enq.bits <> io.req_bits node T_902 = eq(state, UInt<4>("h08")) node T_903 = and(io.replay.ready, T_902) node T_904 = eq(state, UInt<1>("h00")) node T_905 = or(T_903, T_904) rpq.io.deq.ready := T_905 node T_906 = eq(req.cmd, UInt<5>("h01")) node T_907 = eq(req.cmd, UInt<5>("h07")) node T_908 = or(T_906, T_907) node T_909 = bit(req.cmd, 3) node T_910 = eq(req.cmd, UInt<5>("h04")) node T_911 = or(T_909, T_910) node T_912 = or(T_908, T_911) node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) node T_914 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) node T_916 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) node T_917 = mux(T_916, T_913, T_915) node T_918 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) node T_919 = mux(T_918, UInt<1>("h01"), T_917) node T_920 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) wire coh_on_grant : {state : UInt<2>} coh_on_grant.state := UInt<1>("h00") coh_on_grant.state := T_920 node T_972 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_973 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_974 = or(T_972, T_973) node T_975 = bit(io.req_bits.cmd, 3) node T_976 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_977 = or(T_975, T_976) node T_978 = or(T_974, T_977) node T_979 = mux(T_978, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} coh_on_hit.state := UInt<1>("h00") coh_on_hit.state := T_979 node T_1031 = eq(state, UInt<4>("h08")) node T_1033 = eq(rpq.io.deq.valid, UInt<1>("h00")) node T_1034 = and(T_1031, T_1033) when T_1034 : state := UInt<1>("h00") skip node T_1035 = eq(state, UInt<3>("h07")) when T_1035 : state := UInt<4>("h08") skip node T_1036 = eq(state, UInt<3>("h06")) node T_1037 = and(T_1036, io.meta_write.ready) when T_1037 : state := UInt<3>("h07") skip node T_1038 = eq(state, UInt<3>("h05")) when T_1038 : when io.mem_grant.valid : new_coh_state <> coh_on_grant skip when refill_done : state := UInt<3>("h06") skip skip node T_1039 = and(io.mem_req.ready, io.mem_req.valid) when T_1039 : state := UInt<3>("h05") skip node T_1040 = eq(state, UInt<2>("h03")) node T_1041 = and(T_1040, io.meta_write.ready) when T_1041 : state := UInt<3>("h04") skip node T_1042 = eq(state, UInt<2>("h02")) node T_1043 = and(T_1042, io.mem_grant.valid) when T_1043 : state := UInt<2>("h03") skip node T_1044 = and(io.wb_req.ready, io.wb_req.valid) when T_1044 : node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) state := T_1048 skip node T_1049 = and(io.req_sec_val, io.req_sec_rdy) when T_1049 : when cmd_requires_second_acquire : req.cmd := io.req_bits.cmd skip skip node T_1050 = and(io.req_pri_val, io.req_pri_rdy) when T_1050 : req <> io.req_bits when io.req_bits.tag_match : node T_1051 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1052 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1053 = or(T_1051, T_1052) node T_1054 = bit(io.req_bits.cmd, 3) node T_1055 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1056 = or(T_1054, T_1055) node T_1057 = or(T_1053, T_1056) node T_1058 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1059 = or(T_1057, T_1058) node T_1060 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1061 = or(T_1059, T_1060) wire T_1063 : UInt<2>[2] T_1063[0] := UInt<2>("h02") T_1063[1] := UInt<2>("h03") node T_1067 = eq(T_1063[0], io.req_bits.old_meta.coh.state) node T_1068 = eq(T_1063[1], io.req_bits.old_meta.coh.state) node T_1070 = or(UInt<1>("h00"), T_1067) node T_1071 = or(T_1070, T_1068) wire T_1073 : UInt<2>[3] T_1073[0] := UInt<1>("h01") T_1073[1] := UInt<2>("h02") T_1073[2] := UInt<2>("h03") node T_1078 = eq(T_1073[0], io.req_bits.old_meta.coh.state) node T_1079 = eq(T_1073[1], io.req_bits.old_meta.coh.state) node T_1080 = eq(T_1073[2], io.req_bits.old_meta.coh.state) node T_1082 = or(UInt<1>("h00"), T_1078) node T_1083 = or(T_1082, T_1079) node T_1084 = or(T_1083, T_1080) node T_1085 = mux(T_1061, T_1071, T_1084) when T_1085 : state := UInt<3>("h06") new_coh_state <> coh_on_hit skip else : state := UInt<3>("h04") skip skip else : wire T_1087 : UInt<2>[1] T_1087[0] := UInt<2>("h03") node T_1090 = eq(T_1087[0], io.req_bits.old_meta.coh.state) node T_1092 = or(UInt<1>("h00"), T_1090) node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) state := T_1093 skip skip node T_1094 = neq(state, UInt<1>("h00")) node T_1095 = and(T_1094, idx_match) io.idx_match := T_1095 io.refill.way_en := req.way_en node T_1096 = cat(req_idx, refill_cnt) node T_1097 = shl(T_1096, 4) io.refill.addr := T_1097 node T_1098 = shr(req.addr, 12) io.tag := T_1098 node T_1099 = eq(state, UInt<1>("h00")) io.req_pri_rdy := T_1099 node T_1100 = and(sec_rdy, rpq.io.enq.ready) io.req_sec_rdy := T_1100 reg meta_hazard : UInt<2>, clock, reset onreset meta_hazard := UInt<2>("h00") node T_1104 = neq(meta_hazard, UInt<1>("h00")) when T_1104 : node T_1106 = addw(meta_hazard, UInt<1>("h01")) meta_hazard := T_1106 skip node T_1107 = and(io.meta_write.ready, io.meta_write.valid) when T_1107 : meta_hazard := UInt<1>("h01") skip node T_1110 = eq(idx_match, UInt<1>("h00")) node T_1111 = eq(states_before_refill[0], state) node T_1112 = eq(states_before_refill[1], state) node T_1113 = eq(states_before_refill[2], state) node T_1115 = or(UInt<1>("h00"), T_1111) node T_1116 = or(T_1115, T_1112) node T_1117 = or(T_1116, T_1113) node T_1119 = eq(T_1117, UInt<1>("h00")) node T_1121 = eq(meta_hazard, UInt<1>("h00")) node T_1122 = and(T_1119, T_1121) node T_1123 = or(T_1110, T_1122) io.probe_rdy := T_1123 node T_1124 = eq(state, UInt<3>("h06")) node T_1125 = eq(state, UInt<2>("h03")) node T_1126 = or(T_1124, T_1125) io.meta_write.valid := T_1126 io.meta_write.bits.idx := req_idx node T_1127 = eq(state, UInt<2>("h03")) wire T_1129 : UInt<2>[2] T_1129[0] := UInt<2>("h02") T_1129[1] := UInt<2>("h03") node T_1133 = eq(T_1129[0], req.old_meta.coh.state) node T_1134 = eq(T_1129[1], req.old_meta.coh.state) node T_1136 = or(UInt<1>("h00"), T_1133) node T_1137 = or(T_1136, T_1134) node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1144 = mux(T_1143, T_1138, T_1142) node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) wire T_1172 : {state : UInt<2>} T_1172.state := UInt<1>("h00") T_1172.state := T_1146 wire T_1223 : {state : UInt<2>} T_1223 <> new_coh_state when T_1127 : T_1223 <> T_1172 skip io.meta_write.bits.data.coh <> T_1223 io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en node T_1248 = eq(state, UInt<1>("h01")) io.wb_req.valid := T_1248 node T_1250 = cat(req.old_meta.tag, req_idx) wire T_1255 : UInt<2>[1] T_1255[0] := UInt<2>("h03") node T_1258 = eq(T_1255[0], req.old_meta.coh.state) node T_1260 = or(UInt<1>("h00"), T_1258) node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1267 = mux(T_1266, T_1262, T_1265) node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_1269 = mux(T_1268, T_1261, T_1267) wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} T_1300.voluntary := UInt<1>("h00") T_1300.r_type := UInt<1>("h00") T_1300.data := UInt<1>("h00") T_1300.addr_beat := UInt<1>("h00") T_1300.client_xact_id := UInt<1>("h00") T_1300.addr_block := UInt<1>("h00") T_1300.r_type := T_1269 T_1300.client_xact_id := UInt<1>("h01") T_1300.addr_block := T_1250 T_1300.addr_beat := UInt<1>("h00") T_1300.data := UInt<1>("h00") T_1300.voluntary := UInt<1>("h01") io.wb_req.bits <> T_1300 io.wb_req.bits.way_en := req.way_en node T_1336 = eq(state, UInt<3>("h04")) io.mem_req.valid := T_1336 node T_1337 = cat(io.tag, req_idx) node T_1340 = eq(req.cmd, UInt<5>("h01")) node T_1341 = eq(req.cmd, UInt<5>("h07")) node T_1342 = or(T_1340, T_1341) node T_1343 = bit(req.cmd, 3) node T_1344 = eq(req.cmd, UInt<5>("h04")) node T_1345 = or(T_1343, T_1344) node T_1346 = or(T_1342, T_1345) node T_1347 = eq(req.cmd, UInt<5>("h03")) node T_1348 = or(T_1346, T_1347) node T_1349 = eq(req.cmd, UInt<5>("h06")) node T_1350 = or(T_1348, T_1349) node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) node T_1353 = cat(req.cmd, UInt<1>("h01")) wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_1387.union := UInt<1>("h00") T_1387.a_type := UInt<1>("h00") T_1387.is_builtin_type := UInt<1>("h00") T_1387.data := UInt<1>("h00") T_1387.addr_beat := UInt<1>("h00") T_1387.client_xact_id := UInt<1>("h00") T_1387.addr_block := UInt<1>("h00") T_1387.is_builtin_type := UInt<1>("h00") T_1387.a_type := T_1351 T_1387.client_xact_id := UInt<1>("h01") T_1387.addr_block := T_1337 T_1387.addr_beat := UInt<1>("h00") T_1387.data := UInt<1>("h00") T_1387.union := T_1353 io.mem_req.bits <> T_1387 node T_1425 = eq(state, UInt<4>("h08")) io.meta_read.valid := T_1425 io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := io.tag node T_1426 = eq(state, UInt<4>("h08")) node T_1427 = and(T_1426, rpq.io.deq.valid) io.replay.valid := T_1427 io.replay.bits <> rpq.io.deq.bits io.replay.bits.phys := UInt<1>("h01") node T_1429 = bits(rpq.io.deq.bits.addr, 5, 0) node T_1430 = cat(req_idx, T_1429) node T_1431 = cat(io.tag, T_1430) io.replay.bits.addr := T_1431 node T_1433 = eq(io.meta_read.ready, UInt<1>("h00")) when T_1433 : rpq.io.deq.ready := UInt<1>("h00") io.replay.bits.cmd := UInt<5>("h05") skip module Arbiter_88 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") wire T_54 : UInt<1> T_54 := UInt<1>("h00") infer accessor T_56 = io.in[T_54] io.out.valid := T_56.valid infer accessor T_61 = io.in[T_54] io.out.bits := T_61.bits io.chosen := T_54 infer accessor T_66 = io.in[T_54] T_66.ready := UInt<1>("h00") node T_74 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_75 = mux(UInt<1>("h00"), T_74, UInt<1>("h01")) node T_76 = and(T_75, io.out.ready) io.in[0].ready := T_76 node T_78 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) T_54 := T_78 module Arbiter_89 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.store_data := UInt<1>("h00") io.out.bits.data_word_bypass := UInt<1>("h00") io.out.bits.has_data := UInt<1>("h00") io.out.bits.replay := UInt<1>("h00") io.out.bits.nack := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.typ := UInt<1>("h00") io.out.bits.cmd := UInt<1>("h00") io.out.bits.tag := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") wire T_234 : UInt<1> T_234 := UInt<1>("h00") infer accessor T_236 = io.in[T_234] io.out.valid := T_236.valid infer accessor T_261 = io.in[T_234] io.out.bits <> T_261.bits io.chosen := T_234 infer accessor T_286 = io.in[T_234] T_286.ready := UInt<1>("h00") node T_314 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_315 = mux(UInt<1>("h00"), T_314, UInt<1>("h01")) node T_316 = and(T_315, io.out.ready) io.in[0].ready := T_316 node T_318 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) T_234 := T_318 module IOMSHR : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}} io.resp.bits.store_data := UInt<1>("h00") io.resp.bits.data_word_bypass := UInt<1>("h00") io.resp.bits.has_data := UInt<1>("h00") io.resp.bits.replay := UInt<1>("h00") io.resp.bits.nack := UInt<1>("h00") io.resp.bits.data := UInt<1>("h00") io.resp.bits.typ := UInt<1>("h00") io.resp.bits.cmd := UInt<1>("h00") io.resp.bits.tag := UInt<1>("h00") io.resp.bits.addr := UInt<1>("h00") io.resp.valid := UInt<1>("h00") io.acquire.bits.union := UInt<1>("h00") io.acquire.bits.a_type := UInt<1>("h00") io.acquire.bits.is_builtin_type := UInt<1>("h00") io.acquire.bits.data := UInt<1>("h00") io.acquire.bits.addr_beat := UInt<1>("h00") io.acquire.bits.client_xact_id := UInt<1>("h00") io.acquire.bits.addr_block := UInt<1>("h00") io.acquire.valid := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset node req_cmd_sc = eq(req.cmd, UInt<5>("h07")) reg grant_word : UInt<64>, clock, reset node T_355 = eq(req.typ, UInt<3>("h00")) node T_356 = eq(req.typ, UInt<3>("h04")) node T_357 = or(T_355, T_356) node T_358 = eq(req.typ, UInt<3>("h01")) node T_359 = eq(req.typ, UInt<3>("h05")) node T_360 = or(T_358, T_359) node T_361 = eq(req.typ, UInt<3>("h02")) node T_362 = eq(req.typ, UInt<3>("h06")) node T_363 = or(T_361, T_362) node T_364 = eq(req.typ, UInt<3>("h00")) node T_365 = eq(req.typ, UInt<3>("h04")) node T_366 = or(T_364, T_365) node T_367 = eq(req.typ, UInt<3>("h01")) node T_368 = eq(req.typ, UInt<3>("h05")) node T_369 = or(T_367, T_368) node T_370 = eq(req.typ, UInt<3>("h02")) node T_371 = eq(req.typ, UInt<3>("h06")) node T_372 = or(T_370, T_371) node T_373 = eq(req.typ, UInt<3>("h00")) node T_374 = eq(req.typ, UInt<3>("h01")) node T_375 = or(T_373, T_374) node T_376 = eq(req.typ, UInt<3>("h02")) node T_377 = or(T_375, T_376) node T_378 = eq(req.typ, UInt<3>("h03")) node T_379 = or(T_377, T_378) node T_380 = bit(req.addr, 2) node T_381 = bits(grant_word, 63, 32) node T_382 = bits(grant_word, 31, 0) node T_383 = mux(T_380, T_381, T_382) node T_384 = bit(T_383, 31) node T_385 = and(T_379, T_384) node T_387 = subw(UInt<32>("h00"), T_385) node T_388 = bits(grant_word, 63, 32) node T_389 = mux(T_372, T_387, T_388) node T_390 = cat(T_389, T_383) node T_391 = bit(req.addr, 1) node T_392 = bits(T_390, 31, 16) node T_393 = bits(T_390, 15, 0) node T_394 = mux(T_391, T_392, T_393) node T_395 = bit(T_394, 15) node T_396 = and(T_379, T_395) node T_398 = subw(UInt<48>("h00"), T_396) node T_399 = bits(T_390, 63, 16) node T_400 = mux(T_369, T_398, T_399) node T_401 = cat(T_400, T_394) node T_403 = bit(req.addr, 0) node T_404 = bits(T_401, 15, 8) node T_405 = bits(T_401, 7, 0) node T_406 = mux(T_403, T_404, T_405) node T_407 = mux(req_cmd_sc, UInt<1>("h00"), T_406) node T_408 = or(req_cmd_sc, T_366) node T_409 = bit(T_407, 7) node T_410 = and(T_379, T_409) node T_412 = subw(UInt<56>("h00"), T_410) node T_413 = bits(T_401, 63, 8) node T_414 = mux(T_408, T_412, T_413) node T_415 = cat(T_414, T_407) node beat_offset = bits(req.addr, 3, 3) node T_418 = bits(req.addr, 2, 0) node T_419 = dshl(UInt<1>("h01"), T_418) node T_421 = bits(req.addr, 2, 1) node T_423 = cat(T_421, UInt<1>("h00")) node T_424 = dshl(UInt<2>("h03"), T_423) node T_426 = bit(req.addr, 2) node T_428 = cat(T_426, UInt<2>("h00")) node T_429 = dshl(UInt<4>("h0f"), T_428) node T_431 = mux(T_363, T_429, UInt<8>("h0ff")) node T_432 = mux(T_360, T_424, T_431) node T_433 = mux(T_357, T_419, T_432) node T_435 = cat(beat_offset, UInt<3>("h00")) node beat_mask = dshl(T_433, T_435) node T_437 = bits(req.data, 7, 0) node T_438 = cat(T_437, T_437) node T_439 = cat(T_438, T_438) node T_440 = cat(T_439, T_439) node T_441 = bits(req.data, 15, 0) node T_442 = cat(T_441, T_441) node T_443 = cat(T_442, T_442) node T_444 = bits(req.data, 31, 0) node T_445 = cat(T_444, T_444) node T_446 = mux(T_363, T_445, req.data) node T_447 = mux(T_360, T_443, T_446) node T_448 = mux(T_357, T_440, T_447) node beat_data = cat(T_448, T_448) node addr_byte = bits(req.addr, 3, 0) node T_451 = eq(req.cmd, UInt<5>("h00")) node T_452 = eq(req.cmd, UInt<5>("h06")) node T_453 = or(T_451, T_452) node T_454 = eq(req.cmd, UInt<5>("h07")) node T_455 = or(T_453, T_454) node T_456 = bit(req.cmd, 3) node T_457 = eq(req.cmd, UInt<5>("h04")) node T_458 = or(T_456, T_457) node T_459 = or(T_455, T_458) node a_type = mux(T_459, UInt<3>("h00"), UInt<3>("h02")) node T_463 = eq(req.cmd, UInt<5>("h00")) node T_464 = eq(req.cmd, UInt<5>("h06")) node T_465 = or(T_463, T_464) node T_466 = eq(req.cmd, UInt<5>("h07")) node T_467 = or(T_465, T_466) node T_468 = bit(req.cmd, 3) node T_469 = eq(req.cmd, UInt<5>("h04")) node T_470 = or(T_468, T_469) node T_471 = or(T_467, T_470) node T_472 = cat(req.typ, UInt<5>("h00")) node T_473 = cat(addr_byte, T_472) node union = mux(T_471, T_473, beat_mask) reg state : UInt, clock, reset onreset state := UInt<1>("h00") node T_481 = eq(state, UInt<1>("h00")) io.req.ready := T_481 node T_482 = eq(state, UInt<1>("h01")) io.acquire.valid := T_482 node T_485 = bits(req.addr, 31, 6) node T_486 = bits(req.addr, 5, 4) node T_488 = cat(union, UInt<1>("h00")) wire T_520 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} T_520.union := UInt<1>("h00") T_520.a_type := UInt<1>("h00") T_520.is_builtin_type := UInt<1>("h00") T_520.data := UInt<1>("h00") T_520.addr_beat := UInt<1>("h00") T_520.client_xact_id := UInt<1>("h00") T_520.addr_block := UInt<1>("h00") T_520.is_builtin_type := UInt<1>("h01") T_520.a_type := a_type T_520.client_xact_id := UInt<2>("h02") T_520.addr_block := T_485 T_520.addr_beat := T_486 T_520.data := beat_data T_520.union := T_488 io.acquire.bits <> T_520 node T_558 = eq(state, UInt<2>("h03")) io.resp.valid := T_558 io.resp.bits <> req node T_559 = eq(req.cmd, UInt<5>("h00")) node T_560 = eq(req.cmd, UInt<5>("h06")) node T_561 = or(T_559, T_560) node T_562 = eq(req.cmd, UInt<5>("h07")) node T_563 = or(T_561, T_562) node T_564 = bit(req.cmd, 3) node T_565 = eq(req.cmd, UInt<5>("h04")) node T_566 = or(T_564, T_565) node T_567 = or(T_563, T_566) io.resp.bits.has_data := T_567 node T_568 = or(T_415, req_cmd_sc) io.resp.bits.data := T_568 io.resp.bits.store_data := req.data io.resp.bits.nack := UInt<1>("h00") io.resp.bits.replay := io.resp.valid node T_570 = and(io.req.ready, io.req.valid) when T_570 : req <> io.req.bits state := UInt<1>("h01") skip node T_571 = and(io.acquire.ready, io.acquire.valid) when T_571 : state := UInt<2>("h02") skip node T_572 = eq(state, UInt<2>("h02")) node T_573 = and(T_572, io.grant.valid) when T_573 : node T_574 = eq(req.cmd, UInt<5>("h00")) node T_575 = eq(req.cmd, UInt<5>("h06")) node T_576 = or(T_574, T_575) node T_577 = eq(req.cmd, UInt<5>("h07")) node T_578 = or(T_576, T_577) node T_579 = bit(req.cmd, 3) node T_580 = eq(req.cmd, UInt<5>("h04")) node T_581 = or(T_579, T_580) node T_582 = or(T_578, T_581) when T_582 : node T_583 = bits(req.addr, 3, 3) node T_585 = cat(T_583, UInt<6>("h00")) node T_586 = dshr(io.grant.bits.data, T_585) node T_587 = bits(T_586, 63, 0) grant_word := T_587 state := UInt<2>("h03") skip else : state := UInt<1>("h00") skip skip node T_588 = and(io.resp.ready, io.resp.valid) when T_588 : state := UInt<1>("h00") skip module MSHRFile : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>} io.fence_rdy := UInt<1>("h00") io.probe_rdy := UInt<1>("h00") io.wb_req.bits.way_en := UInt<1>("h00") io.wb_req.bits.voluntary := UInt<1>("h00") io.wb_req.bits.r_type := UInt<1>("h00") io.wb_req.bits.data := UInt<1>("h00") io.wb_req.bits.addr_beat := UInt<1>("h00") io.wb_req.bits.client_xact_id := UInt<1>("h00") io.wb_req.bits.addr_block := UInt<1>("h00") io.wb_req.valid := UInt<1>("h00") io.replay.bits.data := UInt<1>("h00") io.replay.bits.phys := UInt<1>("h00") io.replay.bits.kill := UInt<1>("h00") io.replay.bits.typ := UInt<1>("h00") io.replay.bits.cmd := UInt<1>("h00") io.replay.bits.tag := UInt<1>("h00") io.replay.bits.addr := UInt<1>("h00") io.replay.valid := UInt<1>("h00") io.meta_write.bits.data.coh.state := UInt<1>("h00") io.meta_write.bits.data.tag := UInt<1>("h00") io.meta_write.bits.way_en := UInt<1>("h00") io.meta_write.bits.idx := UInt<1>("h00") io.meta_write.valid := UInt<1>("h00") io.meta_read.bits.tag := UInt<1>("h00") io.meta_read.bits.idx := UInt<1>("h00") io.meta_read.valid := UInt<1>("h00") io.refill.addr := UInt<1>("h00") io.refill.way_en := UInt<1>("h00") io.mem_req.bits.union := UInt<1>("h00") io.mem_req.bits.a_type := UInt<1>("h00") io.mem_req.bits.is_builtin_type := UInt<1>("h00") io.mem_req.bits.data := UInt<1>("h00") io.mem_req.bits.addr_beat := UInt<1>("h00") io.mem_req.bits.client_xact_id := UInt<1>("h00") io.mem_req.bits.addr_block := UInt<1>("h00") io.mem_req.valid := UInt<1>("h00") io.secondary_miss := UInt<1>("h00") io.resp.bits.store_data := UInt<1>("h00") io.resp.bits.data_word_bypass := UInt<1>("h00") io.resp.bits.has_data := UInt<1>("h00") io.resp.bits.replay := UInt<1>("h00") io.resp.bits.nack := UInt<1>("h00") io.resp.bits.data := UInt<1>("h00") io.resp.bits.typ := UInt<1>("h00") io.resp.bits.cmd := UInt<1>("h00") io.resp.bits.tag := UInt<1>("h00") io.resp.bits.addr := UInt<1>("h00") io.resp.valid := UInt<1>("h00") io.req.ready := UInt<1>("h00") node cacheable = lt(io.req.bits.addr, UInt<31>("h040000000")) reg sdq_val : UInt<17>, clock, reset onreset sdq_val := UInt<17>("h00") node T_749 = bits(sdq_val, 16, 0) node T_750 = not(T_749) node T_751 = bit(T_750, 0) node T_752 = bit(T_750, 1) node T_753 = bit(T_750, 2) node T_754 = bit(T_750, 3) node T_755 = bit(T_750, 4) node T_756 = bit(T_750, 5) node T_757 = bit(T_750, 6) node T_758 = bit(T_750, 7) node T_759 = bit(T_750, 8) node T_760 = bit(T_750, 9) node T_761 = bit(T_750, 10) node T_762 = bit(T_750, 11) node T_763 = bit(T_750, 12) node T_764 = bit(T_750, 13) node T_765 = bit(T_750, 14) node T_766 = bit(T_750, 15) node T_767 = bit(T_750, 16) wire T_769 : UInt<1>[17] T_769[0] := T_751 T_769[1] := T_752 T_769[2] := T_753 T_769[3] := T_754 T_769[4] := T_755 T_769[5] := T_756 T_769[6] := T_757 T_769[7] := T_758 T_769[8] := T_759 T_769[9] := T_760 T_769[10] := T_761 T_769[11] := T_762 T_769[12] := T_763 T_769[13] := T_764 T_769[14] := T_765 T_769[15] := T_766 T_769[16] := T_767 node T_805 = mux(T_769[15], UInt<4>("h0f"), UInt<5>("h010")) node T_806 = mux(T_769[14], UInt<4>("h0e"), T_805) node T_807 = mux(T_769[13], UInt<4>("h0d"), T_806) node T_808 = mux(T_769[12], UInt<4>("h0c"), T_807) node T_809 = mux(T_769[11], UInt<4>("h0b"), T_808) node T_810 = mux(T_769[10], UInt<4>("h0a"), T_809) node T_811 = mux(T_769[9], UInt<4>("h09"), T_810) node T_812 = mux(T_769[8], UInt<4>("h08"), T_811) node T_813 = mux(T_769[7], UInt<3>("h07"), T_812) node T_814 = mux(T_769[6], UInt<3>("h06"), T_813) node T_815 = mux(T_769[5], UInt<3>("h05"), T_814) node T_816 = mux(T_769[4], UInt<3>("h04"), T_815) node T_817 = mux(T_769[3], UInt<2>("h03"), T_816) node T_818 = mux(T_769[2], UInt<2>("h02"), T_817) node T_819 = mux(T_769[1], UInt<1>("h01"), T_818) node sdq_alloc_id = mux(T_769[0], UInt<1>("h00"), T_819) node T_821 = not(sdq_val) node T_823 = eq(T_821, UInt<1>("h00")) node sdq_rdy = eq(T_823, UInt<1>("h00")) node T_826 = and(io.req.valid, io.req.ready) node T_827 = and(T_826, cacheable) node T_828 = eq(io.req.bits.cmd, UInt<5>("h01")) node T_829 = eq(io.req.bits.cmd, UInt<5>("h07")) node T_830 = or(T_828, T_829) node T_831 = bit(io.req.bits.cmd, 3) node T_832 = eq(io.req.bits.cmd, UInt<5>("h04")) node T_833 = or(T_831, T_832) node T_834 = or(T_830, T_833) node sdq_enq = and(T_827, T_834) cmem sdq : UInt<64>[17], clock when sdq_enq : infer accessor T_838 = sdq[sdq_alloc_id] T_838 := io.req.bits.data skip wire idxMatch : UInt<1>[2] idxMatch[0] := UInt<1>("h00") idxMatch[1] := UInt<1>("h00") wire tagList : UInt<20>[2] tagList[0] := UInt<1>("h00") tagList[1] := UInt<1>("h00") node T_868 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) node T_870 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) node T_872 = or(T_868, T_870) wire T_873 : UInt<20> T_873 := UInt<1>("h00") T_873 := T_872 node T_875 = shr(io.req.bits.addr, 12) node tag_match = eq(T_873, T_875) wire wbTagList : UInt[2] wbTagList[0] := UInt<1>("h00") wbTagList[1] := UInt<1>("h00") wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] refillMux[0].addr := UInt<1>("h00") refillMux[0].way_en := UInt<1>("h00") refillMux[1].addr := UInt<1>("h00") refillMux[1].way_en := UInt<1>("h00") inst meta_read_arb of Arbiter_80 meta_read_arb.io.out.ready := UInt<1>("h00") meta_read_arb.io.in[0].bits.tag := UInt<1>("h00") meta_read_arb.io.in[0].bits.idx := UInt<1>("h00") meta_read_arb.io.in[0].valid := UInt<1>("h00") meta_read_arb.io.in[1].bits.tag := UInt<1>("h00") meta_read_arb.io.in[1].bits.idx := UInt<1>("h00") meta_read_arb.io.in[1].valid := UInt<1>("h00") meta_read_arb.clock := clock meta_read_arb.reset := reset inst meta_write_arb of Arbiter_81 meta_write_arb.io.out.ready := UInt<1>("h00") meta_write_arb.io.in[0].bits.data.coh.state := UInt<1>("h00") meta_write_arb.io.in[0].bits.data.tag := UInt<1>("h00") meta_write_arb.io.in[0].bits.way_en := UInt<1>("h00") meta_write_arb.io.in[0].bits.idx := UInt<1>("h00") meta_write_arb.io.in[0].valid := UInt<1>("h00") meta_write_arb.io.in[1].bits.data.coh.state := UInt<1>("h00") meta_write_arb.io.in[1].bits.data.tag := UInt<1>("h00") meta_write_arb.io.in[1].bits.way_en := UInt<1>("h00") meta_write_arb.io.in[1].bits.idx := UInt<1>("h00") meta_write_arb.io.in[1].valid := UInt<1>("h00") meta_write_arb.clock := clock meta_write_arb.reset := reset inst mem_req_arb of LockingArbiter mem_req_arb.io.out.ready := UInt<1>("h00") mem_req_arb.io.in[0].bits.union := UInt<1>("h00") mem_req_arb.io.in[0].bits.a_type := UInt<1>("h00") mem_req_arb.io.in[0].bits.is_builtin_type := UInt<1>("h00") mem_req_arb.io.in[0].bits.data := UInt<1>("h00") mem_req_arb.io.in[0].bits.addr_beat := UInt<1>("h00") mem_req_arb.io.in[0].bits.client_xact_id := UInt<1>("h00") mem_req_arb.io.in[0].bits.addr_block := UInt<1>("h00") mem_req_arb.io.in[0].valid := UInt<1>("h00") mem_req_arb.io.in[1].bits.union := UInt<1>("h00") mem_req_arb.io.in[1].bits.a_type := UInt<1>("h00") mem_req_arb.io.in[1].bits.is_builtin_type := UInt<1>("h00") mem_req_arb.io.in[1].bits.data := UInt<1>("h00") mem_req_arb.io.in[1].bits.addr_beat := UInt<1>("h00") mem_req_arb.io.in[1].bits.client_xact_id := UInt<1>("h00") mem_req_arb.io.in[1].bits.addr_block := UInt<1>("h00") mem_req_arb.io.in[1].valid := UInt<1>("h00") mem_req_arb.io.in[2].bits.union := UInt<1>("h00") mem_req_arb.io.in[2].bits.a_type := UInt<1>("h00") mem_req_arb.io.in[2].bits.is_builtin_type := UInt<1>("h00") mem_req_arb.io.in[2].bits.data := UInt<1>("h00") mem_req_arb.io.in[2].bits.addr_beat := UInt<1>("h00") mem_req_arb.io.in[2].bits.client_xact_id := UInt<1>("h00") mem_req_arb.io.in[2].bits.addr_block := UInt<1>("h00") mem_req_arb.io.in[2].valid := UInt<1>("h00") mem_req_arb.clock := clock mem_req_arb.reset := reset inst wb_req_arb of Arbiter_82 wb_req_arb.io.out.ready := UInt<1>("h00") wb_req_arb.io.in[0].bits.way_en := UInt<1>("h00") wb_req_arb.io.in[0].bits.voluntary := UInt<1>("h00") wb_req_arb.io.in[0].bits.r_type := UInt<1>("h00") wb_req_arb.io.in[0].bits.data := UInt<1>("h00") wb_req_arb.io.in[0].bits.addr_beat := UInt<1>("h00") wb_req_arb.io.in[0].bits.client_xact_id := UInt<1>("h00") wb_req_arb.io.in[0].bits.addr_block := UInt<1>("h00") wb_req_arb.io.in[0].valid := UInt<1>("h00") wb_req_arb.io.in[1].bits.way_en := UInt<1>("h00") wb_req_arb.io.in[1].bits.voluntary := UInt<1>("h00") wb_req_arb.io.in[1].bits.r_type := UInt<1>("h00") wb_req_arb.io.in[1].bits.data := UInt<1>("h00") wb_req_arb.io.in[1].bits.addr_beat := UInt<1>("h00") wb_req_arb.io.in[1].bits.client_xact_id := UInt<1>("h00") wb_req_arb.io.in[1].bits.addr_block := UInt<1>("h00") wb_req_arb.io.in[1].valid := UInt<1>("h00") wb_req_arb.clock := clock wb_req_arb.reset := reset inst replay_arb of Arbiter_83 replay_arb.io.out.ready := UInt<1>("h00") replay_arb.io.in[0].bits.sdq_id := UInt<1>("h00") replay_arb.io.in[0].bits.phys := UInt<1>("h00") replay_arb.io.in[0].bits.kill := UInt<1>("h00") replay_arb.io.in[0].bits.typ := UInt<1>("h00") replay_arb.io.in[0].bits.cmd := UInt<1>("h00") replay_arb.io.in[0].bits.tag := UInt<1>("h00") replay_arb.io.in[0].bits.addr := UInt<1>("h00") replay_arb.io.in[0].valid := UInt<1>("h00") replay_arb.io.in[1].bits.sdq_id := UInt<1>("h00") replay_arb.io.in[1].bits.phys := UInt<1>("h00") replay_arb.io.in[1].bits.kill := UInt<1>("h00") replay_arb.io.in[1].bits.typ := UInt<1>("h00") replay_arb.io.in[1].bits.cmd := UInt<1>("h00") replay_arb.io.in[1].bits.tag := UInt<1>("h00") replay_arb.io.in[1].bits.addr := UInt<1>("h00") replay_arb.io.in[1].valid := UInt<1>("h00") replay_arb.clock := clock replay_arb.reset := reset inst alloc_arb of Arbiter_84 alloc_arb.io.out.ready := UInt<1>("h00") alloc_arb.io.in[0].bits := UInt<1>("h00") alloc_arb.io.in[0].valid := UInt<1>("h00") alloc_arb.io.in[1].bits := UInt<1>("h00") alloc_arb.io.in[1].valid := UInt<1>("h00") alloc_arb.clock := clock alloc_arb.reset := reset io.fence_rdy := UInt<1>("h01") io.probe_rdy := UInt<1>("h01") inst T_1151 of MSHR T_1151.io.wb_req.ready := UInt<1>("h00") T_1151.io.mem_grant.bits.g_type := UInt<1>("h00") T_1151.io.mem_grant.bits.is_builtin_type := UInt<1>("h00") T_1151.io.mem_grant.bits.manager_xact_id := UInt<1>("h00") T_1151.io.mem_grant.bits.client_xact_id := UInt<1>("h00") T_1151.io.mem_grant.bits.data := UInt<1>("h00") T_1151.io.mem_grant.bits.addr_beat := UInt<1>("h00") T_1151.io.mem_grant.valid := UInt<1>("h00") T_1151.io.replay.ready := UInt<1>("h00") T_1151.io.meta_write.ready := UInt<1>("h00") T_1151.io.meta_read.ready := UInt<1>("h00") T_1151.io.mem_req.ready := UInt<1>("h00") T_1151.io.req_bits.way_en := UInt<1>("h00") T_1151.io.req_bits.old_meta.coh.state := UInt<1>("h00") T_1151.io.req_bits.old_meta.tag := UInt<1>("h00") T_1151.io.req_bits.tag_match := UInt<1>("h00") T_1151.io.req_bits.sdq_id := UInt<1>("h00") T_1151.io.req_bits.phys := UInt<1>("h00") T_1151.io.req_bits.kill := UInt<1>("h00") T_1151.io.req_bits.typ := UInt<1>("h00") T_1151.io.req_bits.cmd := UInt<1>("h00") T_1151.io.req_bits.tag := UInt<1>("h00") T_1151.io.req_bits.addr := UInt<1>("h00") T_1151.io.req_sec_val := UInt<1>("h00") T_1151.io.req_pri_val := UInt<1>("h00") T_1151.clock := clock T_1151.reset := reset idxMatch[0] := T_1151.io.idx_match tagList[0] := T_1151.io.tag node T_1177 = shr(T_1151.io.wb_req.bits.addr_block, 6) wbTagList[0] := T_1177 alloc_arb.io.in[0].valid := T_1151.io.req_pri_rdy T_1151.io.req_pri_val := alloc_arb.io.in[0].ready node T_1178 = and(io.req.valid, sdq_rdy) node T_1179 = and(T_1178, tag_match) T_1151.io.req_sec_val := T_1179 T_1151.io.req_bits <> io.req.bits T_1151.io.req_bits.sdq_id := sdq_alloc_id meta_read_arb.io.in[0] <> T_1151.io.meta_read meta_write_arb.io.in[0] <> T_1151.io.meta_write mem_req_arb.io.in[0] <> T_1151.io.mem_req wb_req_arb.io.in[0] <> T_1151.io.wb_req replay_arb.io.in[0] <> T_1151.io.replay node T_1181 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00")) node T_1182 = and(io.mem_grant.valid, T_1181) T_1151.io.mem_grant.valid := T_1182 T_1151.io.mem_grant.bits <> io.mem_grant.bits refillMux[0] <> T_1151.io.refill node T_1183 = or(UInt<1>("h00"), T_1151.io.req_pri_rdy) node T_1184 = or(UInt<1>("h00"), T_1151.io.req_sec_rdy) node T_1185 = or(UInt<1>("h00"), T_1151.io.idx_match) node T_1187 = eq(T_1151.io.req_pri_rdy, UInt<1>("h00")) when T_1187 : io.fence_rdy := UInt<1>("h00") skip node T_1190 = eq(T_1151.io.probe_rdy, UInt<1>("h00")) when T_1190 : io.probe_rdy := UInt<1>("h00") skip inst T_1192 of MSHR_86 T_1192.io.wb_req.ready := UInt<1>("h00") T_1192.io.mem_grant.bits.g_type := UInt<1>("h00") T_1192.io.mem_grant.bits.is_builtin_type := UInt<1>("h00") T_1192.io.mem_grant.bits.manager_xact_id := UInt<1>("h00") T_1192.io.mem_grant.bits.client_xact_id := UInt<1>("h00") T_1192.io.mem_grant.bits.data := UInt<1>("h00") T_1192.io.mem_grant.bits.addr_beat := UInt<1>("h00") T_1192.io.mem_grant.valid := UInt<1>("h00") T_1192.io.replay.ready := UInt<1>("h00") T_1192.io.meta_write.ready := UInt<1>("h00") T_1192.io.meta_read.ready := UInt<1>("h00") T_1192.io.mem_req.ready := UInt<1>("h00") T_1192.io.req_bits.way_en := UInt<1>("h00") T_1192.io.req_bits.old_meta.coh.state := UInt<1>("h00") T_1192.io.req_bits.old_meta.tag := UInt<1>("h00") T_1192.io.req_bits.tag_match := UInt<1>("h00") T_1192.io.req_bits.sdq_id := UInt<1>("h00") T_1192.io.req_bits.phys := UInt<1>("h00") T_1192.io.req_bits.kill := UInt<1>("h00") T_1192.io.req_bits.typ := UInt<1>("h00") T_1192.io.req_bits.cmd := UInt<1>("h00") T_1192.io.req_bits.tag := UInt<1>("h00") T_1192.io.req_bits.addr := UInt<1>("h00") T_1192.io.req_sec_val := UInt<1>("h00") T_1192.io.req_pri_val := UInt<1>("h00") T_1192.clock := clock T_1192.reset := reset idxMatch[1] := T_1192.io.idx_match tagList[1] := T_1192.io.tag node T_1218 = shr(T_1192.io.wb_req.bits.addr_block, 6) wbTagList[1] := T_1218 alloc_arb.io.in[1].valid := T_1192.io.req_pri_rdy T_1192.io.req_pri_val := alloc_arb.io.in[1].ready node T_1219 = and(io.req.valid, sdq_rdy) node T_1220 = and(T_1219, tag_match) T_1192.io.req_sec_val := T_1220 T_1192.io.req_bits <> io.req.bits T_1192.io.req_bits.sdq_id := sdq_alloc_id meta_read_arb.io.in[1] <> T_1192.io.meta_read meta_write_arb.io.in[1] <> T_1192.io.meta_write mem_req_arb.io.in[1] <> T_1192.io.mem_req wb_req_arb.io.in[1] <> T_1192.io.wb_req replay_arb.io.in[1] <> T_1192.io.replay node T_1222 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01")) node T_1223 = and(io.mem_grant.valid, T_1222) T_1192.io.mem_grant.valid := T_1223 T_1192.io.mem_grant.bits <> io.mem_grant.bits refillMux[1] <> T_1192.io.refill node pri_rdy = or(T_1183, T_1192.io.req_pri_rdy) node sec_rdy = or(T_1184, T_1192.io.req_sec_rdy) node idx_match = or(T_1185, T_1192.io.idx_match) node T_1228 = eq(T_1192.io.req_pri_rdy, UInt<1>("h00")) when T_1228 : io.fence_rdy := UInt<1>("h00") skip node T_1231 = eq(T_1192.io.probe_rdy, UInt<1>("h00")) when T_1231 : io.probe_rdy := UInt<1>("h00") skip node T_1233 = and(io.req.valid, sdq_rdy) node T_1234 = and(T_1233, cacheable) node T_1236 = eq(idx_match, UInt<1>("h00")) node T_1237 = and(T_1234, T_1236) alloc_arb.io.out.ready := T_1237 io.meta_read <> meta_read_arb.io.out io.meta_write <> meta_write_arb.io.out io.mem_req <> mem_req_arb.io.out io.wb_req <> wb_req_arb.io.out inst mmio_alloc_arb of Arbiter_88 mmio_alloc_arb.io.out.ready := UInt<1>("h00") mmio_alloc_arb.io.in[0].bits := UInt<1>("h00") mmio_alloc_arb.io.in[0].valid := UInt<1>("h00") mmio_alloc_arb.clock := clock mmio_alloc_arb.reset := reset inst resp_arb of Arbiter_89 resp_arb.io.out.ready := UInt<1>("h00") resp_arb.io.in[0].bits.store_data := UInt<1>("h00") resp_arb.io.in[0].bits.data_word_bypass := UInt<1>("h00") resp_arb.io.in[0].bits.has_data := UInt<1>("h00") resp_arb.io.in[0].bits.replay := UInt<1>("h00") resp_arb.io.in[0].bits.nack := UInt<1>("h00") resp_arb.io.in[0].bits.data := UInt<1>("h00") resp_arb.io.in[0].bits.typ := UInt<1>("h00") resp_arb.io.in[0].bits.cmd := UInt<1>("h00") resp_arb.io.in[0].bits.tag := UInt<1>("h00") resp_arb.io.in[0].bits.addr := UInt<1>("h00") resp_arb.io.in[0].valid := UInt<1>("h00") resp_arb.clock := clock resp_arb.reset := reset inst T_1268 of IOMSHR T_1268.io.resp.ready := UInt<1>("h00") T_1268.io.grant.bits.g_type := UInt<1>("h00") T_1268.io.grant.bits.is_builtin_type := UInt<1>("h00") T_1268.io.grant.bits.manager_xact_id := UInt<1>("h00") T_1268.io.grant.bits.client_xact_id := UInt<1>("h00") T_1268.io.grant.bits.data := UInt<1>("h00") T_1268.io.grant.bits.addr_beat := UInt<1>("h00") T_1268.io.grant.valid := UInt<1>("h00") T_1268.io.acquire.ready := UInt<1>("h00") T_1268.io.req.bits.data := UInt<1>("h00") T_1268.io.req.bits.phys := UInt<1>("h00") T_1268.io.req.bits.kill := UInt<1>("h00") T_1268.io.req.bits.typ := UInt<1>("h00") T_1268.io.req.bits.cmd := UInt<1>("h00") T_1268.io.req.bits.tag := UInt<1>("h00") T_1268.io.req.bits.addr := UInt<1>("h00") T_1268.io.req.valid := UInt<1>("h00") T_1268.clock := clock T_1268.reset := reset mmio_alloc_arb.io.in[0].valid := T_1268.io.req.ready T_1268.io.req.valid := mmio_alloc_arb.io.in[0].ready T_1268.io.req.bits <> io.req.bits node mmio_rdy = or(UInt<1>("h00"), T_1268.io.req.ready) mem_req_arb.io.in[2] <> T_1268.io.acquire T_1268.io.grant.bits <> io.mem_grant.bits node T_1288 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02")) node T_1289 = and(io.mem_grant.valid, T_1288) T_1268.io.grant.valid := T_1289 resp_arb.io.in[0] <> T_1268.io.resp node T_1291 = eq(T_1268.io.req.ready, UInt<1>("h00")) when T_1291 : io.fence_rdy := UInt<1>("h00") skip node T_1294 = eq(cacheable, UInt<1>("h00")) node T_1295 = and(io.req.valid, T_1294) mmio_alloc_arb.io.out.ready := T_1295 io.resp <> resp_arb.io.out node T_1297 = eq(cacheable, UInt<1>("h00")) node T_1298 = and(tag_match, sec_rdy) node T_1299 = mux(idx_match, T_1298, pri_rdy) node T_1300 = and(T_1299, sdq_rdy) node T_1301 = mux(T_1297, mmio_rdy, T_1300) io.req.ready := T_1301 io.secondary_miss := idx_match infer accessor T_1302 = refillMux[io.mem_grant.bits.client_xact_id] io.refill <> T_1302 node T_1305 = and(io.replay.ready, io.replay.valid) node T_1306 = eq(io.replay.bits.cmd, UInt<5>("h01")) node T_1307 = eq(io.replay.bits.cmd, UInt<5>("h07")) node T_1308 = or(T_1306, T_1307) node T_1309 = bit(io.replay.bits.cmd, 3) node T_1310 = eq(io.replay.bits.cmd, UInt<5>("h04")) node T_1311 = or(T_1309, T_1310) node T_1312 = or(T_1308, T_1311) node free_sdq = and(T_1305, T_1312) reg T_1314 : UInt<5>, clock, reset when free_sdq : T_1314 := replay_arb.io.out.bits.sdq_id skip infer accessor T_1315 = sdq[T_1314] io.replay.bits.data := T_1315 io.replay <> replay_arb.io.out node T_1316 = or(io.replay.valid, sdq_enq) when T_1316 : node T_1318 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id) node T_1320 = subw(UInt<17>("h00"), free_sdq) node T_1321 = and(T_1318, T_1320) node T_1322 = not(T_1321) node T_1323 = and(sdq_val, T_1322) node T_1324 = bits(sdq_val, 16, 0) node T_1325 = not(T_1324) node T_1326 = bit(T_1325, 0) node T_1327 = bit(T_1325, 1) node T_1328 = bit(T_1325, 2) node T_1329 = bit(T_1325, 3) node T_1330 = bit(T_1325, 4) node T_1331 = bit(T_1325, 5) node T_1332 = bit(T_1325, 6) node T_1333 = bit(T_1325, 7) node T_1334 = bit(T_1325, 8) node T_1335 = bit(T_1325, 9) node T_1336 = bit(T_1325, 10) node T_1337 = bit(T_1325, 11) node T_1338 = bit(T_1325, 12) node T_1339 = bit(T_1325, 13) node T_1340 = bit(T_1325, 14) node T_1341 = bit(T_1325, 15) node T_1342 = bit(T_1325, 16) wire T_1361 : UInt<17>[17] T_1361[0] := UInt<17>("h01") T_1361[1] := UInt<17>("h02") T_1361[2] := UInt<17>("h04") T_1361[3] := UInt<17>("h08") T_1361[4] := UInt<17>("h010") T_1361[5] := UInt<17>("h020") T_1361[6] := UInt<17>("h040") T_1361[7] := UInt<17>("h080") T_1361[8] := UInt<17>("h0100") T_1361[9] := UInt<17>("h0200") T_1361[10] := UInt<17>("h0400") T_1361[11] := UInt<17>("h0800") T_1361[12] := UInt<17>("h01000") T_1361[13] := UInt<17>("h02000") T_1361[14] := UInt<17>("h04000") T_1361[15] := UInt<17>("h08000") T_1361[16] := UInt<17>("h010000") node T_1382 = mux(T_1342, T_1361[16], UInt<17>("h00")) node T_1383 = mux(T_1341, T_1361[15], T_1382) node T_1384 = mux(T_1340, T_1361[14], T_1383) node T_1385 = mux(T_1339, T_1361[13], T_1384) node T_1386 = mux(T_1338, T_1361[12], T_1385) node T_1387 = mux(T_1337, T_1361[11], T_1386) node T_1388 = mux(T_1336, T_1361[10], T_1387) node T_1389 = mux(T_1335, T_1361[9], T_1388) node T_1390 = mux(T_1334, T_1361[8], T_1389) node T_1391 = mux(T_1333, T_1361[7], T_1390) node T_1392 = mux(T_1332, T_1361[6], T_1391) node T_1393 = mux(T_1331, T_1361[5], T_1392) node T_1394 = mux(T_1330, T_1361[4], T_1393) node T_1395 = mux(T_1329, T_1361[3], T_1394) node T_1396 = mux(T_1328, T_1361[2], T_1395) node T_1397 = mux(T_1327, T_1361[1], T_1396) node T_1398 = mux(T_1326, T_1361[0], T_1397) node T_1400 = subw(UInt<17>("h00"), sdq_enq) node T_1401 = and(T_1398, T_1400) node T_1402 = or(T_1323, T_1401) sdq_val := T_1402 skip module TLB_90 : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} io.ptw.req.bits.fetch := UInt<1>("h00") io.ptw.req.bits.store := UInt<1>("h00") io.ptw.req.bits.prv := UInt<1>("h00") io.ptw.req.bits.addr := UInt<1>("h00") io.ptw.req.valid := UInt<1>("h00") io.resp.hit_idx := UInt<1>("h00") io.resp.xcpt_if := UInt<1>("h00") io.resp.xcpt_st := UInt<1>("h00") io.resp.xcpt_ld := UInt<1>("h00") io.resp.ppn := UInt<1>("h00") io.resp.miss := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg r_refill_tag : UInt, clock, reset reg r_refill_waddr : UInt, clock, reset reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset inst tag_cam of RocketCAM tag_cam.io.write_addr := UInt<1>("h00") tag_cam.io.write_tag := UInt<1>("h00") tag_cam.io.write := UInt<1>("h00") tag_cam.io.tag := UInt<1>("h00") tag_cam.io.clear_mask := UInt<1>("h00") tag_cam.io.clear := UInt<1>("h00") tag_cam.clock := clock tag_cam.reset := reset cmem tag_ram : UInt<20>[8], clock node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) tag_cam.io.tag := lookup_tag node T_182 = eq(state, UInt<2>("h02")) node T_183 = and(T_182, io.ptw.resp.valid) tag_cam.io.write := T_183 tag_cam.io.write_tag := r_refill_tag tag_cam.io.write_addr := r_refill_waddr node T_184 = bits(tag_cam.io.hits, 7, 4) node T_185 = bits(tag_cam.io.hits, 3, 0) node T_187 = neq(T_184, UInt<1>("h00")) node T_188 = or(T_184, T_185) node T_189 = bits(T_188, 3, 2) node T_190 = bits(T_188, 1, 0) node T_192 = neq(T_189, UInt<1>("h00")) node T_193 = or(T_189, T_190) node T_194 = bit(T_193, 1) node T_195 = cat(T_192, T_194) node tag_hit_addr = cat(T_187, T_195) reg valid_array : UInt<1>[8], clock, reset reg ur_array : UInt<1>[8], clock, reset reg uw_array : UInt<1>[8], clock, reset reg ux_array : UInt<1>[8], clock, reset reg sr_array : UInt<1>[8], clock, reset reg sw_array : UInt<1>[8], clock, reset reg sx_array : UInt<1>[8], clock, reset reg dirty_array : UInt<1>[8], clock, reset when io.ptw.resp.valid : infer accessor T_389 = tag_ram[r_refill_waddr] T_389 := io.ptw.resp.bits.pte.ppn infer accessor T_390 = valid_array[r_refill_waddr] node T_392 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) T_390 := T_392 infer accessor T_393 = ur_array[r_refill_waddr] node T_395 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_396 = and(io.ptw.resp.bits.pte.v, T_395) node T_398 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_399 = and(T_396, T_398) node T_401 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_402 = and(T_399, T_401) T_393 := T_402 infer accessor T_403 = uw_array[r_refill_waddr] node T_405 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_406 = and(io.ptw.resp.bits.pte.v, T_405) node T_408 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_409 = and(T_406, T_408) node T_410 = bit(io.ptw.resp.bits.pte.typ, 0) node T_411 = and(T_409, T_410) node T_413 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_414 = and(T_411, T_413) T_403 := T_414 infer accessor T_415 = ux_array[r_refill_waddr] node T_417 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_418 = and(io.ptw.resp.bits.pte.v, T_417) node T_420 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_421 = and(T_418, T_420) node T_422 = bit(io.ptw.resp.bits.pte.typ, 1) node T_423 = and(T_421, T_422) node T_425 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_426 = and(T_423, T_425) T_415 := T_426 infer accessor T_427 = sr_array[r_refill_waddr] node T_429 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_430 = and(io.ptw.resp.bits.pte.v, T_429) node T_432 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_433 = and(T_430, T_432) T_427 := T_433 infer accessor T_434 = sw_array[r_refill_waddr] node T_436 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_437 = and(io.ptw.resp.bits.pte.v, T_436) node T_438 = bit(io.ptw.resp.bits.pte.typ, 0) node T_439 = and(T_437, T_438) node T_441 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_442 = and(T_439, T_441) T_434 := T_442 infer accessor T_443 = sx_array[r_refill_waddr] node T_445 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) node T_446 = and(io.ptw.resp.bits.pte.v, T_445) node T_447 = bit(io.ptw.resp.bits.pte.typ, 1) node T_448 = and(T_446, T_447) node T_450 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_451 = and(T_448, T_450) T_443 := T_451 infer accessor T_452 = dirty_array[r_refill_waddr] T_452 := io.ptw.resp.bits.pte.d skip node T_453 = not(tag_cam.io.valid_bits) node T_455 = eq(T_453, UInt<1>("h00")) node has_invalid_entry = eq(T_455, UInt<1>("h00")) node T_458 = not(tag_cam.io.valid_bits) node T_459 = bit(T_458, 0) node T_460 = bit(T_458, 1) node T_461 = bit(T_458, 2) node T_462 = bit(T_458, 3) node T_463 = bit(T_458, 4) node T_464 = bit(T_458, 5) node T_465 = bit(T_458, 6) node T_466 = bit(T_458, 7) wire T_468 : UInt<1>[8] T_468[0] := T_459 T_468[1] := T_460 T_468[2] := T_461 T_468[3] := T_462 T_468[4] := T_463 T_468[5] := T_464 T_468[6] := T_465 T_468[7] := T_466 node T_486 = mux(T_468[6], UInt<3>("h06"), UInt<3>("h07")) node T_487 = mux(T_468[5], UInt<3>("h05"), T_486) node T_488 = mux(T_468[4], UInt<3>("h04"), T_487) node T_489 = mux(T_468[3], UInt<2>("h03"), T_488) node T_490 = mux(T_468[2], UInt<2>("h02"), T_489) node T_491 = mux(T_468[1], UInt<1>("h01"), T_490) node invalid_entry = mux(T_468[0], UInt<1>("h00"), T_491) reg T_494 : UInt<8>, clock, reset node T_496 = dshr(T_494, UInt<1>("h01")) node T_497 = bit(T_496, 0) node T_498 = cat(UInt<1>("h01"), T_497) node T_499 = dshr(T_494, T_498) node T_500 = bit(T_499, 0) node T_501 = cat(T_498, T_500) node T_502 = dshr(T_494, T_501) node T_503 = bit(T_502, 0) node T_504 = cat(T_501, T_503) node T_505 = bits(T_504, 2, 0) node repl_waddr = mux(has_invalid_entry, invalid_entry, T_505) node T_508 = eq(io.req.bits.instruction, UInt<1>("h00")) node T_509 = and(io.ptw.status.mprv, T_508) node priv = mux(T_509, io.ptw.status.prv1, io.ptw.status.prv) node priv_s = eq(priv, UInt<1>("h01")) node priv_uses_vm = leq(priv, UInt<1>("h01")) node T_516 = eq(r_req.store, UInt<1>("h00")) node T_517 = or(r_req.instruction, r_req.store) node T_519 = eq(T_517, UInt<1>("h00")) node T_520 = cat(r_req.store, T_519) node req_xwr = cat(T_516, T_520) node T_522 = cat(sr_array[7], sr_array[6]) node T_523 = cat(sr_array[5], sr_array[4]) node T_524 = cat(T_522, T_523) node T_525 = cat(sr_array[3], sr_array[2]) node T_526 = cat(sr_array[1], sr_array[0]) node T_527 = cat(T_525, T_526) node T_528 = cat(T_524, T_527) node T_529 = cat(ur_array[7], ur_array[6]) node T_530 = cat(ur_array[5], ur_array[4]) node T_531 = cat(T_529, T_530) node T_532 = cat(ur_array[3], ur_array[2]) node T_533 = cat(ur_array[1], ur_array[0]) node T_534 = cat(T_532, T_533) node T_535 = cat(T_531, T_534) node r_array = mux(priv_s, T_528, T_535) node T_537 = cat(sw_array[7], sw_array[6]) node T_538 = cat(sw_array[5], sw_array[4]) node T_539 = cat(T_537, T_538) node T_540 = cat(sw_array[3], sw_array[2]) node T_541 = cat(sw_array[1], sw_array[0]) node T_542 = cat(T_540, T_541) node T_543 = cat(T_539, T_542) node T_544 = cat(uw_array[7], uw_array[6]) node T_545 = cat(uw_array[5], uw_array[4]) node T_546 = cat(T_544, T_545) node T_547 = cat(uw_array[3], uw_array[2]) node T_548 = cat(uw_array[1], uw_array[0]) node T_549 = cat(T_547, T_548) node T_550 = cat(T_546, T_549) node w_array = mux(priv_s, T_543, T_550) node T_552 = cat(sx_array[7], sx_array[6]) node T_553 = cat(sx_array[5], sx_array[4]) node T_554 = cat(T_552, T_553) node T_555 = cat(sx_array[3], sx_array[2]) node T_556 = cat(sx_array[1], sx_array[0]) node T_557 = cat(T_555, T_556) node T_558 = cat(T_554, T_557) node T_559 = cat(ux_array[7], ux_array[6]) node T_560 = cat(ux_array[5], ux_array[4]) node T_561 = cat(T_559, T_560) node T_562 = cat(ux_array[3], ux_array[2]) node T_563 = cat(ux_array[1], ux_array[0]) node T_564 = cat(T_562, T_563) node T_565 = cat(T_561, T_564) node x_array = mux(priv_s, T_558, T_565) node T_567 = bit(io.ptw.status.vm, 3) node T_568 = and(T_567, priv_uses_vm) node T_570 = eq(io.req.bits.passthrough, UInt<1>("h00")) node vm_enabled = and(T_568, T_570) node T_572 = bit(io.req.bits.vpn, 27) node T_573 = bit(io.req.bits.vpn, 26) node bad_va = neq(T_572, T_573) node T_575 = cat(dirty_array[7], dirty_array[6]) node T_576 = cat(dirty_array[5], dirty_array[4]) node T_577 = cat(T_575, T_576) node T_578 = cat(dirty_array[3], dirty_array[2]) node T_579 = cat(dirty_array[1], dirty_array[0]) node T_580 = cat(T_578, T_579) node T_581 = cat(T_577, T_580) node T_583 = mux(io.req.bits.store, w_array, UInt<1>("h00")) node T_584 = not(T_583) node T_585 = or(T_581, T_584) node tag_hits = and(tag_cam.io.hits, T_585) node tag_hit = neq(tag_hits, UInt<1>("h00")) node tlb_hit = and(vm_enabled, tag_hit) node T_591 = eq(tag_hit, UInt<1>("h00")) node T_592 = and(vm_enabled, T_591) node T_594 = eq(bad_va, UInt<1>("h00")) node tlb_miss = and(T_592, T_594) node T_596 = and(io.req.valid, tlb_hit) when T_596 : node T_597 = bits(tag_cam.io.hits, 7, 4) node T_598 = bits(tag_cam.io.hits, 3, 0) node T_600 = neq(T_597, UInt<1>("h00")) node T_601 = or(T_597, T_598) node T_602 = bits(T_601, 3, 2) node T_603 = bits(T_601, 1, 0) node T_605 = neq(T_602, UInt<1>("h00")) node T_606 = or(T_602, T_603) node T_607 = bit(T_606, 1) node T_608 = cat(T_605, T_607) node T_609 = cat(T_600, T_608) node T_611 = bit(T_609, 2) node T_613 = dshl(UInt<8>("h01"), UInt<1>("h01")) node T_614 = bits(T_613, 7, 0) node T_615 = not(T_614) node T_616 = and(T_494, T_615) node T_618 = mux(T_611, UInt<1>("h00"), T_614) node T_619 = or(T_616, T_618) node T_620 = cat(UInt<1>("h01"), T_611) node T_621 = bit(T_609, 1) node T_623 = dshl(UInt<8>("h01"), T_620) node T_624 = bits(T_623, 7, 0) node T_625 = not(T_624) node T_626 = and(T_619, T_625) node T_628 = mux(T_621, UInt<1>("h00"), T_624) node T_629 = or(T_626, T_628) node T_630 = cat(T_620, T_621) node T_631 = bit(T_609, 0) node T_633 = dshl(UInt<8>("h01"), T_630) node T_634 = bits(T_633, 7, 0) node T_635 = not(T_634) node T_636 = and(T_629, T_635) node T_638 = mux(T_631, UInt<1>("h00"), T_634) node T_639 = or(T_636, T_638) node T_640 = cat(T_630, T_631) T_494 := T_639 skip node paddr = cat(io.resp.ppn, UInt<12>("h00")) node T_644 = geq(paddr, UInt<1>("h00")) node T_646 = lt(paddr, UInt<31>("h040000000")) node T_647 = and(T_644, T_646) node T_649 = geq(paddr, UInt<31>("h040000000")) node T_651 = lt(paddr, UInt<31>("h040008000")) node T_652 = and(T_649, T_651) node T_654 = geq(paddr, UInt<31>("h040008000")) node T_656 = lt(paddr, UInt<31>("h040008200")) node T_657 = and(T_654, T_656) node T_659 = geq(paddr, UInt<32>("h080000000")) node T_661 = lt(paddr, UInt<33>("h0100000000")) node T_662 = and(T_659, T_661) node T_663 = or(T_647, T_652) node T_664 = or(T_663, T_657) node addr_ok = or(T_664, T_662) node T_667 = geq(paddr, UInt<1>("h00")) node T_669 = lt(paddr, UInt<31>("h040000000")) node T_670 = and(T_667, T_669) wire T_680 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_680.x := UInt<1>("h00") T_680.w := UInt<1>("h00") T_680.r := UInt<1>("h00") T_680.x := UInt<1>("h01") T_680.w := UInt<1>("h01") T_680.r := UInt<1>("h01") node T_691 = geq(paddr, UInt<31>("h040000000")) node T_693 = lt(paddr, UInt<31>("h040008000")) node T_694 = and(T_691, T_693) wire T_704 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_704.x := UInt<1>("h00") T_704.w := UInt<1>("h00") T_704.r := UInt<1>("h00") T_704.x := UInt<1>("h00") T_704.w := UInt<1>("h01") T_704.r := UInt<1>("h01") node T_715 = geq(paddr, UInt<31>("h040008000")) node T_717 = lt(paddr, UInt<31>("h040008200")) node T_718 = and(T_715, T_717) wire T_728 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_728.x := UInt<1>("h00") T_728.w := UInt<1>("h00") T_728.r := UInt<1>("h00") T_728.x := UInt<1>("h00") T_728.w := UInt<1>("h01") T_728.r := UInt<1>("h01") node T_739 = geq(paddr, UInt<32>("h080000000")) node T_741 = lt(paddr, UInt<33>("h0100000000")) node T_742 = and(T_739, T_741) wire T_752 : {r : UInt<1>, w : UInt<1>, x : UInt<1>} T_752.x := UInt<1>("h00") T_752.w := UInt<1>("h00") T_752.r := UInt<1>("h00") T_752.x := UInt<1>("h00") T_752.w := UInt<1>("h01") T_752.r := UInt<1>("h01") node T_762 = cat(T_680.w, T_680.x) node T_763 = cat(T_680.r, T_762) node T_765 = mux(T_670, T_763, UInt<1>("h00")) node T_766 = cat(T_704.w, T_704.x) node T_767 = cat(T_704.r, T_766) node T_769 = mux(T_694, T_767, UInt<1>("h00")) node T_770 = cat(T_728.w, T_728.x) node T_771 = cat(T_728.r, T_770) node T_773 = mux(T_718, T_771, UInt<1>("h00")) node T_774 = cat(T_752.w, T_752.x) node T_775 = cat(T_752.r, T_774) node T_777 = mux(T_742, T_775, UInt<1>("h00")) node T_782 = or(T_765, T_769) node T_783 = or(T_782, T_773) node T_784 = or(T_783, T_777) wire addr_prot : {r : UInt<1>, w : UInt<1>, x : UInt<1>} addr_prot.x := UInt<1>("h00") addr_prot.w := UInt<1>("h00") addr_prot.r := UInt<1>("h00") node T_796 = bits(T_784, 0, 0) addr_prot.x := T_796 node T_797 = bits(T_784, 1, 1) addr_prot.w := T_797 node T_798 = bits(T_784, 2, 2) addr_prot.r := T_798 node T_799 = eq(state, UInt<1>("h00")) io.req.ready := T_799 node T_801 = eq(addr_ok, UInt<1>("h00")) node T_803 = eq(addr_prot.r, UInt<1>("h00")) node T_804 = or(T_801, T_803) node T_805 = or(T_804, bad_va) node T_806 = and(r_array, tag_cam.io.hits) node T_808 = neq(T_806, UInt<1>("h00")) node T_810 = eq(T_808, UInt<1>("h00")) node T_811 = and(tlb_hit, T_810) node T_812 = or(T_805, T_811) io.resp.xcpt_ld := T_812 node T_814 = eq(addr_ok, UInt<1>("h00")) node T_816 = eq(addr_prot.w, UInt<1>("h00")) node T_817 = or(T_814, T_816) node T_818 = or(T_817, bad_va) node T_819 = and(w_array, tag_cam.io.hits) node T_821 = neq(T_819, UInt<1>("h00")) node T_823 = eq(T_821, UInt<1>("h00")) node T_824 = and(tlb_hit, T_823) node T_825 = or(T_818, T_824) io.resp.xcpt_st := T_825 node T_827 = eq(addr_ok, UInt<1>("h00")) node T_829 = eq(addr_prot.x, UInt<1>("h00")) node T_830 = or(T_827, T_829) node T_831 = or(T_830, bad_va) node T_832 = and(x_array, tag_cam.io.hits) node T_834 = neq(T_832, UInt<1>("h00")) node T_836 = eq(T_834, UInt<1>("h00")) node T_837 = and(tlb_hit, T_836) node T_838 = or(T_831, T_837) io.resp.xcpt_if := T_838 io.resp.miss := tlb_miss node T_839 = bit(tag_cam.io.hits, 0) node T_840 = bit(tag_cam.io.hits, 1) node T_841 = bit(tag_cam.io.hits, 2) node T_842 = bit(tag_cam.io.hits, 3) node T_843 = bit(tag_cam.io.hits, 4) node T_844 = bit(tag_cam.io.hits, 5) node T_845 = bit(tag_cam.io.hits, 6) node T_846 = bit(tag_cam.io.hits, 7) infer accessor T_848 = tag_ram[UInt<1>("h00")] infer accessor T_850 = tag_ram[UInt<1>("h01")] infer accessor T_852 = tag_ram[UInt<2>("h02")] infer accessor T_854 = tag_ram[UInt<2>("h03")] infer accessor T_856 = tag_ram[UInt<3>("h04")] infer accessor T_858 = tag_ram[UInt<3>("h05")] infer accessor T_860 = tag_ram[UInt<3>("h06")] infer accessor T_862 = tag_ram[UInt<3>("h07")] node T_864 = mux(T_839, T_848, UInt<1>("h00")) node T_866 = mux(T_840, T_850, UInt<1>("h00")) node T_868 = mux(T_841, T_852, UInt<1>("h00")) node T_870 = mux(T_842, T_854, UInt<1>("h00")) node T_872 = mux(T_843, T_856, UInt<1>("h00")) node T_874 = mux(T_844, T_858, UInt<1>("h00")) node T_876 = mux(T_845, T_860, UInt<1>("h00")) node T_878 = mux(T_846, T_862, UInt<1>("h00")) node T_880 = or(T_864, T_866) node T_881 = or(T_880, T_868) node T_882 = or(T_881, T_870) node T_883 = or(T_882, T_872) node T_884 = or(T_883, T_874) node T_885 = or(T_884, T_876) node T_886 = or(T_885, T_878) wire T_887 : UInt<20> T_887 := UInt<1>("h00") T_887 := T_886 node T_889 = bits(io.req.bits.vpn, 19, 0) node T_890 = mux(vm_enabled, T_887, T_889) io.resp.ppn := T_890 io.resp.hit_idx := tag_cam.io.hits node T_891 = and(io.req.ready, io.req.valid) node T_892 = or(io.ptw.invalidate, T_891) tag_cam.io.clear := T_892 node T_893 = cat(valid_array[7], valid_array[6]) node T_894 = cat(valid_array[5], valid_array[4]) node T_895 = cat(T_893, T_894) node T_896 = cat(valid_array[3], valid_array[2]) node T_897 = cat(valid_array[1], valid_array[0]) node T_898 = cat(T_896, T_897) node T_899 = cat(T_895, T_898) node T_900 = not(T_899) node T_901 = not(tag_hits) node T_902 = and(tag_cam.io.hits, T_901) node T_903 = or(T_900, T_902) tag_cam.io.clear_mask := T_903 when io.ptw.invalidate : node T_905 = not(UInt<8>("h00")) tag_cam.io.clear_mask := T_905 skip node T_906 = eq(state, UInt<1>("h01")) io.ptw.req.valid := T_906 io.ptw.req.bits.addr := r_refill_tag io.ptw.req.bits.prv := io.ptw.status.prv io.ptw.req.bits.store := r_req.store io.ptw.req.bits.fetch := r_req.instruction node T_907 = and(io.req.ready, io.req.valid) node T_908 = and(T_907, tlb_miss) when T_908 : state := UInt<1>("h01") r_refill_tag := lookup_tag r_refill_waddr := repl_waddr r_req <> io.req.bits skip node T_909 = eq(state, UInt<1>("h01")) when T_909 : when io.ptw.invalidate : state := UInt<1>("h00") skip when io.ptw.req.ready : state := UInt<2>("h02") when io.ptw.invalidate : state := UInt<2>("h03") skip skip skip node T_910 = eq(state, UInt<2>("h02")) node T_911 = and(T_910, io.ptw.invalidate) when T_911 : state := UInt<2>("h03") skip when io.ptw.resp.valid : state := UInt<1>("h00") skip module MetadataArray : input clock : Clock input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]} io.resp[0].coh.state := UInt<1>("h00") io.resp[0].tag := UInt<1>("h00") io.resp[1].coh.state := UInt<1>("h00") io.resp[1].tag := UInt<1>("h00") io.resp[2].coh.state := UInt<1>("h00") io.resp[2].tag := UInt<1>("h00") io.resp[3].coh.state := UInt<1>("h00") io.resp[3].tag := UInt<1>("h00") io.write.ready := UInt<1>("h00") io.read.ready := UInt<1>("h00") wire T_54 : {state : UInt<2>} T_54.state := UInt<1>("h00") T_54.state := UInt<1>("h00") wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} rstVal.coh.state := UInt<1>("h00") rstVal.tag := UInt<1>("h00") rstVal.tag := UInt<1>("h00") rstVal.coh <> T_54 reg rst_cnt : UInt<7>, clock, reset onreset rst_cnt := UInt<7>("h00") node rst = lt(rst_cnt, UInt<7>("h040")) node waddr = mux(rst, rst_cnt, io.write.bits.idx) wire T_721 : {tag : UInt<20>, coh : {state : UInt<2>}} T_721 <> io.write.bits.data when rst : T_721 <> rstVal skip node wdata = cat(T_721.tag, T_721.coh.state) node T_750 = asSInt(io.write.bits.way_en) node T_751 = mux(rst, asSInt(UInt<1>("h01")), T_750) node T_752 = bit(T_751, 0) node T_753 = bit(T_751, 1) node T_754 = bit(T_751, 2) node T_755 = bit(T_751, 3) wire wmask : UInt<1>[4] wmask[0] := T_752 wmask[1] := T_753 wmask[2] := T_754 wmask[3] := T_755 when rst : node T_764 = addw(rst_cnt, UInt<1>("h01")) rst_cnt := T_764 skip smem tag_arr : UInt<22>[4][64], clock node T_782 = or(rst, io.write.valid) when T_782 : wire T_784 : UInt<22>[4] T_784[0] := wdata T_784[1] := wdata T_784[2] := wdata T_784[3] := wdata infer accessor T_792 = tag_arr[waddr] when wmask[0] : T_792[0] := T_784[0] skip when wmask[1] : T_792[1] := T_784[1] skip when wmask[2] : T_792[2] := T_784[2] skip when wmask[3] : T_792[3] := T_784[3] skip skip poison T_798 : UInt<6> node T_799 = mux(io.read.valid, io.read.bits.idx, T_798) infer accessor T_802 = tag_arr[T_799] node T_808 = cat(T_802[3], T_802[2]) node T_809 = cat(T_802[1], T_802[0]) node tags = cat(T_808, T_809) wire T_1055 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] T_1055[0].coh.state := UInt<1>("h00") T_1055[0].tag := UInt<1>("h00") T_1055[1].coh.state := UInt<1>("h00") T_1055[1].tag := UInt<1>("h00") T_1055[2].coh.state := UInt<1>("h00") T_1055[2].tag := UInt<1>("h00") T_1055[3].coh.state := UInt<1>("h00") T_1055[3].tag := UInt<1>("h00") node T_1199 = bits(tags, 1, 0) T_1055[0].coh.state := T_1199 node T_1200 = bits(tags, 21, 2) T_1055[0].tag := T_1200 node T_1201 = bits(tags, 23, 22) T_1055[1].coh.state := T_1201 node T_1202 = bits(tags, 43, 24) T_1055[1].tag := T_1202 node T_1203 = bits(tags, 45, 44) T_1055[2].coh.state := T_1203 node T_1204 = bits(tags, 65, 46) T_1055[2].tag := T_1204 node T_1205 = bits(tags, 67, 66) T_1055[3].coh.state := T_1205 node T_1206 = bits(tags, 87, 68) T_1055[3].tag := T_1206 io.resp := T_1055 node T_1208 = eq(rst, UInt<1>("h00")) node T_1210 = eq(io.write.valid, UInt<1>("h00")) node T_1211 = and(T_1208, T_1210) io.read.ready := T_1211 node T_1213 = eq(rst, UInt<1>("h00")) io.write.ready := T_1213 module Arbiter_92 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, chosen : UInt<3>} io.chosen := UInt<1>("h00") io.out.bits.idx := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") io.in[4].ready := UInt<1>("h00") wire T_128 : UInt<3> T_128 := UInt<1>("h00") infer accessor T_130 = io.in[T_128] io.out.valid := T_130.valid infer accessor T_137 = io.in[T_128] io.out.bits <> T_137.bits io.chosen := T_128 infer accessor T_144 = io.in[T_128] T_144.ready := UInt<1>("h00") node T_154 = or(UInt<1>("h00"), io.in[0].valid) node T_156 = eq(T_154, UInt<1>("h00")) node T_158 = or(UInt<1>("h00"), io.in[0].valid) node T_159 = or(T_158, io.in[1].valid) node T_161 = eq(T_159, UInt<1>("h00")) node T_163 = or(UInt<1>("h00"), io.in[0].valid) node T_164 = or(T_163, io.in[1].valid) node T_165 = or(T_164, io.in[2].valid) node T_167 = eq(T_165, UInt<1>("h00")) node T_169 = or(UInt<1>("h00"), io.in[0].valid) node T_170 = or(T_169, io.in[1].valid) node T_171 = or(T_170, io.in[2].valid) node T_172 = or(T_171, io.in[3].valid) node T_174 = eq(T_172, UInt<1>("h00")) node T_176 = eq(UInt<3>("h04"), UInt<1>("h00")) node T_177 = mux(UInt<1>("h00"), T_176, UInt<1>("h01")) node T_178 = and(T_177, io.out.ready) io.in[0].ready := T_178 node T_180 = eq(UInt<3>("h04"), UInt<1>("h01")) node T_181 = mux(UInt<1>("h00"), T_180, T_156) node T_182 = and(T_181, io.out.ready) io.in[1].ready := T_182 node T_184 = eq(UInt<3>("h04"), UInt<2>("h02")) node T_185 = mux(UInt<1>("h00"), T_184, T_161) node T_186 = and(T_185, io.out.ready) io.in[2].ready := T_186 node T_188 = eq(UInt<3>("h04"), UInt<2>("h03")) node T_189 = mux(UInt<1>("h00"), T_188, T_167) node T_190 = and(T_189, io.out.ready) io.in[3].ready := T_190 node T_192 = eq(UInt<3>("h04"), UInt<3>("h04")) node T_193 = mux(UInt<1>("h00"), T_192, T_174) node T_194 = and(T_193, io.out.ready) io.in[4].ready := T_194 node T_197 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) node T_199 = mux(io.in[2].valid, UInt<2>("h02"), T_197) node T_201 = mux(io.in[1].valid, UInt<1>("h01"), T_199) node T_203 = mux(io.in[0].valid, UInt<1>("h00"), T_201) node T_204 = mux(UInt<1>("h00"), UInt<3>("h04"), T_203) T_128 := T_204 module DataArray : input clock : Clock input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]} io.resp[0] := UInt<1>("h00") io.resp[1] := UInt<1>("h00") io.resp[2] := UInt<1>("h00") io.resp[3] := UInt<1>("h00") io.write.ready := UInt<1>("h00") io.read.ready := UInt<1>("h00") node waddr = shr(io.write.bits.addr, 4) node raddr = shr(io.read.bits.addr, 4) node T_66 = bits(io.write.bits.way_en, 1, 0) node T_67 = bits(io.read.bits.way_en, 1, 0) wire T_76 : UInt<128>[2] T_76[0] := UInt<1>("h00") T_76[1] := UInt<1>("h00") reg T_82 : UInt<12>, clock, reset when io.read.valid : T_82 := io.read.bits.addr skip smem T_95 : UInt<64>[2][256], clock node T_97 = neq(T_66, UInt<1>("h00")) node T_98 = and(T_97, io.write.valid) node T_99 = bit(io.write.bits.wmask, 0) node T_100 = and(T_98, T_99) when T_100 : node T_101 = bits(io.write.bits.data, 63, 0) node T_102 = bits(io.write.bits.data, 63, 0) wire T_104 : UInt<64>[2] T_104[0] := T_101 T_104[1] := T_102 node T_108 = bit(T_66, 0) node T_109 = bit(T_66, 1) wire T_111 : UInt<1>[2] T_111[0] := T_108 T_111[1] := T_109 infer accessor T_117 = T_95[waddr] when T_111[0] : T_117[0] := T_104[0] skip when T_111[1] : T_117[1] := T_104[1] skip skip node T_122 = neq(T_67, UInt<1>("h00")) node T_123 = and(T_122, io.read.valid) poison T_124 : UInt<8> node T_125 = mux(T_123, raddr, T_124) infer accessor T_128 = T_95[T_125] node T_132 = cat(T_128[1], T_128[0]) T_76[0] := T_132 smem T_145 : UInt<64>[2][256], clock node T_147 = neq(T_66, UInt<1>("h00")) node T_148 = and(T_147, io.write.valid) node T_149 = bit(io.write.bits.wmask, 1) node T_150 = and(T_148, T_149) when T_150 : node T_151 = bits(io.write.bits.data, 127, 64) node T_152 = bits(io.write.bits.data, 127, 64) wire T_154 : UInt<64>[2] T_154[0] := T_151 T_154[1] := T_152 node T_158 = bit(T_66, 0) node T_159 = bit(T_66, 1) wire T_161 : UInt<1>[2] T_161[0] := T_158 T_161[1] := T_159 infer accessor T_167 = T_145[waddr] when T_161[0] : T_167[0] := T_154[0] skip when T_161[1] : T_167[1] := T_154[1] skip skip node T_172 = neq(T_67, UInt<1>("h00")) node T_173 = and(T_172, io.read.valid) poison T_174 : UInt<8> node T_175 = mux(T_173, raddr, T_174) infer accessor T_178 = T_145[T_175] node T_182 = cat(T_178[1], T_178[0]) T_76[1] := T_182 node T_183 = bits(T_76[0], 63, 0) node T_184 = bits(T_76[1], 63, 0) wire T_186 : UInt<64>[2] T_186[0] := T_183 T_186[1] := T_184 node T_190 = bits(T_82, 3, 3) infer accessor T_191 = T_186[T_190] wire T_193 : UInt<64>[2] T_193[0] := T_191 T_193[1] := T_186[1] node T_197 = cat(T_193[1], T_193[0]) io.resp[0] := T_197 node T_198 = bits(T_76[0], 127, 64) node T_199 = bits(T_76[1], 127, 64) wire T_201 : UInt<64>[2] T_201[0] := T_198 T_201[1] := T_199 node T_205 = bits(T_82, 3, 3) infer accessor T_206 = T_201[T_205] wire T_208 : UInt<64>[2] T_208[0] := T_206 T_208[1] := T_201[1] node T_212 = cat(T_208[1], T_208[0]) io.resp[1] := T_212 node T_213 = bits(io.write.bits.way_en, 3, 2) node T_214 = bits(io.read.bits.way_en, 3, 2) wire T_223 : UInt<128>[2] T_223[0] := UInt<1>("h00") T_223[1] := UInt<1>("h00") reg T_229 : UInt<12>, clock, reset when io.read.valid : T_229 := io.read.bits.addr skip smem T_242 : UInt<64>[2][256], clock node T_244 = neq(T_213, UInt<1>("h00")) node T_245 = and(T_244, io.write.valid) node T_246 = bit(io.write.bits.wmask, 0) node T_247 = and(T_245, T_246) when T_247 : node T_248 = bits(io.write.bits.data, 63, 0) node T_249 = bits(io.write.bits.data, 63, 0) wire T_251 : UInt<64>[2] T_251[0] := T_248 T_251[1] := T_249 node T_255 = bit(T_213, 0) node T_256 = bit(T_213, 1) wire T_258 : UInt<1>[2] T_258[0] := T_255 T_258[1] := T_256 infer accessor T_264 = T_242[waddr] when T_258[0] : T_264[0] := T_251[0] skip when T_258[1] : T_264[1] := T_251[1] skip skip node T_269 = neq(T_214, UInt<1>("h00")) node T_270 = and(T_269, io.read.valid) poison T_271 : UInt<8> node T_272 = mux(T_270, raddr, T_271) infer accessor T_275 = T_242[T_272] node T_279 = cat(T_275[1], T_275[0]) T_223[0] := T_279 smem T_292 : UInt<64>[2][256], clock node T_294 = neq(T_213, UInt<1>("h00")) node T_295 = and(T_294, io.write.valid) node T_296 = bit(io.write.bits.wmask, 1) node T_297 = and(T_295, T_296) when T_297 : node T_298 = bits(io.write.bits.data, 127, 64) node T_299 = bits(io.write.bits.data, 127, 64) wire T_301 : UInt<64>[2] T_301[0] := T_298 T_301[1] := T_299 node T_305 = bit(T_213, 0) node T_306 = bit(T_213, 1) wire T_308 : UInt<1>[2] T_308[0] := T_305 T_308[1] := T_306 infer accessor T_314 = T_292[waddr] when T_308[0] : T_314[0] := T_301[0] skip when T_308[1] : T_314[1] := T_301[1] skip skip node T_319 = neq(T_214, UInt<1>("h00")) node T_320 = and(T_319, io.read.valid) poison T_321 : UInt<8> node T_322 = mux(T_320, raddr, T_321) infer accessor T_325 = T_292[T_322] node T_329 = cat(T_325[1], T_325[0]) T_223[1] := T_329 node T_330 = bits(T_223[0], 63, 0) node T_331 = bits(T_223[1], 63, 0) wire T_333 : UInt<64>[2] T_333[0] := T_330 T_333[1] := T_331 node T_337 = bits(T_229, 3, 3) infer accessor T_338 = T_333[T_337] wire T_340 : UInt<64>[2] T_340[0] := T_338 T_340[1] := T_333[1] node T_344 = cat(T_340[1], T_340[0]) io.resp[2] := T_344 node T_345 = bits(T_223[0], 127, 64) node T_346 = bits(T_223[1], 127, 64) wire T_348 : UInt<64>[2] T_348[0] := T_345 T_348[1] := T_346 node T_352 = bits(T_229, 3, 3) infer accessor T_353 = T_348[T_352] wire T_355 : UInt<64>[2] T_355[0] := T_353 T_355[1] := T_348[1] node T_359 = cat(T_355[1], T_355[0]) io.resp[3] := T_359 io.read.ready := UInt<1>("h01") io.write.ready := UInt<1>("h01") module Arbiter_94 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>} io.chosen := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.bits.way_en := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") io.in[2].ready := UInt<1>("h00") io.in[3].ready := UInt<1>("h00") wire T_144 : UInt<2> T_144 := UInt<1>("h00") infer accessor T_146 = io.in[T_144] io.out.valid := T_146.valid infer accessor T_155 = io.in[T_144] io.out.bits <> T_155.bits io.chosen := T_144 infer accessor T_164 = io.in[T_144] T_164.ready := UInt<1>("h00") node T_176 = or(UInt<1>("h00"), io.in[0].valid) node T_178 = eq(T_176, UInt<1>("h00")) node T_180 = or(UInt<1>("h00"), io.in[0].valid) node T_181 = or(T_180, io.in[1].valid) node T_183 = eq(T_181, UInt<1>("h00")) node T_185 = or(UInt<1>("h00"), io.in[0].valid) node T_186 = or(T_185, io.in[1].valid) node T_187 = or(T_186, io.in[2].valid) node T_189 = eq(T_187, UInt<1>("h00")) node T_191 = eq(UInt<2>("h03"), UInt<1>("h00")) node T_192 = mux(UInt<1>("h00"), T_191, UInt<1>("h01")) node T_193 = and(T_192, io.out.ready) io.in[0].ready := T_193 node T_195 = eq(UInt<2>("h03"), UInt<1>("h01")) node T_196 = mux(UInt<1>("h00"), T_195, T_178) node T_197 = and(T_196, io.out.ready) io.in[1].ready := T_197 node T_199 = eq(UInt<2>("h03"), UInt<2>("h02")) node T_200 = mux(UInt<1>("h00"), T_199, T_183) node T_201 = and(T_200, io.out.ready) io.in[2].ready := T_201 node T_203 = eq(UInt<2>("h03"), UInt<2>("h03")) node T_204 = mux(UInt<1>("h00"), T_203, T_189) node T_205 = and(T_204, io.out.ready) io.in[3].ready := T_205 node T_208 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) node T_210 = mux(io.in[1].valid, UInt<1>("h01"), T_208) node T_212 = mux(io.in[0].valid, UInt<1>("h00"), T_210) node T_213 = mux(UInt<1>("h00"), UInt<2>("h03"), T_212) T_144 := T_213 module Arbiter_95 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.wmask := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.bits.way_en := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_152 : UInt<1> T_152 := UInt<1>("h00") infer accessor T_154 = io.in[T_152] io.out.valid := T_154.valid infer accessor T_167 = io.in[T_152] io.out.bits <> T_167.bits io.chosen := T_152 infer accessor T_180 = io.in[T_152] T_180.ready := UInt<1>("h00") node T_196 = or(UInt<1>("h00"), io.in[0].valid) node T_198 = eq(T_196, UInt<1>("h00")) node T_200 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_201 = mux(UInt<1>("h00"), T_200, UInt<1>("h01")) node T_202 = and(T_201, io.out.ready) io.in[0].ready := T_202 node T_204 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_205 = mux(UInt<1>("h00"), T_204, T_198) node T_206 = and(T_205, io.out.ready) io.in[1].ready := T_206 node T_209 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_210 = mux(UInt<1>("h00"), UInt<1>("h01"), T_209) T_152 := T_210 module AMOALU : input clock : Clock input reset : UInt<1> output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} io.out := UInt<1>("h00") node T_10 = eq(io.typ, UInt<3>("h00")) node T_11 = eq(io.typ, UInt<3>("h04")) node T_12 = or(T_10, T_11) node T_13 = eq(io.typ, UInt<3>("h01")) node T_14 = eq(io.typ, UInt<3>("h05")) node T_15 = or(T_13, T_14) node T_16 = eq(io.typ, UInt<3>("h02")) node T_17 = eq(io.typ, UInt<3>("h06")) node T_18 = or(T_16, T_17) node T_19 = bits(io.rhs, 31, 0) node T_20 = cat(T_19, T_19) node rhs = mux(T_18, T_20, io.rhs) node T_22 = eq(io.cmd, UInt<5>("h0c")) node T_23 = eq(io.cmd, UInt<5>("h0d")) node sgned = or(T_22, T_23) node T_25 = eq(io.cmd, UInt<5>("h0d")) node T_26 = eq(io.cmd, UInt<5>("h0f")) node max = or(T_25, T_26) node T_28 = eq(io.cmd, UInt<5>("h0c")) node T_29 = eq(io.cmd, UInt<5>("h0e")) node min = or(T_28, T_29) node T_31 = eq(io.typ, UInt<3>("h02")) node T_32 = eq(io.typ, UInt<3>("h06")) node T_33 = or(T_31, T_32) node T_34 = eq(io.typ, UInt<3>("h00")) node T_35 = or(T_33, T_34) node T_36 = eq(io.typ, UInt<3>("h04")) node word = or(T_35, T_36) node T_39 = not(UInt<64>("h00")) node T_40 = bit(io.addr, 2) node T_41 = shl(T_40, 31) node mask = xor(T_39, T_41) node T_43 = and(io.lhs, mask) node T_44 = and(rhs, mask) node adder_out = addw(T_43, T_44) node T_46 = bit(io.addr, 2) node T_48 = eq(T_46, UInt<1>("h00")) node T_49 = and(word, T_48) node T_50 = bit(io.lhs, 31) node T_51 = bit(io.lhs, 63) node cmp_lhs = mux(T_49, T_50, T_51) node T_53 = bit(io.addr, 2) node T_55 = eq(T_53, UInt<1>("h00")) node T_56 = and(word, T_55) node T_57 = bit(rhs, 31) node T_58 = bit(rhs, 63) node cmp_rhs = mux(T_56, T_57, T_58) node T_60 = bits(io.lhs, 31, 0) node T_61 = bits(rhs, 31, 0) node lt_lo = lt(T_60, T_61) node T_63 = bits(io.lhs, 63, 32) node T_64 = bits(rhs, 63, 32) node lt_hi = lt(T_63, T_64) node T_66 = bits(io.lhs, 63, 32) node T_67 = bits(rhs, 63, 32) node eq_hi = eq(T_66, T_67) node T_69 = bit(io.addr, 2) node T_70 = mux(T_69, lt_hi, lt_lo) node T_71 = and(eq_hi, lt_lo) node T_72 = or(lt_hi, T_71) node lt = mux(word, T_70, T_72) node T_74 = eq(cmp_lhs, cmp_rhs) node T_75 = mux(sgned, cmp_lhs, cmp_rhs) node less = mux(T_74, lt, T_75) node T_77 = eq(io.cmd, UInt<5>("h08")) node T_78 = eq(io.cmd, UInt<5>("h0b")) node T_79 = and(io.lhs, rhs) node T_80 = eq(io.cmd, UInt<5>("h0a")) node T_81 = or(io.lhs, rhs) node T_82 = eq(io.cmd, UInt<5>("h09")) node T_83 = xor(io.lhs, rhs) node T_84 = mux(less, min, max) node T_85 = bits(io.rhs, 7, 0) node T_86 = cat(T_85, T_85) node T_87 = cat(T_86, T_86) node T_88 = cat(T_87, T_87) node T_89 = bits(io.rhs, 15, 0) node T_90 = cat(T_89, T_89) node T_91 = cat(T_90, T_90) node T_92 = mux(T_15, T_91, rhs) node T_93 = mux(T_12, T_88, T_92) node T_94 = mux(T_84, io.lhs, T_93) node T_95 = mux(T_82, T_83, T_94) node T_96 = mux(T_80, T_81, T_95) node T_97 = mux(T_78, T_79, T_96) node out = mux(T_77, adder_out, T_97) node T_100 = bits(io.addr, 2, 0) node T_101 = dshl(UInt<1>("h01"), T_100) node T_103 = bits(io.addr, 2, 1) node T_105 = cat(T_103, UInt<1>("h00")) node T_106 = dshl(UInt<2>("h03"), T_105) node T_108 = bit(io.addr, 2) node T_110 = cat(T_108, UInt<2>("h00")) node T_111 = dshl(UInt<4>("h0f"), T_110) node T_113 = mux(T_18, T_111, UInt<8>("h0ff")) node T_114 = mux(T_15, T_106, T_113) node T_115 = mux(T_12, T_101, T_114) node T_116 = bit(T_115, 0) node T_117 = bit(T_115, 1) node T_118 = bit(T_115, 2) node T_119 = bit(T_115, 3) node T_120 = bit(T_115, 4) node T_121 = bit(T_115, 5) node T_122 = bit(T_115, 6) node T_123 = bit(T_115, 7) node T_124 = bit(T_115, 8) node T_125 = bit(T_115, 9) node T_126 = bit(T_115, 10) wire T_128 : UInt<1>[11] T_128[0] := T_116 T_128[1] := T_117 T_128[2] := T_118 T_128[3] := T_119 T_128[4] := T_120 T_128[5] := T_121 T_128[6] := T_122 T_128[7] := T_123 T_128[8] := T_124 T_128[9] := T_125 T_128[10] := T_126 node T_142 = subw(UInt<8>("h00"), T_128[0]) node T_144 = subw(UInt<8>("h00"), T_128[1]) node T_146 = subw(UInt<8>("h00"), T_128[2]) node T_148 = subw(UInt<8>("h00"), T_128[3]) node T_150 = subw(UInt<8>("h00"), T_128[4]) node T_152 = subw(UInt<8>("h00"), T_128[5]) node T_154 = subw(UInt<8>("h00"), T_128[6]) node T_156 = subw(UInt<8>("h00"), T_128[7]) node T_158 = subw(UInt<8>("h00"), T_128[8]) node T_160 = subw(UInt<8>("h00"), T_128[9]) node T_162 = subw(UInt<8>("h00"), T_128[10]) wire T_164 : UInt<8>[11] T_164[0] := T_142 T_164[1] := T_144 T_164[2] := T_146 T_164[3] := T_148 T_164[4] := T_150 T_164[5] := T_152 T_164[6] := T_154 T_164[7] := T_156 T_164[8] := T_158 T_164[9] := T_160 T_164[10] := T_162 node T_177 = cat(T_164[10], T_164[9]) node T_178 = cat(T_164[7], T_164[6]) node T_179 = cat(T_164[8], T_178) node T_180 = cat(T_177, T_179) node T_181 = cat(T_164[4], T_164[3]) node T_182 = cat(T_164[5], T_181) node T_183 = cat(T_164[1], T_164[0]) node T_184 = cat(T_164[2], T_183) node T_185 = cat(T_182, T_184) node wmask = cat(T_180, T_185) node T_187 = and(wmask, out) node T_188 = not(wmask) node T_189 = and(T_188, io.lhs) node T_190 = or(T_187, T_189) io.out := T_190 module LockingArbiter_96 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.voluntary := UInt<1>("h00") io.out.bits.r_type := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.bits.addr_beat := UInt<1>("h00") io.out.bits.client_xact_id := UInt<1>("h00") io.out.bits.addr_block := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") reg T_700 : UInt<1>, clock, reset onreset T_700 := UInt<1>("h00") reg T_702 : UInt, clock, reset onreset T_702 := UInt<1>("h01") wire T_704 : UInt<1> T_704 := UInt<1>("h00") infer accessor T_706 = io.in[T_704] io.out.valid := T_706.valid infer accessor T_769 = io.in[T_704] io.out.bits <> T_769.bits io.chosen := T_704 infer accessor T_832 = io.in[T_704] T_832.ready := UInt<1>("h00") node T_898 = or(UInt<1>("h00"), io.in[0].valid) node T_900 = eq(T_898, UInt<1>("h00")) node T_902 = eq(T_702, UInt<1>("h00")) node T_903 = mux(T_700, T_902, UInt<1>("h01")) node T_904 = and(T_903, io.out.ready) io.in[0].ready := T_904 node T_906 = eq(T_702, UInt<1>("h01")) node T_907 = mux(T_700, T_906, T_900) node T_908 = and(T_907, io.out.ready) io.in[1].ready := T_908 reg T_910 : UInt<2>, clock, reset onreset T_910 := UInt<2>("h00") node T_912 = addw(T_910, UInt<1>("h01")) node T_913 = and(io.out.ready, io.out.valid) when T_913 : wire T_916 : UInt<2>[3] T_916[0] := UInt<1>("h00") T_916[1] := UInt<1>("h01") T_916[2] := UInt<2>("h02") node T_921 = eq(T_916[0], io.out.bits.r_type) node T_922 = eq(T_916[1], io.out.bits.r_type) node T_923 = eq(T_916[2], io.out.bits.r_type) node T_925 = or(UInt<1>("h00"), T_921) node T_926 = or(T_925, T_922) node T_927 = or(T_926, T_923) node T_928 = and(UInt<1>("h01"), T_927) when T_928 : T_910 := T_912 node T_930 = eq(T_700, UInt<1>("h00")) when T_930 : T_700 := UInt<1>("h01") node T_932 = and(io.in[0].ready, io.in[0].valid) node T_933 = and(io.in[1].ready, io.in[1].valid) wire T_935 : UInt<1>[2] T_935[0] := T_932 T_935[1] := T_933 node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01")) T_702 := T_941 skip skip node T_943 = eq(T_912, UInt<1>("h00")) when T_943 : T_700 := UInt<1>("h00") skip skip node choose = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_948 = mux(T_700, T_702, choose) T_704 := T_948 module HellaCache : input clock : Clock input reset : UInt<1> output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} io.mem.release.bits.voluntary := UInt<1>("h00") io.mem.release.bits.r_type := UInt<1>("h00") io.mem.release.bits.data := UInt<1>("h00") io.mem.release.bits.addr_beat := UInt<1>("h00") io.mem.release.bits.client_xact_id := UInt<1>("h00") io.mem.release.bits.addr_block := UInt<1>("h00") io.mem.release.valid := UInt<1>("h00") io.mem.probe.ready := UInt<1>("h00") io.mem.grant.ready := UInt<1>("h00") io.mem.acquire.bits.union := UInt<1>("h00") io.mem.acquire.bits.a_type := UInt<1>("h00") io.mem.acquire.bits.is_builtin_type := UInt<1>("h00") io.mem.acquire.bits.data := UInt<1>("h00") io.mem.acquire.bits.addr_beat := UInt<1>("h00") io.mem.acquire.bits.client_xact_id := UInt<1>("h00") io.mem.acquire.bits.addr_block := UInt<1>("h00") io.mem.acquire.valid := UInt<1>("h00") io.ptw.req.bits.fetch := UInt<1>("h00") io.ptw.req.bits.store := UInt<1>("h00") io.ptw.req.bits.prv := UInt<1>("h00") io.ptw.req.bits.addr := UInt<1>("h00") io.ptw.req.valid := UInt<1>("h00") io.cpu.ordered := UInt<1>("h00") io.cpu.xcpt.pf.st := UInt<1>("h00") io.cpu.xcpt.pf.ld := UInt<1>("h00") io.cpu.xcpt.ma.st := UInt<1>("h00") io.cpu.xcpt.ma.ld := UInt<1>("h00") io.cpu.replay_next.bits := UInt<1>("h00") io.cpu.replay_next.valid := UInt<1>("h00") io.cpu.resp.bits.store_data := UInt<1>("h00") io.cpu.resp.bits.data_word_bypass := UInt<1>("h00") io.cpu.resp.bits.has_data := UInt<1>("h00") io.cpu.resp.bits.replay := UInt<1>("h00") io.cpu.resp.bits.nack := UInt<1>("h00") io.cpu.resp.bits.data := UInt<1>("h00") io.cpu.resp.bits.typ := UInt<1>("h00") io.cpu.resp.bits.cmd := UInt<1>("h00") io.cpu.resp.bits.tag := UInt<1>("h00") io.cpu.resp.bits.addr := UInt<1>("h00") io.cpu.resp.valid := UInt<1>("h00") io.cpu.req.ready := UInt<1>("h00") inst wb of WritebackUnit wb.io.release.ready := UInt<1>("h00") wb.io.data_resp := UInt<1>("h00") wb.io.data_req.ready := UInt<1>("h00") wb.io.meta_read.ready := UInt<1>("h00") wb.io.req.bits.way_en := UInt<1>("h00") wb.io.req.bits.voluntary := UInt<1>("h00") wb.io.req.bits.r_type := UInt<1>("h00") wb.io.req.bits.data := UInt<1>("h00") wb.io.req.bits.addr_beat := UInt<1>("h00") wb.io.req.bits.client_xact_id := UInt<1>("h00") wb.io.req.bits.addr_block := UInt<1>("h00") wb.io.req.valid := UInt<1>("h00") wb.clock := clock wb.reset := reset inst prober of ProbeUnit prober.io.block_state.state := UInt<1>("h00") prober.io.mshr_rdy := UInt<1>("h00") prober.io.way_en := UInt<1>("h00") prober.io.wb_req.ready := UInt<1>("h00") prober.io.meta_write.ready := UInt<1>("h00") prober.io.meta_read.ready := UInt<1>("h00") prober.io.rep.ready := UInt<1>("h00") prober.io.req.bits.client_xact_id := UInt<1>("h00") prober.io.req.bits.p_type := UInt<1>("h00") prober.io.req.bits.addr_block := UInt<1>("h00") prober.io.req.valid := UInt<1>("h00") prober.clock := clock prober.reset := reset inst mshrs of MSHRFile mshrs.io.wb_req.ready := UInt<1>("h00") mshrs.io.mem_grant.bits.g_type := UInt<1>("h00") mshrs.io.mem_grant.bits.is_builtin_type := UInt<1>("h00") mshrs.io.mem_grant.bits.manager_xact_id := UInt<1>("h00") mshrs.io.mem_grant.bits.client_xact_id := UInt<1>("h00") mshrs.io.mem_grant.bits.data := UInt<1>("h00") mshrs.io.mem_grant.bits.addr_beat := UInt<1>("h00") mshrs.io.mem_grant.valid := UInt<1>("h00") mshrs.io.replay.ready := UInt<1>("h00") mshrs.io.meta_write.ready := UInt<1>("h00") mshrs.io.meta_read.ready := UInt<1>("h00") mshrs.io.mem_req.ready := UInt<1>("h00") mshrs.io.resp.ready := UInt<1>("h00") mshrs.io.req.bits.way_en := UInt<1>("h00") mshrs.io.req.bits.old_meta.coh.state := UInt<1>("h00") mshrs.io.req.bits.old_meta.tag := UInt<1>("h00") mshrs.io.req.bits.tag_match := UInt<1>("h00") mshrs.io.req.bits.data := UInt<1>("h00") mshrs.io.req.bits.phys := UInt<1>("h00") mshrs.io.req.bits.kill := UInt<1>("h00") mshrs.io.req.bits.typ := UInt<1>("h00") mshrs.io.req.bits.cmd := UInt<1>("h00") mshrs.io.req.bits.tag := UInt<1>("h00") mshrs.io.req.bits.addr := UInt<1>("h00") mshrs.io.req.valid := UInt<1>("h00") mshrs.clock := clock mshrs.reset := reset io.cpu.req.ready := UInt<1>("h01") node T_888 = and(io.cpu.req.ready, io.cpu.req.valid) reg s1_valid : UInt<1>, clock, reset onreset s1_valid := UInt<1>("h00") s1_valid := T_888 reg s1_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset node T_900 = eq(io.cpu.req.bits.kill, UInt<1>("h00")) node s1_valid_masked = and(s1_valid, T_900) reg s1_replay : UInt<1>, clock, reset onreset s1_replay := UInt<1>("h00") reg s1_clk_en : UInt<1>, clock, reset reg s2_valid : UInt<1>, clock, reset onreset s2_valid := UInt<1>("h00") s2_valid := s1_valid_masked reg s2_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset reg T_917 : UInt<1>, clock, reset onreset T_917 := UInt<1>("h00") T_917 := s1_replay node T_918 = neq(s2_req.cmd, UInt<5>("h05")) node s2_replay = and(T_917, T_918) wire s2_recycle : UInt<1> s2_recycle := UInt<1>("h00") wire s2_valid_masked : UInt<1> s2_valid_masked := UInt<1>("h00") reg s3_valid : UInt<1>, clock, reset onreset s3_valid := UInt<1>("h00") reg s3_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset reg s3_way : UInt, clock, reset reg s1_recycled : UInt<1>, clock, reset onreset s1_recycled := UInt<1>("h00") when s1_clk_en : s1_recycled := s2_recycle skip node T_940 = eq(s1_req.cmd, UInt<5>("h00")) node T_941 = eq(s1_req.cmd, UInt<5>("h06")) node T_942 = or(T_940, T_941) node T_943 = eq(s1_req.cmd, UInt<5>("h07")) node T_944 = or(T_942, T_943) node T_945 = bit(s1_req.cmd, 3) node T_946 = eq(s1_req.cmd, UInt<5>("h04")) node T_947 = or(T_945, T_946) node s1_read = or(T_944, T_947) node T_949 = eq(s1_req.cmd, UInt<5>("h01")) node T_950 = eq(s1_req.cmd, UInt<5>("h07")) node T_951 = or(T_949, T_950) node T_952 = bit(s1_req.cmd, 3) node T_953 = eq(s1_req.cmd, UInt<5>("h04")) node T_954 = or(T_952, T_953) node s1_write = or(T_951, T_954) node T_956 = or(s1_read, s1_write) node T_957 = eq(s1_req.cmd, UInt<5>("h02")) node T_958 = eq(s1_req.cmd, UInt<5>("h03")) node T_959 = or(T_957, T_958) node s1_readwrite = or(T_956, T_959) inst dtlb of TLB_90 dtlb.io.ptw.invalidate := UInt<1>("h00") dtlb.io.ptw.status.ie := UInt<1>("h00") dtlb.io.ptw.status.prv := UInt<1>("h00") dtlb.io.ptw.status.ie1 := UInt<1>("h00") dtlb.io.ptw.status.prv1 := UInt<1>("h00") dtlb.io.ptw.status.ie2 := UInt<1>("h00") dtlb.io.ptw.status.prv2 := UInt<1>("h00") dtlb.io.ptw.status.ie3 := UInt<1>("h00") dtlb.io.ptw.status.prv3 := UInt<1>("h00") dtlb.io.ptw.status.fs := UInt<1>("h00") dtlb.io.ptw.status.xs := UInt<1>("h00") dtlb.io.ptw.status.mprv := UInt<1>("h00") dtlb.io.ptw.status.vm := UInt<1>("h00") dtlb.io.ptw.status.zero1 := UInt<1>("h00") dtlb.io.ptw.status.sd_rv32 := UInt<1>("h00") dtlb.io.ptw.status.zero2 := UInt<1>("h00") dtlb.io.ptw.status.sd := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.v := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.typ := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.r := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.d := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.ppn := UInt<1>("h00") dtlb.io.ptw.resp.bits.error := UInt<1>("h00") dtlb.io.ptw.resp.valid := UInt<1>("h00") dtlb.io.ptw.req.ready := UInt<1>("h00") dtlb.io.req.bits.store := UInt<1>("h00") dtlb.io.req.bits.instruction := UInt<1>("h00") dtlb.io.req.bits.passthrough := UInt<1>("h00") dtlb.io.req.bits.vpn := UInt<1>("h00") dtlb.io.req.bits.asid := UInt<1>("h00") dtlb.io.req.valid := UInt<1>("h00") dtlb.clock := clock dtlb.reset := reset io.ptw <> dtlb.io.ptw node T_994 = and(s1_valid_masked, s1_readwrite) node T_996 = eq(s1_req.phys, UInt<1>("h00")) node T_997 = and(T_994, T_996) dtlb.io.req.valid := T_997 dtlb.io.req.bits.passthrough := s1_req.phys dtlb.io.req.bits.asid := UInt<1>("h00") node T_999 = shr(s1_req.addr, 12) dtlb.io.req.bits.vpn := T_999 dtlb.io.req.bits.instruction := UInt<1>("h00") dtlb.io.req.bits.store := s1_write node T_1002 = eq(dtlb.io.req.ready, UInt<1>("h00")) node T_1004 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) node T_1005 = and(T_1002, T_1004) when T_1005 : io.cpu.req.ready := UInt<1>("h00") skip when io.cpu.req.valid : s1_req <> io.cpu.req.bits skip when wb.io.meta_read.valid : node T_1007 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) node T_1008 = shl(T_1007, 6) s1_req.addr := T_1008 s1_req.phys := UInt<1>("h01") skip when prober.io.meta_read.valid : node T_1010 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) node T_1011 = shl(T_1010, 6) s1_req.addr := T_1011 s1_req.phys := UInt<1>("h01") skip when mshrs.io.replay.valid : s1_req <> mshrs.io.replay.bits skip when s2_recycle : s1_req <> s2_req skip node T_1013 = bits(s1_req.addr, 11, 0) node s1_addr = cat(dtlb.io.resp.ppn, T_1013) when s1_clk_en : s2_req.kill := s1_req.kill s2_req.typ := s1_req.typ s2_req.phys := s1_req.phys s2_req.addr := s1_addr when s1_write : node T_1015 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) s2_req.data := T_1015 skip when s1_recycled : s2_req.data := s1_req.data skip s2_req.tag := s1_req.tag s2_req.cmd := s1_req.cmd skip node T_1016 = eq(s1_req.typ, UInt<3>("h01")) node T_1017 = eq(s1_req.typ, UInt<3>("h05")) node T_1018 = or(T_1016, T_1017) node T_1019 = bit(s1_req.addr, 0) node T_1021 = neq(T_1019, UInt<1>("h00")) node T_1022 = and(T_1018, T_1021) node T_1023 = eq(s1_req.typ, UInt<3>("h02")) node T_1024 = eq(s1_req.typ, UInt<3>("h06")) node T_1025 = or(T_1023, T_1024) node T_1026 = bits(s1_req.addr, 1, 0) node T_1028 = neq(T_1026, UInt<1>("h00")) node T_1029 = and(T_1025, T_1028) node T_1030 = or(T_1022, T_1029) node T_1031 = eq(s1_req.typ, UInt<3>("h03")) node T_1032 = bits(s1_req.addr, 2, 0) node T_1034 = neq(T_1032, UInt<1>("h00")) node T_1035 = and(T_1031, T_1034) node misaligned = or(T_1030, T_1035) node T_1037 = and(s1_read, misaligned) io.cpu.xcpt.ma.ld := T_1037 node T_1038 = and(s1_write, misaligned) io.cpu.xcpt.ma.st := T_1038 node T_1039 = and(s1_read, dtlb.io.resp.xcpt_ld) io.cpu.xcpt.pf.ld := T_1039 node T_1040 = and(s1_write, dtlb.io.resp.xcpt_st) io.cpu.xcpt.pf.st := T_1040 node T_1041 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) node T_1042 = or(T_1041, io.cpu.xcpt.pf.ld) node T_1043 = or(T_1042, io.cpu.xcpt.pf.st) reg T_1044 : UInt<1>, clock, reset T_1044 := T_1043 node T_1045 = and(T_1044, io.cpu.resp.valid) node T_1047 = eq(T_1045, UInt<1>("h00")) inst meta of MetadataArray meta.io.write.bits.data.coh.state := UInt<1>("h00") meta.io.write.bits.data.tag := UInt<1>("h00") meta.io.write.bits.way_en := UInt<1>("h00") meta.io.write.bits.idx := UInt<1>("h00") meta.io.write.valid := UInt<1>("h00") meta.io.read.bits.idx := UInt<1>("h00") meta.io.read.valid := UInt<1>("h00") meta.clock := clock meta.reset := reset inst metaReadArb of Arbiter_92 metaReadArb.io.out.ready := UInt<1>("h00") metaReadArb.io.in[0].bits.idx := UInt<1>("h00") metaReadArb.io.in[0].valid := UInt<1>("h00") metaReadArb.io.in[1].bits.idx := UInt<1>("h00") metaReadArb.io.in[1].valid := UInt<1>("h00") metaReadArb.io.in[2].bits.idx := UInt<1>("h00") metaReadArb.io.in[2].valid := UInt<1>("h00") metaReadArb.io.in[3].bits.idx := UInt<1>("h00") metaReadArb.io.in[3].valid := UInt<1>("h00") metaReadArb.io.in[4].bits.idx := UInt<1>("h00") metaReadArb.io.in[4].valid := UInt<1>("h00") metaReadArb.clock := clock metaReadArb.reset := reset inst metaWriteArb of Arbiter_81 metaWriteArb.io.out.ready := UInt<1>("h00") metaWriteArb.io.in[0].bits.data.coh.state := UInt<1>("h00") metaWriteArb.io.in[0].bits.data.tag := UInt<1>("h00") metaWriteArb.io.in[0].bits.way_en := UInt<1>("h00") metaWriteArb.io.in[0].bits.idx := UInt<1>("h00") metaWriteArb.io.in[0].valid := UInt<1>("h00") metaWriteArb.io.in[1].bits.data.coh.state := UInt<1>("h00") metaWriteArb.io.in[1].bits.data.tag := UInt<1>("h00") metaWriteArb.io.in[1].bits.way_en := UInt<1>("h00") metaWriteArb.io.in[1].bits.idx := UInt<1>("h00") metaWriteArb.io.in[1].valid := UInt<1>("h00") metaWriteArb.clock := clock metaWriteArb.reset := reset meta.io.read <> metaReadArb.io.out meta.io.write <> metaWriteArb.io.out inst data of DataArray data.io.write.bits.data := UInt<1>("h00") data.io.write.bits.wmask := UInt<1>("h00") data.io.write.bits.addr := UInt<1>("h00") data.io.write.bits.way_en := UInt<1>("h00") data.io.write.valid := UInt<1>("h00") data.io.read.bits.addr := UInt<1>("h00") data.io.read.bits.way_en := UInt<1>("h00") data.io.read.valid := UInt<1>("h00") data.clock := clock data.reset := reset inst readArb of Arbiter_94 readArb.io.out.ready := UInt<1>("h00") readArb.io.in[0].bits.addr := UInt<1>("h00") readArb.io.in[0].bits.way_en := UInt<1>("h00") readArb.io.in[0].valid := UInt<1>("h00") readArb.io.in[1].bits.addr := UInt<1>("h00") readArb.io.in[1].bits.way_en := UInt<1>("h00") readArb.io.in[1].valid := UInt<1>("h00") readArb.io.in[2].bits.addr := UInt<1>("h00") readArb.io.in[2].bits.way_en := UInt<1>("h00") readArb.io.in[2].valid := UInt<1>("h00") readArb.io.in[3].bits.addr := UInt<1>("h00") readArb.io.in[3].bits.way_en := UInt<1>("h00") readArb.io.in[3].valid := UInt<1>("h00") readArb.clock := clock readArb.reset := reset inst writeArb of Arbiter_95 writeArb.io.out.ready := UInt<1>("h00") writeArb.io.in[0].bits.data := UInt<1>("h00") writeArb.io.in[0].bits.wmask := UInt<1>("h00") writeArb.io.in[0].bits.addr := UInt<1>("h00") writeArb.io.in[0].bits.way_en := UInt<1>("h00") writeArb.io.in[0].valid := UInt<1>("h00") writeArb.io.in[1].bits.data := UInt<1>("h00") writeArb.io.in[1].bits.wmask := UInt<1>("h00") writeArb.io.in[1].bits.addr := UInt<1>("h00") writeArb.io.in[1].bits.way_en := UInt<1>("h00") writeArb.io.in[1].valid := UInt<1>("h00") writeArb.clock := clock writeArb.reset := reset data.io.write.valid := writeArb.io.out.valid writeArb.io.out.ready := data.io.write.ready data.io.write.bits <> writeArb.io.out.bits node T_1182 = bits(writeArb.io.out.bits.data, 63, 0) node T_1183 = bits(writeArb.io.out.bits.data, 127, 64) wire T_1185 : UInt<64>[2] T_1185[0] := T_1182 T_1185[1] := T_1183 node T_1189 = cat(T_1185[1], T_1185[0]) data.io.write.bits.data := T_1189 metaReadArb.io.in[4].valid := io.cpu.req.valid node T_1190 = shr(io.cpu.req.bits.addr, 6) metaReadArb.io.in[4].bits.idx := T_1190 node T_1192 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00")) when T_1192 : io.cpu.req.ready := UInt<1>("h00") skip readArb.io.in[3].valid := io.cpu.req.valid readArb.io.in[3].bits.addr := io.cpu.req.bits.addr node T_1195 = not(UInt<4>("h00")) readArb.io.in[3].bits.way_en := T_1195 node T_1197 = eq(readArb.io.in[3].ready, UInt<1>("h00")) when T_1197 : io.cpu.req.ready := UInt<1>("h00") skip metaReadArb.io.in[0].valid := s2_recycle node T_1199 = shr(s2_req.addr, 6) metaReadArb.io.in[0].bits.idx := T_1199 readArb.io.in[0].valid := s2_recycle readArb.io.in[0].bits.addr := s2_req.addr node T_1201 = not(UInt<4>("h00")) readArb.io.in[0].bits.way_en := T_1201 node T_1202 = shr(s1_addr, 12) node T_1203 = eq(meta.io.resp[0].tag, T_1202) node T_1204 = shr(s1_addr, 12) node T_1205 = eq(meta.io.resp[1].tag, T_1204) node T_1206 = shr(s1_addr, 12) node T_1207 = eq(meta.io.resp[2].tag, T_1206) node T_1208 = shr(s1_addr, 12) node T_1209 = eq(meta.io.resp[3].tag, T_1208) wire T_1211 : UInt<1>[4] T_1211[0] := T_1203 T_1211[1] := T_1205 T_1211[2] := T_1207 T_1211[3] := T_1209 node T_1217 = cat(T_1211[3], T_1211[2]) node T_1218 = cat(T_1211[1], T_1211[0]) node s1_tag_eq_way = cat(T_1217, T_1218) node T_1220 = bit(s1_tag_eq_way, 0) node T_1221 = neq(meta.io.resp[0].coh.state, UInt<1>("h00")) node T_1222 = and(T_1220, T_1221) node T_1223 = bit(s1_tag_eq_way, 1) node T_1224 = neq(meta.io.resp[1].coh.state, UInt<1>("h00")) node T_1225 = and(T_1223, T_1224) node T_1226 = bit(s1_tag_eq_way, 2) node T_1227 = neq(meta.io.resp[2].coh.state, UInt<1>("h00")) node T_1228 = and(T_1226, T_1227) node T_1229 = bit(s1_tag_eq_way, 3) node T_1230 = neq(meta.io.resp[3].coh.state, UInt<1>("h00")) node T_1231 = and(T_1229, T_1230) wire T_1233 : UInt<1>[4] T_1233[0] := T_1222 T_1233[1] := T_1225 T_1233[2] := T_1228 T_1233[3] := T_1231 node T_1239 = cat(T_1233[3], T_1233[2]) node T_1240 = cat(T_1233[1], T_1233[0]) node s1_tag_match_way = cat(T_1239, T_1240) s1_clk_en := metaReadArb.io.out.valid node T_1243 = eq(s1_valid, UInt<1>("h00")) node T_1244 = and(s1_clk_en, T_1243) node T_1246 = eq(s1_replay, UInt<1>("h00")) node s1_writeback = and(T_1244, T_1246) reg s2_tag_match_way : UInt<4>, clock, reset when s1_clk_en : s2_tag_match_way := s1_tag_match_way skip node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) reg T_1251 : {state : UInt<2>}, clock, reset when s1_clk_en : T_1251 <> meta.io.resp[0].coh skip reg T_1276 : {state : UInt<2>}, clock, reset when s1_clk_en : T_1276 <> meta.io.resp[1].coh skip reg T_1301 : {state : UInt<2>}, clock, reset when s1_clk_en : T_1301 <> meta.io.resp[2].coh skip reg T_1326 : {state : UInt<2>}, clock, reset when s1_clk_en : T_1326 <> meta.io.resp[3].coh skip wire T_1376 : {state : UInt<2>}[4] T_1376[0] <> T_1251 T_1376[1] <> T_1276 T_1376[2] <> T_1301 T_1376[3] <> T_1326 node T_1502 = bit(s2_tag_match_way, 0) node T_1503 = bit(s2_tag_match_way, 1) node T_1504 = bit(s2_tag_match_way, 2) node T_1505 = bit(s2_tag_match_way, 3) node T_1507 = mux(T_1502, T_1376[0].state, UInt<1>("h00")) node T_1509 = mux(T_1503, T_1376[1].state, UInt<1>("h00")) node T_1511 = mux(T_1504, T_1376[2].state, UInt<1>("h00")) node T_1513 = mux(T_1505, T_1376[3].state, UInt<1>("h00")) node T_1539 = or(T_1507, T_1509) node T_1540 = or(T_1539, T_1511) node T_1541 = or(T_1540, T_1513) wire s2_hit_state : {state : UInt<2>} s2_hit_state.state := UInt<1>("h00") node T_1593 = bits(T_1541, 1, 0) s2_hit_state.state := T_1593 node T_1594 = eq(s2_req.cmd, UInt<5>("h01")) node T_1595 = eq(s2_req.cmd, UInt<5>("h07")) node T_1596 = or(T_1594, T_1595) node T_1597 = bit(s2_req.cmd, 3) node T_1598 = eq(s2_req.cmd, UInt<5>("h04")) node T_1599 = or(T_1597, T_1598) node T_1600 = or(T_1596, T_1599) node T_1601 = eq(s2_req.cmd, UInt<5>("h03")) node T_1602 = or(T_1600, T_1601) node T_1603 = eq(s2_req.cmd, UInt<5>("h06")) node T_1604 = or(T_1602, T_1603) wire T_1606 : UInt<2>[2] T_1606[0] := UInt<2>("h02") T_1606[1] := UInt<2>("h03") node T_1610 = eq(T_1606[0], s2_hit_state.state) node T_1611 = eq(T_1606[1], s2_hit_state.state) node T_1613 = or(UInt<1>("h00"), T_1610) node T_1614 = or(T_1613, T_1611) wire T_1616 : UInt<2>[3] T_1616[0] := UInt<1>("h01") T_1616[1] := UInt<2>("h02") T_1616[2] := UInt<2>("h03") node T_1621 = eq(T_1616[0], s2_hit_state.state) node T_1622 = eq(T_1616[1], s2_hit_state.state) node T_1623 = eq(T_1616[2], s2_hit_state.state) node T_1625 = or(UInt<1>("h00"), T_1621) node T_1626 = or(T_1625, T_1622) node T_1627 = or(T_1626, T_1623) node T_1628 = mux(T_1604, T_1614, T_1627) node T_1629 = and(s2_tag_match, T_1628) node T_1630 = eq(s2_req.cmd, UInt<5>("h01")) node T_1631 = eq(s2_req.cmd, UInt<5>("h07")) node T_1632 = or(T_1630, T_1631) node T_1633 = bit(s2_req.cmd, 3) node T_1634 = eq(s2_req.cmd, UInt<5>("h04")) node T_1635 = or(T_1633, T_1634) node T_1636 = or(T_1632, T_1635) node T_1637 = mux(T_1636, UInt<2>("h03"), s2_hit_state.state) wire T_1663 : {state : UInt<2>} T_1663.state := UInt<1>("h00") T_1663.state := T_1637 node T_1689 = eq(s2_hit_state.state, T_1663.state) node s2_hit = and(T_1629, T_1689) reg lrsc_count : UInt, clock, reset onreset lrsc_count := UInt<1>("h00") node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) reg lrsc_addr : UInt, clock, reset node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) node T_1699 = shr(s2_req.addr, 6) node T_1700 = eq(lrsc_addr, T_1699) node s2_lrsc_addr_match = and(lrsc_valid, T_1700) node T_1703 = eq(s2_lrsc_addr_match, UInt<1>("h00")) node s2_sc_fail = and(s2_sc, T_1703) when lrsc_valid : node T_1706 = subw(lrsc_count, UInt<1>("h01")) lrsc_count := T_1706 skip node T_1707 = and(s2_valid_masked, s2_hit) node T_1708 = or(T_1707, s2_replay) when T_1708 : when s2_lr : node T_1710 = eq(lrsc_valid, UInt<1>("h00")) when T_1710 : lrsc_count := UInt<5>("h01f") skip node T_1712 = shr(s2_req.addr, 6) lrsc_addr := T_1712 skip when s2_sc : lrsc_count := UInt<1>("h00") skip skip when io.cpu.invalidate_lr : lrsc_count := UInt<1>("h00") skip wire s2_data : UInt<128>[4] s2_data[0] := UInt<1>("h00") s2_data[1] := UInt<1>("h00") s2_data[2] := UInt<1>("h00") s2_data[3] := UInt<1>("h00") reg T_1743 : UInt<64>[2], clock, reset node T_1747 = bit(s1_tag_eq_way, 0) node T_1748 = and(s1_clk_en, T_1747) node T_1752 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1753 = or(UInt<1>("h01"), T_1752) node T_1754 = or(T_1753, s1_writeback) node T_1755 = and(T_1748, T_1754) when T_1755 : node T_1756 = shr(data.io.resp[0], 0) T_1743[0] := T_1756 skip node T_1760 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1761 = or(UInt<1>("h00"), T_1760) node T_1762 = or(T_1761, s1_writeback) node T_1763 = and(T_1748, T_1762) when T_1763 : node T_1764 = shr(data.io.resp[0], 64) T_1743[1] := T_1764 skip node T_1765 = cat(T_1743[1], T_1743[0]) s2_data[0] := T_1765 reg T_1774 : UInt<64>[2], clock, reset node T_1778 = bit(s1_tag_eq_way, 1) node T_1779 = and(s1_clk_en, T_1778) node T_1783 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1784 = or(UInt<1>("h01"), T_1783) node T_1785 = or(T_1784, s1_writeback) node T_1786 = and(T_1779, T_1785) when T_1786 : node T_1787 = shr(data.io.resp[1], 0) T_1774[0] := T_1787 skip node T_1791 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1792 = or(UInt<1>("h00"), T_1791) node T_1793 = or(T_1792, s1_writeback) node T_1794 = and(T_1779, T_1793) when T_1794 : node T_1795 = shr(data.io.resp[1], 64) T_1774[1] := T_1795 skip node T_1796 = cat(T_1774[1], T_1774[0]) s2_data[1] := T_1796 reg T_1805 : UInt<64>[2], clock, reset node T_1809 = bit(s1_tag_eq_way, 2) node T_1810 = and(s1_clk_en, T_1809) node T_1814 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1815 = or(UInt<1>("h01"), T_1814) node T_1816 = or(T_1815, s1_writeback) node T_1817 = and(T_1810, T_1816) when T_1817 : node T_1818 = shr(data.io.resp[2], 0) T_1805[0] := T_1818 skip node T_1822 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1823 = or(UInt<1>("h00"), T_1822) node T_1824 = or(T_1823, s1_writeback) node T_1825 = and(T_1810, T_1824) when T_1825 : node T_1826 = shr(data.io.resp[2], 64) T_1805[1] := T_1826 skip node T_1827 = cat(T_1805[1], T_1805[0]) s2_data[2] := T_1827 reg T_1836 : UInt<64>[2], clock, reset node T_1840 = bit(s1_tag_eq_way, 3) node T_1841 = and(s1_clk_en, T_1840) node T_1845 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1846 = or(UInt<1>("h01"), T_1845) node T_1847 = or(T_1846, s1_writeback) node T_1848 = and(T_1841, T_1847) when T_1848 : node T_1849 = shr(data.io.resp[3], 0) T_1836[0] := T_1849 skip node T_1853 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1854 = or(UInt<1>("h00"), T_1853) node T_1855 = or(T_1854, s1_writeback) node T_1856 = and(T_1841, T_1855) when T_1856 : node T_1857 = shr(data.io.resp[3], 64) T_1836[1] := T_1857 skip node T_1858 = cat(T_1836[1], T_1836[0]) s2_data[3] := T_1858 node T_1859 = bit(s2_tag_match_way, 0) node T_1860 = bit(s2_tag_match_way, 1) node T_1861 = bit(s2_tag_match_way, 2) node T_1862 = bit(s2_tag_match_way, 3) node T_1864 = mux(T_1859, s2_data[0], UInt<1>("h00")) node T_1866 = mux(T_1860, s2_data[1], UInt<1>("h00")) node T_1868 = mux(T_1861, s2_data[2], UInt<1>("h00")) node T_1870 = mux(T_1862, s2_data[3], UInt<1>("h00")) node T_1872 = or(T_1864, T_1866) node T_1873 = or(T_1872, T_1868) node T_1874 = or(T_1873, T_1870) wire s2_data_muxed : UInt<128> s2_data_muxed := UInt<1>("h00") s2_data_muxed := T_1874 node T_1877 = bits(s2_data_muxed, 63, 0) node T_1878 = bits(s2_data_muxed, 127, 64) wire T_1880 : UInt<64>[2] T_1880[0] := T_1877 T_1880[1] := T_1878 node s2_data_corrected = cat(T_1880[1], T_1880[0]) wire T_1886 : UInt<64>[2] T_1886[0] := T_1877 T_1886[1] := T_1878 node s2_data_uncorrected = cat(T_1886[1], T_1886[0]) wire T_1895 : UInt<1>[2] T_1895[0] := UInt<1>("h00") T_1895[1] := UInt<1>("h00") node T_1899 = cat(T_1895[1], T_1895[0]) node T_1900 = dshr(T_1899, UInt<1>("h00")) node s2_data_correctable = bit(T_1900, 0) node T_1902 = and(s2_valid_masked, s2_hit) node T_1903 = or(T_1902, s2_replay) node T_1905 = eq(s2_sc_fail, UInt<1>("h00")) node T_1906 = and(T_1903, T_1905) node T_1907 = eq(s2_req.cmd, UInt<5>("h01")) node T_1908 = eq(s2_req.cmd, UInt<5>("h07")) node T_1909 = or(T_1907, T_1908) node T_1910 = bit(s2_req.cmd, 3) node T_1911 = eq(s2_req.cmd, UInt<5>("h04")) node T_1912 = or(T_1910, T_1911) node T_1913 = or(T_1909, T_1912) node T_1914 = and(T_1906, T_1913) s3_valid := T_1914 inst amoalu of AMOALU amoalu.io.rhs := UInt<1>("h00") amoalu.io.lhs := UInt<1>("h00") amoalu.io.typ := UInt<1>("h00") amoalu.io.cmd := UInt<1>("h00") amoalu.io.addr := UInt<1>("h00") amoalu.clock := clock amoalu.reset := reset node T_1921 = or(s2_valid, s2_replay) node T_1922 = eq(s2_req.cmd, UInt<5>("h01")) node T_1923 = eq(s2_req.cmd, UInt<5>("h07")) node T_1924 = or(T_1922, T_1923) node T_1925 = bit(s2_req.cmd, 3) node T_1926 = eq(s2_req.cmd, UInt<5>("h04")) node T_1927 = or(T_1925, T_1926) node T_1928 = or(T_1924, T_1927) node T_1929 = or(T_1928, s2_data_correctable) node T_1930 = and(T_1921, T_1929) when T_1930 : s3_req <> s2_req node T_1931 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) s3_req.data := T_1931 s3_way := s2_tag_match_way skip writeArb.io.in[0].bits.addr := s3_req.addr node rowIdx = bits(s3_req.addr, 3, 3) node rowWMask = dshl(UInt<1>("h01"), rowIdx) writeArb.io.in[0].bits.wmask := rowWMask node T_1935 = cat(s3_req.data, s3_req.data) writeArb.io.in[0].bits.data := T_1935 writeArb.io.in[0].valid := s3_valid writeArb.io.in[0].bits.way_en := s3_way wire T_1937 : UInt<1> T_1937 := UInt<1>("h00") T_1937 := UInt<1>("h00") reg T_1941 : UInt<16>, clock, reset onreset T_1941 := UInt<16>("h01") when T_1937 : node T_1942 = bit(T_1941, 0) node T_1943 = bit(T_1941, 2) node T_1944 = xor(T_1942, T_1943) node T_1945 = bit(T_1941, 3) node T_1946 = xor(T_1944, T_1945) node T_1947 = bit(T_1941, 5) node T_1948 = xor(T_1946, T_1947) node T_1949 = bits(T_1941, 15, 1) node T_1950 = cat(T_1948, T_1949) T_1941 := T_1950 skip node T_1951 = bits(T_1941, 1, 0) node s1_replaced_way_en = dshl(UInt<1>("h01"), T_1951) node T_1954 = bits(T_1941, 1, 0) reg T_1955 : UInt<2>, clock, reset when s1_clk_en : T_1955 := T_1954 skip node s2_replaced_way_en = dshl(UInt<1>("h01"), T_1955) node T_1958 = bit(s1_replaced_way_en, 0) node T_1959 = and(s1_clk_en, T_1958) reg T_1960 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset when T_1959 : T_1960 <> meta.io.resp[0] skip node T_1987 = bit(s1_replaced_way_en, 1) node T_1988 = and(s1_clk_en, T_1987) reg T_1989 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset when T_1988 : T_1989 <> meta.io.resp[1] skip node T_2016 = bit(s1_replaced_way_en, 2) node T_2017 = and(s1_clk_en, T_2016) reg T_2018 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset when T_2017 : T_2018 <> meta.io.resp[2] skip node T_2045 = bit(s1_replaced_way_en, 3) node T_2046 = and(s1_clk_en, T_2045) reg T_2047 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset when T_2046 : T_2047 <> meta.io.resp[3] skip wire T_2101 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] T_2101[0] <> T_1960 T_2101[1] <> T_1989 T_2101[2] <> T_2018 T_2101[3] <> T_2047 node T_2237 = bit(s2_replaced_way_en, 0) node T_2238 = bit(s2_replaced_way_en, 1) node T_2239 = bit(s2_replaced_way_en, 2) node T_2240 = bit(s2_replaced_way_en, 3) node T_2241 = cat(T_2101[0].tag, T_2101[0].coh.state) node T_2243 = mux(T_2237, T_2241, UInt<1>("h00")) node T_2244 = cat(T_2101[1].tag, T_2101[1].coh.state) node T_2246 = mux(T_2238, T_2244, UInt<1>("h00")) node T_2247 = cat(T_2101[2].tag, T_2101[2].coh.state) node T_2249 = mux(T_2239, T_2247, UInt<1>("h00")) node T_2250 = cat(T_2101[3].tag, T_2101[3].coh.state) node T_2252 = mux(T_2240, T_2250, UInt<1>("h00")) node T_2280 = or(T_2243, T_2246) node T_2281 = or(T_2280, T_2249) node T_2282 = or(T_2281, T_2252) wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} s2_repl_meta.coh.state := UInt<1>("h00") s2_repl_meta.tag := UInt<1>("h00") node T_2339 = bits(T_2282, 1, 0) s2_repl_meta.coh.state := T_2339 node T_2340 = bits(T_2282, 21, 2) s2_repl_meta.tag := T_2340 node T_2342 = eq(s2_hit, UInt<1>("h00")) node T_2343 = and(s2_valid_masked, T_2342) node T_2344 = eq(s2_req.cmd, UInt<5>("h02")) node T_2345 = eq(s2_req.cmd, UInt<5>("h03")) node T_2346 = or(T_2344, T_2345) node T_2347 = eq(s2_req.cmd, UInt<5>("h00")) node T_2348 = eq(s2_req.cmd, UInt<5>("h06")) node T_2349 = or(T_2347, T_2348) node T_2350 = eq(s2_req.cmd, UInt<5>("h07")) node T_2351 = or(T_2349, T_2350) node T_2352 = bit(s2_req.cmd, 3) node T_2353 = eq(s2_req.cmd, UInt<5>("h04")) node T_2354 = or(T_2352, T_2353) node T_2355 = or(T_2351, T_2354) node T_2356 = or(T_2346, T_2355) node T_2357 = eq(s2_req.cmd, UInt<5>("h01")) node T_2358 = eq(s2_req.cmd, UInt<5>("h07")) node T_2359 = or(T_2357, T_2358) node T_2360 = bit(s2_req.cmd, 3) node T_2361 = eq(s2_req.cmd, UInt<5>("h04")) node T_2362 = or(T_2360, T_2361) node T_2363 = or(T_2359, T_2362) node T_2364 = or(T_2356, T_2363) node T_2365 = and(T_2343, T_2364) mshrs.io.req.valid := T_2365 mshrs.io.req.bits <> s2_req mshrs.io.req.bits.tag_match := s2_tag_match wire T_2393 : {tag : UInt<20>, coh : {state : UInt<2>}} T_2393.coh.state := UInt<1>("h00") T_2393.tag := UInt<1>("h00") T_2393.tag := s2_repl_meta.tag T_2393.coh <> s2_hit_state wire T_2449 : {tag : UInt<20>, coh : {state : UInt<2>}} T_2449 <> s2_repl_meta when s2_tag_match : T_2449 <> T_2393 skip mshrs.io.req.bits.old_meta <> T_2449 node T_2476 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) mshrs.io.req.bits.way_en := T_2476 mshrs.io.req.bits.data := s2_req.data node T_2477 = and(mshrs.io.req.ready, mshrs.io.req.valid) when T_2477 : T_1937 := UInt<1>("h01") skip io.mem.acquire <> mshrs.io.mem_req readArb.io.in[1].valid := mshrs.io.replay.valid readArb.io.in[1].bits <> mshrs.io.replay.bits node T_2480 = not(UInt<4>("h00")) readArb.io.in[1].bits.way_en := T_2480 mshrs.io.replay.ready := readArb.io.in[1].ready node T_2481 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) s1_replay := T_2481 metaReadArb.io.in[1] <> mshrs.io.meta_read metaWriteArb.io.in[0] <> mshrs.io.meta_write inst releaseArb of LockingArbiter_96 releaseArb.io.out.ready := UInt<1>("h00") releaseArb.io.in[0].bits.voluntary := UInt<1>("h00") releaseArb.io.in[0].bits.r_type := UInt<1>("h00") releaseArb.io.in[0].bits.data := UInt<1>("h00") releaseArb.io.in[0].bits.addr_beat := UInt<1>("h00") releaseArb.io.in[0].bits.client_xact_id := UInt<1>("h00") releaseArb.io.in[0].bits.addr_block := UInt<1>("h00") releaseArb.io.in[0].valid := UInt<1>("h00") releaseArb.io.in[1].bits.voluntary := UInt<1>("h00") releaseArb.io.in[1].bits.r_type := UInt<1>("h00") releaseArb.io.in[1].bits.data := UInt<1>("h00") releaseArb.io.in[1].bits.addr_beat := UInt<1>("h00") releaseArb.io.in[1].bits.client_xact_id := UInt<1>("h00") releaseArb.io.in[1].bits.addr_block := UInt<1>("h00") releaseArb.io.in[1].valid := UInt<1>("h00") releaseArb.clock := clock releaseArb.reset := reset io.mem.release <> releaseArb.io.out node T_2529 = eq(lrsc_valid, UInt<1>("h00")) node T_2530 = and(io.mem.probe.valid, T_2529) prober.io.req.valid := T_2530 node T_2532 = eq(lrsc_valid, UInt<1>("h00")) node T_2533 = and(prober.io.req.ready, T_2532) io.mem.probe.ready := T_2533 prober.io.req.bits <> io.mem.probe.bits releaseArb.io.in[1] <> prober.io.rep prober.io.way_en := s2_tag_match_way prober.io.block_state <> s2_hit_state metaReadArb.io.in[2] <> prober.io.meta_read metaWriteArb.io.in[1] <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy inst T_2534 of FlowThroughSerializer T_2534.io.out.ready := UInt<1>("h00") T_2534.io.in.bits.g_type := UInt<1>("h00") T_2534.io.in.bits.is_builtin_type := UInt<1>("h00") T_2534.io.in.bits.manager_xact_id := UInt<1>("h00") T_2534.io.in.bits.client_xact_id := UInt<1>("h00") T_2534.io.in.bits.data := UInt<1>("h00") T_2534.io.in.bits.addr_beat := UInt<1>("h00") T_2534.io.in.valid := UInt<1>("h00") T_2534.clock := clock T_2534.reset := reset T_2534.io.in.valid := io.mem.grant.valid T_2534.io.in.bits <> io.mem.grant.bits io.mem.grant.ready := T_2534.io.in.ready node T_2543 = and(T_2534.io.out.ready, T_2534.io.out.valid) mshrs.io.mem_grant.valid := T_2543 mshrs.io.mem_grant.bits <> T_2534.io.out.bits wire T_2547 : UInt<3>[2] T_2547[0] := UInt<3>("h05") T_2547[1] := UInt<3>("h04") node T_2551 = eq(T_2547[0], T_2534.io.out.bits.g_type) node T_2552 = eq(T_2547[1], T_2534.io.out.bits.g_type) node T_2554 = or(UInt<1>("h00"), T_2551) node T_2555 = or(T_2554, T_2552) wire T_2557 : UInt<1>[2] T_2557[0] := UInt<1>("h00") T_2557[1] := UInt<1>("h01") node T_2561 = eq(T_2557[0], T_2534.io.out.bits.g_type) node T_2562 = eq(T_2557[1], T_2534.io.out.bits.g_type) node T_2564 = or(UInt<1>("h00"), T_2561) node T_2565 = or(T_2564, T_2562) node T_2566 = mux(T_2534.io.out.bits.is_builtin_type, T_2555, T_2565) node T_2568 = eq(T_2566, UInt<1>("h00")) node T_2569 = or(writeArb.io.in[1].ready, T_2568) T_2534.io.out.ready := T_2569 wire T_2573 : UInt<3>[2] T_2573[0] := UInt<3>("h05") T_2573[1] := UInt<3>("h04") node T_2577 = eq(T_2573[0], T_2534.io.out.bits.g_type) node T_2578 = eq(T_2573[1], T_2534.io.out.bits.g_type) node T_2580 = or(UInt<1>("h00"), T_2577) node T_2581 = or(T_2580, T_2578) wire T_2583 : UInt<1>[2] T_2583[0] := UInt<1>("h00") T_2583[1] := UInt<1>("h01") node T_2587 = eq(T_2583[0], T_2534.io.out.bits.g_type) node T_2588 = eq(T_2583[1], T_2534.io.out.bits.g_type) node T_2590 = or(UInt<1>("h00"), T_2587) node T_2591 = or(T_2590, T_2588) node T_2592 = mux(T_2534.io.out.bits.is_builtin_type, T_2581, T_2591) node T_2593 = and(T_2534.io.out.valid, T_2592) node T_2595 = lt(T_2534.io.out.bits.client_xact_id, UInt<2>("h02")) node T_2596 = and(T_2593, T_2595) writeArb.io.in[1].valid := T_2596 writeArb.io.in[1].bits.addr := mshrs.io.refill.addr writeArb.io.in[1].bits.way_en := mshrs.io.refill.way_en node T_2598 = not(UInt<2>("h00")) writeArb.io.in[1].bits.wmask := T_2598 node T_2599 = bits(T_2534.io.out.bits.data, 127, 0) writeArb.io.in[1].bits.data := T_2599 data.io.read <> readArb.io.out node T_2601 = eq(T_2534.io.out.valid, UInt<1>("h00")) node T_2602 = or(T_2601, T_2534.io.out.ready) readArb.io.out.ready := T_2602 inst wbArb of Arbiter_82 wbArb.io.out.ready := UInt<1>("h00") wbArb.io.in[0].bits.way_en := UInt<1>("h00") wbArb.io.in[0].bits.voluntary := UInt<1>("h00") wbArb.io.in[0].bits.r_type := UInt<1>("h00") wbArb.io.in[0].bits.data := UInt<1>("h00") wbArb.io.in[0].bits.addr_beat := UInt<1>("h00") wbArb.io.in[0].bits.client_xact_id := UInt<1>("h00") wbArb.io.in[0].bits.addr_block := UInt<1>("h00") wbArb.io.in[0].valid := UInt<1>("h00") wbArb.io.in[1].bits.way_en := UInt<1>("h00") wbArb.io.in[1].bits.voluntary := UInt<1>("h00") wbArb.io.in[1].bits.r_type := UInt<1>("h00") wbArb.io.in[1].bits.data := UInt<1>("h00") wbArb.io.in[1].bits.addr_beat := UInt<1>("h00") wbArb.io.in[1].bits.client_xact_id := UInt<1>("h00") wbArb.io.in[1].bits.addr_block := UInt<1>("h00") wbArb.io.in[1].valid := UInt<1>("h00") wbArb.clock := clock wbArb.reset := reset wbArb.io.in[0] <> prober.io.wb_req wbArb.io.in[1] <> mshrs.io.wb_req wb.io.req <> wbArb.io.out metaReadArb.io.in[3] <> wb.io.meta_read readArb.io.in[2] <> wb.io.data_req wb.io.data_resp := s2_data_corrected releaseArb.io.in[0] <> wb.io.release reg s4_valid : UInt<1>, clock, reset onreset s4_valid := UInt<1>("h00") s4_valid := s3_valid node T_2654 = and(s3_valid, metaReadArb.io.out.valid) reg s4_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset when T_2654 : s4_req <> s3_req skip node T_2663 = or(s2_valid_masked, s2_replay) node T_2665 = eq(s2_sc_fail, UInt<1>("h00")) node T_2666 = and(T_2663, T_2665) node T_2667 = shr(s1_addr, 3) node T_2668 = shr(s2_req.addr, 3) node T_2669 = eq(T_2667, T_2668) node T_2670 = and(T_2666, T_2669) node T_2671 = eq(s2_req.cmd, UInt<5>("h01")) node T_2672 = eq(s2_req.cmd, UInt<5>("h07")) node T_2673 = or(T_2671, T_2672) node T_2674 = bit(s2_req.cmd, 3) node T_2675 = eq(s2_req.cmd, UInt<5>("h04")) node T_2676 = or(T_2674, T_2675) node T_2677 = or(T_2673, T_2676) node T_2678 = and(T_2670, T_2677) node T_2679 = shr(s1_addr, 3) node T_2680 = shr(s3_req.addr, 3) node T_2681 = eq(T_2679, T_2680) node T_2682 = and(s3_valid, T_2681) node T_2683 = eq(s3_req.cmd, UInt<5>("h01")) node T_2684 = eq(s3_req.cmd, UInt<5>("h07")) node T_2685 = or(T_2683, T_2684) node T_2686 = bit(s3_req.cmd, 3) node T_2687 = eq(s3_req.cmd, UInt<5>("h04")) node T_2688 = or(T_2686, T_2687) node T_2689 = or(T_2685, T_2688) node T_2690 = and(T_2682, T_2689) node T_2691 = shr(s1_addr, 3) node T_2692 = shr(s4_req.addr, 3) node T_2693 = eq(T_2691, T_2692) node T_2694 = and(s4_valid, T_2693) node T_2695 = eq(s4_req.cmd, UInt<5>("h01")) node T_2696 = eq(s4_req.cmd, UInt<5>("h07")) node T_2697 = or(T_2695, T_2696) node T_2698 = bit(s4_req.cmd, 3) node T_2699 = eq(s4_req.cmd, UInt<5>("h04")) node T_2700 = or(T_2698, T_2699) node T_2701 = or(T_2697, T_2700) node T_2702 = and(T_2694, T_2701) reg s2_store_bypass_data : UInt<64>, clock, reset reg s2_store_bypass : UInt<1>, clock, reset when s1_clk_en : s2_store_bypass := UInt<1>("h00") node T_2708 = or(T_2678, T_2690) node T_2709 = or(T_2708, T_2702) when T_2709 : node T_2710 = mux(T_2690, s3_req.data, s4_req.data) node T_2711 = mux(T_2678, amoalu.io.out, T_2710) s2_store_bypass_data := T_2711 s2_store_bypass := UInt<1>("h01") skip skip node T_2714 = cat(UInt<1>("h00"), UInt<6>("h00")) node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_2714) node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) node T_2717 = eq(s2_req.typ, UInt<3>("h00")) node T_2718 = eq(s2_req.typ, UInt<3>("h04")) node T_2719 = or(T_2717, T_2718) node T_2720 = eq(s2_req.typ, UInt<3>("h01")) node T_2721 = eq(s2_req.typ, UInt<3>("h05")) node T_2722 = or(T_2720, T_2721) node T_2723 = eq(s2_req.typ, UInt<3>("h02")) node T_2724 = eq(s2_req.typ, UInt<3>("h06")) node T_2725 = or(T_2723, T_2724) node T_2726 = eq(s2_req.typ, UInt<3>("h00")) node T_2727 = eq(s2_req.typ, UInt<3>("h01")) node T_2728 = or(T_2726, T_2727) node T_2729 = eq(s2_req.typ, UInt<3>("h02")) node T_2730 = or(T_2728, T_2729) node T_2731 = eq(s2_req.typ, UInt<3>("h03")) node T_2732 = or(T_2730, T_2731) node T_2733 = bit(s2_req.addr, 2) node T_2734 = bits(s2_data_word, 63, 32) node T_2735 = bits(s2_data_word, 31, 0) node T_2736 = mux(T_2733, T_2734, T_2735) node T_2737 = bit(T_2736, 31) node T_2738 = and(T_2732, T_2737) node T_2740 = subw(UInt<32>("h00"), T_2738) node T_2741 = bits(s2_data_word, 63, 32) node T_2742 = mux(T_2725, T_2740, T_2741) node T_2743 = cat(T_2742, T_2736) node T_2744 = bit(s2_req.addr, 1) node T_2745 = bits(T_2743, 31, 16) node T_2746 = bits(T_2743, 15, 0) node T_2747 = mux(T_2744, T_2745, T_2746) node T_2748 = bit(T_2747, 15) node T_2749 = and(T_2732, T_2748) node T_2751 = subw(UInt<48>("h00"), T_2749) node T_2752 = bits(T_2743, 63, 16) node T_2753 = mux(T_2722, T_2751, T_2752) node T_2754 = cat(T_2753, T_2747) node T_2756 = bit(s2_req.addr, 0) node T_2757 = bits(T_2754, 15, 8) node T_2758 = bits(T_2754, 7, 0) node T_2759 = mux(T_2756, T_2757, T_2758) node T_2760 = mux(s2_sc, UInt<1>("h00"), T_2759) node T_2761 = or(s2_sc, T_2719) node T_2762 = bit(T_2760, 7) node T_2763 = and(T_2732, T_2762) node T_2765 = subw(UInt<56>("h00"), T_2763) node T_2766 = bits(T_2754, 63, 8) node T_2767 = mux(T_2761, T_2765, T_2766) node T_2768 = cat(T_2767, T_2760) amoalu.io.addr := s2_req.addr amoalu.io.cmd := s2_req.cmd amoalu.io.typ := s2_req.typ amoalu.io.lhs := s2_data_word amoalu.io.rhs := s2_req.data node T_2769 = and(dtlb.io.req.valid, dtlb.io.resp.miss) node T_2770 = bits(s1_req.addr, 11, 6) node T_2771 = eq(T_2770, prober.io.meta_write.bits.idx) node T_2773 = eq(prober.io.req.ready, UInt<1>("h00")) node T_2774 = and(T_2771, T_2773) node s1_nack = or(T_2769, T_2774) node T_2776 = or(s1_valid, s1_replay) reg s2_nack_hit : UInt<1>, clock, reset when T_2776 : s2_nack_hit := s1_nack skip when s2_nack_hit : mshrs.io.req.valid := UInt<1>("h00") skip node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss) node T_2781 = eq(s2_hit, UInt<1>("h00")) node T_2783 = eq(mshrs.io.req.ready, UInt<1>("h00")) node s2_nack_miss = and(T_2781, T_2783) node T_2785 = or(s2_nack_hit, s2_nack_victim) node s2_nack = or(T_2785, s2_nack_miss) node T_2788 = eq(s2_nack, UInt<1>("h00")) node T_2789 = and(s2_valid, T_2788) s2_valid_masked := T_2789 node T_2790 = or(s2_valid, s2_replay) node T_2791 = and(T_2790, s2_hit) node s2_recycle_ecc = and(T_2791, s2_data_correctable) reg s2_recycle_next : UInt<1>, clock, reset onreset s2_recycle_next := UInt<1>("h00") node T_2795 = or(s1_valid, s1_replay) when T_2795 : s2_recycle_next := s2_recycle_ecc skip node T_2796 = or(s2_recycle_ecc, s2_recycle_next) s2_recycle := T_2796 reg block_miss : UInt<1>, clock, reset onreset block_miss := UInt<1>("h00") node T_2799 = or(s2_valid, block_miss) node T_2800 = and(T_2799, s2_nack_miss) block_miss := T_2800 when block_miss : io.cpu.req.ready := UInt<1>("h00") skip wire cache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} cache_resp.bits.store_data := UInt<1>("h00") cache_resp.bits.data_word_bypass := UInt<1>("h00") cache_resp.bits.has_data := UInt<1>("h00") cache_resp.bits.replay := UInt<1>("h00") cache_resp.bits.nack := UInt<1>("h00") cache_resp.bits.data := UInt<1>("h00") cache_resp.bits.typ := UInt<1>("h00") cache_resp.bits.cmd := UInt<1>("h00") cache_resp.bits.tag := UInt<1>("h00") cache_resp.bits.addr := UInt<1>("h00") cache_resp.valid := UInt<1>("h00") node T_2872 = and(s2_valid_masked, s2_hit) node T_2873 = or(s2_replay, T_2872) node T_2875 = eq(s2_data_correctable, UInt<1>("h00")) node T_2876 = and(T_2873, T_2875) cache_resp.valid := T_2876 cache_resp.bits <> s2_req node T_2877 = eq(s2_req.cmd, UInt<5>("h00")) node T_2878 = eq(s2_req.cmd, UInt<5>("h06")) node T_2879 = or(T_2877, T_2878) node T_2880 = eq(s2_req.cmd, UInt<5>("h07")) node T_2881 = or(T_2879, T_2880) node T_2882 = bit(s2_req.cmd, 3) node T_2883 = eq(s2_req.cmd, UInt<5>("h04")) node T_2884 = or(T_2882, T_2883) node T_2885 = or(T_2881, T_2884) cache_resp.bits.has_data := T_2885 node T_2886 = or(T_2768, s2_sc_fail) cache_resp.bits.data := T_2886 cache_resp.bits.store_data := s2_req.data node T_2887 = and(s2_valid, s2_nack) cache_resp.bits.nack := T_2887 cache_resp.bits.replay := s2_replay wire uncache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} uncache_resp.bits.store_data := UInt<1>("h00") uncache_resp.bits.data_word_bypass := UInt<1>("h00") uncache_resp.bits.has_data := UInt<1>("h00") uncache_resp.bits.replay := UInt<1>("h00") uncache_resp.bits.nack := UInt<1>("h00") uncache_resp.bits.data := UInt<1>("h00") uncache_resp.bits.typ := UInt<1>("h00") uncache_resp.bits.cmd := UInt<1>("h00") uncache_resp.bits.tag := UInt<1>("h00") uncache_resp.bits.addr := UInt<1>("h00") uncache_resp.valid := UInt<1>("h00") uncache_resp.bits <> mshrs.io.resp.bits uncache_resp.valid := mshrs.io.resp.valid node cache_pass = or(s2_valid, s2_replay) node T_2960 = eq(cache_pass, UInt<1>("h00")) mshrs.io.resp.ready := T_2960 wire T_2985 : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} T_2985 <> uncache_resp when cache_pass : T_2985 <> cache_resp skip io.cpu.resp <> T_2985 io.cpu.resp.bits.data_word_bypass := T_2743 node T_3010 = eq(s1_valid, UInt<1>("h00")) node T_3011 = and(mshrs.io.fence_rdy, T_3010) node T_3013 = eq(s2_valid, UInt<1>("h00")) node T_3014 = and(T_3011, T_3013) io.cpu.ordered := T_3014 node T_3015 = and(s1_replay, s1_read) io.cpu.replay_next.valid := T_3015 io.cpu.replay_next.bits := s1_req.tag module RRArbiter_99 : input clock : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} io.chosen := UInt<1>("h00") io.out.bits.fetch := UInt<1>("h00") io.out.bits.store := UInt<1>("h00") io.out.bits.prv := UInt<1>("h00") io.out.bits.addr := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.in[0].ready := UInt<1>("h00") io.in[1].ready := UInt<1>("h00") wire T_152 : UInt<1> T_152 := UInt<1>("h00") infer accessor T_154 = io.in[T_152] io.out.valid := T_154.valid infer accessor T_167 = io.in[T_152] io.out.bits <> T_167.bits io.chosen := T_152 infer accessor T_180 = io.in[T_152] T_180.ready := UInt<1>("h00") reg T_196 : UInt<1>, clock, reset onreset T_196 := UInt<1>("h00") node T_197 = gt(UInt<1>("h00"), T_196) node T_198 = and(io.in[0].valid, T_197) node T_200 = gt(UInt<1>("h01"), T_196) node T_201 = and(io.in[1].valid, T_200) node T_204 = or(UInt<1>("h00"), T_198) node T_206 = eq(T_204, UInt<1>("h00")) node T_208 = or(UInt<1>("h00"), T_198) node T_209 = or(T_208, T_201) node T_211 = eq(T_209, UInt<1>("h00")) node T_213 = or(UInt<1>("h00"), T_198) node T_214 = or(T_213, T_201) node T_215 = or(T_214, io.in[0].valid) node T_217 = eq(T_215, UInt<1>("h00")) node T_219 = gt(UInt<1>("h00"), T_196) node T_220 = and(UInt<1>("h01"), T_219) node T_221 = or(T_220, T_211) node T_223 = gt(UInt<1>("h01"), T_196) node T_224 = and(T_206, T_223) node T_225 = or(T_224, T_217) node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_228 = mux(UInt<1>("h00"), T_227, T_221) node T_229 = and(T_228, io.out.ready) io.in[0].ready := T_229 node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_232 = mux(UInt<1>("h00"), T_231, T_225) node T_233 = and(T_232, io.out.ready) io.in[1].ready := T_233 node T_236 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_238 = gt(UInt<1>("h01"), T_196) node T_239 = and(io.in[1].valid, T_238) node T_241 = mux(T_239, UInt<1>("h01"), T_236) node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) T_152 := T_242 node T_243 = and(io.out.ready, io.out.valid) when T_243 : T_196 := T_152 skip module PTW : input clock : Clock input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}} io.mem.invalidate_lr := UInt<1>("h00") io.mem.req.bits.data := UInt<1>("h00") io.mem.req.bits.phys := UInt<1>("h00") io.mem.req.bits.kill := UInt<1>("h00") io.mem.req.bits.typ := UInt<1>("h00") io.mem.req.bits.cmd := UInt<1>("h00") io.mem.req.bits.tag := UInt<1>("h00") io.mem.req.bits.addr := UInt<1>("h00") io.mem.req.valid := UInt<1>("h00") io.requestor[0].invalidate := UInt<1>("h00") io.requestor[0].status.ie := UInt<1>("h00") io.requestor[0].status.prv := UInt<1>("h00") io.requestor[0].status.ie1 := UInt<1>("h00") io.requestor[0].status.prv1 := UInt<1>("h00") io.requestor[0].status.ie2 := UInt<1>("h00") io.requestor[0].status.prv2 := UInt<1>("h00") io.requestor[0].status.ie3 := UInt<1>("h00") io.requestor[0].status.prv3 := UInt<1>("h00") io.requestor[0].status.fs := UInt<1>("h00") io.requestor[0].status.xs := UInt<1>("h00") io.requestor[0].status.mprv := UInt<1>("h00") io.requestor[0].status.vm := UInt<1>("h00") io.requestor[0].status.zero1 := UInt<1>("h00") io.requestor[0].status.sd_rv32 := UInt<1>("h00") io.requestor[0].status.zero2 := UInt<1>("h00") io.requestor[0].status.sd := UInt<1>("h00") io.requestor[0].resp.bits.pte.v := UInt<1>("h00") io.requestor[0].resp.bits.pte.typ := UInt<1>("h00") io.requestor[0].resp.bits.pte.r := UInt<1>("h00") io.requestor[0].resp.bits.pte.d := UInt<1>("h00") io.requestor[0].resp.bits.pte.reserved_for_software := UInt<1>("h00") io.requestor[0].resp.bits.pte.ppn := UInt<1>("h00") io.requestor[0].resp.bits.error := UInt<1>("h00") io.requestor[0].resp.valid := UInt<1>("h00") io.requestor[0].req.ready := UInt<1>("h00") io.requestor[1].invalidate := UInt<1>("h00") io.requestor[1].status.ie := UInt<1>("h00") io.requestor[1].status.prv := UInt<1>("h00") io.requestor[1].status.ie1 := UInt<1>("h00") io.requestor[1].status.prv1 := UInt<1>("h00") io.requestor[1].status.ie2 := UInt<1>("h00") io.requestor[1].status.prv2 := UInt<1>("h00") io.requestor[1].status.ie3 := UInt<1>("h00") io.requestor[1].status.prv3 := UInt<1>("h00") io.requestor[1].status.fs := UInt<1>("h00") io.requestor[1].status.xs := UInt<1>("h00") io.requestor[1].status.mprv := UInt<1>("h00") io.requestor[1].status.vm := UInt<1>("h00") io.requestor[1].status.zero1 := UInt<1>("h00") io.requestor[1].status.sd_rv32 := UInt<1>("h00") io.requestor[1].status.zero2 := UInt<1>("h00") io.requestor[1].status.sd := UInt<1>("h00") io.requestor[1].resp.bits.pte.v := UInt<1>("h00") io.requestor[1].resp.bits.pte.typ := UInt<1>("h00") io.requestor[1].resp.bits.pte.r := UInt<1>("h00") io.requestor[1].resp.bits.pte.d := UInt<1>("h00") io.requestor[1].resp.bits.pte.reserved_for_software := UInt<1>("h00") io.requestor[1].resp.bits.pte.ppn := UInt<1>("h00") io.requestor[1].resp.bits.error := UInt<1>("h00") io.requestor[1].resp.valid := UInt<1>("h00") io.requestor[1].req.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg count : UInt<2>, clock, reset reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clock, reset reg r_req_dest : UInt, clock, reset reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clock, reset node T_1222 = shr(r_req.addr, 18) node T_1223 = bits(T_1222, 8, 0) node T_1224 = shr(r_req.addr, 9) node T_1225 = bits(T_1224, 8, 0) node T_1226 = shr(r_req.addr, 0) node T_1227 = bits(T_1226, 8, 0) wire T_1229 : UInt<9>[3] T_1229[0] := T_1223 T_1229[1] := T_1225 T_1229[2] := T_1227 infer accessor vpn_idx = T_1229[count] inst arb of RRArbiter_99 arb.io.out.ready := UInt<1>("h00") arb.io.in[0].bits.fetch := UInt<1>("h00") arb.io.in[0].bits.store := UInt<1>("h00") arb.io.in[0].bits.prv := UInt<1>("h00") arb.io.in[0].bits.addr := UInt<1>("h00") arb.io.in[0].valid := UInt<1>("h00") arb.io.in[1].bits.fetch := UInt<1>("h00") arb.io.in[1].bits.store := UInt<1>("h00") arb.io.in[1].bits.prv := UInt<1>("h00") arb.io.in[1].bits.addr := UInt<1>("h00") arb.io.in[1].valid := UInt<1>("h00") arb.clock := clock arb.reset := reset arb.io.in[0] <> io.requestor[0].req arb.io.in[1] <> io.requestor[1].req node T_1252 = eq(state, UInt<1>("h00")) arb.io.out.ready := T_1252 wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} pte.v := UInt<1>("h00") pte.typ := UInt<1>("h00") pte.r := UInt<1>("h00") pte.d := UInt<1>("h00") pte.reserved_for_software := UInt<1>("h00") pte.ppn := UInt<1>("h00") node T_1280 = bits(io.mem.resp.bits.data, 0, 0) pte.v := T_1280 node T_1281 = bits(io.mem.resp.bits.data, 4, 1) pte.typ := T_1281 node T_1282 = bits(io.mem.resp.bits.data, 5, 5) pte.r := T_1282 node T_1283 = bits(io.mem.resp.bits.data, 6, 6) pte.d := T_1283 node T_1284 = bits(io.mem.resp.bits.data, 9, 7) pte.reserved_for_software := T_1284 node T_1285 = bits(io.mem.resp.bits.data, 29, 10) pte.ppn := T_1285 node T_1286 = cat(r_pte.ppn, vpn_idx) node pte_addr = shl(T_1286, 3) node T_1288 = and(arb.io.out.ready, arb.io.out.valid) when T_1288 : r_req <> arb.io.out.bits r_req_dest := arb.io.chosen node T_1289 = bits(io.dpath.ptbr, 31, 12) r_pte.ppn := T_1289 skip reg T_1291 : UInt<3>, clock, reset reg T_1301 : UInt<1>[3], clock, reset node T_1306 = cat(T_1301[1], T_1301[0]) node T_1307 = cat(T_1301[2], T_1306) cmem T_1310 : UInt<32>[3], clock cmem T_1313 : UInt<20>[3], clock infer accessor T_1315 = T_1310[UInt<1>("h00")] node T_1316 = eq(T_1315, pte_addr) infer accessor T_1318 = T_1310[UInt<1>("h01")] node T_1319 = eq(T_1318, pte_addr) infer accessor T_1321 = T_1310[UInt<2>("h02")] node T_1322 = eq(T_1321, pte_addr) wire T_1324 : UInt<1>[3] T_1324[0] := T_1316 T_1324[1] := T_1319 T_1324[2] := T_1322 node T_1329 = cat(T_1324[1], T_1324[0]) node T_1330 = cat(T_1324[2], T_1329) node T_1331 = and(T_1330, T_1307) node pte_cache_hit = neq(T_1331, UInt<1>("h00")) node T_1335 = lt(pte.typ, UInt<2>("h02")) node T_1336 = and(pte.v, T_1335) node T_1337 = and(io.mem.resp.valid, T_1336) node T_1339 = eq(pte_cache_hit, UInt<1>("h00")) node T_1340 = and(T_1337, T_1339) when T_1340 : node T_1341 = not(T_1307) node T_1343 = eq(T_1341, UInt<1>("h00")) node T_1345 = dshr(T_1291, UInt<1>("h01")) node T_1346 = bit(T_1345, 0) node T_1347 = cat(UInt<1>("h01"), T_1346) node T_1348 = dshr(T_1291, T_1347) node T_1349 = bit(T_1348, 0) node T_1350 = cat(T_1347, T_1349) node T_1351 = bits(T_1350, 1, 0) node T_1352 = not(T_1307) node T_1353 = bit(T_1352, 0) node T_1354 = bit(T_1352, 1) node T_1355 = bit(T_1352, 2) wire T_1357 : UInt<1>[3] T_1357[0] := T_1353 T_1357[1] := T_1354 T_1357[2] := T_1355 node T_1365 = mux(T_1357[1], UInt<1>("h01"), UInt<2>("h02")) node T_1366 = mux(T_1357[0], UInt<1>("h00"), T_1365) node T_1367 = mux(T_1343, T_1351, T_1366) infer accessor T_1368 = T_1301[T_1367] T_1368 := UInt<1>("h01") infer accessor T_1370 = T_1310[T_1367] T_1370 := pte_addr infer accessor T_1371 = T_1313[T_1367] T_1371 := pte.ppn skip node T_1372 = eq(state, UInt<1>("h01")) node T_1373 = and(pte_cache_hit, T_1372) when T_1373 : node T_1374 = bits(T_1331, 2, 2) node T_1375 = bits(T_1331, 1, 0) node T_1377 = neq(T_1374, UInt<1>("h00")) node T_1378 = or(T_1374, T_1375) node T_1379 = bit(T_1378, 1) node T_1380 = cat(T_1377, T_1379) node T_1382 = bit(T_1380, 1) node T_1384 = dshl(UInt<3>("h01"), UInt<1>("h01")) node T_1385 = bits(T_1384, 2, 0) node T_1386 = not(T_1385) node T_1387 = and(T_1291, T_1386) node T_1389 = mux(T_1382, UInt<1>("h00"), T_1385) node T_1390 = or(T_1387, T_1389) node T_1391 = cat(UInt<1>("h01"), T_1382) node T_1392 = bit(T_1380, 0) node T_1394 = dshl(UInt<3>("h01"), T_1391) node T_1395 = bits(T_1394, 2, 0) node T_1396 = not(T_1395) node T_1397 = and(T_1390, T_1396) node T_1399 = mux(T_1392, UInt<1>("h00"), T_1395) node T_1400 = or(T_1397, T_1399) node T_1401 = cat(T_1391, T_1392) T_1291 := T_1400 skip node T_1402 = or(reset, io.dpath.invalidate) when T_1402 : T_1301[0] := UInt<1>("h00") T_1301[1] := UInt<1>("h00") T_1301[2] := UInt<1>("h00") skip node T_1406 = bit(T_1331, 0) node T_1407 = bit(T_1331, 1) node T_1408 = bit(T_1331, 2) infer accessor T_1410 = T_1313[UInt<1>("h00")] infer accessor T_1412 = T_1313[UInt<1>("h01")] infer accessor T_1414 = T_1313[UInt<2>("h02")] node T_1416 = mux(T_1406, T_1410, UInt<1>("h00")) node T_1418 = mux(T_1407, T_1412, UInt<1>("h00")) node T_1420 = mux(T_1408, T_1414, UInt<1>("h00")) node T_1422 = or(T_1416, T_1418) node T_1423 = or(T_1422, T_1420) wire pte_cache_data : UInt<20> pte_cache_data := UInt<1>("h00") pte_cache_data := T_1423 node T_1426 = bit(r_req.prv, 0) node T_1428 = geq(pte.typ, UInt<3>("h04")) node T_1429 = and(pte.v, T_1428) node T_1430 = bit(pte.typ, 1) node T_1431 = and(T_1429, T_1430) node T_1433 = geq(pte.typ, UInt<2>("h02")) node T_1434 = and(pte.v, T_1433) node T_1435 = bit(pte.typ, 0) node T_1436 = and(T_1434, T_1435) node T_1438 = geq(pte.typ, UInt<2>("h02")) node T_1439 = and(pte.v, T_1438) node T_1440 = mux(r_req.store, T_1436, T_1439) node T_1441 = mux(r_req.fetch, T_1431, T_1440) node T_1443 = geq(pte.typ, UInt<2>("h02")) node T_1444 = and(pte.v, T_1443) node T_1446 = lt(pte.typ, UInt<4>("h08")) node T_1447 = and(T_1444, T_1446) node T_1448 = bit(pte.typ, 1) node T_1449 = and(T_1447, T_1448) node T_1451 = geq(pte.typ, UInt<2>("h02")) node T_1452 = and(pte.v, T_1451) node T_1454 = lt(pte.typ, UInt<4>("h08")) node T_1455 = and(T_1452, T_1454) node T_1456 = bit(pte.typ, 0) node T_1457 = and(T_1455, T_1456) node T_1459 = geq(pte.typ, UInt<2>("h02")) node T_1460 = and(pte.v, T_1459) node T_1462 = lt(pte.typ, UInt<4>("h08")) node T_1463 = and(T_1460, T_1462) node T_1464 = mux(r_req.store, T_1457, T_1463) node T_1465 = mux(r_req.fetch, T_1449, T_1464) node perm_ok = mux(T_1426, T_1441, T_1465) node T_1468 = eq(pte.r, UInt<1>("h00")) node T_1470 = eq(pte.d, UInt<1>("h00")) node T_1471 = and(r_req.store, T_1470) node T_1472 = or(T_1468, T_1471) node set_dirty_bit = and(perm_ok, T_1472) node T_1474 = eq(state, UInt<2>("h02")) node T_1475 = and(io.mem.resp.valid, T_1474) node T_1477 = eq(set_dirty_bit, UInt<1>("h00")) node T_1478 = and(T_1475, T_1477) when T_1478 : r_pte <> pte skip wire T_1494 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} T_1494.v := UInt<1>("h00") T_1494.typ := UInt<1>("h00") T_1494.r := UInt<1>("h00") T_1494.d := UInt<1>("h00") T_1494.reserved_for_software := UInt<1>("h00") T_1494.ppn := UInt<1>("h00") T_1494.v := UInt<1>("h00") T_1494.typ := UInt<4>("h00") T_1494.r := UInt<1>("h00") T_1494.d := UInt<1>("h00") T_1494.reserved_for_software := UInt<3>("h00") T_1494.ppn := UInt<20>("h00") wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} pte_wdata <> T_1494 pte_wdata.r := UInt<1>("h01") pte_wdata.d := r_req.store node T_1521 = eq(state, UInt<1>("h01")) node T_1522 = eq(state, UInt<2>("h03")) node T_1523 = or(T_1521, T_1522) io.mem.req.valid := T_1523 io.mem.req.bits.phys := UInt<1>("h01") node T_1525 = eq(state, UInt<2>("h03")) node T_1526 = mux(T_1525, UInt<5>("h0a"), UInt<5>("h00")) io.mem.req.bits.cmd := T_1526 io.mem.req.bits.typ := UInt<3>("h03") io.mem.req.bits.addr := pte_addr io.mem.req.bits.kill := UInt<1>("h00") node T_1528 = cat(pte_wdata.reserved_for_software, pte_wdata.d) node T_1529 = cat(pte_wdata.ppn, T_1528) node T_1530 = cat(pte_wdata.typ, pte_wdata.v) node T_1531 = cat(pte_wdata.r, T_1530) node T_1532 = cat(T_1529, T_1531) io.mem.req.bits.data := T_1532 node resp_err = eq(state, UInt<3>("h06")) node T_1534 = eq(state, UInt<3>("h05")) node resp_val = or(T_1534, resp_err) node r_resp_ppn = shr(io.mem.req.bits.addr, 12) node T_1537 = shr(r_resp_ppn, 18) node T_1538 = bits(r_req.addr, 17, 0) node T_1539 = cat(T_1537, T_1538) node T_1540 = shr(r_resp_ppn, 9) node T_1541 = bits(r_req.addr, 8, 0) node T_1542 = cat(T_1540, T_1541) wire T_1544 : UInt<28>[3] T_1544[0] := T_1539 T_1544[1] := T_1542 T_1544[2] := r_resp_ppn infer accessor resp_ppn = T_1544[count] node T_1551 = eq(r_req_dest, UInt<1>("h00")) node T_1552 = and(resp_val, T_1551) io.requestor[0].resp.valid := T_1552 io.requestor[0].resp.bits.error := resp_err io.requestor[0].resp.bits.pte <> r_pte io.requestor[0].resp.bits.pte.ppn := resp_ppn io.requestor[0].invalidate := io.dpath.invalidate io.requestor[0].status <> io.dpath.status node T_1554 = eq(r_req_dest, UInt<1>("h01")) node T_1555 = and(resp_val, T_1554) io.requestor[1].resp.valid := T_1555 io.requestor[1].resp.bits.error := resp_err io.requestor[1].resp.bits.pte <> r_pte io.requestor[1].resp.bits.pte.ppn := resp_ppn io.requestor[1].invalidate := io.dpath.invalidate io.requestor[1].status <> io.dpath.status node T_1556 = eq(UInt<1>("h00"), state) when T_1556 : when arb.io.out.valid : state := UInt<1>("h01") skip count := UInt<1>("h00") skip node T_1558 = eq(UInt<1>("h01"), state) when T_1558 : node T_1560 = lt(count, UInt<2>("h02")) node T_1561 = and(pte_cache_hit, T_1560) when T_1561 : io.mem.req.valid := UInt<1>("h00") state := UInt<1>("h01") node T_1564 = addw(count, UInt<1>("h01")) count := T_1564 r_pte.ppn := pte_cache_data skip else : when io.mem.req.ready : state := UInt<2>("h02") skip skip skip node T_1565 = eq(UInt<2>("h02"), state) when T_1565 : when io.mem.resp.bits.nack : state := UInt<1>("h01") skip when io.mem.resp.valid : state := UInt<3>("h06") node T_1567 = lt(pte.typ, UInt<2>("h02")) node T_1568 = and(pte.v, T_1567) node T_1570 = lt(count, UInt<2>("h02")) node T_1571 = and(T_1568, T_1570) when T_1571 : state := UInt<1>("h01") node T_1573 = addw(count, UInt<1>("h01")) count := T_1573 skip node T_1575 = geq(pte.typ, UInt<2>("h02")) node T_1576 = and(pte.v, T_1575) when T_1576 : node T_1577 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) state := T_1577 skip skip skip node T_1578 = eq(UInt<2>("h03"), state) when T_1578 : when io.mem.req.ready : state := UInt<3>("h04") skip skip node T_1579 = eq(UInt<3>("h04"), state) when T_1579 : when io.mem.resp.bits.nack : state := UInt<2>("h03") skip when io.mem.resp.valid : state := UInt<1>("h01") skip skip node T_1580 = eq(UInt<3>("h05"), state) when T_1580 : state := UInt<1>("h00") skip node T_1581 = eq(UInt<3>("h06"), state) when T_1581 : state := UInt<1>("h00") skip module CSRFile : input clock : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_replay : UInt<1>, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>}, interrupt : UInt<1>, interrupt_cause : UInt<64>} io.interrupt_cause := UInt<1>("h00") io.interrupt := UInt<1>("h00") io.rocc.exception := UInt<1>("h00") io.rocc.pptw.invalidate := UInt<1>("h00") io.rocc.pptw.status.ie := UInt<1>("h00") io.rocc.pptw.status.prv := UInt<1>("h00") io.rocc.pptw.status.ie1 := UInt<1>("h00") io.rocc.pptw.status.prv1 := UInt<1>("h00") io.rocc.pptw.status.ie2 := UInt<1>("h00") io.rocc.pptw.status.prv2 := UInt<1>("h00") io.rocc.pptw.status.ie3 := UInt<1>("h00") io.rocc.pptw.status.prv3 := UInt<1>("h00") io.rocc.pptw.status.fs := UInt<1>("h00") io.rocc.pptw.status.xs := UInt<1>("h00") io.rocc.pptw.status.mprv := UInt<1>("h00") io.rocc.pptw.status.vm := UInt<1>("h00") io.rocc.pptw.status.zero1 := UInt<1>("h00") io.rocc.pptw.status.sd_rv32 := UInt<1>("h00") io.rocc.pptw.status.zero2 := UInt<1>("h00") io.rocc.pptw.status.sd := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.pptw.resp.bits.error := UInt<1>("h00") io.rocc.pptw.resp.valid := UInt<1>("h00") io.rocc.pptw.req.ready := UInt<1>("h00") io.rocc.dptw.invalidate := UInt<1>("h00") io.rocc.dptw.status.ie := UInt<1>("h00") io.rocc.dptw.status.prv := UInt<1>("h00") io.rocc.dptw.status.ie1 := UInt<1>("h00") io.rocc.dptw.status.prv1 := UInt<1>("h00") io.rocc.dptw.status.ie2 := UInt<1>("h00") io.rocc.dptw.status.prv2 := UInt<1>("h00") io.rocc.dptw.status.ie3 := UInt<1>("h00") io.rocc.dptw.status.prv3 := UInt<1>("h00") io.rocc.dptw.status.fs := UInt<1>("h00") io.rocc.dptw.status.xs := UInt<1>("h00") io.rocc.dptw.status.mprv := UInt<1>("h00") io.rocc.dptw.status.vm := UInt<1>("h00") io.rocc.dptw.status.zero1 := UInt<1>("h00") io.rocc.dptw.status.sd_rv32 := UInt<1>("h00") io.rocc.dptw.status.zero2 := UInt<1>("h00") io.rocc.dptw.status.sd := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.dptw.resp.bits.error := UInt<1>("h00") io.rocc.dptw.resp.valid := UInt<1>("h00") io.rocc.dptw.req.ready := UInt<1>("h00") io.rocc.iptw.invalidate := UInt<1>("h00") io.rocc.iptw.status.ie := UInt<1>("h00") io.rocc.iptw.status.prv := UInt<1>("h00") io.rocc.iptw.status.ie1 := UInt<1>("h00") io.rocc.iptw.status.prv1 := UInt<1>("h00") io.rocc.iptw.status.ie2 := UInt<1>("h00") io.rocc.iptw.status.prv2 := UInt<1>("h00") io.rocc.iptw.status.ie3 := UInt<1>("h00") io.rocc.iptw.status.prv3 := UInt<1>("h00") io.rocc.iptw.status.fs := UInt<1>("h00") io.rocc.iptw.status.xs := UInt<1>("h00") io.rocc.iptw.status.mprv := UInt<1>("h00") io.rocc.iptw.status.vm := UInt<1>("h00") io.rocc.iptw.status.zero1 := UInt<1>("h00") io.rocc.iptw.status.sd_rv32 := UInt<1>("h00") io.rocc.iptw.status.zero2 := UInt<1>("h00") io.rocc.iptw.status.sd := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.iptw.resp.bits.error := UInt<1>("h00") io.rocc.iptw.resp.valid := UInt<1>("h00") io.rocc.iptw.req.ready := UInt<1>("h00") io.rocc.dmem.grant.bits.g_type := UInt<1>("h00") io.rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") io.rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") io.rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") io.rocc.dmem.grant.bits.data := UInt<1>("h00") io.rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") io.rocc.dmem.grant.valid := UInt<1>("h00") io.rocc.dmem.acquire.ready := UInt<1>("h00") io.rocc.imem.grant.bits.g_type := UInt<1>("h00") io.rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") io.rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") io.rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") io.rocc.imem.grant.bits.data := UInt<1>("h00") io.rocc.imem.grant.bits.addr_beat := UInt<1>("h00") io.rocc.imem.grant.valid := UInt<1>("h00") io.rocc.imem.acquire.ready := UInt<1>("h00") io.rocc.s := UInt<1>("h00") io.rocc.mem.ordered := UInt<1>("h00") io.rocc.mem.xcpt.pf.st := UInt<1>("h00") io.rocc.mem.xcpt.pf.ld := UInt<1>("h00") io.rocc.mem.xcpt.ma.st := UInt<1>("h00") io.rocc.mem.xcpt.ma.ld := UInt<1>("h00") io.rocc.mem.replay_next.bits := UInt<1>("h00") io.rocc.mem.replay_next.valid := UInt<1>("h00") io.rocc.mem.resp.bits.store_data := UInt<1>("h00") io.rocc.mem.resp.bits.data_word_bypass := UInt<1>("h00") io.rocc.mem.resp.bits.has_data := UInt<1>("h00") io.rocc.mem.resp.bits.replay := UInt<1>("h00") io.rocc.mem.resp.bits.nack := UInt<1>("h00") io.rocc.mem.resp.bits.data := UInt<1>("h00") io.rocc.mem.resp.bits.typ := UInt<1>("h00") io.rocc.mem.resp.bits.cmd := UInt<1>("h00") io.rocc.mem.resp.bits.tag := UInt<1>("h00") io.rocc.mem.resp.bits.addr := UInt<1>("h00") io.rocc.mem.resp.valid := UInt<1>("h00") io.rocc.mem.req.ready := UInt<1>("h00") io.rocc.resp.ready := UInt<1>("h00") io.rocc.cmd.bits.rs2 := UInt<1>("h00") io.rocc.cmd.bits.rs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.opcode := UInt<1>("h00") io.rocc.cmd.bits.inst.rd := UInt<1>("h00") io.rocc.cmd.bits.inst.xs2 := UInt<1>("h00") io.rocc.cmd.bits.inst.xs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.xd := UInt<1>("h00") io.rocc.cmd.bits.inst.rs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.rs2 := UInt<1>("h00") io.rocc.cmd.bits.inst.funct := UInt<1>("h00") io.rocc.cmd.valid := UInt<1>("h00") io.fcsr_rm := UInt<1>("h00") io.time := UInt<1>("h00") io.fatc := UInt<1>("h00") io.evec := UInt<1>("h00") io.ptbr := UInt<1>("h00") io.status.ie := UInt<1>("h00") io.status.prv := UInt<1>("h00") io.status.ie1 := UInt<1>("h00") io.status.prv1 := UInt<1>("h00") io.status.ie2 := UInt<1>("h00") io.status.prv2 := UInt<1>("h00") io.status.ie3 := UInt<1>("h00") io.status.prv3 := UInt<1>("h00") io.status.fs := UInt<1>("h00") io.status.xs := UInt<1>("h00") io.status.mprv := UInt<1>("h00") io.status.vm := UInt<1>("h00") io.status.zero1 := UInt<1>("h00") io.status.sd_rv32 := UInt<1>("h00") io.status.zero2 := UInt<1>("h00") io.status.sd := UInt<1>("h00") io.eret := UInt<1>("h00") io.csr_xcpt := UInt<1>("h00") io.csr_stall := UInt<1>("h00") io.csr_replay := UInt<1>("h00") io.rw.rdata := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.ipi_rep.ready := UInt<1>("h00") io.host.ipi_req.bits := UInt<1>("h00") io.host.ipi_req.valid := UInt<1>("h00") io.host.pcr.resp.bits := UInt<1>("h00") io.host.pcr.resp.valid := UInt<1>("h00") io.host.pcr.req.ready := UInt<1>("h00") reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clock, reset wire T_2332 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_2332.usip := UInt<1>("h00") T_2332.ssip := UInt<1>("h00") T_2332.hsip := UInt<1>("h00") T_2332.msip := UInt<1>("h00") T_2332.utip := UInt<1>("h00") T_2332.stip := UInt<1>("h00") T_2332.htip := UInt<1>("h00") T_2332.mtip := UInt<1>("h00") T_2332.usip := UInt<1>("h00") T_2332.ssip := UInt<1>("h00") T_2332.hsip := UInt<1>("h00") T_2332.msip := UInt<1>("h00") T_2332.utip := UInt<1>("h00") T_2332.stip := UInt<1>("h00") T_2332.htip := UInt<1>("h00") T_2332.mtip := UInt<1>("h00") reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset onreset reg_mie := T_2332 wire T_2385 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_2385.usip := UInt<1>("h00") T_2385.ssip := UInt<1>("h00") T_2385.hsip := UInt<1>("h00") T_2385.msip := UInt<1>("h00") T_2385.utip := UInt<1>("h00") T_2385.stip := UInt<1>("h00") T_2385.htip := UInt<1>("h00") T_2385.mtip := UInt<1>("h00") T_2385.usip := UInt<1>("h00") T_2385.ssip := UInt<1>("h00") T_2385.hsip := UInt<1>("h00") T_2385.msip := UInt<1>("h00") T_2385.utip := UInt<1>("h00") T_2385.stip := UInt<1>("h00") T_2385.htip := UInt<1>("h00") T_2385.mtip := UInt<1>("h00") reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset onreset reg_mip := T_2385 reg reg_mepc : UInt<40>, clock, reset reg reg_mcause : UInt<64>, clock, reset reg reg_mbadaddr : UInt<40>, clock, reset reg reg_mscratch : UInt<64>, clock, reset reg reg_sepc : UInt<40>, clock, reset reg reg_scause : UInt<64>, clock, reset reg reg_sbadaddr : UInt<40>, clock, reset reg reg_sscratch : UInt<64>, clock, reset reg reg_stvec : UInt<39>, clock, reset reg reg_mtimecmp : UInt<64>, clock, reset reg reg_sptbr : UInt<32>, clock, reset reg reg_wfi : UInt<1>, clock, reset onreset reg_wfi := UInt<1>("h00") reg reg_tohost : UInt<64>, clock, reset onreset reg_tohost := UInt<64>("h00") reg reg_fromhost : UInt<64>, clock, reset onreset reg_fromhost := UInt<64>("h00") reg reg_stats : UInt<1>, clock, reset onreset reg_stats := UInt<1>("h00") reg reg_time : UInt<64>, clock, reset reg T_2452 : UInt<6>, clock, reset onreset T_2452 := UInt<6>("h00") node T_2454 = neq(io.retire, UInt<1>("h00")) node T_2456 = addw(T_2452, UInt<7>("h01")) when T_2454 : node T_2457 = bits(T_2456, 5, 0) T_2452 := T_2457 skip reg T_2459 : UInt<58>, clock, reset onreset T_2459 := UInt<58>("h00") node T_2460 = bit(T_2456, 6) node T_2461 = and(T_2454, T_2460) when T_2461 : node T_2463 = addw(T_2459, UInt<1>("h01")) T_2459 := T_2463 skip node T_2464 = cat(T_2459, T_2452) reg T_2467 : UInt<6>, clock, reset onreset T_2467 := UInt<6>("h00") node T_2469 = neq(UInt<1>("h01"), UInt<1>("h00")) node T_2471 = addw(T_2467, UInt<7>("h01")) when T_2469 : node T_2472 = bits(T_2471, 5, 0) T_2467 := T_2472 skip reg T_2474 : UInt<58>, clock, reset onreset T_2474 := UInt<58>("h00") node T_2475 = bit(T_2471, 6) node T_2476 = and(T_2469, T_2475) when T_2476 : node T_2478 = addw(T_2474, UInt<1>("h01")) T_2474 := T_2478 skip node T_2479 = cat(T_2474, T_2467) reg T_2481 : UInt<6>, clock, reset onreset T_2481 := UInt<6>("h00") node T_2483 = neq(io.uarch_counters[0], UInt<1>("h00")) node T_2485 = addw(T_2481, UInt<7>("h01")) when T_2483 : node T_2486 = bits(T_2485, 5, 0) T_2481 := T_2486 skip reg T_2488 : UInt<58>, clock, reset onreset T_2488 := UInt<58>("h00") node T_2489 = bit(T_2485, 6) node T_2490 = and(T_2483, T_2489) when T_2490 : node T_2492 = addw(T_2488, UInt<1>("h01")) T_2488 := T_2492 skip node T_2493 = cat(T_2488, T_2481) reg T_2495 : UInt<6>, clock, reset onreset T_2495 := UInt<6>("h00") node T_2497 = neq(io.uarch_counters[1], UInt<1>("h00")) node T_2499 = addw(T_2495, UInt<7>("h01")) when T_2497 : node T_2500 = bits(T_2499, 5, 0) T_2495 := T_2500 skip reg T_2502 : UInt<58>, clock, reset onreset T_2502 := UInt<58>("h00") node T_2503 = bit(T_2499, 6) node T_2504 = and(T_2497, T_2503) when T_2504 : node T_2506 = addw(T_2502, UInt<1>("h01")) T_2502 := T_2506 skip node T_2507 = cat(T_2502, T_2495) reg T_2509 : UInt<6>, clock, reset onreset T_2509 := UInt<6>("h00") node T_2511 = neq(io.uarch_counters[2], UInt<1>("h00")) node T_2513 = addw(T_2509, UInt<7>("h01")) when T_2511 : node T_2514 = bits(T_2513, 5, 0) T_2509 := T_2514 skip reg T_2516 : UInt<58>, clock, reset onreset T_2516 := UInt<58>("h00") node T_2517 = bit(T_2513, 6) node T_2518 = and(T_2511, T_2517) when T_2518 : node T_2520 = addw(T_2516, UInt<1>("h01")) T_2516 := T_2520 skip node T_2521 = cat(T_2516, T_2509) reg T_2523 : UInt<6>, clock, reset onreset T_2523 := UInt<6>("h00") node T_2525 = neq(io.uarch_counters[3], UInt<1>("h00")) node T_2527 = addw(T_2523, UInt<7>("h01")) when T_2525 : node T_2528 = bits(T_2527, 5, 0) T_2523 := T_2528 skip reg T_2530 : UInt<58>, clock, reset onreset T_2530 := UInt<58>("h00") node T_2531 = bit(T_2527, 6) node T_2532 = and(T_2525, T_2531) when T_2532 : node T_2534 = addw(T_2530, UInt<1>("h01")) T_2530 := T_2534 skip node T_2535 = cat(T_2530, T_2523) reg T_2537 : UInt<6>, clock, reset onreset T_2537 := UInt<6>("h00") node T_2539 = neq(io.uarch_counters[4], UInt<1>("h00")) node T_2541 = addw(T_2537, UInt<7>("h01")) when T_2539 : node T_2542 = bits(T_2541, 5, 0) T_2537 := T_2542 skip reg T_2544 : UInt<58>, clock, reset onreset T_2544 := UInt<58>("h00") node T_2545 = bit(T_2541, 6) node T_2546 = and(T_2539, T_2545) when T_2546 : node T_2548 = addw(T_2544, UInt<1>("h01")) T_2544 := T_2548 skip node T_2549 = cat(T_2544, T_2537) reg T_2551 : UInt<6>, clock, reset onreset T_2551 := UInt<6>("h00") node T_2553 = neq(io.uarch_counters[5], UInt<1>("h00")) node T_2555 = addw(T_2551, UInt<7>("h01")) when T_2553 : node T_2556 = bits(T_2555, 5, 0) T_2551 := T_2556 skip reg T_2558 : UInt<58>, clock, reset onreset T_2558 := UInt<58>("h00") node T_2559 = bit(T_2555, 6) node T_2560 = and(T_2553, T_2559) when T_2560 : node T_2562 = addw(T_2558, UInt<1>("h01")) T_2558 := T_2562 skip node T_2563 = cat(T_2558, T_2551) reg T_2565 : UInt<6>, clock, reset onreset T_2565 := UInt<6>("h00") node T_2567 = neq(io.uarch_counters[6], UInt<1>("h00")) node T_2569 = addw(T_2565, UInt<7>("h01")) when T_2567 : node T_2570 = bits(T_2569, 5, 0) T_2565 := T_2570 skip reg T_2572 : UInt<58>, clock, reset onreset T_2572 := UInt<58>("h00") node T_2573 = bit(T_2569, 6) node T_2574 = and(T_2567, T_2573) when T_2574 : node T_2576 = addw(T_2572, UInt<1>("h01")) T_2572 := T_2576 skip node T_2577 = cat(T_2572, T_2565) reg T_2579 : UInt<6>, clock, reset onreset T_2579 := UInt<6>("h00") node T_2581 = neq(io.uarch_counters[7], UInt<1>("h00")) node T_2583 = addw(T_2579, UInt<7>("h01")) when T_2581 : node T_2584 = bits(T_2583, 5, 0) T_2579 := T_2584 skip reg T_2586 : UInt<58>, clock, reset onreset T_2586 := UInt<58>("h00") node T_2587 = bit(T_2583, 6) node T_2588 = and(T_2581, T_2587) when T_2588 : node T_2590 = addw(T_2586, UInt<1>("h01")) T_2586 := T_2590 skip node T_2591 = cat(T_2586, T_2579) reg T_2593 : UInt<6>, clock, reset onreset T_2593 := UInt<6>("h00") node T_2595 = neq(io.uarch_counters[8], UInt<1>("h00")) node T_2597 = addw(T_2593, UInt<7>("h01")) when T_2595 : node T_2598 = bits(T_2597, 5, 0) T_2593 := T_2598 skip reg T_2600 : UInt<58>, clock, reset onreset T_2600 := UInt<58>("h00") node T_2601 = bit(T_2597, 6) node T_2602 = and(T_2595, T_2601) when T_2602 : node T_2604 = addw(T_2600, UInt<1>("h01")) T_2600 := T_2604 skip node T_2605 = cat(T_2600, T_2593) reg T_2607 : UInt<6>, clock, reset onreset T_2607 := UInt<6>("h00") node T_2609 = neq(io.uarch_counters[9], UInt<1>("h00")) node T_2611 = addw(T_2607, UInt<7>("h01")) when T_2609 : node T_2612 = bits(T_2611, 5, 0) T_2607 := T_2612 skip reg T_2614 : UInt<58>, clock, reset onreset T_2614 := UInt<58>("h00") node T_2615 = bit(T_2611, 6) node T_2616 = and(T_2609, T_2615) when T_2616 : node T_2618 = addw(T_2614, UInt<1>("h01")) T_2614 := T_2618 skip node T_2619 = cat(T_2614, T_2607) reg T_2621 : UInt<6>, clock, reset onreset T_2621 := UInt<6>("h00") node T_2623 = neq(io.uarch_counters[10], UInt<1>("h00")) node T_2625 = addw(T_2621, UInt<7>("h01")) when T_2623 : node T_2626 = bits(T_2625, 5, 0) T_2621 := T_2626 skip reg T_2628 : UInt<58>, clock, reset onreset T_2628 := UInt<58>("h00") node T_2629 = bit(T_2625, 6) node T_2630 = and(T_2623, T_2629) when T_2630 : node T_2632 = addw(T_2628, UInt<1>("h01")) T_2628 := T_2632 skip node T_2633 = cat(T_2628, T_2621) reg T_2635 : UInt<6>, clock, reset onreset T_2635 := UInt<6>("h00") node T_2637 = neq(io.uarch_counters[11], UInt<1>("h00")) node T_2639 = addw(T_2635, UInt<7>("h01")) when T_2637 : node T_2640 = bits(T_2639, 5, 0) T_2635 := T_2640 skip reg T_2642 : UInt<58>, clock, reset onreset T_2642 := UInt<58>("h00") node T_2643 = bit(T_2639, 6) node T_2644 = and(T_2637, T_2643) when T_2644 : node T_2646 = addw(T_2642, UInt<1>("h01")) T_2642 := T_2646 skip node T_2647 = cat(T_2642, T_2635) reg T_2649 : UInt<6>, clock, reset onreset T_2649 := UInt<6>("h00") node T_2651 = neq(io.uarch_counters[12], UInt<1>("h00")) node T_2653 = addw(T_2649, UInt<7>("h01")) when T_2651 : node T_2654 = bits(T_2653, 5, 0) T_2649 := T_2654 skip reg T_2656 : UInt<58>, clock, reset onreset T_2656 := UInt<58>("h00") node T_2657 = bit(T_2653, 6) node T_2658 = and(T_2651, T_2657) when T_2658 : node T_2660 = addw(T_2656, UInt<1>("h01")) T_2656 := T_2660 skip node T_2661 = cat(T_2656, T_2649) reg T_2663 : UInt<6>, clock, reset onreset T_2663 := UInt<6>("h00") node T_2665 = neq(io.uarch_counters[13], UInt<1>("h00")) node T_2667 = addw(T_2663, UInt<7>("h01")) when T_2665 : node T_2668 = bits(T_2667, 5, 0) T_2663 := T_2668 skip reg T_2670 : UInt<58>, clock, reset onreset T_2670 := UInt<58>("h00") node T_2671 = bit(T_2667, 6) node T_2672 = and(T_2665, T_2671) when T_2672 : node T_2674 = addw(T_2670, UInt<1>("h01")) T_2670 := T_2674 skip node T_2675 = cat(T_2670, T_2663) reg T_2677 : UInt<6>, clock, reset onreset T_2677 := UInt<6>("h00") node T_2679 = neq(io.uarch_counters[14], UInt<1>("h00")) node T_2681 = addw(T_2677, UInt<7>("h01")) when T_2679 : node T_2682 = bits(T_2681, 5, 0) T_2677 := T_2682 skip reg T_2684 : UInt<58>, clock, reset onreset T_2684 := UInt<58>("h00") node T_2685 = bit(T_2681, 6) node T_2686 = and(T_2679, T_2685) when T_2686 : node T_2688 = addw(T_2684, UInt<1>("h01")) T_2684 := T_2688 skip node T_2689 = cat(T_2684, T_2677) reg T_2691 : UInt<6>, clock, reset onreset T_2691 := UInt<6>("h00") node T_2693 = neq(io.uarch_counters[15], UInt<1>("h00")) node T_2695 = addw(T_2691, UInt<7>("h01")) when T_2693 : node T_2696 = bits(T_2695, 5, 0) T_2691 := T_2696 skip reg T_2698 : UInt<58>, clock, reset onreset T_2698 := UInt<58>("h00") node T_2699 = bit(T_2695, 6) node T_2700 = and(T_2693, T_2699) when T_2700 : node T_2702 = addw(T_2698, UInt<1>("h01")) T_2698 := T_2702 skip node T_2703 = cat(T_2698, T_2691) reg reg_fflags : UInt<5>, clock, reset reg reg_frm : UInt<3>, clock, reset node irq_rocc = and(UInt<1>("h00"), io.rocc.interrupt) io.interrupt_cause := UInt<1>("h00") node T_2711 = bit(io.interrupt_cause, 63) io.interrupt := T_2711 wire some_interrupt_pending : UInt<1> some_interrupt_pending := UInt<1>("h00") node T_2715 = and(reg_mie.ssip, reg_mip.ssip) node T_2716 = lt(reg_mstatus.prv, UInt<1>("h01")) node T_2717 = eq(reg_mstatus.prv, UInt<1>("h01")) node T_2718 = and(T_2717, reg_mstatus.ie) node T_2719 = or(T_2716, T_2718) node T_2720 = and(T_2715, T_2719) when T_2720 : io.interrupt_cause := UInt<64>("h08000000000000000") skip node T_2722 = leq(reg_mstatus.prv, UInt<1>("h01")) node T_2723 = and(T_2715, T_2722) when T_2723 : some_interrupt_pending := UInt<1>("h01") skip node T_2726 = and(reg_mie.msip, reg_mip.msip) node T_2727 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_2728 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_2729 = and(T_2728, reg_mstatus.ie) node T_2730 = or(T_2727, T_2729) node T_2731 = and(T_2726, T_2730) when T_2731 : io.interrupt_cause := UInt<64>("h08000000000000000") skip node T_2733 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_2734 = and(T_2726, T_2733) when T_2734 : some_interrupt_pending := UInt<1>("h01") skip node T_2737 = and(reg_mie.stip, reg_mip.stip) node T_2738 = lt(reg_mstatus.prv, UInt<1>("h01")) node T_2739 = eq(reg_mstatus.prv, UInt<1>("h01")) node T_2740 = and(T_2739, reg_mstatus.ie) node T_2741 = or(T_2738, T_2740) node T_2742 = and(T_2737, T_2741) when T_2742 : io.interrupt_cause := UInt<64>("h08000000000000001") skip node T_2744 = leq(reg_mstatus.prv, UInt<1>("h01")) node T_2745 = and(T_2737, T_2744) when T_2745 : some_interrupt_pending := UInt<1>("h01") skip node T_2748 = and(reg_mie.mtip, reg_mip.mtip) node T_2749 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_2750 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_2751 = and(T_2750, reg_mstatus.ie) node T_2752 = or(T_2749, T_2751) node T_2753 = and(T_2748, T_2752) when T_2753 : io.interrupt_cause := UInt<64>("h08000000000000001") skip node T_2755 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_2756 = and(T_2748, T_2755) when T_2756 : some_interrupt_pending := UInt<1>("h01") skip node T_2760 = neq(reg_fromhost, UInt<1>("h00")) node T_2761 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_2762 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_2763 = and(T_2762, reg_mstatus.ie) node T_2764 = or(T_2761, T_2763) node T_2765 = and(T_2760, T_2764) when T_2765 : io.interrupt_cause := UInt<64>("h08000000000000002") skip node T_2767 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_2768 = and(T_2760, T_2767) when T_2768 : some_interrupt_pending := UInt<1>("h01") skip node T_2771 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_2772 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_2773 = and(T_2772, reg_mstatus.ie) node T_2774 = or(T_2771, T_2773) node T_2775 = and(irq_rocc, T_2774) when T_2775 : io.interrupt_cause := UInt<64>("h08000000000000003") skip node T_2777 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_2778 = and(irq_rocc, T_2777) when T_2778 : some_interrupt_pending := UInt<1>("h01") skip node system_insn = eq(io.rw.cmd, UInt<3>("h04")) node T_2781 = neq(io.rw.cmd, UInt<3>("h00")) node T_2783 = eq(system_insn, UInt<1>("h00")) node cpu_ren = and(T_2781, T_2783) reg host_pcr_req_valid : UInt<1>, clock, reset node T_2788 = eq(cpu_ren, UInt<1>("h00")) node host_pcr_req_fire = and(host_pcr_req_valid, T_2788) reg host_pcr_rep_valid : UInt<1>, clock, reset reg host_pcr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clock, reset node T_2797 = eq(host_pcr_req_valid, UInt<1>("h00")) node T_2799 = eq(host_pcr_rep_valid, UInt<1>("h00")) node T_2800 = and(T_2797, T_2799) io.host.pcr.req.ready := T_2800 io.host.pcr.resp.valid := host_pcr_rep_valid io.host.pcr.resp.bits := host_pcr_bits.data node T_2801 = and(io.host.pcr.req.ready, io.host.pcr.req.valid) when T_2801 : host_pcr_req_valid := UInt<1>("h01") host_pcr_bits <> io.host.pcr.req.bits skip when host_pcr_req_fire : host_pcr_req_valid := UInt<1>("h00") host_pcr_rep_valid := UInt<1>("h01") host_pcr_bits.data := io.rw.rdata skip node T_2805 = and(io.host.pcr.resp.ready, io.host.pcr.resp.valid) when T_2805 : host_pcr_rep_valid := UInt<1>("h00") skip io.host.debug_stats_pcr := reg_stats node T_2807 = cat(io.status.sd, io.status.zero2) node T_2808 = cat(io.status.sd_rv32, io.status.zero1) node T_2809 = cat(T_2807, T_2808) node T_2810 = cat(io.status.vm, io.status.mprv) node T_2811 = cat(io.status.xs, io.status.fs) node T_2812 = cat(T_2810, T_2811) node T_2813 = cat(T_2809, T_2812) node T_2814 = cat(io.status.prv3, io.status.ie3) node T_2815 = cat(io.status.prv2, io.status.ie2) node T_2816 = cat(T_2814, T_2815) node T_2817 = cat(io.status.prv1, io.status.ie1) node T_2818 = cat(io.status.prv, io.status.ie) node T_2819 = cat(T_2817, T_2818) node T_2820 = cat(T_2816, T_2819) node read_mstatus = cat(T_2813, T_2820) node T_2822 = cat(reg_frm, reg_fflags) node T_2828 = cat(reg_mip.mtip, reg_mip.htip) node T_2829 = cat(reg_mip.stip, reg_mip.utip) node T_2830 = cat(T_2828, T_2829) node T_2831 = cat(reg_mip.msip, reg_mip.hsip) node T_2832 = cat(reg_mip.ssip, reg_mip.usip) node T_2833 = cat(T_2831, T_2832) node T_2834 = cat(T_2830, T_2833) node T_2835 = cat(reg_mie.mtip, reg_mie.htip) node T_2836 = cat(reg_mie.stip, reg_mie.utip) node T_2837 = cat(T_2835, T_2836) node T_2838 = cat(reg_mie.msip, reg_mie.hsip) node T_2839 = cat(reg_mie.ssip, reg_mie.usip) node T_2840 = cat(T_2838, T_2839) node T_2841 = cat(T_2837, T_2840) node T_2842 = bit(reg_mepc, 39) node T_2844 = subw(UInt<24>("h00"), T_2842) node T_2845 = cat(T_2844, reg_mepc) node T_2846 = bit(reg_mbadaddr, 39) node T_2848 = subw(UInt<24>("h00"), T_2846) node T_2849 = cat(T_2848, reg_mbadaddr) wire T_2876 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_2876.ie := UInt<1>("h00") T_2876.zero1 := UInt<1>("h00") T_2876.pie := UInt<1>("h00") T_2876.ps := UInt<1>("h00") T_2876.zero2 := UInt<1>("h00") T_2876.fs := UInt<1>("h00") T_2876.xs := UInt<1>("h00") T_2876.mprv := UInt<1>("h00") T_2876.zero3 := UInt<1>("h00") T_2876.sd_rv32 := UInt<1>("h00") T_2876.zero4 := UInt<1>("h00") T_2876.sd := UInt<1>("h00") node T_2901 = bits(read_mstatus, 0, 0) T_2876.ie := T_2901 node T_2902 = bits(read_mstatus, 2, 1) T_2876.zero1 := T_2902 node T_2903 = bits(read_mstatus, 3, 3) T_2876.pie := T_2903 node T_2904 = bits(read_mstatus, 4, 4) T_2876.ps := T_2904 node T_2905 = bits(read_mstatus, 11, 5) T_2876.zero2 := T_2905 node T_2906 = bits(read_mstatus, 13, 12) T_2876.fs := T_2906 node T_2907 = bits(read_mstatus, 15, 14) T_2876.xs := T_2907 node T_2908 = bits(read_mstatus, 16, 16) T_2876.mprv := T_2908 node T_2909 = bits(read_mstatus, 30, 17) T_2876.zero3 := T_2909 node T_2910 = bits(read_mstatus, 31, 31) T_2876.sd_rv32 := T_2910 node T_2911 = bits(read_mstatus, 62, 32) T_2876.zero4 := T_2911 node T_2912 = bits(read_mstatus, 63, 63) T_2876.sd := T_2912 wire T_2913 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_2913 <> T_2876 T_2913.zero1 := UInt<1>("h00") T_2913.zero2 := UInt<1>("h00") T_2913.zero3 := UInt<1>("h00") T_2913.zero4 := UInt<1>("h00") wire T_2949 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_2949.usip := UInt<1>("h00") T_2949.ssip := UInt<1>("h00") T_2949.hsip := UInt<1>("h00") T_2949.msip := UInt<1>("h00") T_2949.utip := UInt<1>("h00") T_2949.stip := UInt<1>("h00") T_2949.htip := UInt<1>("h00") T_2949.mtip := UInt<1>("h00") T_2949.usip := UInt<1>("h00") T_2949.ssip := UInt<1>("h00") T_2949.hsip := UInt<1>("h00") T_2949.msip := UInt<1>("h00") T_2949.utip := UInt<1>("h00") T_2949.stip := UInt<1>("h00") T_2949.htip := UInt<1>("h00") T_2949.mtip := UInt<1>("h00") wire T_2974 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_2974 <> T_2949 T_2974.ssip := reg_mip.ssip T_2974.stip := reg_mip.stip wire T_3002 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3002.usip := UInt<1>("h00") T_3002.ssip := UInt<1>("h00") T_3002.hsip := UInt<1>("h00") T_3002.msip := UInt<1>("h00") T_3002.utip := UInt<1>("h00") T_3002.stip := UInt<1>("h00") T_3002.htip := UInt<1>("h00") T_3002.mtip := UInt<1>("h00") T_3002.usip := UInt<1>("h00") T_3002.ssip := UInt<1>("h00") T_3002.hsip := UInt<1>("h00") T_3002.msip := UInt<1>("h00") T_3002.utip := UInt<1>("h00") T_3002.stip := UInt<1>("h00") T_3002.htip := UInt<1>("h00") T_3002.mtip := UInt<1>("h00") wire T_3027 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3027 <> T_3002 T_3027.ssip := reg_mie.ssip T_3027.stip := reg_mie.stip node T_3036 = cat(T_2913.zero4, T_2913.sd_rv32) node T_3037 = cat(T_2913.sd, T_3036) node T_3038 = cat(T_2913.mprv, T_2913.xs) node T_3039 = cat(T_2913.zero3, T_3038) node T_3040 = cat(T_3037, T_3039) node T_3041 = cat(T_2913.zero2, T_2913.ps) node T_3042 = cat(T_2913.fs, T_3041) node T_3043 = cat(T_2913.zero1, T_2913.ie) node T_3044 = cat(T_2913.pie, T_3043) node T_3045 = cat(T_3042, T_3044) node T_3046 = cat(T_3040, T_3045) node T_3047 = cat(T_2974.mtip, T_2974.htip) node T_3048 = cat(T_2974.stip, T_2974.utip) node T_3049 = cat(T_3047, T_3048) node T_3050 = cat(T_2974.msip, T_2974.hsip) node T_3051 = cat(T_2974.ssip, T_2974.usip) node T_3052 = cat(T_3050, T_3051) node T_3053 = cat(T_3049, T_3052) node T_3054 = cat(T_3027.mtip, T_3027.htip) node T_3055 = cat(T_3027.stip, T_3027.utip) node T_3056 = cat(T_3054, T_3055) node T_3057 = cat(T_3027.msip, T_3027.hsip) node T_3058 = cat(T_3027.ssip, T_3027.usip) node T_3059 = cat(T_3057, T_3058) node T_3060 = cat(T_3056, T_3059) node T_3061 = bit(reg_sbadaddr, 39) node T_3063 = subw(UInt<24>("h00"), T_3061) node T_3064 = cat(T_3063, reg_sbadaddr) node T_3066 = bit(reg_sepc, 39) node T_3068 = subw(UInt<24>("h00"), T_3066) node T_3069 = cat(T_3068, reg_sepc) node T_3070 = bit(reg_stvec, 38) node T_3072 = subw(UInt<25>("h00"), T_3070) node T_3073 = cat(T_3072, reg_stvec) node addr = mux(cpu_ren, io.rw.addr, host_pcr_bits.addr) node T_3076 = eq(addr, UInt<1>("h01")) node T_3078 = eq(addr, UInt<2>("h02")) node T_3080 = eq(addr, UInt<2>("h03")) node T_3082 = eq(addr, UInt<12>("h0c00")) node T_3084 = eq(addr, UInt<12>("h0900")) node T_3086 = eq(addr, UInt<12>("h0c01")) node T_3088 = eq(addr, UInt<12>("h0901")) node T_3090 = eq(addr, UInt<12>("h0d01")) node T_3092 = eq(addr, UInt<12>("h0a01")) node T_3094 = eq(addr, UInt<11>("h0701")) node T_3096 = eq(addr, UInt<12>("h0f00")) node T_3098 = eq(addr, UInt<12>("h0f01")) node T_3100 = eq(addr, UInt<10>("h0300")) node T_3102 = eq(addr, UInt<10>("h0302")) node T_3104 = eq(addr, UInt<11>("h0782")) node T_3106 = eq(addr, UInt<10>("h0301")) node T_3108 = eq(addr, UInt<10>("h0344")) node T_3110 = eq(addr, UInt<10>("h0304")) node T_3112 = eq(addr, UInt<10>("h0340")) node T_3114 = eq(addr, UInt<10>("h0341")) node T_3116 = eq(addr, UInt<10>("h0343")) node T_3118 = eq(addr, UInt<10>("h0342")) node T_3120 = eq(addr, UInt<10>("h0321")) node T_3122 = eq(addr, UInt<12>("h0f10")) node T_3124 = eq(addr, UInt<11>("h0783")) node T_3126 = eq(addr, UInt<8>("h0c0")) node T_3128 = eq(addr, UInt<11>("h0780")) node T_3130 = eq(addr, UInt<11>("h0781")) node T_3132 = eq(addr, UInt<12>("h0c02")) node T_3134 = eq(addr, UInt<12>("h0902")) node T_3136 = eq(addr, UInt<12>("h0cc0")) node T_3138 = eq(addr, UInt<12>("h0cc1")) node T_3140 = eq(addr, UInt<12>("h0cc2")) node T_3142 = eq(addr, UInt<12>("h0cc3")) node T_3144 = eq(addr, UInt<12>("h0cc4")) node T_3146 = eq(addr, UInt<12>("h0cc5")) node T_3148 = eq(addr, UInt<12>("h0cc6")) node T_3150 = eq(addr, UInt<12>("h0cc7")) node T_3152 = eq(addr, UInt<12>("h0cc8")) node T_3154 = eq(addr, UInt<12>("h0cc9")) node T_3156 = eq(addr, UInt<12>("h0cca")) node T_3158 = eq(addr, UInt<12>("h0ccb")) node T_3160 = eq(addr, UInt<12>("h0ccc")) node T_3162 = eq(addr, UInt<12>("h0ccd")) node T_3164 = eq(addr, UInt<12>("h0cce")) node T_3166 = eq(addr, UInt<12>("h0ccf")) node T_3168 = eq(addr, UInt<9>("h0100")) node T_3170 = eq(addr, UInt<9>("h0144")) node T_3172 = eq(addr, UInt<9>("h0104")) node T_3174 = eq(addr, UInt<9>("h0140")) node T_3176 = eq(addr, UInt<12>("h0d42")) node T_3178 = eq(addr, UInt<12>("h0d43")) node T_3180 = eq(addr, UInt<9>("h0180")) node T_3182 = eq(addr, UInt<9>("h0181")) node T_3184 = eq(addr, UInt<9>("h0141")) node T_3186 = eq(addr, UInt<9>("h0101")) node T_3187 = or(T_3076, T_3078) node T_3188 = or(T_3187, T_3080) node T_3189 = or(T_3188, T_3082) node T_3190 = or(T_3189, T_3084) node T_3191 = or(T_3190, T_3086) node T_3192 = or(T_3191, T_3088) node T_3193 = or(T_3192, T_3090) node T_3194 = or(T_3193, T_3092) node T_3195 = or(T_3194, T_3094) node T_3196 = or(T_3195, T_3096) node T_3197 = or(T_3196, T_3098) node T_3198 = or(T_3197, T_3100) node T_3199 = or(T_3198, T_3102) node T_3200 = or(T_3199, T_3104) node T_3201 = or(T_3200, T_3106) node T_3202 = or(T_3201, T_3108) node T_3203 = or(T_3202, T_3110) node T_3204 = or(T_3203, T_3112) node T_3205 = or(T_3204, T_3114) node T_3206 = or(T_3205, T_3116) node T_3207 = or(T_3206, T_3118) node T_3208 = or(T_3207, T_3120) node T_3209 = or(T_3208, T_3122) node T_3210 = or(T_3209, T_3124) node T_3211 = or(T_3210, T_3126) node T_3212 = or(T_3211, T_3128) node T_3213 = or(T_3212, T_3130) node T_3214 = or(T_3213, T_3132) node T_3215 = or(T_3214, T_3134) node T_3216 = or(T_3215, T_3136) node T_3217 = or(T_3216, T_3138) node T_3218 = or(T_3217, T_3140) node T_3219 = or(T_3218, T_3142) node T_3220 = or(T_3219, T_3144) node T_3221 = or(T_3220, T_3146) node T_3222 = or(T_3221, T_3148) node T_3223 = or(T_3222, T_3150) node T_3224 = or(T_3223, T_3152) node T_3225 = or(T_3224, T_3154) node T_3226 = or(T_3225, T_3156) node T_3227 = or(T_3226, T_3158) node T_3228 = or(T_3227, T_3160) node T_3229 = or(T_3228, T_3162) node T_3230 = or(T_3229, T_3164) node T_3231 = or(T_3230, T_3166) node T_3232 = or(T_3231, T_3168) node T_3233 = or(T_3232, T_3170) node T_3234 = or(T_3233, T_3172) node T_3235 = or(T_3234, T_3174) node T_3236 = or(T_3235, T_3176) node T_3237 = or(T_3236, T_3178) node T_3238 = or(T_3237, T_3180) node T_3239 = or(T_3238, T_3182) node T_3240 = or(T_3239, T_3184) node addr_valid = or(T_3240, T_3186) node T_3242 = or(T_3076, T_3078) node fp_csr = or(T_3242, T_3080) node csr_addr_priv = bits(io.rw.addr, 9, 8) node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) node T_3246 = bits(io.rw.addr, 11, 10) node T_3247 = not(T_3246) node read_only = eq(T_3247, UInt<1>("h00")) node T_3250 = neq(io.rw.cmd, UInt<3>("h05")) node T_3251 = and(cpu_ren, T_3250) node cpu_wen = and(T_3251, priv_sufficient) node T_3254 = eq(read_only, UInt<1>("h00")) node T_3255 = and(cpu_wen, T_3254) node T_3256 = and(host_pcr_req_fire, host_pcr_bits.rw) node wen = or(T_3255, T_3256) node T_3258 = eq(io.rw.cmd, UInt<3>("h01")) node T_3259 = eq(io.rw.cmd, UInt<3>("h03")) node T_3260 = not(io.rw.wdata) node T_3261 = and(io.rw.rdata, T_3260) node T_3262 = eq(io.rw.cmd, UInt<3>("h02")) node T_3263 = or(io.rw.rdata, io.rw.wdata) node T_3264 = mux(T_3262, T_3263, host_pcr_bits.data) node T_3265 = mux(T_3259, T_3261, T_3264) node wdata = mux(T_3258, io.rw.wdata, T_3265) node T_3267 = bit(io.rw.addr, 8) node T_3269 = eq(T_3267, UInt<1>("h00")) node T_3270 = bit(io.rw.addr, 0) node T_3272 = eq(T_3270, UInt<1>("h00")) node T_3273 = and(T_3269, T_3272) node insn_call = and(T_3273, system_insn) node T_3275 = bit(io.rw.addr, 8) node T_3277 = eq(T_3275, UInt<1>("h00")) node T_3278 = bit(io.rw.addr, 0) node T_3279 = and(T_3277, T_3278) node insn_break = and(T_3279, system_insn) node T_3281 = bit(io.rw.addr, 8) node T_3282 = bit(io.rw.addr, 1) node T_3284 = eq(T_3282, UInt<1>("h00")) node T_3285 = and(T_3281, T_3284) node T_3286 = bit(io.rw.addr, 0) node T_3288 = eq(T_3286, UInt<1>("h00")) node T_3289 = and(T_3285, T_3288) node T_3290 = and(T_3289, system_insn) node insn_ret = and(T_3290, priv_sufficient) node T_3292 = bit(io.rw.addr, 8) node T_3293 = bit(io.rw.addr, 1) node T_3295 = eq(T_3293, UInt<1>("h00")) node T_3296 = and(T_3292, T_3295) node T_3297 = bit(io.rw.addr, 0) node T_3298 = and(T_3296, T_3297) node T_3299 = and(T_3298, system_insn) node insn_sfence_vm = and(T_3299, priv_sufficient) node T_3301 = bit(io.rw.addr, 2) node maybe_insn_redirect_trap = and(T_3301, system_insn) node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) node T_3304 = bit(io.rw.addr, 8) node T_3305 = bit(io.rw.addr, 1) node T_3306 = and(T_3304, T_3305) node T_3307 = bit(io.rw.addr, 0) node T_3309 = eq(T_3307, UInt<1>("h00")) node T_3310 = and(T_3306, T_3309) node T_3311 = and(T_3310, system_insn) node insn_wfi = and(T_3311, priv_sufficient) node T_3313 = and(cpu_wen, read_only) node T_3315 = eq(priv_sufficient, UInt<1>("h00")) node T_3317 = eq(addr_valid, UInt<1>("h00")) node T_3318 = or(T_3315, T_3317) node T_3320 = neq(io.status.fs, UInt<1>("h00")) node T_3322 = eq(T_3320, UInt<1>("h00")) node T_3323 = and(fp_csr, T_3322) node T_3324 = or(T_3318, T_3323) node T_3325 = and(cpu_ren, T_3324) node T_3326 = or(T_3313, T_3325) node T_3328 = eq(priv_sufficient, UInt<1>("h00")) node T_3329 = and(system_insn, T_3328) node T_3330 = or(T_3326, T_3329) node T_3331 = or(T_3330, insn_call) node csr_xcpt = or(T_3331, insn_break) when insn_wfi : reg_wfi := UInt<1>("h01") skip when some_interrupt_pending : reg_wfi := UInt<1>("h00") skip io.fatc := insn_sfence_vm node T_3335 = or(io.exception, csr_xcpt) node T_3336 = shl(reg_mstatus.prv, 6) node T_3338 = addw(T_3336, UInt<9>("h0100")) node T_3339 = bit(reg_stvec, 38) node T_3340 = cat(T_3339, reg_stvec) node T_3341 = bit(reg_mstatus.prv, 1) node T_3342 = mux(T_3341, reg_mepc, reg_sepc) node T_3343 = mux(maybe_insn_redirect_trap, T_3340, T_3342) node T_3344 = mux(T_3335, T_3338, T_3343) io.evec := T_3344 io.ptbr := reg_sptbr io.csr_xcpt := csr_xcpt node T_3345 = or(insn_ret, insn_redirect_trap) io.eret := T_3345 io.status <> reg_mstatus node T_3347 = neq(reg_mstatus.fs, UInt<1>("h00")) node T_3349 = subw(UInt<2>("h00"), T_3347) io.status.fs := T_3349 node T_3351 = neq(reg_mstatus.xs, UInt<1>("h00")) node T_3353 = subw(UInt<2>("h00"), T_3351) io.status.xs := T_3353 node T_3354 = not(io.status.fs) node T_3356 = eq(T_3354, UInt<1>("h00")) node T_3357 = not(io.status.xs) node T_3359 = eq(T_3357, UInt<1>("h00")) node T_3360 = or(T_3356, T_3359) io.status.sd := T_3360 node T_3361 = or(io.exception, csr_xcpt) when T_3361 : reg_mstatus.ie := UInt<1>("h00") reg_mstatus.prv := UInt<2>("h03") reg_mstatus.mprv := UInt<1>("h00") reg_mstatus.prv1 := reg_mstatus.prv reg_mstatus.ie1 := reg_mstatus.ie reg_mstatus.prv2 := reg_mstatus.prv1 reg_mstatus.ie2 := reg_mstatus.ie1 node T_3365 = not(io.pc) node T_3367 = or(T_3365, UInt<2>("h03")) node T_3368 = not(T_3367) reg_mepc := T_3368 reg_mcause := io.cause when csr_xcpt : reg_mcause := UInt<2>("h02") when insn_break : reg_mcause := UInt<2>("h03") skip when insn_call : node T_3372 = addw(reg_mstatus.prv, UInt<4>("h08")) reg_mcause := T_3372 skip skip reg_mbadaddr := io.pc node T_3374 = eq(io.cause, UInt<3>("h05")) node T_3376 = eq(io.cause, UInt<3>("h04")) node T_3377 = or(T_3374, T_3376) node T_3379 = eq(io.cause, UInt<3>("h07")) node T_3380 = or(T_3377, T_3379) node T_3382 = eq(io.cause, UInt<3>("h06")) node T_3383 = or(T_3380, T_3382) when T_3383 : node T_3384 = bits(io.rw.wdata, 63, 39) node T_3385 = bits(io.rw.wdata, 38, 0) node T_3386 = asSInt(T_3385) node T_3388 = lt(T_3386, asSInt(UInt<1>("h00"))) node T_3389 = not(T_3384) node T_3391 = eq(T_3389, UInt<1>("h00")) node T_3393 = neq(T_3384, UInt<1>("h00")) node T_3394 = mux(T_3388, T_3391, T_3393) node T_3395 = cat(T_3394, T_3385) reg_mbadaddr := T_3395 skip skip when insn_ret : reg_mstatus.ie := reg_mstatus.ie1 reg_mstatus.prv := reg_mstatus.prv1 reg_mstatus.prv1 := reg_mstatus.prv2 reg_mstatus.ie1 := reg_mstatus.ie2 reg_mstatus.prv2 := UInt<1>("h00") reg_mstatus.ie2 := UInt<1>("h01") skip when insn_redirect_trap : reg_mstatus.prv := UInt<1>("h01") reg_sbadaddr := reg_mbadaddr reg_scause := reg_mcause reg_sepc := reg_mepc skip node T_3400 = cat(UInt<1>("h00"), insn_redirect_trap) node T_3401 = addw(insn_ret, T_3400) node T_3405 = cat(UInt<1>("h00"), io.csr_replay) node T_3406 = addw(csr_xcpt, T_3405) node T_3407 = cat(UInt<1>("h00"), T_3406) node T_3408 = addw(io.exception, T_3407) node T_3409 = cat(UInt<1>("h00"), T_3408) node T_3410 = addw(T_3401, T_3409) node T_3412 = leq(T_3410, UInt<1>("h01")) node T_3413 = geq(reg_time, reg_mtimecmp) when T_3413 : reg_mip.mtip := UInt<1>("h01") skip io.time := T_2479 node T_3415 = and(cpu_wen, T_3124) io.host.ipi_req.valid := T_3415 io.host.ipi_req.bits := io.rw.wdata node T_3417 = eq(io.host.ipi_req.ready, UInt<1>("h00")) node T_3418 = and(io.host.ipi_req.valid, T_3417) io.csr_replay := T_3418 io.csr_stall := reg_wfi node T_3420 = eq(host_pcr_bits.rw, UInt<1>("h00")) node T_3421 = and(host_pcr_req_fire, T_3420) node T_3422 = and(T_3421, T_3128) when T_3422 : reg_tohost := UInt<1>("h00") skip node T_3425 = mux(T_3076, reg_fflags, UInt<1>("h00")) node T_3427 = mux(T_3078, reg_frm, UInt<1>("h00")) node T_3429 = mux(T_3080, T_2822, UInt<1>("h00")) node T_3431 = mux(T_3082, T_2479, UInt<1>("h00")) node T_3433 = mux(T_3084, T_2479, UInt<1>("h00")) node T_3435 = mux(T_3086, reg_time, UInt<1>("h00")) node T_3437 = mux(T_3088, reg_time, UInt<1>("h00")) node T_3439 = mux(T_3090, reg_time, UInt<1>("h00")) node T_3441 = mux(T_3092, reg_time, UInt<1>("h00")) node T_3443 = mux(T_3094, reg_time, UInt<1>("h00")) node T_3445 = mux(T_3096, UInt<64>("h08000000000041129"), UInt<1>("h00")) node T_3447 = mux(T_3098, UInt<1>("h01"), UInt<1>("h00")) node T_3449 = mux(T_3100, read_mstatus, UInt<1>("h00")) node T_3451 = mux(T_3102, UInt<1>("h00"), UInt<1>("h00")) node T_3453 = mux(T_3104, UInt<1>("h00"), UInt<1>("h00")) node T_3455 = mux(T_3106, UInt<9>("h0100"), UInt<1>("h00")) node T_3457 = mux(T_3108, T_2834, UInt<1>("h00")) node T_3459 = mux(T_3110, T_2841, UInt<1>("h00")) node T_3461 = mux(T_3112, reg_mscratch, UInt<1>("h00")) node T_3463 = mux(T_3114, T_2845, UInt<1>("h00")) node T_3465 = mux(T_3116, T_2849, UInt<1>("h00")) node T_3467 = mux(T_3118, reg_mcause, UInt<1>("h00")) node T_3469 = mux(T_3120, reg_mtimecmp, UInt<1>("h00")) node T_3471 = mux(T_3122, io.host.id, UInt<1>("h00")) node T_3473 = mux(T_3124, io.host.id, UInt<1>("h00")) node T_3475 = shl(reg_stats, 0) node T_3476 = mux(T_3126, T_3475, UInt<1>("h00")) node T_3478 = mux(T_3128, reg_tohost, UInt<1>("h00")) node T_3480 = mux(T_3130, reg_fromhost, UInt<1>("h00")) node T_3482 = mux(T_3132, T_2464, UInt<1>("h00")) node T_3484 = mux(T_3134, T_2464, UInt<1>("h00")) node T_3486 = mux(T_3136, T_2493, UInt<1>("h00")) node T_3488 = mux(T_3138, T_2507, UInt<1>("h00")) node T_3490 = mux(T_3140, T_2521, UInt<1>("h00")) node T_3492 = mux(T_3142, T_2535, UInt<1>("h00")) node T_3494 = mux(T_3144, T_2549, UInt<1>("h00")) node T_3496 = mux(T_3146, T_2563, UInt<1>("h00")) node T_3498 = mux(T_3148, T_2577, UInt<1>("h00")) node T_3500 = mux(T_3150, T_2591, UInt<1>("h00")) node T_3502 = mux(T_3152, T_2605, UInt<1>("h00")) node T_3504 = mux(T_3154, T_2619, UInt<1>("h00")) node T_3506 = mux(T_3156, T_2633, UInt<1>("h00")) node T_3508 = mux(T_3158, T_2647, UInt<1>("h00")) node T_3510 = mux(T_3160, T_2661, UInt<1>("h00")) node T_3512 = mux(T_3162, T_2675, UInt<1>("h00")) node T_3514 = mux(T_3164, T_2689, UInt<1>("h00")) node T_3516 = mux(T_3166, T_2703, UInt<1>("h00")) node T_3518 = mux(T_3168, T_3046, UInt<1>("h00")) node T_3520 = mux(T_3170, T_3053, UInt<1>("h00")) node T_3522 = mux(T_3172, T_3060, UInt<1>("h00")) node T_3524 = mux(T_3174, reg_sscratch, UInt<1>("h00")) node T_3526 = mux(T_3176, reg_scause, UInt<1>("h00")) node T_3528 = mux(T_3178, T_3064, UInt<1>("h00")) node T_3530 = mux(T_3180, reg_sptbr, UInt<1>("h00")) node T_3532 = mux(T_3182, UInt<1>("h00"), UInt<1>("h00")) node T_3534 = mux(T_3184, T_3069, UInt<1>("h00")) node T_3536 = mux(T_3186, T_3073, UInt<1>("h00")) node T_3538 = or(T_3425, T_3427) node T_3539 = or(T_3538, T_3429) node T_3540 = or(T_3539, T_3431) node T_3541 = or(T_3540, T_3433) node T_3542 = or(T_3541, T_3435) node T_3543 = or(T_3542, T_3437) node T_3544 = or(T_3543, T_3439) node T_3545 = or(T_3544, T_3441) node T_3546 = or(T_3545, T_3443) node T_3547 = or(T_3546, T_3445) node T_3548 = or(T_3547, T_3447) node T_3549 = or(T_3548, T_3449) node T_3550 = or(T_3549, T_3451) node T_3551 = or(T_3550, T_3453) node T_3552 = or(T_3551, T_3455) node T_3553 = or(T_3552, T_3457) node T_3554 = or(T_3553, T_3459) node T_3555 = or(T_3554, T_3461) node T_3556 = or(T_3555, T_3463) node T_3557 = or(T_3556, T_3465) node T_3558 = or(T_3557, T_3467) node T_3559 = or(T_3558, T_3469) node T_3560 = or(T_3559, T_3471) node T_3561 = or(T_3560, T_3473) node T_3562 = or(T_3561, T_3476) node T_3563 = or(T_3562, T_3478) node T_3564 = or(T_3563, T_3480) node T_3565 = or(T_3564, T_3482) node T_3566 = or(T_3565, T_3484) node T_3567 = or(T_3566, T_3486) node T_3568 = or(T_3567, T_3488) node T_3569 = or(T_3568, T_3490) node T_3570 = or(T_3569, T_3492) node T_3571 = or(T_3570, T_3494) node T_3572 = or(T_3571, T_3496) node T_3573 = or(T_3572, T_3498) node T_3574 = or(T_3573, T_3500) node T_3575 = or(T_3574, T_3502) node T_3576 = or(T_3575, T_3504) node T_3577 = or(T_3576, T_3506) node T_3578 = or(T_3577, T_3508) node T_3579 = or(T_3578, T_3510) node T_3580 = or(T_3579, T_3512) node T_3581 = or(T_3580, T_3514) node T_3582 = or(T_3581, T_3516) node T_3583 = or(T_3582, T_3518) node T_3584 = or(T_3583, T_3520) node T_3585 = or(T_3584, T_3522) node T_3586 = or(T_3585, T_3524) node T_3587 = or(T_3586, T_3526) node T_3588 = or(T_3587, T_3528) node T_3589 = or(T_3588, T_3530) node T_3590 = or(T_3589, T_3532) node T_3591 = or(T_3590, T_3534) node T_3592 = or(T_3591, T_3536) wire T_3593 : UInt<64> T_3593 := UInt<1>("h00") T_3593 := T_3592 io.rw.rdata := T_3593 io.fcsr_rm := reg_frm when io.fcsr_flags.valid : node T_3595 = or(reg_fflags, io.fcsr_flags.bits) reg_fflags := T_3595 skip when wen : when T_3100 : wire T_3630 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} T_3630.ie := UInt<1>("h00") T_3630.prv := UInt<1>("h00") T_3630.ie1 := UInt<1>("h00") T_3630.prv1 := UInt<1>("h00") T_3630.ie2 := UInt<1>("h00") T_3630.prv2 := UInt<1>("h00") T_3630.ie3 := UInt<1>("h00") T_3630.prv3 := UInt<1>("h00") T_3630.fs := UInt<1>("h00") T_3630.xs := UInt<1>("h00") T_3630.mprv := UInt<1>("h00") T_3630.vm := UInt<1>("h00") T_3630.zero1 := UInt<1>("h00") T_3630.sd_rv32 := UInt<1>("h00") T_3630.zero2 := UInt<1>("h00") T_3630.sd := UInt<1>("h00") node T_3663 = bits(wdata, 0, 0) T_3630.ie := T_3663 node T_3664 = bits(wdata, 2, 1) T_3630.prv := T_3664 node T_3665 = bits(wdata, 3, 3) T_3630.ie1 := T_3665 node T_3666 = bits(wdata, 5, 4) T_3630.prv1 := T_3666 node T_3667 = bits(wdata, 6, 6) T_3630.ie2 := T_3667 node T_3668 = bits(wdata, 8, 7) T_3630.prv2 := T_3668 node T_3669 = bits(wdata, 9, 9) T_3630.ie3 := T_3669 node T_3670 = bits(wdata, 11, 10) T_3630.prv3 := T_3670 node T_3671 = bits(wdata, 13, 12) T_3630.fs := T_3671 node T_3672 = bits(wdata, 15, 14) T_3630.xs := T_3672 node T_3673 = bits(wdata, 16, 16) T_3630.mprv := T_3673 node T_3674 = bits(wdata, 21, 17) T_3630.vm := T_3674 node T_3675 = bits(wdata, 30, 22) T_3630.zero1 := T_3675 node T_3676 = bits(wdata, 31, 31) T_3630.sd_rv32 := T_3676 node T_3677 = bits(wdata, 62, 32) T_3630.zero2 := T_3677 node T_3678 = bits(wdata, 63, 63) T_3630.sd := T_3678 reg_mstatus.ie := T_3630.ie reg_mstatus.ie1 := T_3630.ie1 wire T_3683 : UInt<2>[3] T_3683[0] := UInt<2>("h03") T_3683[1] := UInt<1>("h00") T_3683[2] := UInt<1>("h01") reg_mstatus.mprv := T_3630.mprv node T_3688 = eq(T_3683[0], T_3630.prv) node T_3689 = eq(T_3683[1], T_3630.prv) node T_3690 = eq(T_3683[2], T_3630.prv) node T_3692 = or(UInt<1>("h00"), T_3688) node T_3693 = or(T_3692, T_3689) node T_3694 = or(T_3693, T_3690) when T_3694 : reg_mstatus.prv := T_3630.prv skip node T_3695 = eq(T_3683[0], T_3630.prv1) node T_3696 = eq(T_3683[1], T_3630.prv1) node T_3697 = eq(T_3683[2], T_3630.prv1) node T_3699 = or(UInt<1>("h00"), T_3695) node T_3700 = or(T_3699, T_3696) node T_3701 = or(T_3700, T_3697) when T_3701 : reg_mstatus.prv1 := T_3630.prv1 skip node T_3702 = eq(T_3683[0], T_3630.prv2) node T_3703 = eq(T_3683[1], T_3630.prv2) node T_3704 = eq(T_3683[2], T_3630.prv2) node T_3706 = or(UInt<1>("h00"), T_3702) node T_3707 = or(T_3706, T_3703) node T_3708 = or(T_3707, T_3704) when T_3708 : reg_mstatus.prv2 := T_3630.prv2 skip reg_mstatus.ie2 := T_3630.ie2 node T_3710 = eq(T_3630.vm, UInt<1>("h00")) when T_3710 : reg_mstatus.vm := UInt<1>("h00") skip node T_3713 = eq(T_3630.vm, UInt<4>("h09")) when T_3713 : reg_mstatus.vm := UInt<4>("h09") skip reg_mstatus.fs := T_3630.fs skip when T_3108 : wire T_3733 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3733.usip := UInt<1>("h00") T_3733.ssip := UInt<1>("h00") T_3733.hsip := UInt<1>("h00") T_3733.msip := UInt<1>("h00") T_3733.utip := UInt<1>("h00") T_3733.stip := UInt<1>("h00") T_3733.htip := UInt<1>("h00") T_3733.mtip := UInt<1>("h00") node T_3750 = bits(wdata, 0, 0) T_3733.usip := T_3750 node T_3751 = bits(wdata, 1, 1) T_3733.ssip := T_3751 node T_3752 = bits(wdata, 2, 2) T_3733.hsip := T_3752 node T_3753 = bits(wdata, 3, 3) T_3733.msip := T_3753 node T_3754 = bits(wdata, 4, 4) T_3733.utip := T_3754 node T_3755 = bits(wdata, 5, 5) T_3733.stip := T_3755 node T_3756 = bits(wdata, 6, 6) T_3733.htip := T_3756 node T_3757 = bits(wdata, 7, 7) T_3733.mtip := T_3757 reg_mip.ssip := T_3733.ssip reg_mip.stip := T_3733.stip reg_mip.msip := T_3733.msip skip when T_3110 : wire T_3776 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3776.usip := UInt<1>("h00") T_3776.ssip := UInt<1>("h00") T_3776.hsip := UInt<1>("h00") T_3776.msip := UInt<1>("h00") T_3776.utip := UInt<1>("h00") T_3776.stip := UInt<1>("h00") T_3776.htip := UInt<1>("h00") T_3776.mtip := UInt<1>("h00") node T_3793 = bits(wdata, 0, 0) T_3776.usip := T_3793 node T_3794 = bits(wdata, 1, 1) T_3776.ssip := T_3794 node T_3795 = bits(wdata, 2, 2) T_3776.hsip := T_3795 node T_3796 = bits(wdata, 3, 3) T_3776.msip := T_3796 node T_3797 = bits(wdata, 4, 4) T_3776.utip := T_3797 node T_3798 = bits(wdata, 5, 5) T_3776.stip := T_3798 node T_3799 = bits(wdata, 6, 6) T_3776.htip := T_3799 node T_3800 = bits(wdata, 7, 7) T_3776.mtip := T_3800 reg_mie.ssip := T_3776.ssip reg_mie.stip := T_3776.stip reg_mie.msip := T_3776.msip reg_mie.mtip := T_3776.mtip skip when T_3076 : reg_fflags := wdata skip when T_3078 : reg_frm := wdata skip when T_3080 : reg_fflags := wdata node T_3801 = shr(wdata, 5) reg_frm := T_3801 skip when T_3114 : node T_3802 = not(wdata) node T_3804 = or(T_3802, UInt<2>("h03")) node T_3805 = not(T_3804) reg_mepc := T_3805 skip when T_3112 : reg_mscratch := wdata skip when T_3118 : node T_3807 = and(wdata, UInt<64>("h0800000000000001f")) reg_mcause := T_3807 skip when T_3116 : node T_3808 = bits(wdata, 39, 0) reg_mbadaddr := T_3808 skip when T_3134 : node T_3809 = bits(wdata, 5, 0) T_2452 := T_3809 node T_3810 = bits(wdata, 63, 6) T_2459 := T_3810 skip when T_3120 : reg_mtimecmp := wdata reg_mip.mtip := UInt<1>("h00") skip when T_3094 : reg_time := wdata skip when T_3130 : node T_3813 = eq(reg_fromhost, UInt<1>("h00")) node T_3815 = eq(host_pcr_req_fire, UInt<1>("h00")) node T_3816 = or(T_3813, T_3815) when T_3816 : reg_fromhost := wdata skip skip when T_3128 : node T_3818 = eq(reg_tohost, UInt<1>("h00")) node T_3819 = or(T_3818, host_pcr_req_fire) when T_3819 : reg_tohost := wdata skip skip when T_3126 : node T_3820 = bit(wdata, 0) reg_stats := T_3820 skip when T_3168 : wire T_3847 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_3847.ie := UInt<1>("h00") T_3847.zero1 := UInt<1>("h00") T_3847.pie := UInt<1>("h00") T_3847.ps := UInt<1>("h00") T_3847.zero2 := UInt<1>("h00") T_3847.fs := UInt<1>("h00") T_3847.xs := UInt<1>("h00") T_3847.mprv := UInt<1>("h00") T_3847.zero3 := UInt<1>("h00") T_3847.sd_rv32 := UInt<1>("h00") T_3847.zero4 := UInt<1>("h00") T_3847.sd := UInt<1>("h00") node T_3872 = bits(wdata, 0, 0) T_3847.ie := T_3872 node T_3873 = bits(wdata, 2, 1) T_3847.zero1 := T_3873 node T_3874 = bits(wdata, 3, 3) T_3847.pie := T_3874 node T_3875 = bits(wdata, 4, 4) T_3847.ps := T_3875 node T_3876 = bits(wdata, 11, 5) T_3847.zero2 := T_3876 node T_3877 = bits(wdata, 13, 12) T_3847.fs := T_3877 node T_3878 = bits(wdata, 15, 14) T_3847.xs := T_3878 node T_3879 = bits(wdata, 16, 16) T_3847.mprv := T_3879 node T_3880 = bits(wdata, 30, 17) T_3847.zero3 := T_3880 node T_3881 = bits(wdata, 31, 31) T_3847.sd_rv32 := T_3881 node T_3882 = bits(wdata, 62, 32) T_3847.zero4 := T_3882 node T_3883 = bits(wdata, 63, 63) T_3847.sd := T_3883 reg_mstatus.ie := T_3847.ie reg_mstatus.ie1 := T_3847.pie node T_3886 = mux(T_3847.ps, UInt<1>("h01"), UInt<1>("h00")) reg_mstatus.prv1 := T_3886 reg_mstatus.mprv := T_3847.mprv reg_mstatus.fs := T_3847.fs skip when T_3170 : wire T_3905 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3905.usip := UInt<1>("h00") T_3905.ssip := UInt<1>("h00") T_3905.hsip := UInt<1>("h00") T_3905.msip := UInt<1>("h00") T_3905.utip := UInt<1>("h00") T_3905.stip := UInt<1>("h00") T_3905.htip := UInt<1>("h00") T_3905.mtip := UInt<1>("h00") node T_3922 = bits(wdata, 0, 0) T_3905.usip := T_3922 node T_3923 = bits(wdata, 1, 1) T_3905.ssip := T_3923 node T_3924 = bits(wdata, 2, 2) T_3905.hsip := T_3924 node T_3925 = bits(wdata, 3, 3) T_3905.msip := T_3925 node T_3926 = bits(wdata, 4, 4) T_3905.utip := T_3926 node T_3927 = bits(wdata, 5, 5) T_3905.stip := T_3927 node T_3928 = bits(wdata, 6, 6) T_3905.htip := T_3928 node T_3929 = bits(wdata, 7, 7) T_3905.mtip := T_3929 reg_mip.ssip := T_3905.ssip skip when T_3172 : wire T_3948 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_3948.usip := UInt<1>("h00") T_3948.ssip := UInt<1>("h00") T_3948.hsip := UInt<1>("h00") T_3948.msip := UInt<1>("h00") T_3948.utip := UInt<1>("h00") T_3948.stip := UInt<1>("h00") T_3948.htip := UInt<1>("h00") T_3948.mtip := UInt<1>("h00") node T_3965 = bits(wdata, 0, 0) T_3948.usip := T_3965 node T_3966 = bits(wdata, 1, 1) T_3948.ssip := T_3966 node T_3967 = bits(wdata, 2, 2) T_3948.hsip := T_3967 node T_3968 = bits(wdata, 3, 3) T_3948.msip := T_3968 node T_3969 = bits(wdata, 4, 4) T_3948.utip := T_3969 node T_3970 = bits(wdata, 5, 5) T_3948.stip := T_3970 node T_3971 = bits(wdata, 6, 6) T_3948.htip := T_3971 node T_3972 = bits(wdata, 7, 7) T_3948.mtip := T_3972 reg_mie.ssip := T_3948.ssip reg_mie.stip := T_3948.stip skip when T_3174 : reg_sscratch := wdata skip when T_3180 : node T_3973 = bits(wdata, 31, 12) node T_3975 = cat(T_3973, UInt<12>("h00")) reg_sptbr := T_3975 skip when T_3184 : node T_3976 = not(wdata) node T_3978 = or(T_3976, UInt<2>("h03")) node T_3979 = not(T_3978) reg_sepc := T_3979 skip when T_3186 : node T_3980 = not(wdata) node T_3982 = or(T_3980, UInt<2>("h03")) node T_3983 = not(T_3982) reg_stvec := T_3983 skip skip io.host.ipi_rep.ready := UInt<1>("h01") when io.host.ipi_rep.valid : reg_mip.msip := UInt<1>("h01") skip when reset : reg_mstatus.zero1 := UInt<1>("h00") reg_mstatus.zero2 := UInt<1>("h00") reg_mstatus.ie := UInt<1>("h00") reg_mstatus.prv := UInt<2>("h03") reg_mstatus.ie1 := UInt<1>("h00") reg_mstatus.prv1 := UInt<2>("h03") reg_mstatus.ie2 := UInt<1>("h00") reg_mstatus.prv2 := UInt<1>("h00") reg_mstatus.ie3 := UInt<1>("h00") reg_mstatus.prv3 := UInt<1>("h00") reg_mstatus.mprv := UInt<1>("h00") reg_mstatus.vm := UInt<1>("h00") reg_mstatus.fs := UInt<1>("h00") reg_mstatus.xs := UInt<1>("h00") reg_mstatus.sd_rv32 := UInt<1>("h00") reg_mstatus.sd := UInt<1>("h00") skip module ALU : input clock : Clock input reset : UInt<1> output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>} io.adder_out := UInt<1>("h00") io.out := UInt<1>("h00") node T_11 = bit(io.fn, 3) node T_13 = subw(UInt<1>("h00"), io.in2) node T_14 = mux(T_11, T_13, io.in2) node sum = addw(io.in1, T_14) node T_16 = bit(io.fn, 0) node T_17 = bit(io.fn, 2) node T_19 = eq(T_17, UInt<1>("h00")) node T_21 = eq(sum, UInt<1>("h00")) node T_22 = bit(io.in1, 63) node T_23 = bit(io.in2, 63) node T_24 = eq(T_22, T_23) node T_25 = bit(sum, 63) node T_26 = bit(io.fn, 1) node T_27 = bit(io.in2, 63) node T_28 = bit(io.in1, 63) node T_29 = mux(T_26, T_27, T_28) node T_30 = mux(T_24, T_25, T_29) node T_31 = mux(T_19, T_21, T_30) node cmp = xor(T_16, T_31) node T_33 = bit(io.in2, 5) node T_36 = and(io.dw, UInt<1>("h01")) node T_37 = eq(UInt<1>("h01"), T_36) node T_38 = and(T_33, T_37) node T_39 = bits(io.in2, 4, 0) node shamt = cat(T_38, T_39) node T_41 = bit(io.fn, 3) node T_42 = bit(io.in1, 31) node T_44 = subw(UInt<32>("h00"), T_42) node shin_hi_32 = mux(T_41, T_44, UInt<32>("h00")) node T_49 = and(io.dw, UInt<1>("h01")) node T_50 = eq(UInt<1>("h01"), T_49) node T_51 = bits(io.in1, 63, 32) node shin_hi = mux(T_50, T_51, shin_hi_32) node T_53 = bits(io.in1, 31, 0) node shin_r = cat(shin_hi, T_53) node T_55 = eq(io.fn, UInt<3>("h05")) node T_56 = eq(io.fn, UInt<4>("h0b")) node T_57 = or(T_55, T_56) node T_60 = shl(UInt<32>("h0ffffffff"), 32) node T_61 = xor(UInt<64>("h0ffffffffffffffff"), T_60) node T_62 = shr(shin_r, 32) node T_63 = and(T_62, T_61) node T_64 = bits(shin_r, 31, 0) node T_65 = shl(T_64, 32) node T_66 = not(T_61) node T_67 = and(T_65, T_66) node T_68 = or(T_63, T_67) node T_69 = bits(T_61, 47, 0) node T_70 = shl(T_69, 16) node T_71 = xor(T_61, T_70) node T_72 = shr(T_68, 16) node T_73 = and(T_72, T_71) node T_74 = bits(T_68, 47, 0) node T_75 = shl(T_74, 16) node T_76 = not(T_71) node T_77 = and(T_75, T_76) node T_78 = or(T_73, T_77) node T_79 = bits(T_71, 55, 0) node T_80 = shl(T_79, 8) node T_81 = xor(T_71, T_80) node T_82 = shr(T_78, 8) node T_83 = and(T_82, T_81) node T_84 = bits(T_78, 55, 0) node T_85 = shl(T_84, 8) node T_86 = not(T_81) node T_87 = and(T_85, T_86) node T_88 = or(T_83, T_87) node T_89 = bits(T_81, 59, 0) node T_90 = shl(T_89, 4) node T_91 = xor(T_81, T_90) node T_92 = shr(T_88, 4) node T_93 = and(T_92, T_91) node T_94 = bits(T_88, 59, 0) node T_95 = shl(T_94, 4) node T_96 = not(T_91) node T_97 = and(T_95, T_96) node T_98 = or(T_93, T_97) node T_99 = bits(T_91, 61, 0) node T_100 = shl(T_99, 2) node T_101 = xor(T_91, T_100) node T_102 = shr(T_98, 2) node T_103 = and(T_102, T_101) node T_104 = bits(T_98, 61, 0) node T_105 = shl(T_104, 2) node T_106 = not(T_101) node T_107 = and(T_105, T_106) node T_108 = or(T_103, T_107) node T_109 = bits(T_101, 62, 0) node T_110 = shl(T_109, 1) node T_111 = xor(T_101, T_110) node T_112 = shr(T_108, 1) node T_113 = and(T_112, T_111) node T_114 = bits(T_108, 62, 0) node T_115 = shl(T_114, 1) node T_116 = not(T_111) node T_117 = and(T_115, T_116) node T_118 = or(T_113, T_117) node shin = mux(T_57, shin_r, T_118) node T_120 = bit(io.fn, 3) node T_121 = bit(shin, 63) node T_122 = and(T_120, T_121) node T_123 = cat(T_122, shin) node T_124 = asSInt(T_123) node T_125 = dshr(T_124, shamt) node shout_r = bits(T_125, 63, 0) node T_129 = shl(UInt<32>("h0ffffffff"), 32) node T_130 = xor(UInt<64>("h0ffffffffffffffff"), T_129) node T_131 = shr(shout_r, 32) node T_132 = and(T_131, T_130) node T_133 = bits(shout_r, 31, 0) node T_134 = shl(T_133, 32) node T_135 = not(T_130) node T_136 = and(T_134, T_135) node T_137 = or(T_132, T_136) node T_138 = bits(T_130, 47, 0) node T_139 = shl(T_138, 16) node T_140 = xor(T_130, T_139) node T_141 = shr(T_137, 16) node T_142 = and(T_141, T_140) node T_143 = bits(T_137, 47, 0) node T_144 = shl(T_143, 16) node T_145 = not(T_140) node T_146 = and(T_144, T_145) node T_147 = or(T_142, T_146) node T_148 = bits(T_140, 55, 0) node T_149 = shl(T_148, 8) node T_150 = xor(T_140, T_149) node T_151 = shr(T_147, 8) node T_152 = and(T_151, T_150) node T_153 = bits(T_147, 55, 0) node T_154 = shl(T_153, 8) node T_155 = not(T_150) node T_156 = and(T_154, T_155) node T_157 = or(T_152, T_156) node T_158 = bits(T_150, 59, 0) node T_159 = shl(T_158, 4) node T_160 = xor(T_150, T_159) node T_161 = shr(T_157, 4) node T_162 = and(T_161, T_160) node T_163 = bits(T_157, 59, 0) node T_164 = shl(T_163, 4) node T_165 = not(T_160) node T_166 = and(T_164, T_165) node T_167 = or(T_162, T_166) node T_168 = bits(T_160, 61, 0) node T_169 = shl(T_168, 2) node T_170 = xor(T_160, T_169) node T_171 = shr(T_167, 2) node T_172 = and(T_171, T_170) node T_173 = bits(T_167, 61, 0) node T_174 = shl(T_173, 2) node T_175 = not(T_170) node T_176 = and(T_174, T_175) node T_177 = or(T_172, T_176) node T_178 = bits(T_170, 62, 0) node T_179 = shl(T_178, 1) node T_180 = xor(T_170, T_179) node T_181 = shr(T_177, 1) node T_182 = and(T_181, T_180) node T_183 = bits(T_177, 62, 0) node T_184 = shl(T_183, 1) node T_185 = not(T_180) node T_186 = and(T_184, T_185) node shout_l = or(T_182, T_186) node T_188 = eq(io.fn, UInt<1>("h00")) node T_189 = eq(io.fn, UInt<4>("h0a")) node T_190 = or(T_188, T_189) node T_191 = eq(io.fn, UInt<3>("h05")) node T_192 = eq(io.fn, UInt<4>("h0b")) node T_193 = or(T_191, T_192) node T_194 = eq(io.fn, UInt<1>("h01")) node T_195 = eq(io.fn, UInt<3>("h07")) node T_196 = and(io.in1, io.in2) node T_197 = eq(io.fn, UInt<3>("h06")) node T_198 = or(io.in1, io.in2) node T_199 = eq(io.fn, UInt<3>("h04")) node T_200 = xor(io.in1, io.in2) node T_201 = shl(cmp, 0) node T_202 = mux(T_199, T_200, T_201) node T_203 = mux(T_197, T_198, T_202) node T_204 = mux(T_195, T_196, T_203) node T_205 = mux(T_194, shout_l, T_204) node T_206 = mux(T_193, shout_r, T_205) node out64 = mux(T_190, sum, T_206) node T_210 = and(io.dw, UInt<1>("h01")) node T_211 = eq(UInt<1>("h01"), T_210) node T_212 = bits(out64, 63, 32) node T_213 = bit(out64, 31) node T_215 = subw(UInt<32>("h00"), T_213) node out_hi = mux(T_211, T_212, T_215) node T_217 = bits(out64, 31, 0) node T_218 = cat(out_hi, T_217) io.out := T_218 io.adder_out := sum module MulDiv : input clock : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} io.resp.bits.tag := UInt<1>("h00") io.resp.bits.data := UInt<1>("h00") io.resp.valid := UInt<1>("h00") io.req.ready := UInt<1>("h00") reg state : UInt, clock, reset onreset state := UInt<1>("h00") reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock, reset reg count : UInt<7>, clock, reset reg neg_out : UInt<1>, clock, reset reg isMul : UInt<1>, clock, reset reg isHi : UInt<1>, clock, reset reg divisor : UInt<65>, clock, reset reg remainder : UInt<130>, clock, reset node T_81 = and(io.req.bits.fn, UInt<4>("h04")) node T_83 = eq(T_81, UInt<4>("h00")) node T_85 = and(io.req.bits.fn, UInt<4>("h08")) node T_87 = eq(T_85, UInt<4>("h08")) node T_89 = or(UInt<1>("h00"), T_83) node T_90 = or(T_89, T_87) node T_92 = and(io.req.bits.fn, UInt<4>("h05")) node T_94 = eq(T_92, UInt<4>("h01")) node T_96 = and(io.req.bits.fn, UInt<4>("h02")) node T_98 = eq(T_96, UInt<4>("h02")) node T_100 = or(UInt<1>("h00"), T_94) node T_101 = or(T_100, T_98) node T_102 = or(T_101, T_87) node T_104 = and(io.req.bits.fn, UInt<4>("h09")) node T_106 = eq(T_104, UInt<4>("h00")) node T_108 = and(io.req.bits.fn, UInt<4>("h03")) node T_110 = eq(T_108, UInt<4>("h00")) node T_112 = or(UInt<1>("h00"), T_106) node T_113 = or(T_112, T_83) node T_114 = or(T_113, T_110) node T_116 = or(UInt<1>("h00"), T_106) node T_117 = or(T_116, T_83) node cmdMul = bit(T_90, 0) node cmdHi = bit(T_102, 0) node lhsSigned = bit(T_114, 0) node rhsSigned = bit(T_117, 0) node T_124 = and(io.req.bits.dw, UInt<1>("h01")) node T_125 = eq(UInt<1>("h01"), T_124) node T_126 = bit(io.req.bits.in1, 63) node T_127 = bit(io.req.bits.in1, 31) node T_128 = mux(T_125, T_126, T_127) node lhs_sign = and(lhsSigned, T_128) node T_132 = and(io.req.bits.dw, UInt<1>("h01")) node T_133 = eq(UInt<1>("h01"), T_132) node T_134 = bits(io.req.bits.in1, 63, 32) node T_136 = subw(UInt<32>("h00"), lhs_sign) node T_137 = mux(T_133, T_134, T_136) node T_138 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(T_137, T_138) node T_142 = and(io.req.bits.dw, UInt<1>("h01")) node T_143 = eq(UInt<1>("h01"), T_142) node T_144 = bit(io.req.bits.in2, 63) node T_145 = bit(io.req.bits.in2, 31) node T_146 = mux(T_143, T_144, T_145) node rhs_sign = and(rhsSigned, T_146) node T_150 = and(io.req.bits.dw, UInt<1>("h01")) node T_151 = eq(UInt<1>("h01"), T_150) node T_152 = bits(io.req.bits.in2, 63, 32) node T_154 = subw(UInt<32>("h00"), rhs_sign) node T_155 = mux(T_151, T_152, T_154) node T_156 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(T_155, T_156) node T_158 = bits(remainder, 128, 64) node T_159 = bits(divisor, 64, 0) node subtractor = subw(T_158, T_159) node less = bit(subtractor, 64) node T_162 = bits(remainder, 63, 0) node negated_remainder = subw(UInt<1>("h00"), T_162) node T_165 = eq(state, UInt<1>("h01")) when T_165 : node T_166 = bit(remainder, 63) node T_167 = or(T_166, isMul) when T_167 : remainder := negated_remainder skip node T_168 = bit(divisor, 63) node T_169 = or(T_168, isMul) when T_169 : divisor := subtractor skip state := UInt<2>("h02") skip node T_170 = eq(state, UInt<3>("h04")) when T_170 : remainder := negated_remainder state := UInt<3>("h05") skip node T_171 = eq(state, UInt<2>("h03")) when T_171 : node T_172 = bits(remainder, 128, 65) remainder := T_172 node T_173 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) state := T_173 skip node T_174 = eq(state, UInt<2>("h02")) node T_175 = and(T_174, isMul) when T_175 : node T_176 = bits(remainder, 129, 65) node T_177 = bits(remainder, 63, 0) node T_178 = cat(T_176, T_177) node T_179 = bits(T_178, 63, 0) node T_180 = bits(T_178, 128, 64) node T_181 = asSInt(T_180) node T_182 = asSInt(divisor) node T_183 = bits(T_179, 7, 0) node T_184 = mul(T_182, T_183) node T_185 = addw(T_184, T_181) node T_186 = bits(T_179, 63, 8) node T_187 = asUInt(T_185) node T_188 = cat(T_187, T_186) node T_191 = mul(count, UInt<4>("h08")) node T_192 = bits(T_191, 5, 0) node T_193 = dshr(asSInt(UInt<65>("h010000000000000000")), T_192) node T_194 = bits(T_193, 63, 0) node T_197 = neq(count, UInt<3>("h07")) node T_198 = and(UInt<1>("h01"), T_197) node T_200 = neq(count, UInt<1>("h00")) node T_201 = and(T_198, T_200) node T_203 = eq(isHi, UInt<1>("h00")) node T_204 = and(T_201, T_203) node T_205 = not(T_194) node T_206 = and(T_179, T_205) node T_208 = eq(T_206, UInt<1>("h00")) node T_209 = and(T_204, T_208) node T_212 = mul(count, UInt<4>("h08")) node T_213 = subw(UInt<7>("h040"), T_212) node T_214 = bits(T_213, 5, 0) node T_215 = dshr(T_178, T_214) node T_216 = bits(T_188, 128, 64) node T_217 = mux(T_209, T_215, T_188) node T_218 = bits(T_217, 63, 0) node T_219 = cat(T_216, T_218) node T_220 = shr(T_219, 64) node T_222 = bits(T_219, 63, 0) node T_223 = cat(UInt<1>("h00"), T_222) node T_224 = cat(T_220, T_223) remainder := T_224 node T_226 = addw(count, UInt<1>("h01")) count := T_226 node T_228 = eq(count, UInt<3>("h07")) node T_229 = or(T_209, T_228) when T_229 : node T_230 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) state := T_230 skip skip node T_231 = eq(state, UInt<2>("h02")) node T_233 = eq(isMul, UInt<1>("h00")) node T_234 = and(T_231, T_233) when T_234 : node T_236 = eq(count, UInt<7>("h040")) when T_236 : node T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) node T_238 = mux(isHi, UInt<2>("h03"), T_237) state := T_238 skip node T_240 = addw(count, UInt<1>("h01")) count := T_240 node T_241 = bits(remainder, 127, 64) node T_242 = bits(subtractor, 63, 0) node T_243 = mux(less, T_241, T_242) node T_244 = bits(remainder, 63, 0) node T_246 = eq(less, UInt<1>("h00")) node T_247 = cat(T_244, T_246) node T_248 = cat(T_243, T_247) remainder := T_248 node T_249 = bits(divisor, 63, 0) node T_250 = bit(T_249, 63) node T_252 = bit(T_249, 62) node T_254 = bit(T_249, 61) node T_256 = bit(T_249, 60) node T_258 = bit(T_249, 59) node T_260 = bit(T_249, 58) node T_262 = bit(T_249, 57) node T_264 = bit(T_249, 56) node T_266 = bit(T_249, 55) node T_268 = bit(T_249, 54) node T_270 = bit(T_249, 53) node T_272 = bit(T_249, 52) node T_274 = bit(T_249, 51) node T_276 = bit(T_249, 50) node T_278 = bit(T_249, 49) node T_280 = bit(T_249, 48) node T_282 = bit(T_249, 47) node T_284 = bit(T_249, 46) node T_286 = bit(T_249, 45) node T_288 = bit(T_249, 44) node T_290 = bit(T_249, 43) node T_292 = bit(T_249, 42) node T_294 = bit(T_249, 41) node T_296 = bit(T_249, 40) node T_298 = bit(T_249, 39) node T_300 = bit(T_249, 38) node T_302 = bit(T_249, 37) node T_304 = bit(T_249, 36) node T_306 = bit(T_249, 35) node T_308 = bit(T_249, 34) node T_310 = bit(T_249, 33) node T_312 = bit(T_249, 32) node T_314 = bit(T_249, 31) node T_316 = bit(T_249, 30) node T_318 = bit(T_249, 29) node T_320 = bit(T_249, 28) node T_322 = bit(T_249, 27) node T_324 = bit(T_249, 26) node T_326 = bit(T_249, 25) node T_328 = bit(T_249, 24) node T_330 = bit(T_249, 23) node T_332 = bit(T_249, 22) node T_334 = bit(T_249, 21) node T_336 = bit(T_249, 20) node T_338 = bit(T_249, 19) node T_340 = bit(T_249, 18) node T_342 = bit(T_249, 17) node T_344 = bit(T_249, 16) node T_346 = bit(T_249, 15) node T_348 = bit(T_249, 14) node T_350 = bit(T_249, 13) node T_352 = bit(T_249, 12) node T_354 = bit(T_249, 11) node T_356 = bit(T_249, 10) node T_358 = bit(T_249, 9) node T_360 = bit(T_249, 8) node T_362 = bit(T_249, 7) node T_364 = bit(T_249, 6) node T_366 = bit(T_249, 5) node T_368 = bit(T_249, 4) node T_370 = bit(T_249, 3) node T_372 = bit(T_249, 2) node T_374 = bit(T_249, 1) node T_375 = shl(T_374, 0) node T_376 = mux(T_372, UInt<2>("h02"), T_375) node T_377 = mux(T_370, UInt<2>("h03"), T_376) node T_378 = mux(T_368, UInt<3>("h04"), T_377) node T_379 = mux(T_366, UInt<3>("h05"), T_378) node T_380 = mux(T_364, UInt<3>("h06"), T_379) node T_381 = mux(T_362, UInt<3>("h07"), T_380) node T_382 = mux(T_360, UInt<4>("h08"), T_381) node T_383 = mux(T_358, UInt<4>("h09"), T_382) node T_384 = mux(T_356, UInt<4>("h0a"), T_383) node T_385 = mux(T_354, UInt<4>("h0b"), T_384) node T_386 = mux(T_352, UInt<4>("h0c"), T_385) node T_387 = mux(T_350, UInt<4>("h0d"), T_386) node T_388 = mux(T_348, UInt<4>("h0e"), T_387) node T_389 = mux(T_346, UInt<4>("h0f"), T_388) node T_390 = mux(T_344, UInt<5>("h010"), T_389) node T_391 = mux(T_342, UInt<5>("h011"), T_390) node T_392 = mux(T_340, UInt<5>("h012"), T_391) node T_393 = mux(T_338, UInt<5>("h013"), T_392) node T_394 = mux(T_336, UInt<5>("h014"), T_393) node T_395 = mux(T_334, UInt<5>("h015"), T_394) node T_396 = mux(T_332, UInt<5>("h016"), T_395) node T_397 = mux(T_330, UInt<5>("h017"), T_396) node T_398 = mux(T_328, UInt<5>("h018"), T_397) node T_399 = mux(T_326, UInt<5>("h019"), T_398) node T_400 = mux(T_324, UInt<5>("h01a"), T_399) node T_401 = mux(T_322, UInt<5>("h01b"), T_400) node T_402 = mux(T_320, UInt<5>("h01c"), T_401) node T_403 = mux(T_318, UInt<5>("h01d"), T_402) node T_404 = mux(T_316, UInt<5>("h01e"), T_403) node T_405 = mux(T_314, UInt<5>("h01f"), T_404) node T_406 = mux(T_312, UInt<6>("h020"), T_405) node T_407 = mux(T_310, UInt<6>("h021"), T_406) node T_408 = mux(T_308, UInt<6>("h022"), T_407) node T_409 = mux(T_306, UInt<6>("h023"), T_408) node T_410 = mux(T_304, UInt<6>("h024"), T_409) node T_411 = mux(T_302, UInt<6>("h025"), T_410) node T_412 = mux(T_300, UInt<6>("h026"), T_411) node T_413 = mux(T_298, UInt<6>("h027"), T_412) node T_414 = mux(T_296, UInt<6>("h028"), T_413) node T_415 = mux(T_294, UInt<6>("h029"), T_414) node T_416 = mux(T_292, UInt<6>("h02a"), T_415) node T_417 = mux(T_290, UInt<6>("h02b"), T_416) node T_418 = mux(T_288, UInt<6>("h02c"), T_417) node T_419 = mux(T_286, UInt<6>("h02d"), T_418) node T_420 = mux(T_284, UInt<6>("h02e"), T_419) node T_421 = mux(T_282, UInt<6>("h02f"), T_420) node T_422 = mux(T_280, UInt<6>("h030"), T_421) node T_423 = mux(T_278, UInt<6>("h031"), T_422) node T_424 = mux(T_276, UInt<6>("h032"), T_423) node T_425 = mux(T_274, UInt<6>("h033"), T_424) node T_426 = mux(T_272, UInt<6>("h034"), T_425) node T_427 = mux(T_270, UInt<6>("h035"), T_426) node T_428 = mux(T_268, UInt<6>("h036"), T_427) node T_429 = mux(T_266, UInt<6>("h037"), T_428) node T_430 = mux(T_264, UInt<6>("h038"), T_429) node T_431 = mux(T_262, UInt<6>("h039"), T_430) node T_432 = mux(T_260, UInt<6>("h03a"), T_431) node T_433 = mux(T_258, UInt<6>("h03b"), T_432) node T_434 = mux(T_256, UInt<6>("h03c"), T_433) node T_435 = mux(T_254, UInt<6>("h03d"), T_434) node T_436 = mux(T_252, UInt<6>("h03e"), T_435) node T_437 = mux(T_250, UInt<6>("h03f"), T_436) node T_438 = bits(remainder, 63, 0) node T_439 = bit(T_438, 63) node T_441 = bit(T_438, 62) node T_443 = bit(T_438, 61) node T_445 = bit(T_438, 60) node T_447 = bit(T_438, 59) node T_449 = bit(T_438, 58) node T_451 = bit(T_438, 57) node T_453 = bit(T_438, 56) node T_455 = bit(T_438, 55) node T_457 = bit(T_438, 54) node T_459 = bit(T_438, 53) node T_461 = bit(T_438, 52) node T_463 = bit(T_438, 51) node T_465 = bit(T_438, 50) node T_467 = bit(T_438, 49) node T_469 = bit(T_438, 48) node T_471 = bit(T_438, 47) node T_473 = bit(T_438, 46) node T_475 = bit(T_438, 45) node T_477 = bit(T_438, 44) node T_479 = bit(T_438, 43) node T_481 = bit(T_438, 42) node T_483 = bit(T_438, 41) node T_485 = bit(T_438, 40) node T_487 = bit(T_438, 39) node T_489 = bit(T_438, 38) node T_491 = bit(T_438, 37) node T_493 = bit(T_438, 36) node T_495 = bit(T_438, 35) node T_497 = bit(T_438, 34) node T_499 = bit(T_438, 33) node T_501 = bit(T_438, 32) node T_503 = bit(T_438, 31) node T_505 = bit(T_438, 30) node T_507 = bit(T_438, 29) node T_509 = bit(T_438, 28) node T_511 = bit(T_438, 27) node T_513 = bit(T_438, 26) node T_515 = bit(T_438, 25) node T_517 = bit(T_438, 24) node T_519 = bit(T_438, 23) node T_521 = bit(T_438, 22) node T_523 = bit(T_438, 21) node T_525 = bit(T_438, 20) node T_527 = bit(T_438, 19) node T_529 = bit(T_438, 18) node T_531 = bit(T_438, 17) node T_533 = bit(T_438, 16) node T_535 = bit(T_438, 15) node T_537 = bit(T_438, 14) node T_539 = bit(T_438, 13) node T_541 = bit(T_438, 12) node T_543 = bit(T_438, 11) node T_545 = bit(T_438, 10) node T_547 = bit(T_438, 9) node T_549 = bit(T_438, 8) node T_551 = bit(T_438, 7) node T_553 = bit(T_438, 6) node T_555 = bit(T_438, 5) node T_557 = bit(T_438, 4) node T_559 = bit(T_438, 3) node T_561 = bit(T_438, 2) node T_563 = bit(T_438, 1) node T_564 = shl(T_563, 0) node T_565 = mux(T_561, UInt<2>("h02"), T_564) node T_566 = mux(T_559, UInt<2>("h03"), T_565) node T_567 = mux(T_557, UInt<3>("h04"), T_566) node T_568 = mux(T_555, UInt<3>("h05"), T_567) node T_569 = mux(T_553, UInt<3>("h06"), T_568) node T_570 = mux(T_551, UInt<3>("h07"), T_569) node T_571 = mux(T_549, UInt<4>("h08"), T_570) node T_572 = mux(T_547, UInt<4>("h09"), T_571) node T_573 = mux(T_545, UInt<4>("h0a"), T_572) node T_574 = mux(T_543, UInt<4>("h0b"), T_573) node T_575 = mux(T_541, UInt<4>("h0c"), T_574) node T_576 = mux(T_539, UInt<4>("h0d"), T_575) node T_577 = mux(T_537, UInt<4>("h0e"), T_576) node T_578 = mux(T_535, UInt<4>("h0f"), T_577) node T_579 = mux(T_533, UInt<5>("h010"), T_578) node T_580 = mux(T_531, UInt<5>("h011"), T_579) node T_581 = mux(T_529, UInt<5>("h012"), T_580) node T_582 = mux(T_527, UInt<5>("h013"), T_581) node T_583 = mux(T_525, UInt<5>("h014"), T_582) node T_584 = mux(T_523, UInt<5>("h015"), T_583) node T_585 = mux(T_521, UInt<5>("h016"), T_584) node T_586 = mux(T_519, UInt<5>("h017"), T_585) node T_587 = mux(T_517, UInt<5>("h018"), T_586) node T_588 = mux(T_515, UInt<5>("h019"), T_587) node T_589 = mux(T_513, UInt<5>("h01a"), T_588) node T_590 = mux(T_511, UInt<5>("h01b"), T_589) node T_591 = mux(T_509, UInt<5>("h01c"), T_590) node T_592 = mux(T_507, UInt<5>("h01d"), T_591) node T_593 = mux(T_505, UInt<5>("h01e"), T_592) node T_594 = mux(T_503, UInt<5>("h01f"), T_593) node T_595 = mux(T_501, UInt<6>("h020"), T_594) node T_596 = mux(T_499, UInt<6>("h021"), T_595) node T_597 = mux(T_497, UInt<6>("h022"), T_596) node T_598 = mux(T_495, UInt<6>("h023"), T_597) node T_599 = mux(T_493, UInt<6>("h024"), T_598) node T_600 = mux(T_491, UInt<6>("h025"), T_599) node T_601 = mux(T_489, UInt<6>("h026"), T_600) node T_602 = mux(T_487, UInt<6>("h027"), T_601) node T_603 = mux(T_485, UInt<6>("h028"), T_602) node T_604 = mux(T_483, UInt<6>("h029"), T_603) node T_605 = mux(T_481, UInt<6>("h02a"), T_604) node T_606 = mux(T_479, UInt<6>("h02b"), T_605) node T_607 = mux(T_477, UInt<6>("h02c"), T_606) node T_608 = mux(T_475, UInt<6>("h02d"), T_607) node T_609 = mux(T_473, UInt<6>("h02e"), T_608) node T_610 = mux(T_471, UInt<6>("h02f"), T_609) node T_611 = mux(T_469, UInt<6>("h030"), T_610) node T_612 = mux(T_467, UInt<6>("h031"), T_611) node T_613 = mux(T_465, UInt<6>("h032"), T_612) node T_614 = mux(T_463, UInt<6>("h033"), T_613) node T_615 = mux(T_461, UInt<6>("h034"), T_614) node T_616 = mux(T_459, UInt<6>("h035"), T_615) node T_617 = mux(T_457, UInt<6>("h036"), T_616) node T_618 = mux(T_455, UInt<6>("h037"), T_617) node T_619 = mux(T_453, UInt<6>("h038"), T_618) node T_620 = mux(T_451, UInt<6>("h039"), T_619) node T_621 = mux(T_449, UInt<6>("h03a"), T_620) node T_622 = mux(T_447, UInt<6>("h03b"), T_621) node T_623 = mux(T_445, UInt<6>("h03c"), T_622) node T_624 = mux(T_443, UInt<6>("h03d"), T_623) node T_625 = mux(T_441, UInt<6>("h03e"), T_624) node T_626 = mux(T_439, UInt<6>("h03f"), T_625) node T_628 = addw(UInt<6>("h03f"), T_437) node T_629 = subw(T_628, T_626) node T_630 = gt(T_437, T_626) node T_632 = eq(count, UInt<1>("h00")) node T_633 = and(T_632, less) node T_635 = gt(T_629, UInt<1>("h00")) node T_636 = or(T_635, T_630) node T_637 = and(T_633, T_636) node T_639 = and(UInt<1>("h01"), T_637) when T_639 : node T_641 = bits(T_629, 5, 0) node T_642 = mux(T_630, UInt<6>("h03f"), T_641) node T_643 = bits(remainder, 63, 0) node T_644 = dshl(T_643, T_642) remainder := T_644 count := T_642 skip node T_646 = eq(count, UInt<1>("h00")) node T_648 = eq(less, UInt<1>("h00")) node T_649 = and(T_646, T_648) node T_651 = eq(isHi, UInt<1>("h00")) node T_652 = and(T_649, T_651) when T_652 : neg_out := UInt<1>("h00") skip skip node T_654 = and(io.resp.ready, io.resp.valid) node T_655 = or(T_654, io.kill) when T_655 : state := UInt<1>("h00") skip node T_656 = and(io.req.ready, io.req.valid) when T_656 : node T_658 = eq(cmdMul, UInt<1>("h00")) node T_659 = and(rhs_sign, T_658) node T_660 = or(lhs_sign, T_659) node T_661 = mux(T_660, UInt<1>("h01"), UInt<2>("h02")) state := T_661 isMul := cmdMul isHi := cmdHi count := UInt<1>("h00") node T_664 = eq(cmdMul, UInt<1>("h00")) node T_665 = neq(lhs_sign, rhs_sign) node T_666 = mux(cmdHi, lhs_sign, T_665) node T_667 = and(T_664, T_666) neg_out := T_667 node T_668 = cat(rhs_sign, rhs_in) divisor := T_668 remainder := lhs_in req <> io.req.bits skip io.resp.bits <> req node T_671 = and(req.dw, UInt<1>("h01")) node T_672 = eq(UInt<1>("h00"), T_671) node T_673 = bit(remainder, 31) node T_675 = subw(UInt<32>("h00"), T_673) node T_676 = bits(remainder, 31, 0) node T_677 = cat(T_675, T_676) node T_678 = bits(remainder, 63, 0) node T_679 = mux(T_672, T_677, T_678) io.resp.bits.data := T_679 node T_680 = eq(state, UInt<3>("h05")) io.resp.valid := T_680 node T_681 = eq(state, UInt<1>("h00")) io.req.ready := T_681 module Rocket : input clock : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>}} io.rocc.exception := UInt<1>("h00") io.rocc.pptw.invalidate := UInt<1>("h00") io.rocc.pptw.status.ie := UInt<1>("h00") io.rocc.pptw.status.prv := UInt<1>("h00") io.rocc.pptw.status.ie1 := UInt<1>("h00") io.rocc.pptw.status.prv1 := UInt<1>("h00") io.rocc.pptw.status.ie2 := UInt<1>("h00") io.rocc.pptw.status.prv2 := UInt<1>("h00") io.rocc.pptw.status.ie3 := UInt<1>("h00") io.rocc.pptw.status.prv3 := UInt<1>("h00") io.rocc.pptw.status.fs := UInt<1>("h00") io.rocc.pptw.status.xs := UInt<1>("h00") io.rocc.pptw.status.mprv := UInt<1>("h00") io.rocc.pptw.status.vm := UInt<1>("h00") io.rocc.pptw.status.zero1 := UInt<1>("h00") io.rocc.pptw.status.sd_rv32 := UInt<1>("h00") io.rocc.pptw.status.zero2 := UInt<1>("h00") io.rocc.pptw.status.sd := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.pptw.resp.bits.error := UInt<1>("h00") io.rocc.pptw.resp.valid := UInt<1>("h00") io.rocc.pptw.req.ready := UInt<1>("h00") io.rocc.dptw.invalidate := UInt<1>("h00") io.rocc.dptw.status.ie := UInt<1>("h00") io.rocc.dptw.status.prv := UInt<1>("h00") io.rocc.dptw.status.ie1 := UInt<1>("h00") io.rocc.dptw.status.prv1 := UInt<1>("h00") io.rocc.dptw.status.ie2 := UInt<1>("h00") io.rocc.dptw.status.prv2 := UInt<1>("h00") io.rocc.dptw.status.ie3 := UInt<1>("h00") io.rocc.dptw.status.prv3 := UInt<1>("h00") io.rocc.dptw.status.fs := UInt<1>("h00") io.rocc.dptw.status.xs := UInt<1>("h00") io.rocc.dptw.status.mprv := UInt<1>("h00") io.rocc.dptw.status.vm := UInt<1>("h00") io.rocc.dptw.status.zero1 := UInt<1>("h00") io.rocc.dptw.status.sd_rv32 := UInt<1>("h00") io.rocc.dptw.status.zero2 := UInt<1>("h00") io.rocc.dptw.status.sd := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.dptw.resp.bits.error := UInt<1>("h00") io.rocc.dptw.resp.valid := UInt<1>("h00") io.rocc.dptw.req.ready := UInt<1>("h00") io.rocc.iptw.invalidate := UInt<1>("h00") io.rocc.iptw.status.ie := UInt<1>("h00") io.rocc.iptw.status.prv := UInt<1>("h00") io.rocc.iptw.status.ie1 := UInt<1>("h00") io.rocc.iptw.status.prv1 := UInt<1>("h00") io.rocc.iptw.status.ie2 := UInt<1>("h00") io.rocc.iptw.status.prv2 := UInt<1>("h00") io.rocc.iptw.status.ie3 := UInt<1>("h00") io.rocc.iptw.status.prv3 := UInt<1>("h00") io.rocc.iptw.status.fs := UInt<1>("h00") io.rocc.iptw.status.xs := UInt<1>("h00") io.rocc.iptw.status.mprv := UInt<1>("h00") io.rocc.iptw.status.vm := UInt<1>("h00") io.rocc.iptw.status.zero1 := UInt<1>("h00") io.rocc.iptw.status.sd_rv32 := UInt<1>("h00") io.rocc.iptw.status.zero2 := UInt<1>("h00") io.rocc.iptw.status.sd := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.v := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.r := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.d := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") io.rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") io.rocc.iptw.resp.bits.error := UInt<1>("h00") io.rocc.iptw.resp.valid := UInt<1>("h00") io.rocc.iptw.req.ready := UInt<1>("h00") io.rocc.dmem.grant.bits.g_type := UInt<1>("h00") io.rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") io.rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") io.rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") io.rocc.dmem.grant.bits.data := UInt<1>("h00") io.rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") io.rocc.dmem.grant.valid := UInt<1>("h00") io.rocc.dmem.acquire.ready := UInt<1>("h00") io.rocc.imem.grant.bits.g_type := UInt<1>("h00") io.rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") io.rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") io.rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") io.rocc.imem.grant.bits.data := UInt<1>("h00") io.rocc.imem.grant.bits.addr_beat := UInt<1>("h00") io.rocc.imem.grant.valid := UInt<1>("h00") io.rocc.imem.acquire.ready := UInt<1>("h00") io.rocc.s := UInt<1>("h00") io.rocc.mem.ordered := UInt<1>("h00") io.rocc.mem.xcpt.pf.st := UInt<1>("h00") io.rocc.mem.xcpt.pf.ld := UInt<1>("h00") io.rocc.mem.xcpt.ma.st := UInt<1>("h00") io.rocc.mem.xcpt.ma.ld := UInt<1>("h00") io.rocc.mem.replay_next.bits := UInt<1>("h00") io.rocc.mem.replay_next.valid := UInt<1>("h00") io.rocc.mem.resp.bits.store_data := UInt<1>("h00") io.rocc.mem.resp.bits.data_word_bypass := UInt<1>("h00") io.rocc.mem.resp.bits.has_data := UInt<1>("h00") io.rocc.mem.resp.bits.replay := UInt<1>("h00") io.rocc.mem.resp.bits.nack := UInt<1>("h00") io.rocc.mem.resp.bits.data := UInt<1>("h00") io.rocc.mem.resp.bits.typ := UInt<1>("h00") io.rocc.mem.resp.bits.cmd := UInt<1>("h00") io.rocc.mem.resp.bits.tag := UInt<1>("h00") io.rocc.mem.resp.bits.addr := UInt<1>("h00") io.rocc.mem.resp.valid := UInt<1>("h00") io.rocc.mem.req.ready := UInt<1>("h00") io.rocc.resp.ready := UInt<1>("h00") io.rocc.cmd.bits.rs2 := UInt<1>("h00") io.rocc.cmd.bits.rs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.opcode := UInt<1>("h00") io.rocc.cmd.bits.inst.rd := UInt<1>("h00") io.rocc.cmd.bits.inst.xs2 := UInt<1>("h00") io.rocc.cmd.bits.inst.xs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.xd := UInt<1>("h00") io.rocc.cmd.bits.inst.rs1 := UInt<1>("h00") io.rocc.cmd.bits.inst.rs2 := UInt<1>("h00") io.rocc.cmd.bits.inst.funct := UInt<1>("h00") io.rocc.cmd.valid := UInt<1>("h00") io.fpu.killm := UInt<1>("h00") io.fpu.killx := UInt<1>("h00") io.fpu.valid := UInt<1>("h00") io.fpu.dmem_resp_data := UInt<1>("h00") io.fpu.dmem_resp_tag := UInt<1>("h00") io.fpu.dmem_resp_type := UInt<1>("h00") io.fpu.dmem_resp_val := UInt<1>("h00") io.fpu.fcsr_rm := UInt<1>("h00") io.fpu.fromint_data := UInt<1>("h00") io.fpu.inst := UInt<1>("h00") io.ptw.status.ie := UInt<1>("h00") io.ptw.status.prv := UInt<1>("h00") io.ptw.status.ie1 := UInt<1>("h00") io.ptw.status.prv1 := UInt<1>("h00") io.ptw.status.ie2 := UInt<1>("h00") io.ptw.status.prv2 := UInt<1>("h00") io.ptw.status.ie3 := UInt<1>("h00") io.ptw.status.prv3 := UInt<1>("h00") io.ptw.status.fs := UInt<1>("h00") io.ptw.status.xs := UInt<1>("h00") io.ptw.status.mprv := UInt<1>("h00") io.ptw.status.vm := UInt<1>("h00") io.ptw.status.zero1 := UInt<1>("h00") io.ptw.status.sd_rv32 := UInt<1>("h00") io.ptw.status.zero2 := UInt<1>("h00") io.ptw.status.sd := UInt<1>("h00") io.ptw.invalidate := UInt<1>("h00") io.ptw.ptbr := UInt<1>("h00") io.dmem.invalidate_lr := UInt<1>("h00") io.dmem.req.bits.data := UInt<1>("h00") io.dmem.req.bits.phys := UInt<1>("h00") io.dmem.req.bits.kill := UInt<1>("h00") io.dmem.req.bits.typ := UInt<1>("h00") io.dmem.req.bits.cmd := UInt<1>("h00") io.dmem.req.bits.tag := UInt<1>("h00") io.dmem.req.bits.addr := UInt<1>("h00") io.dmem.req.valid := UInt<1>("h00") io.imem.invalidate := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.entry := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.target := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.mask := UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.taken := UInt<1>("h00") io.imem.ras_update.bits.prediction.valid := UInt<1>("h00") io.imem.ras_update.bits.returnAddr := UInt<1>("h00") io.imem.ras_update.bits.isReturn := UInt<1>("h00") io.imem.ras_update.bits.isCall := UInt<1>("h00") io.imem.ras_update.valid := UInt<1>("h00") io.imem.bht_update.bits.mispredict := UInt<1>("h00") io.imem.bht_update.bits.taken := UInt<1>("h00") io.imem.bht_update.bits.pc := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.entry := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.target := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.mask := UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.taken := UInt<1>("h00") io.imem.bht_update.bits.prediction.valid := UInt<1>("h00") io.imem.bht_update.valid := UInt<1>("h00") io.imem.btb_update.bits.br_pc := UInt<1>("h00") io.imem.btb_update.bits.isReturn := UInt<1>("h00") io.imem.btb_update.bits.isJump := UInt<1>("h00") io.imem.btb_update.bits.taken := UInt<1>("h00") io.imem.btb_update.bits.target := UInt<1>("h00") io.imem.btb_update.bits.pc := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.entry := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.target := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.mask := UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.taken := UInt<1>("h00") io.imem.btb_update.bits.prediction.valid := UInt<1>("h00") io.imem.btb_update.valid := UInt<1>("h00") io.imem.resp.ready := UInt<1>("h00") io.imem.req.bits.pc := UInt<1>("h00") io.imem.req.valid := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.ipi_rep.ready := UInt<1>("h00") io.host.ipi_req.bits := UInt<1>("h00") io.host.ipi_req.valid := UInt<1>("h00") io.host.pcr.resp.bits := UInt<1>("h00") io.host.pcr.resp.valid := UInt<1>("h00") io.host.pcr.req.ready := UInt<1>("h00") reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset reg ex_reg_xcpt_interrupt : UInt<1>, clock, reset reg ex_reg_valid : UInt<1>, clock, reset reg ex_reg_btb_hit : UInt<1>, clock, reset reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset reg ex_reg_xcpt : UInt<1>, clock, reset reg ex_reg_flush_pipe : UInt<1>, clock, reset reg ex_reg_load_use : UInt<1>, clock, reset reg ex_reg_cause : UInt, clock, reset reg ex_reg_pc : UInt, clock, reset reg ex_reg_inst : UInt, clock, reset reg mem_reg_xcpt_interrupt : UInt<1>, clock, reset reg mem_reg_valid : UInt<1>, clock, reset reg mem_reg_btb_hit : UInt<1>, clock, reset reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset reg mem_reg_xcpt : UInt<1>, clock, reset reg mem_reg_replay : UInt<1>, clock, reset reg mem_reg_flush_pipe : UInt<1>, clock, reset reg mem_reg_cause : UInt, clock, reset reg mem_reg_slow_bypass : UInt<1>, clock, reset reg mem_reg_pc : UInt, clock, reset reg mem_reg_inst : UInt, clock, reset reg mem_reg_wdata : UInt, clock, reset reg mem_reg_rs2 : UInt, clock, reset wire take_pc_mem : UInt<1> take_pc_mem := UInt<1>("h00") reg wb_reg_valid : UInt<1>, clock, reset reg wb_reg_xcpt : UInt<1>, clock, reset reg wb_reg_replay : UInt<1>, clock, reset reg wb_reg_cause : UInt, clock, reset reg wb_reg_rocc_pending : UInt<1>, clock, reset onreset wb_reg_rocc_pending := UInt<1>("h00") reg wb_reg_pc : UInt, clock, reset reg wb_reg_inst : UInt, clock, reset reg wb_reg_wdata : UInt, clock, reset reg wb_reg_rs2 : UInt, clock, reset wire take_pc_wb : UInt<1> take_pc_wb := UInt<1>("h00") node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} id_ctrl.amo := UInt<1>("h00") id_ctrl.fence := UInt<1>("h00") id_ctrl.fence_i := UInt<1>("h00") id_ctrl.csr := UInt<1>("h00") id_ctrl.wxd := UInt<1>("h00") id_ctrl.div := UInt<1>("h00") id_ctrl.wfd := UInt<1>("h00") id_ctrl.rfs3 := UInt<1>("h00") id_ctrl.rfs2 := UInt<1>("h00") id_ctrl.rfs1 := UInt<1>("h00") id_ctrl.mem_type := UInt<1>("h00") id_ctrl.mem_cmd := UInt<1>("h00") id_ctrl.mem := UInt<1>("h00") id_ctrl.alu_fn := UInt<1>("h00") id_ctrl.alu_dw := UInt<1>("h00") id_ctrl.sel_imm := UInt<1>("h00") id_ctrl.sel_alu1 := UInt<1>("h00") id_ctrl.sel_alu2 := UInt<1>("h00") id_ctrl.rxs1 := UInt<1>("h00") id_ctrl.rxs2 := UInt<1>("h00") id_ctrl.jalr := UInt<1>("h00") id_ctrl.jal := UInt<1>("h00") id_ctrl.branch := UInt<1>("h00") id_ctrl.rocc := UInt<1>("h00") id_ctrl.fp := UInt<1>("h00") id_ctrl.legal := UInt<1>("h00") node T_3295 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_3297 = eq(T_3295, UInt<32>("h03")) node T_3299 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f")) node T_3301 = eq(T_3299, UInt<32>("h03")) node T_3303 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f")) node T_3305 = eq(T_3303, UInt<32>("h0f")) node T_3307 = and(io.imem.resp.bits.data[0], UInt<32>("h07077")) node T_3309 = eq(T_3307, UInt<32>("h013")) node T_3311 = and(io.imem.resp.bits.data[0], UInt<32>("h05f")) node T_3313 = eq(T_3311, UInt<32>("h017")) node T_3315 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f")) node T_3317 = eq(T_3315, UInt<32>("h033")) node T_3319 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) node T_3321 = eq(T_3319, UInt<32>("h033")) node T_3323 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073")) node T_3325 = eq(T_3323, UInt<32>("h043")) node T_3327 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f")) node T_3329 = eq(T_3327, UInt<32>("h053")) node T_3331 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b")) node T_3333 = eq(T_3331, UInt<32>("h063")) node T_3335 = and(io.imem.resp.bits.data[0], UInt<32>("h07f")) node T_3337 = eq(T_3335, UInt<32>("h06f")) node T_3339 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff")) node T_3341 = eq(T_3339, UInt<32>("h073")) node T_3343 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f")) node T_3345 = eq(T_3343, UInt<32>("h01013")) node T_3347 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f")) node T_3349 = eq(T_3347, UInt<32>("h0101b")) node T_3351 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b")) node T_3353 = eq(T_3351, UInt<32>("h02003")) node T_3355 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_3357 = eq(T_3355, UInt<32>("h02013")) node T_3359 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f")) node T_3361 = eq(T_3359, UInt<32>("h0202f")) node T_3363 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_3365 = eq(T_3363, UInt<32>("h02073")) node T_3367 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f")) node T_3369 = eq(T_3367, UInt<32>("h05013")) node T_3371 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f")) node T_3373 = eq(T_3371, UInt<32>("h0501b")) node T_3375 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) node T_3377 = eq(T_3375, UInt<32>("h05033")) node T_3379 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077")) node T_3381 = eq(T_3379, UInt<32>("h02004033")) node T_3383 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f")) node T_3385 = eq(T_3383, UInt<32>("h0800202f")) node T_3387 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) node T_3389 = eq(T_3387, UInt<32>("h010000073")) node T_3391 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) node T_3393 = eq(T_3391, UInt<32>("h01000202f")) node T_3395 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff")) node T_3397 = eq(T_3395, UInt<32>("h010100073")) node T_3399 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f")) node T_3401 = eq(T_3399, UInt<32>("h020000053")) node T_3403 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f")) node T_3405 = eq(T_3403, UInt<32>("h020000053")) node T_3407 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f")) node T_3409 = eq(T_3407, UInt<32>("h020000053")) node T_3411 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073")) node T_3413 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) node T_3415 = eq(T_3413, UInt<32>("h040100053")) node T_3417 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) node T_3419 = eq(T_3417, UInt<32>("h042000053")) node T_3421 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) node T_3423 = eq(T_3421, UInt<32>("h058000053")) node T_3425 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f")) node T_3427 = eq(T_3425, UInt<32>("h0c0000053")) node T_3429 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) node T_3431 = eq(T_3429, UInt<32>("h0e0000053")) node T_3433 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f")) node T_3435 = eq(T_3433, UInt<32>("h0e0000053")) node T_3437 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f")) node T_3439 = eq(T_3437, UInt<32>("h023")) node T_3441 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f")) node T_3443 = eq(T_3441, UInt<32>("h01063")) node T_3445 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f")) node T_3447 = eq(T_3445, UInt<32>("h04063")) node T_3449 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077")) node T_3451 = eq(T_3449, UInt<32>("h033")) node T_3453 = or(UInt<1>("h00"), T_3297) node T_3454 = or(T_3453, T_3301) node T_3455 = or(T_3454, T_3305) node T_3456 = or(T_3455, T_3309) node T_3457 = or(T_3456, T_3313) node T_3458 = or(T_3457, T_3317) node T_3459 = or(T_3458, T_3321) node T_3460 = or(T_3459, T_3325) node T_3461 = or(T_3460, T_3329) node T_3462 = or(T_3461, T_3333) node T_3463 = or(T_3462, T_3337) node T_3464 = or(T_3463, T_3341) node T_3465 = or(T_3464, T_3345) node T_3466 = or(T_3465, T_3349) node T_3467 = or(T_3466, T_3353) node T_3468 = or(T_3467, T_3357) node T_3469 = or(T_3468, T_3361) node T_3470 = or(T_3469, T_3365) node T_3471 = or(T_3470, T_3369) node T_3472 = or(T_3471, T_3373) node T_3473 = or(T_3472, T_3377) node T_3474 = or(T_3473, T_3381) node T_3475 = or(T_3474, T_3385) node T_3476 = or(T_3475, T_3389) node T_3477 = or(T_3476, T_3393) node T_3478 = or(T_3477, T_3397) node T_3479 = or(T_3478, T_3401) node T_3480 = or(T_3479, T_3405) node T_3481 = or(T_3480, T_3409) node T_3482 = or(T_3481, T_3411) node T_3483 = or(T_3482, T_3415) node T_3484 = or(T_3483, T_3419) node T_3485 = or(T_3484, T_3423) node T_3486 = or(T_3485, T_3427) node T_3487 = or(T_3486, T_3431) node T_3488 = or(T_3487, T_3435) node T_3489 = or(T_3488, T_3439) node T_3490 = or(T_3489, T_3443) node T_3491 = or(T_3490, T_3447) node T_3492 = or(T_3491, T_3451) node T_3494 = and(io.imem.resp.bits.data[0], UInt<32>("h05c")) node T_3496 = eq(T_3494, UInt<32>("h04")) node T_3498 = and(io.imem.resp.bits.data[0], UInt<32>("h060")) node T_3500 = eq(T_3498, UInt<32>("h040")) node T_3502 = or(UInt<1>("h00"), T_3496) node T_3503 = or(T_3502, T_3500) node T_3506 = and(io.imem.resp.bits.data[0], UInt<32>("h074")) node T_3508 = eq(T_3506, UInt<32>("h060")) node T_3510 = or(UInt<1>("h00"), T_3508) node T_3512 = and(io.imem.resp.bits.data[0], UInt<32>("h068")) node T_3514 = eq(T_3512, UInt<32>("h068")) node T_3516 = or(UInt<1>("h00"), T_3514) node T_3518 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c")) node T_3520 = eq(T_3518, UInt<32>("h024")) node T_3522 = or(UInt<1>("h00"), T_3520) node T_3524 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) node T_3526 = eq(T_3524, UInt<32>("h020")) node T_3528 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) node T_3530 = eq(T_3528, UInt<32>("h020")) node T_3532 = and(io.imem.resp.bits.data[0], UInt<32>("h02048")) node T_3534 = eq(T_3532, UInt<32>("h02008")) node T_3536 = or(UInt<1>("h00"), T_3526) node T_3537 = or(T_3536, T_3530) node T_3538 = or(T_3537, T_3534) node T_3540 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) node T_3542 = eq(T_3540, UInt<32>("h00")) node T_3544 = and(io.imem.resp.bits.data[0], UInt<32>("h04024")) node T_3546 = eq(T_3544, UInt<32>("h020")) node T_3548 = and(io.imem.resp.bits.data[0], UInt<32>("h038")) node T_3550 = eq(T_3548, UInt<32>("h020")) node T_3552 = and(io.imem.resp.bits.data[0], UInt<32>("h02050")) node T_3554 = eq(T_3552, UInt<32>("h02000")) node T_3556 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034")) node T_3558 = eq(T_3556, UInt<32>("h090000010")) node T_3560 = or(UInt<1>("h00"), T_3542) node T_3561 = or(T_3560, T_3546) node T_3562 = or(T_3561, T_3550) node T_3563 = or(T_3562, T_3554) node T_3564 = or(T_3563, T_3558) node T_3566 = and(io.imem.resp.bits.data[0], UInt<32>("h058")) node T_3568 = eq(T_3566, UInt<32>("h00")) node T_3570 = and(io.imem.resp.bits.data[0], UInt<32>("h020")) node T_3572 = eq(T_3570, UInt<32>("h00")) node T_3574 = and(io.imem.resp.bits.data[0], UInt<32>("h0c")) node T_3576 = eq(T_3574, UInt<32>("h04")) node T_3578 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) node T_3580 = eq(T_3578, UInt<32>("h048")) node T_3582 = and(io.imem.resp.bits.data[0], UInt<32>("h04050")) node T_3584 = eq(T_3582, UInt<32>("h04050")) node T_3586 = or(UInt<1>("h00"), T_3568) node T_3587 = or(T_3586, T_3572) node T_3588 = or(T_3587, T_3576) node T_3589 = or(T_3588, T_3580) node T_3590 = or(T_3589, T_3584) node T_3592 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) node T_3594 = eq(T_3592, UInt<32>("h00")) node T_3596 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) node T_3598 = eq(T_3596, UInt<32>("h00")) node T_3600 = and(io.imem.resp.bits.data[0], UInt<32>("h04008")) node T_3602 = eq(T_3600, UInt<32>("h04000")) node T_3604 = or(UInt<1>("h00"), T_3594) node T_3605 = or(T_3604, T_3542) node T_3606 = or(T_3605, T_3598) node T_3607 = or(T_3606, T_3602) node T_3608 = cat(T_3607, T_3590) node T_3610 = and(io.imem.resp.bits.data[0], UInt<32>("h04004")) node T_3612 = eq(T_3610, UInt<32>("h00")) node T_3614 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) node T_3616 = eq(T_3614, UInt<32>("h00")) node T_3618 = and(io.imem.resp.bits.data[0], UInt<32>("h024")) node T_3620 = eq(T_3618, UInt<32>("h00")) node T_3622 = or(UInt<1>("h00"), T_3612) node T_3623 = or(T_3622, T_3616) node T_3624 = or(T_3623, T_3542) node T_3625 = or(T_3624, T_3620) node T_3626 = or(T_3625, T_3598) node T_3628 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) node T_3630 = eq(T_3628, UInt<32>("h014")) node T_3632 = or(UInt<1>("h00"), T_3630) node T_3633 = or(T_3632, T_3580) node T_3634 = cat(T_3633, T_3626) node T_3636 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) node T_3638 = eq(T_3636, UInt<32>("h08")) node T_3640 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) node T_3642 = eq(T_3640, UInt<32>("h040")) node T_3644 = or(UInt<1>("h00"), T_3638) node T_3645 = or(T_3644, T_3642) node T_3647 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) node T_3649 = eq(T_3647, UInt<32>("h014")) node T_3651 = or(UInt<1>("h00"), T_3638) node T_3652 = or(T_3651, T_3649) node T_3654 = and(io.imem.resp.bits.data[0], UInt<32>("h030")) node T_3656 = eq(T_3654, UInt<32>("h00")) node T_3658 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c")) node T_3660 = eq(T_3658, UInt<32>("h04")) node T_3662 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) node T_3664 = eq(T_3662, UInt<32>("h010")) node T_3666 = or(UInt<1>("h00"), T_3656) node T_3667 = or(T_3666, T_3660) node T_3668 = or(T_3667, T_3664) node T_3669 = cat(T_3652, T_3645) node T_3670 = cat(T_3668, T_3669) node T_3672 = and(io.imem.resp.bits.data[0], UInt<32>("h010")) node T_3674 = eq(T_3672, UInt<32>("h00")) node T_3676 = and(io.imem.resp.bits.data[0], UInt<32>("h08")) node T_3678 = eq(T_3676, UInt<32>("h00")) node T_3680 = or(UInt<1>("h00"), T_3674) node T_3681 = or(T_3680, T_3678) node T_3683 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) node T_3685 = eq(T_3683, UInt<32>("h01010")) node T_3687 = and(io.imem.resp.bits.data[0], UInt<32>("h01058")) node T_3689 = eq(T_3687, UInt<32>("h01040")) node T_3691 = and(io.imem.resp.bits.data[0], UInt<32>("h07044")) node T_3693 = eq(T_3691, UInt<32>("h07000")) node T_3695 = or(UInt<1>("h00"), T_3685) node T_3696 = or(T_3695, T_3689) node T_3697 = or(T_3696, T_3693) node T_3699 = and(io.imem.resp.bits.data[0], UInt<32>("h02058")) node T_3701 = eq(T_3699, UInt<32>("h02040")) node T_3703 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) node T_3705 = eq(T_3703, UInt<32>("h03010")) node T_3707 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) node T_3709 = eq(T_3707, UInt<32>("h06010")) node T_3711 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034")) node T_3713 = eq(T_3711, UInt<32>("h040000030")) node T_3715 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054")) node T_3717 = eq(T_3715, UInt<32>("h040001010")) node T_3719 = or(UInt<1>("h00"), T_3701) node T_3720 = or(T_3719, T_3705) node T_3721 = or(T_3720, T_3709) node T_3722 = or(T_3721, T_3713) node T_3723 = or(T_3722, T_3717) node T_3725 = and(io.imem.resp.bits.data[0], UInt<32>("h02054")) node T_3727 = eq(T_3725, UInt<32>("h02010")) node T_3729 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054")) node T_3731 = eq(T_3729, UInt<32>("h04010")) node T_3733 = and(io.imem.resp.bits.data[0], UInt<32>("h05054")) node T_3735 = eq(T_3733, UInt<32>("h04010")) node T_3737 = and(io.imem.resp.bits.data[0], UInt<32>("h04058")) node T_3739 = eq(T_3737, UInt<32>("h04040")) node T_3741 = or(UInt<1>("h00"), T_3727) node T_3742 = or(T_3741, T_3731) node T_3743 = or(T_3742, T_3735) node T_3744 = or(T_3743, T_3739) node T_3746 = and(io.imem.resp.bits.data[0], UInt<32>("h054")) node T_3748 = eq(T_3746, UInt<32>("h040")) node T_3750 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) node T_3752 = eq(T_3750, UInt<32>("h02010")) node T_3754 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054")) node T_3756 = eq(T_3754, UInt<32>("h040001010")) node T_3758 = or(UInt<1>("h00"), T_3748) node T_3759 = or(T_3758, T_3752) node T_3760 = or(T_3759, T_3713) node T_3761 = or(T_3760, T_3756) node T_3762 = cat(T_3723, T_3697) node T_3763 = cat(T_3744, T_3762) node T_3764 = cat(T_3761, T_3763) node T_3766 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f")) node T_3768 = eq(T_3766, UInt<32>("h03")) node T_3770 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f")) node T_3772 = eq(T_3770, UInt<32>("h03")) node T_3774 = or(UInt<1>("h00"), T_3768) node T_3775 = or(T_3774, T_3297) node T_3776 = or(T_3775, T_3772) node T_3777 = or(T_3776, T_3353) node T_3778 = or(T_3777, T_3361) node T_3779 = or(T_3778, T_3385) node T_3780 = or(T_3779, T_3393) node T_3782 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) node T_3784 = eq(T_3782, UInt<32>("h020")) node T_3786 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020")) node T_3788 = eq(T_3786, UInt<32>("h018000020")) node T_3790 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020")) node T_3792 = eq(T_3790, UInt<32>("h020000020")) node T_3794 = or(UInt<1>("h00"), T_3784) node T_3795 = or(T_3794, T_3788) node T_3796 = or(T_3795, T_3792) node T_3798 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008")) node T_3800 = eq(T_3798, UInt<32>("h010000008")) node T_3802 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008")) node T_3804 = eq(T_3802, UInt<32>("h040000008")) node T_3806 = or(UInt<1>("h00"), T_3800) node T_3807 = or(T_3806, T_3804) node T_3809 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008")) node T_3811 = eq(T_3809, UInt<32>("h08000008")) node T_3813 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008")) node T_3815 = eq(T_3813, UInt<32>("h080000008")) node T_3817 = or(UInt<1>("h00"), T_3811) node T_3818 = or(T_3817, T_3800) node T_3819 = or(T_3818, T_3815) node T_3821 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008")) node T_3823 = eq(T_3821, UInt<32>("h08")) node T_3825 = or(UInt<1>("h00"), T_3823) node T_3827 = cat(T_3807, T_3796) node T_3828 = cat(T_3819, T_3827) node T_3829 = cat(T_3825, T_3828) node T_3830 = cat(UInt<1>("h00"), T_3829) node T_3832 = and(io.imem.resp.bits.data[0], UInt<32>("h01000")) node T_3834 = eq(T_3832, UInt<32>("h01000")) node T_3836 = or(UInt<1>("h00"), T_3834) node T_3838 = and(io.imem.resp.bits.data[0], UInt<32>("h02000")) node T_3840 = eq(T_3838, UInt<32>("h02000")) node T_3842 = or(UInt<1>("h00"), T_3840) node T_3844 = and(io.imem.resp.bits.data[0], UInt<32>("h04000")) node T_3846 = eq(T_3844, UInt<32>("h04000")) node T_3848 = or(UInt<1>("h00"), T_3846) node T_3849 = cat(T_3842, T_3836) node T_3850 = cat(T_3848, T_3849) node T_3852 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060")) node T_3854 = eq(T_3852, UInt<32>("h040")) node T_3856 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) node T_3858 = eq(T_3856, UInt<32>("h040")) node T_3860 = and(io.imem.resp.bits.data[0], UInt<32>("h070")) node T_3862 = eq(T_3860, UInt<32>("h040")) node T_3864 = or(UInt<1>("h00"), T_3854) node T_3865 = or(T_3864, T_3858) node T_3866 = or(T_3865, T_3862) node T_3868 = and(io.imem.resp.bits.data[0], UInt<32>("h07c")) node T_3870 = eq(T_3868, UInt<32>("h024")) node T_3872 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060")) node T_3874 = eq(T_3872, UInt<32>("h040")) node T_3876 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060")) node T_3878 = eq(T_3876, UInt<32>("h010000040")) node T_3880 = or(UInt<1>("h00"), T_3870) node T_3881 = or(T_3880, T_3874) node T_3882 = or(T_3881, T_3862) node T_3883 = or(T_3882, T_3878) node T_3885 = or(UInt<1>("h00"), T_3862) node T_3887 = and(io.imem.resp.bits.data[0], UInt<32>("h03c")) node T_3889 = eq(T_3887, UInt<32>("h04")) node T_3891 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) node T_3893 = eq(T_3891, UInt<32>("h010000040")) node T_3895 = or(UInt<1>("h00"), T_3889) node T_3896 = or(T_3895, T_3854) node T_3897 = or(T_3896, T_3862) node T_3898 = or(T_3897, T_3893) node T_3900 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074")) node T_3902 = eq(T_3900, UInt<32>("h02000030")) node T_3904 = or(UInt<1>("h00"), T_3902) node T_3906 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) node T_3908 = eq(T_3906, UInt<32>("h00")) node T_3910 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) node T_3912 = eq(T_3910, UInt<32>("h010")) node T_3914 = and(io.imem.resp.bits.data[0], UInt<32>("h02024")) node T_3916 = eq(T_3914, UInt<32>("h024")) node T_3918 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) node T_3920 = eq(T_3918, UInt<32>("h028")) node T_3922 = and(io.imem.resp.bits.data[0], UInt<32>("h01030")) node T_3924 = eq(T_3922, UInt<32>("h01030")) node T_3926 = and(io.imem.resp.bits.data[0], UInt<32>("h02030")) node T_3928 = eq(T_3926, UInt<32>("h02030")) node T_3930 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010")) node T_3932 = eq(T_3930, UInt<32>("h080000010")) node T_3934 = or(UInt<1>("h00"), T_3908) node T_3935 = or(T_3934, T_3912) node T_3936 = or(T_3935, T_3916) node T_3937 = or(T_3936, T_3920) node T_3938 = or(T_3937, T_3924) node T_3939 = or(T_3938, T_3928) node T_3940 = or(T_3939, T_3932) node T_3942 = and(io.imem.resp.bits.data[0], UInt<32>("h01070")) node T_3944 = eq(T_3942, UInt<32>("h01070")) node T_3946 = or(UInt<1>("h00"), T_3944) node T_3948 = and(io.imem.resp.bits.data[0], UInt<32>("h02070")) node T_3950 = eq(T_3948, UInt<32>("h02070")) node T_3952 = or(UInt<1>("h00"), T_3950) node T_3954 = and(io.imem.resp.bits.data[0], UInt<32>("h03070")) node T_3956 = eq(T_3954, UInt<32>("h070")) node T_3958 = or(UInt<1>("h00"), T_3956) node T_3959 = cat(T_3952, T_3946) node T_3960 = cat(T_3958, T_3959) node T_3962 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) node T_3964 = eq(T_3962, UInt<32>("h01008")) node T_3966 = or(UInt<1>("h00"), T_3964) node T_3968 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) node T_3970 = eq(T_3968, UInt<32>("h08")) node T_3972 = or(UInt<1>("h00"), T_3970) node T_3974 = and(io.imem.resp.bits.data[0], UInt<32>("h06048")) node T_3976 = eq(T_3974, UInt<32>("h02008")) node T_3978 = or(UInt<1>("h00"), T_3976) id_ctrl.legal := T_3492 id_ctrl.fp := T_3503 id_ctrl.rocc := UInt<1>("h00") id_ctrl.branch := T_3510 id_ctrl.jal := T_3516 id_ctrl.jalr := T_3522 id_ctrl.rxs2 := T_3538 id_ctrl.rxs1 := T_3564 id_ctrl.sel_alu2 := T_3608 id_ctrl.sel_alu1 := T_3634 id_ctrl.sel_imm := T_3670 id_ctrl.alu_dw := T_3681 id_ctrl.alu_fn := T_3764 id_ctrl.mem := T_3780 id_ctrl.mem_cmd := T_3830 id_ctrl.mem_type := T_3850 id_ctrl.rfs1 := T_3866 id_ctrl.rfs2 := T_3883 id_ctrl.rfs3 := T_3885 id_ctrl.wfd := T_3898 id_ctrl.div := T_3904 id_ctrl.wxd := T_3940 id_ctrl.csr := T_3960 id_ctrl.fence_i := T_3966 id_ctrl.fence := T_3972 id_ctrl.amo := T_3978 node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27) node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20) node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15) node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7) wire id_load_use : UInt<1> id_load_use := UInt<1>("h00") reg id_reg_fence : UInt<1>, clock, reset onreset id_reg_fence := UInt<1>("h00") cmem T_3990 : UInt<64>[31], clock wire T_3992 : UInt T_3992 := UInt<1>("h00") node T_3994 = not(id_raddr1) infer accessor T_3995 = T_3990[T_3994] T_3992 := T_3995 wire T_3997 : UInt T_3997 := UInt<1>("h00") node T_3999 = not(id_raddr2) infer accessor T_4000 = T_3990[T_3999] T_3997 := T_4000 wire ctrl_killd : UInt<1> ctrl_killd := UInt<1>("h00") inst csr of CSRFile csr.io.rocc.pptw.req.bits.fetch := UInt<1>("h00") csr.io.rocc.pptw.req.bits.store := UInt<1>("h00") csr.io.rocc.pptw.req.bits.prv := UInt<1>("h00") csr.io.rocc.pptw.req.bits.addr := UInt<1>("h00") csr.io.rocc.pptw.req.valid := UInt<1>("h00") csr.io.rocc.dptw.req.bits.fetch := UInt<1>("h00") csr.io.rocc.dptw.req.bits.store := UInt<1>("h00") csr.io.rocc.dptw.req.bits.prv := UInt<1>("h00") csr.io.rocc.dptw.req.bits.addr := UInt<1>("h00") csr.io.rocc.dptw.req.valid := UInt<1>("h00") csr.io.rocc.iptw.req.bits.fetch := UInt<1>("h00") csr.io.rocc.iptw.req.bits.store := UInt<1>("h00") csr.io.rocc.iptw.req.bits.prv := UInt<1>("h00") csr.io.rocc.iptw.req.bits.addr := UInt<1>("h00") csr.io.rocc.iptw.req.valid := UInt<1>("h00") csr.io.rocc.dmem.grant.ready := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.union := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.data := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") csr.io.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") csr.io.rocc.dmem.acquire.valid := UInt<1>("h00") csr.io.rocc.imem.grant.ready := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.union := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.a_type := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.data := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") csr.io.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") csr.io.rocc.imem.acquire.valid := UInt<1>("h00") csr.io.rocc.interrupt := UInt<1>("h00") csr.io.rocc.busy := UInt<1>("h00") csr.io.rocc.mem.invalidate_lr := UInt<1>("h00") csr.io.rocc.mem.req.bits.data := UInt<1>("h00") csr.io.rocc.mem.req.bits.phys := UInt<1>("h00") csr.io.rocc.mem.req.bits.kill := UInt<1>("h00") csr.io.rocc.mem.req.bits.typ := UInt<1>("h00") csr.io.rocc.mem.req.bits.cmd := UInt<1>("h00") csr.io.rocc.mem.req.bits.tag := UInt<1>("h00") csr.io.rocc.mem.req.bits.addr := UInt<1>("h00") csr.io.rocc.mem.req.valid := UInt<1>("h00") csr.io.rocc.resp.bits.data := UInt<1>("h00") csr.io.rocc.resp.bits.rd := UInt<1>("h00") csr.io.rocc.resp.valid := UInt<1>("h00") csr.io.rocc.cmd.ready := UInt<1>("h00") csr.io.fcsr_flags.bits := UInt<1>("h00") csr.io.fcsr_flags.valid := UInt<1>("h00") csr.io.pc := UInt<1>("h00") csr.io.cause := UInt<1>("h00") csr.io.uarch_counters[0] := UInt<1>("h00") csr.io.uarch_counters[1] := UInt<1>("h00") csr.io.uarch_counters[2] := UInt<1>("h00") csr.io.uarch_counters[3] := UInt<1>("h00") csr.io.uarch_counters[4] := UInt<1>("h00") csr.io.uarch_counters[5] := UInt<1>("h00") csr.io.uarch_counters[6] := UInt<1>("h00") csr.io.uarch_counters[7] := UInt<1>("h00") csr.io.uarch_counters[8] := UInt<1>("h00") csr.io.uarch_counters[9] := UInt<1>("h00") csr.io.uarch_counters[10] := UInt<1>("h00") csr.io.uarch_counters[11] := UInt<1>("h00") csr.io.uarch_counters[12] := UInt<1>("h00") csr.io.uarch_counters[13] := UInt<1>("h00") csr.io.uarch_counters[14] := UInt<1>("h00") csr.io.uarch_counters[15] := UInt<1>("h00") csr.io.retire := UInt<1>("h00") csr.io.exception := UInt<1>("h00") csr.io.rw.wdata := UInt<1>("h00") csr.io.rw.cmd := UInt<1>("h00") csr.io.rw.addr := UInt<1>("h00") csr.io.host.ipi_rep.bits := UInt<1>("h00") csr.io.host.ipi_rep.valid := UInt<1>("h00") csr.io.host.ipi_req.ready := UInt<1>("h00") csr.io.host.pcr.resp.ready := UInt<1>("h00") csr.io.host.pcr.req.bits.data := UInt<1>("h00") csr.io.host.pcr.req.bits.addr := UInt<1>("h00") csr.io.host.pcr.req.bits.rw := UInt<1>("h00") csr.io.host.pcr.req.valid := UInt<1>("h00") csr.io.host.id := UInt<1>("h00") csr.io.host.reset := UInt<1>("h00") csr.clock := clock csr.reset := reset node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) node T_4090 = eq(id_ctrl.csr, UInt<3>("h02")) node T_4091 = eq(id_ctrl.csr, UInt<3>("h03")) node T_4092 = or(T_4090, T_4091) node T_4094 = eq(id_raddr1, UInt<1>("h00")) node id_csr_ren = and(T_4092, T_4094) node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20) node T_4099 = eq(id_csr_ren, UInt<1>("h00")) node T_4100 = and(id_csr_en, T_4099) node T_4158 = and(id_csr_addr, UInt<12>("h08c4")) node T_4160 = eq(T_4158, UInt<12>("h040")) node T_4162 = or(UInt<1>("h00"), T_4160) node T_4163 = bit(T_4162, 0) node T_4165 = eq(T_4163, UInt<1>("h00")) node T_4166 = and(T_4100, T_4165) node id_csr_flush = or(id_system_insn, T_4166) node T_4169 = eq(id_ctrl.legal, UInt<1>("h00")) node T_4171 = neq(csr.io.status.fs, UInt<1>("h00")) node T_4173 = eq(T_4171, UInt<1>("h00")) node T_4174 = and(id_ctrl.fp, T_4173) node T_4175 = or(T_4169, T_4174) node T_4177 = neq(csr.io.status.xs, UInt<1>("h00")) node T_4179 = eq(T_4177, UInt<1>("h00")) node T_4180 = and(id_ctrl.rocc, T_4179) node id_illegal_insn = or(T_4175, T_4180) node id_amo_aq = bit(io.imem.resp.bits.data[0], 26) node id_amo_rl = bit(io.imem.resp.bits.data[0], 25) node T_4184 = and(id_ctrl.amo, id_amo_rl) node id_fence_next = or(id_ctrl.fence, T_4184) node T_4187 = eq(io.dmem.ordered, UInt<1>("h00")) node id_mem_busy = or(T_4187, io.dmem.req.valid) node T_4190 = and(ex_reg_valid, ex_ctrl.rocc) node T_4191 = or(io.rocc.busy, T_4190) node T_4192 = and(mem_reg_valid, mem_ctrl.rocc) node T_4193 = or(T_4191, T_4192) node T_4194 = and(wb_reg_valid, wb_ctrl.rocc) node T_4195 = or(T_4193, T_4194) node id_rocc_busy = and(UInt<1>("h00"), T_4195) node T_4197 = and(id_reg_fence, id_mem_busy) node T_4198 = or(id_fence_next, T_4197) id_reg_fence := T_4198 node T_4199 = and(id_rocc_busy, id_ctrl.fence) node T_4200 = and(id_ctrl.amo, id_amo_aq) node T_4201 = or(T_4200, id_ctrl.fence_i) node T_4202 = or(id_ctrl.mem, id_ctrl.rocc) node T_4203 = and(id_reg_fence, T_4202) node T_4204 = or(T_4201, T_4203) node T_4205 = or(T_4204, id_csr_en) node T_4206 = and(id_mem_busy, T_4205) node id_do_fence = or(T_4199, T_4206) node T_4210 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) node id_xcpt = or(T_4210, id_illegal_insn) node T_4212 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_4212) node ex_waddr = bits(ex_reg_inst, 11, 7) node mem_waddr = bits(mem_reg_inst, 11, 7) node wb_waddr = bits(wb_reg_inst, 11, 7) node T_4220 = and(ex_reg_valid, ex_ctrl.wxd) node T_4221 = and(mem_reg_valid, mem_ctrl.wxd) node T_4223 = eq(mem_ctrl.mem, UInt<1>("h00")) node T_4224 = and(T_4221, T_4223) node T_4225 = and(mem_reg_valid, mem_ctrl.wxd) node T_4226 = eq(UInt<1>("h00"), id_raddr1) node T_4227 = and(UInt<1>("h01"), T_4226) node T_4228 = eq(ex_waddr, id_raddr1) node T_4229 = and(T_4220, T_4228) node T_4230 = eq(mem_waddr, id_raddr1) node T_4231 = and(T_4224, T_4230) node T_4232 = eq(mem_waddr, id_raddr1) node T_4233 = and(T_4225, T_4232) node T_4234 = eq(UInt<1>("h00"), id_raddr2) node T_4235 = and(UInt<1>("h01"), T_4234) node T_4236 = eq(ex_waddr, id_raddr2) node T_4237 = and(T_4220, T_4236) node T_4238 = eq(mem_waddr, id_raddr2) node T_4239 = and(T_4224, T_4238) node T_4240 = eq(mem_waddr, id_raddr2) node T_4241 = and(T_4225, T_4240) wire bypass_mux : UInt[4] bypass_mux[0] := UInt<1>("h00") bypass_mux[1] := mem_reg_wdata bypass_mux[2] := wb_reg_wdata bypass_mux[3] := io.dmem.resp.bits.data_word_bypass reg ex_reg_rs_bypass : UInt<1>[2], clock, reset reg ex_reg_rs_lsb : UInt[2], clock, reset reg ex_reg_rs_msb : UInt[2], clock, reset infer accessor T_4285 = bypass_mux[ex_reg_rs_lsb[0]] node T_4286 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) node T_4287 = mux(ex_reg_rs_bypass[0], T_4285, T_4286) infer accessor T_4288 = bypass_mux[ex_reg_rs_lsb[1]] node T_4289 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) node T_4290 = mux(ex_reg_rs_bypass[1], T_4288, T_4289) node T_4291 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_4293 = bit(ex_reg_inst, 31) node T_4294 = asSInt(T_4293) node T_4295 = mux(T_4291, asSInt(UInt<1>("h00")), T_4294) node T_4296 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_4297 = bits(ex_reg_inst, 30, 20) node T_4298 = asSInt(T_4297) node T_4299 = mux(T_4296, T_4298, T_4295) node T_4300 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_4301 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) node T_4302 = and(T_4300, T_4301) node T_4303 = bits(ex_reg_inst, 19, 12) node T_4304 = asSInt(T_4303) node T_4305 = mux(T_4302, T_4295, T_4304) node T_4306 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_4307 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_4308 = or(T_4306, T_4307) node T_4310 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) node T_4311 = bit(ex_reg_inst, 20) node T_4312 = asSInt(T_4311) node T_4313 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) node T_4314 = bit(ex_reg_inst, 7) node T_4315 = asSInt(T_4314) node T_4316 = mux(T_4313, T_4315, T_4295) node T_4317 = mux(T_4310, T_4312, T_4316) node T_4318 = mux(T_4308, asSInt(UInt<1>("h00")), T_4317) node T_4319 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_4320 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_4321 = or(T_4319, T_4320) node T_4323 = bits(ex_reg_inst, 30, 25) node T_4324 = mux(T_4321, UInt<1>("h00"), T_4323) node T_4325 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_4327 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) node T_4328 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) node T_4329 = or(T_4327, T_4328) node T_4330 = bits(ex_reg_inst, 11, 8) node T_4331 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_4332 = bits(ex_reg_inst, 19, 16) node T_4333 = bits(ex_reg_inst, 24, 21) node T_4334 = mux(T_4331, T_4332, T_4333) node T_4335 = mux(T_4329, T_4330, T_4334) node T_4336 = mux(T_4325, UInt<1>("h00"), T_4335) node T_4337 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) node T_4338 = bit(ex_reg_inst, 7) node T_4339 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) node T_4340 = bit(ex_reg_inst, 20) node T_4341 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_4342 = bit(ex_reg_inst, 15) node T_4344 = shl(T_4342, 0) node T_4345 = mux(T_4341, T_4344, UInt<1>("h00")) node T_4346 = shl(T_4340, 0) node T_4347 = mux(T_4339, T_4346, T_4345) node T_4348 = shl(T_4338, 0) node T_4349 = mux(T_4337, T_4348, T_4347) node T_4350 = asUInt(T_4295) node T_4351 = asUInt(T_4299) node T_4352 = asUInt(T_4305) node T_4353 = cat(T_4351, T_4352) node T_4354 = cat(T_4350, T_4353) node T_4355 = asUInt(T_4318) node T_4356 = cat(T_4355, T_4324) node T_4357 = cat(T_4336, T_4349) node T_4358 = cat(T_4356, T_4357) node T_4359 = cat(T_4354, T_4358) node ex_imm = asSInt(T_4359) node T_4362 = asSInt(T_4287) node T_4363 = asSInt(ex_reg_pc) node T_4364 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) node T_4365 = mux(T_4364, T_4363, asSInt(UInt<1>("h00"))) node T_4366 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) node ex_op1 = mux(T_4366, T_4362, T_4365) node T_4369 = asSInt(T_4290) node T_4371 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) node T_4372 = mux(T_4371, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) node T_4373 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) node T_4374 = mux(T_4373, ex_imm, T_4372) node T_4375 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) node ex_op2 = mux(T_4375, T_4369, T_4374) inst alu of ALU alu.io.in1 := UInt<1>("h00") alu.io.in2 := UInt<1>("h00") alu.io.fn := UInt<1>("h00") alu.io.dw := UInt<1>("h00") alu.clock := clock alu.reset := reset alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn node T_4382 = asUInt(ex_op2) alu.io.in2 := T_4382 node T_4383 = asUInt(ex_op1) alu.io.in1 := T_4383 inst div of MulDiv div.io.resp.ready := UInt<1>("h00") div.io.kill := UInt<1>("h00") div.io.req.bits.tag := UInt<1>("h00") div.io.req.bits.in2 := UInt<1>("h00") div.io.req.bits.in1 := UInt<1>("h00") div.io.req.bits.dw := UInt<1>("h00") div.io.req.bits.fn := UInt<1>("h00") div.io.req.valid := UInt<1>("h00") div.clock := clock div.reset := reset node T_4393 = and(ex_reg_valid, ex_ctrl.div) div.io.req.valid := T_4393 div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := T_4287 div.io.req.bits.in2 := T_4290 div.io.req.bits.tag := ex_waddr node T_4395 = eq(ctrl_killd, UInt<1>("h00")) ex_reg_valid := T_4395 node T_4397 = eq(ctrl_killd, UInt<1>("h00")) node T_4398 = and(T_4397, id_xcpt) ex_reg_xcpt := T_4398 node T_4400 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_4401 = and(csr.io.interrupt, T_4400) node T_4402 = and(T_4401, io.imem.resp.valid) ex_reg_xcpt_interrupt := T_4402 when id_xcpt : ex_reg_cause := id_cause skip node T_4404 = eq(ctrl_killd, UInt<1>("h00")) when T_4404 : ex_ctrl <> id_ctrl ex_ctrl.csr := id_csr ex_reg_btb_hit := io.imem.btb_resp.valid when io.imem.btb_resp.valid : ex_reg_btb_resp <> io.imem.btb_resp.bits skip node T_4405 = or(id_ctrl.fence_i, id_csr_flush) ex_reg_flush_pipe := T_4405 ex_reg_load_use := id_load_use node T_4406 = or(T_4227, T_4229) node T_4407 = or(T_4406, T_4231) node T_4408 = or(T_4407, T_4233) node T_4413 = mux(T_4231, UInt<2>("h02"), UInt<2>("h03")) node T_4414 = mux(T_4229, UInt<1>("h01"), T_4413) node T_4415 = mux(T_4227, UInt<1>("h00"), T_4414) ex_reg_rs_bypass[0] := T_4408 ex_reg_rs_lsb[0] := T_4415 node T_4417 = eq(T_4408, UInt<1>("h00")) node T_4418 = and(id_ctrl.rxs1, T_4417) when T_4418 : node T_4419 = bits(T_3992, 1, 0) ex_reg_rs_lsb[0] := T_4419 node T_4420 = shr(T_3992, 2) ex_reg_rs_msb[0] := T_4420 skip node T_4421 = or(T_4235, T_4237) node T_4422 = or(T_4421, T_4239) node T_4423 = or(T_4422, T_4241) node T_4428 = mux(T_4239, UInt<2>("h02"), UInt<2>("h03")) node T_4429 = mux(T_4237, UInt<1>("h01"), T_4428) node T_4430 = mux(T_4235, UInt<1>("h00"), T_4429) ex_reg_rs_bypass[1] := T_4423 ex_reg_rs_lsb[1] := T_4430 node T_4432 = eq(T_4423, UInt<1>("h00")) node T_4433 = and(id_ctrl.rxs2, T_4432) when T_4433 : node T_4434 = bits(T_3997, 1, 0) ex_reg_rs_lsb[1] := T_4434 node T_4435 = shr(T_3997, 2) ex_reg_rs_msb[1] := T_4435 skip skip node T_4437 = eq(ctrl_killd, UInt<1>("h00")) node T_4438 = or(T_4437, csr.io.interrupt) when T_4438 : ex_reg_inst := io.imem.resp.bits.data[0] ex_reg_pc := io.imem.resp.bits.pc skip node T_4440 = eq(io.dmem.resp.valid, UInt<1>("h00")) node wb_dcache_miss = and(wb_ctrl.mem, T_4440) node T_4443 = eq(io.dmem.req.ready, UInt<1>("h00")) node T_4444 = and(ex_ctrl.mem, T_4443) node T_4446 = eq(div.io.req.ready, UInt<1>("h00")) node T_4447 = and(ex_ctrl.div, T_4446) node replay_ex_structural = or(T_4444, T_4447) node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) node T_4450 = or(replay_ex_structural, replay_ex_load_use) node replay_ex = and(ex_reg_valid, T_4450) node T_4452 = or(take_pc_mem_wb, replay_ex) node T_4454 = eq(ex_reg_valid, UInt<1>("h00")) node ctrl_killx = or(T_4452, T_4454) node T_4456 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) wire T_4458 : UInt<3>[4] T_4458[0] := UInt<3>("h00") T_4458[1] := UInt<3>("h04") T_4458[2] := UInt<3>("h01") T_4458[3] := UInt<3>("h05") node T_4464 = eq(T_4458[0], ex_ctrl.mem_type) node T_4465 = eq(T_4458[1], ex_ctrl.mem_type) node T_4466 = eq(T_4458[2], ex_ctrl.mem_type) node T_4467 = eq(T_4458[3], ex_ctrl.mem_type) node T_4469 = or(UInt<1>("h00"), T_4464) node T_4470 = or(T_4469, T_4465) node T_4471 = or(T_4470, T_4466) node T_4472 = or(T_4471, T_4467) node ex_slow_bypass = or(T_4456, T_4472) node T_4474 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) node T_4475 = and(ex_ctrl.fp, io.fpu.illegal_rm) node ex_xcpt = or(T_4474, T_4475) node ex_cause = mux(T_4474, ex_reg_cause, UInt<2>("h02")) node mem_br_taken = bit(mem_reg_wdata, 0) node T_4480 = asSInt(mem_reg_pc) node T_4481 = and(mem_ctrl.branch, mem_br_taken) node T_4482 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_4484 = bit(mem_reg_inst, 31) node T_4485 = asSInt(T_4484) node T_4486 = mux(T_4482, asSInt(UInt<1>("h00")), T_4485) node T_4487 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_4488 = bits(mem_reg_inst, 30, 20) node T_4489 = asSInt(T_4488) node T_4490 = mux(T_4487, T_4489, T_4486) node T_4491 = neq(UInt<3>("h01"), UInt<3>("h02")) node T_4492 = neq(UInt<3>("h01"), UInt<3>("h03")) node T_4493 = and(T_4491, T_4492) node T_4494 = bits(mem_reg_inst, 19, 12) node T_4495 = asSInt(T_4494) node T_4496 = mux(T_4493, T_4486, T_4495) node T_4497 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_4498 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_4499 = or(T_4497, T_4498) node T_4501 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_4502 = bit(mem_reg_inst, 20) node T_4503 = asSInt(T_4502) node T_4504 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_4505 = bit(mem_reg_inst, 7) node T_4506 = asSInt(T_4505) node T_4507 = mux(T_4504, T_4506, T_4486) node T_4508 = mux(T_4501, T_4503, T_4507) node T_4509 = mux(T_4499, asSInt(UInt<1>("h00")), T_4508) node T_4510 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_4511 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_4512 = or(T_4510, T_4511) node T_4514 = bits(mem_reg_inst, 30, 25) node T_4515 = mux(T_4512, UInt<1>("h00"), T_4514) node T_4516 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_4518 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_4519 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_4520 = or(T_4518, T_4519) node T_4521 = bits(mem_reg_inst, 11, 8) node T_4522 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_4523 = bits(mem_reg_inst, 19, 16) node T_4524 = bits(mem_reg_inst, 24, 21) node T_4525 = mux(T_4522, T_4523, T_4524) node T_4526 = mux(T_4520, T_4521, T_4525) node T_4527 = mux(T_4516, UInt<1>("h00"), T_4526) node T_4528 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_4529 = bit(mem_reg_inst, 7) node T_4530 = eq(UInt<3>("h01"), UInt<3>("h04")) node T_4531 = bit(mem_reg_inst, 20) node T_4532 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_4533 = bit(mem_reg_inst, 15) node T_4535 = shl(T_4533, 0) node T_4536 = mux(T_4532, T_4535, UInt<1>("h00")) node T_4537 = shl(T_4531, 0) node T_4538 = mux(T_4530, T_4537, T_4536) node T_4539 = shl(T_4529, 0) node T_4540 = mux(T_4528, T_4539, T_4538) node T_4541 = asUInt(T_4486) node T_4542 = asUInt(T_4490) node T_4543 = asUInt(T_4496) node T_4544 = cat(T_4542, T_4543) node T_4545 = cat(T_4541, T_4544) node T_4546 = asUInt(T_4509) node T_4547 = cat(T_4546, T_4515) node T_4548 = cat(T_4527, T_4540) node T_4549 = cat(T_4547, T_4548) node T_4550 = cat(T_4545, T_4549) node T_4551 = asSInt(T_4550) node T_4552 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_4554 = bit(mem_reg_inst, 31) node T_4555 = asSInt(T_4554) node T_4556 = mux(T_4552, asSInt(UInt<1>("h00")), T_4555) node T_4557 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_4558 = bits(mem_reg_inst, 30, 20) node T_4559 = asSInt(T_4558) node T_4560 = mux(T_4557, T_4559, T_4556) node T_4561 = neq(UInt<3>("h03"), UInt<3>("h02")) node T_4562 = neq(UInt<3>("h03"), UInt<3>("h03")) node T_4563 = and(T_4561, T_4562) node T_4564 = bits(mem_reg_inst, 19, 12) node T_4565 = asSInt(T_4564) node T_4566 = mux(T_4563, T_4556, T_4565) node T_4567 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_4568 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_4569 = or(T_4567, T_4568) node T_4571 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_4572 = bit(mem_reg_inst, 20) node T_4573 = asSInt(T_4572) node T_4574 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_4575 = bit(mem_reg_inst, 7) node T_4576 = asSInt(T_4575) node T_4577 = mux(T_4574, T_4576, T_4556) node T_4578 = mux(T_4571, T_4573, T_4577) node T_4579 = mux(T_4569, asSInt(UInt<1>("h00")), T_4578) node T_4580 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_4581 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_4582 = or(T_4580, T_4581) node T_4584 = bits(mem_reg_inst, 30, 25) node T_4585 = mux(T_4582, UInt<1>("h00"), T_4584) node T_4586 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_4588 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_4589 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_4590 = or(T_4588, T_4589) node T_4591 = bits(mem_reg_inst, 11, 8) node T_4592 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_4593 = bits(mem_reg_inst, 19, 16) node T_4594 = bits(mem_reg_inst, 24, 21) node T_4595 = mux(T_4592, T_4593, T_4594) node T_4596 = mux(T_4590, T_4591, T_4595) node T_4597 = mux(T_4586, UInt<1>("h00"), T_4596) node T_4598 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_4599 = bit(mem_reg_inst, 7) node T_4600 = eq(UInt<3>("h03"), UInt<3>("h04")) node T_4601 = bit(mem_reg_inst, 20) node T_4602 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_4603 = bit(mem_reg_inst, 15) node T_4605 = shl(T_4603, 0) node T_4606 = mux(T_4602, T_4605, UInt<1>("h00")) node T_4607 = shl(T_4601, 0) node T_4608 = mux(T_4600, T_4607, T_4606) node T_4609 = shl(T_4599, 0) node T_4610 = mux(T_4598, T_4609, T_4608) node T_4611 = asUInt(T_4556) node T_4612 = asUInt(T_4560) node T_4613 = asUInt(T_4566) node T_4614 = cat(T_4612, T_4613) node T_4615 = cat(T_4611, T_4614) node T_4616 = asUInt(T_4579) node T_4617 = cat(T_4616, T_4585) node T_4618 = cat(T_4597, T_4610) node T_4619 = cat(T_4617, T_4618) node T_4620 = cat(T_4615, T_4619) node T_4621 = asSInt(T_4620) node T_4623 = mux(mem_ctrl.jal, T_4621, asSInt(UInt<4>("h04"))) node T_4624 = mux(T_4481, T_4551, T_4623) node mem_br_target = addw(T_4480, T_4624) node T_4626 = asSInt(mem_reg_wdata) node T_4627 = mux(mem_ctrl.jalr, mem_br_target, T_4626) node mem_int_wdata = asUInt(T_4627) node T_4629 = shr(mem_reg_wdata, 38) node T_4630 = bits(mem_reg_wdata, 39, 38) node T_4632 = eq(T_4629, UInt<1>("h00")) node T_4634 = eq(T_4629, UInt<1>("h01")) node T_4635 = or(T_4632, T_4634) node T_4637 = neq(T_4630, UInt<1>("h00")) node T_4638 = asSInt(T_4629) node T_4640 = eq(T_4638, asSInt(UInt<1>("h01"))) node T_4641 = asSInt(T_4629) node T_4643 = eq(T_4641, asSInt(UInt<2>("h02"))) node T_4644 = or(T_4640, T_4643) node T_4645 = asSInt(T_4630) node T_4647 = eq(T_4645, asSInt(UInt<1>("h01"))) node T_4648 = bit(T_4630, 0) node T_4649 = mux(T_4644, T_4647, T_4648) node T_4650 = mux(T_4635, T_4637, T_4649) node T_4651 = bits(mem_reg_wdata, 38, 0) node T_4652 = cat(T_4650, T_4651) node T_4653 = asSInt(T_4652) node T_4654 = mux(mem_ctrl.jalr, T_4653, mem_br_target) node T_4656 = and(T_4654, asSInt(UInt<2>("h02"))) node mem_npc = asUInt(T_4656) node T_4658 = neq(mem_npc, ex_reg_pc) node T_4660 = eq(ex_reg_valid, UInt<1>("h00")) node mem_wrong_npc = or(T_4658, T_4660) node mem_npc_misaligned = bit(mem_npc, 1) node T_4663 = and(mem_wrong_npc, mem_reg_valid) node T_4664 = or(mem_ctrl.branch, mem_ctrl.jalr) node T_4665 = or(T_4664, mem_ctrl.jal) node mem_misprediction = and(T_4663, T_4665) node T_4667 = or(mem_misprediction, mem_reg_flush_pipe) node want_take_pc_mem = and(mem_reg_valid, T_4667) node T_4670 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_4671 = and(want_take_pc_mem, T_4670) take_pc_mem := T_4671 node T_4673 = eq(ctrl_killx, UInt<1>("h00")) mem_reg_valid := T_4673 node T_4675 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_4676 = and(T_4675, replay_ex) mem_reg_replay := T_4676 node T_4678 = eq(ctrl_killx, UInt<1>("h00")) node T_4679 = and(T_4678, ex_xcpt) mem_reg_xcpt := T_4679 node T_4681 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_4682 = and(T_4681, ex_reg_xcpt_interrupt) mem_reg_xcpt_interrupt := T_4682 when ex_xcpt : mem_reg_cause := ex_cause skip node T_4683 = or(ex_reg_valid, ex_reg_xcpt_interrupt) when T_4683 : mem_ctrl <> ex_ctrl mem_reg_btb_hit := ex_reg_btb_hit when ex_reg_btb_hit : mem_reg_btb_resp <> ex_reg_btb_resp skip mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_inst := ex_reg_inst mem_reg_pc := ex_reg_pc mem_reg_wdata := alu.io.out node T_4684 = or(ex_ctrl.mem, ex_ctrl.rocc) node T_4685 = and(ex_ctrl.rxs2, T_4684) when T_4685 : mem_reg_rs2 := T_4290 skip skip node T_4686 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) node T_4687 = and(want_take_pc_mem, mem_npc_misaligned) node T_4689 = and(mem_reg_valid, mem_ctrl.mem) node T_4690 = and(T_4689, io.dmem.xcpt.ma.st) node T_4692 = and(mem_reg_valid, mem_ctrl.mem) node T_4693 = and(T_4692, io.dmem.xcpt.ma.ld) node T_4695 = and(mem_reg_valid, mem_ctrl.mem) node T_4696 = and(T_4695, io.dmem.xcpt.pf.st) node T_4698 = and(mem_reg_valid, mem_ctrl.mem) node T_4699 = and(T_4698, io.dmem.xcpt.pf.ld) node T_4701 = or(T_4686, T_4687) node T_4702 = or(T_4701, T_4690) node T_4703 = or(T_4702, T_4693) node T_4704 = or(T_4703, T_4696) node mem_xcpt = or(T_4704, T_4699) node T_4706 = mux(T_4696, UInt<3>("h07"), UInt<3>("h05")) node T_4707 = mux(T_4693, UInt<3>("h04"), T_4706) node T_4708 = mux(T_4690, UInt<3>("h06"), T_4707) node T_4709 = mux(T_4687, UInt<1>("h00"), T_4708) node mem_cause = mux(T_4686, mem_reg_cause, T_4709) node T_4711 = and(mem_reg_valid, mem_ctrl.wxd) node dcache_kill_mem = and(T_4711, io.dmem.replay_next.valid) node T_4713 = and(mem_reg_valid, mem_ctrl.fp) node fpu_kill_mem = and(T_4713, io.fpu.nack_mem) node T_4715 = or(dcache_kill_mem, mem_reg_replay) node replay_mem = or(T_4715, fpu_kill_mem) node T_4717 = or(dcache_kill_mem, take_pc_wb) node T_4718 = or(T_4717, mem_reg_xcpt) node T_4720 = eq(mem_reg_valid, UInt<1>("h00")) node killm_common = or(T_4718, T_4720) node T_4722 = and(div.io.req.ready, div.io.req.valid) reg T_4723 : UInt<1>, clock, reset T_4723 := T_4722 node T_4724 = and(killm_common, T_4723) div.io.kill := T_4724 node T_4725 = or(killm_common, mem_xcpt) node ctrl_killm = or(T_4725, fpu_kill_mem) node T_4728 = eq(ctrl_killm, UInt<1>("h00")) wb_reg_valid := T_4728 node T_4730 = eq(take_pc_wb, UInt<1>("h00")) node T_4731 = and(replay_mem, T_4730) wb_reg_replay := T_4731 node T_4733 = eq(take_pc_wb, UInt<1>("h00")) node T_4734 = and(mem_xcpt, T_4733) wb_reg_xcpt := T_4734 when mem_xcpt : wb_reg_cause := mem_cause skip node T_4735 = or(mem_reg_valid, mem_reg_replay) node T_4736 = or(T_4735, mem_reg_xcpt_interrupt) when T_4736 : wb_ctrl <> mem_ctrl node T_4737 = and(mem_ctrl.fp, mem_ctrl.wxd) node T_4738 = mux(T_4737, io.fpu.toint_data, mem_int_wdata) wb_reg_wdata := T_4738 when mem_ctrl.rocc : wb_reg_rs2 := mem_reg_rs2 skip wb_reg_inst := mem_reg_inst wb_reg_pc := mem_reg_pc skip node T_4739 = or(wb_ctrl.div, wb_dcache_miss) node wb_set_sboard = or(T_4739, wb_ctrl.rocc) node T_4741 = or(io.dmem.resp.bits.nack, wb_reg_replay) node replay_wb_common = or(T_4741, csr.io.csr_replay) node T_4743 = and(wb_reg_valid, wb_ctrl.rocc) node T_4745 = eq(replay_wb_common, UInt<1>("h00")) node wb_rocc_val = and(T_4743, T_4745) node T_4747 = and(wb_reg_valid, wb_ctrl.rocc) node T_4749 = eq(io.rocc.cmd.ready, UInt<1>("h00")) node T_4750 = and(T_4747, T_4749) node replay_wb = or(replay_wb_common, T_4750) node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) node T_4753 = or(replay_wb, wb_xcpt) node T_4754 = or(T_4753, csr.io.eret) take_pc_wb := T_4754 when wb_rocc_val : node T_4756 = eq(io.rocc.cmd.ready, UInt<1>("h00")) wb_reg_rocc_pending := T_4756 skip when wb_reg_xcpt : wb_reg_rocc_pending := UInt<1>("h00") skip node T_4758 = bit(io.dmem.resp.bits.tag, 0) node T_4759 = bit(T_4758, 0) node dmem_resp_xpu = eq(T_4759, UInt<1>("h00")) node T_4762 = bit(io.dmem.resp.bits.tag, 0) node dmem_resp_fpu = bit(T_4762, 0) node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data) node T_4767 = and(wb_reg_valid, wb_ctrl.wxd) node T_4769 = eq(T_4767, UInt<1>("h00")) div.io.resp.ready := T_4769 wire ll_wdata : UInt ll_wdata := div.io.resp.bits.data wire ll_waddr : UInt ll_waddr := div.io.resp.bits.tag node T_4772 = and(div.io.resp.ready, div.io.resp.valid) wire ll_wen : UInt<1> ll_wen := T_4772 node T_4774 = and(dmem_resp_replay, dmem_resp_xpu) when T_4774 : div.io.resp.ready := UInt<1>("h00") ll_waddr := dmem_resp_waddr ll_wen := UInt<1>("h01") skip node T_4778 = eq(replay_wb, UInt<1>("h00")) node T_4779 = and(wb_reg_valid, T_4778) node T_4781 = eq(csr.io.csr_xcpt, UInt<1>("h00")) node wb_valid = and(T_4779, T_4781) node wb_wen = and(wb_valid, wb_ctrl.wxd) node rf_wen = or(wb_wen, ll_wen) node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) node T_4786 = and(dmem_resp_valid, dmem_resp_xpu) node T_4787 = neq(wb_ctrl.csr, UInt<3>("h00")) node T_4788 = mux(T_4787, csr.io.rw.rdata, wb_reg_wdata) node T_4789 = mux(ll_wen, ll_wdata, T_4788) node rf_wdata = mux(T_4786, io.dmem.resp.bits.data, T_4789) when rf_wen : node T_4792 = neq(rf_waddr, UInt<1>("h00")) when T_4792 : node T_4793 = not(rf_waddr) infer accessor T_4794 = T_3990[T_4793] T_4794 := rf_wdata node T_4795 = eq(rf_waddr, id_raddr1) when T_4795 : T_3992 := rf_wdata skip node T_4796 = eq(rf_waddr, id_raddr2) when T_4796 : T_3997 := rf_wdata skip skip skip csr.io.exception := wb_reg_xcpt csr.io.cause := wb_reg_cause csr.io.retire := wb_valid io.host <> csr.io.host io.fpu.fcsr_rm := csr.io.fcsr_rm csr.io.fcsr_flags <> io.fpu.fcsr_flags csr.io.rocc <> io.rocc csr.io.pc := wb_reg_pc csr.io.uarch_counters[0] := UInt<1>("h00") csr.io.uarch_counters[1] := UInt<1>("h00") csr.io.uarch_counters[2] := UInt<1>("h00") csr.io.uarch_counters[3] := UInt<1>("h00") csr.io.uarch_counters[4] := UInt<1>("h00") csr.io.uarch_counters[5] := UInt<1>("h00") csr.io.uarch_counters[6] := UInt<1>("h00") csr.io.uarch_counters[7] := UInt<1>("h00") csr.io.uarch_counters[8] := UInt<1>("h00") csr.io.uarch_counters[9] := UInt<1>("h00") csr.io.uarch_counters[10] := UInt<1>("h00") csr.io.uarch_counters[11] := UInt<1>("h00") csr.io.uarch_counters[12] := UInt<1>("h00") csr.io.uarch_counters[13] := UInt<1>("h00") csr.io.uarch_counters[14] := UInt<1>("h00") csr.io.uarch_counters[15] := UInt<1>("h00") io.ptw.ptbr := csr.io.ptbr io.ptw.invalidate := csr.io.fatc io.ptw.status <> csr.io.status node T_4813 = bits(wb_reg_inst, 31, 20) csr.io.rw.addr := T_4813 node T_4814 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) csr.io.rw.cmd := T_4814 csr.io.rw.wdata := wb_reg_wdata node T_4816 = neq(id_raddr1, UInt<1>("h00")) node T_4817 = and(id_ctrl.rxs1, T_4816) node T_4819 = neq(id_raddr2, UInt<1>("h00")) node T_4820 = and(id_ctrl.rxs2, T_4819) node T_4822 = neq(id_waddr, UInt<1>("h00")) node T_4823 = and(id_ctrl.wxd, T_4822) reg T_4825 : UInt<32>, clock, reset onreset T_4825 := UInt<32>("h00") node T_4828 = dshl(UInt<1>("h01"), ll_waddr) node T_4830 = mux(ll_wen, T_4828, UInt<1>("h00")) node T_4831 = not(T_4830) node T_4832 = and(T_4825, T_4831) node T_4833 = or(UInt<1>("h00"), ll_wen) when T_4833 : T_4825 := T_4832 skip node T_4834 = dshr(T_4832, id_raddr1) node T_4835 = bit(T_4834, 0) node T_4836 = and(T_4817, T_4835) node T_4837 = dshr(T_4832, id_raddr2) node T_4838 = bit(T_4837, 0) node T_4839 = and(T_4820, T_4838) node T_4840 = dshr(T_4832, id_waddr) node T_4841 = bit(T_4840, 0) node T_4842 = and(T_4823, T_4841) node T_4843 = or(T_4836, T_4839) node id_sboard_hazard = or(T_4843, T_4842) node T_4845 = and(wb_set_sboard, wb_wen) node T_4847 = dshl(UInt<1>("h01"), wb_waddr) node T_4849 = mux(T_4845, T_4847, UInt<1>("h00")) node T_4850 = or(T_4832, T_4849) node T_4851 = or(T_4833, T_4845) when T_4851 : T_4825 := T_4850 skip node T_4852 = neq(ex_ctrl.csr, UInt<3>("h00")) node T_4853 = or(T_4852, ex_ctrl.jalr) node T_4854 = or(T_4853, ex_ctrl.mem) node T_4855 = or(T_4854, ex_ctrl.div) node T_4856 = or(T_4855, ex_ctrl.fp) node ex_cannot_bypass = or(T_4856, ex_ctrl.rocc) node T_4858 = eq(id_raddr1, ex_waddr) node T_4859 = and(T_4817, T_4858) node T_4860 = eq(id_raddr2, ex_waddr) node T_4861 = and(T_4820, T_4860) node T_4862 = eq(id_waddr, ex_waddr) node T_4863 = and(T_4823, T_4862) node T_4864 = or(T_4859, T_4861) node T_4865 = or(T_4864, T_4863) node data_hazard_ex = and(ex_ctrl.wxd, T_4865) node T_4867 = eq(id_raddr1, ex_waddr) node T_4868 = and(io.fpu.dec.ren1, T_4867) node T_4869 = eq(id_raddr2, ex_waddr) node T_4870 = and(io.fpu.dec.ren2, T_4869) node T_4871 = eq(id_raddr3, ex_waddr) node T_4872 = and(io.fpu.dec.ren3, T_4871) node T_4873 = eq(id_waddr, ex_waddr) node T_4874 = and(io.fpu.dec.wen, T_4873) node T_4875 = or(T_4868, T_4870) node T_4876 = or(T_4875, T_4872) node T_4877 = or(T_4876, T_4874) node fp_data_hazard_ex = and(ex_ctrl.wfd, T_4877) node T_4879 = and(data_hazard_ex, ex_cannot_bypass) node T_4880 = or(T_4879, fp_data_hazard_ex) node id_ex_hazard = and(ex_reg_valid, T_4880) node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) node T_4884 = neq(mem_ctrl.csr, UInt<3>("h00")) node T_4885 = and(mem_ctrl.mem, mem_mem_cmd_bh) node T_4886 = or(T_4884, T_4885) node T_4887 = or(T_4886, mem_ctrl.div) node T_4888 = or(T_4887, mem_ctrl.fp) node mem_cannot_bypass = or(T_4888, mem_ctrl.rocc) node T_4890 = eq(id_raddr1, mem_waddr) node T_4891 = and(T_4817, T_4890) node T_4892 = eq(id_raddr2, mem_waddr) node T_4893 = and(T_4820, T_4892) node T_4894 = eq(id_waddr, mem_waddr) node T_4895 = and(T_4823, T_4894) node T_4896 = or(T_4891, T_4893) node T_4897 = or(T_4896, T_4895) node data_hazard_mem = and(mem_ctrl.wxd, T_4897) node T_4899 = eq(id_raddr1, mem_waddr) node T_4900 = and(io.fpu.dec.ren1, T_4899) node T_4901 = eq(id_raddr2, mem_waddr) node T_4902 = and(io.fpu.dec.ren2, T_4901) node T_4903 = eq(id_raddr3, mem_waddr) node T_4904 = and(io.fpu.dec.ren3, T_4903) node T_4905 = eq(id_waddr, mem_waddr) node T_4906 = and(io.fpu.dec.wen, T_4905) node T_4907 = or(T_4900, T_4902) node T_4908 = or(T_4907, T_4904) node T_4909 = or(T_4908, T_4906) node fp_data_hazard_mem = and(mem_ctrl.wfd, T_4909) node T_4911 = and(data_hazard_mem, mem_cannot_bypass) node T_4912 = or(T_4911, fp_data_hazard_mem) node id_mem_hazard = and(mem_reg_valid, T_4912) node T_4914 = and(mem_reg_valid, data_hazard_mem) node T_4915 = and(T_4914, mem_ctrl.mem) id_load_use := T_4915 node T_4916 = eq(id_raddr1, wb_waddr) node T_4917 = and(T_4817, T_4916) node T_4918 = eq(id_raddr2, wb_waddr) node T_4919 = and(T_4820, T_4918) node T_4920 = eq(id_waddr, wb_waddr) node T_4921 = and(T_4823, T_4920) node T_4922 = or(T_4917, T_4919) node T_4923 = or(T_4922, T_4921) node data_hazard_wb = and(wb_ctrl.wxd, T_4923) node T_4925 = eq(id_raddr1, wb_waddr) node T_4926 = and(io.fpu.dec.ren1, T_4925) node T_4927 = eq(id_raddr2, wb_waddr) node T_4928 = and(io.fpu.dec.ren2, T_4927) node T_4929 = eq(id_raddr3, wb_waddr) node T_4930 = and(io.fpu.dec.ren3, T_4929) node T_4931 = eq(id_waddr, wb_waddr) node T_4932 = and(io.fpu.dec.wen, T_4931) node T_4933 = or(T_4926, T_4928) node T_4934 = or(T_4933, T_4930) node T_4935 = or(T_4934, T_4932) node fp_data_hazard_wb = and(wb_ctrl.wfd, T_4935) node T_4937 = and(data_hazard_wb, wb_set_sboard) node T_4938 = or(T_4937, fp_data_hazard_wb) node id_wb_hazard = and(wb_reg_valid, T_4938) reg T_4941 : UInt<32>, clock, reset onreset T_4941 := UInt<32>("h00") node T_4943 = and(wb_dcache_miss, wb_ctrl.wfd) node T_4944 = or(T_4943, io.fpu.sboard_set) node T_4945 = and(T_4944, wb_valid) node T_4947 = dshl(UInt<1>("h01"), wb_waddr) node T_4949 = mux(T_4945, T_4947, UInt<1>("h00")) node T_4950 = or(T_4941, T_4949) node T_4951 = or(UInt<1>("h00"), T_4945) when T_4951 : T_4941 := T_4950 skip node T_4952 = and(dmem_resp_replay, dmem_resp_fpu) node T_4954 = dshl(UInt<1>("h01"), dmem_resp_waddr) node T_4956 = mux(T_4952, T_4954, UInt<1>("h00")) node T_4957 = not(T_4956) node T_4958 = and(T_4950, T_4957) node T_4959 = or(T_4951, T_4952) when T_4959 : T_4941 := T_4958 skip node T_4961 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) node T_4963 = mux(io.fpu.sboard_clr, T_4961, UInt<1>("h00")) node T_4964 = not(T_4963) node T_4965 = and(T_4958, T_4964) node T_4966 = or(T_4959, io.fpu.sboard_clr) when T_4966 : T_4941 := T_4965 skip node T_4968 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) node T_4969 = and(id_csr_en, T_4968) node T_4970 = dshr(T_4941, id_raddr1) node T_4971 = bit(T_4970, 0) node T_4972 = and(io.fpu.dec.ren1, T_4971) node T_4973 = dshr(T_4941, id_raddr2) node T_4974 = bit(T_4973, 0) node T_4975 = and(io.fpu.dec.ren2, T_4974) node T_4976 = dshr(T_4941, id_raddr3) node T_4977 = bit(T_4976, 0) node T_4978 = and(io.fpu.dec.ren3, T_4977) node T_4979 = dshr(T_4941, id_waddr) node T_4980 = bit(T_4979, 0) node T_4981 = and(io.fpu.dec.wen, T_4980) node T_4982 = or(T_4972, T_4975) node T_4983 = or(T_4982, T_4978) node T_4984 = or(T_4983, T_4981) node id_stall_fpu = or(T_4969, T_4984) node T_4986 = or(id_ex_hazard, id_mem_hazard) node T_4987 = or(T_4986, id_wb_hazard) node T_4988 = or(T_4987, id_sboard_hazard) node T_4989 = and(id_ctrl.fp, id_stall_fpu) node T_4990 = or(T_4988, T_4989) node T_4992 = eq(io.dmem.req.ready, UInt<1>("h00")) node T_4993 = and(id_ctrl.mem, T_4992) node T_4994 = or(T_4990, T_4993) node T_4996 = and(UInt<1>("h00"), wb_reg_rocc_pending) node T_4997 = and(T_4996, id_ctrl.rocc) node T_4999 = eq(io.rocc.cmd.ready, UInt<1>("h00")) node T_5000 = and(T_4997, T_4999) node T_5001 = or(T_4994, T_5000) node T_5002 = or(T_5001, id_do_fence) node ctrl_stalld = or(T_5002, csr.io.csr_stall) node T_5005 = eq(io.imem.resp.valid, UInt<1>("h00")) node T_5006 = or(T_5005, take_pc_mem_wb) node T_5007 = or(T_5006, ctrl_stalld) node T_5008 = or(T_5007, csr.io.interrupt) ctrl_killd := T_5008 io.imem.req.valid := take_pc_mem_wb node T_5009 = or(wb_xcpt, csr.io.eret) node T_5010 = mux(replay_wb, wb_reg_pc, mem_npc) node T_5011 = mux(T_5009, csr.io.evec, T_5010) io.imem.req.bits.pc := T_5011 node T_5012 = and(wb_reg_valid, wb_ctrl.fence_i) io.imem.invalidate := T_5012 node T_5014 = eq(ctrl_stalld, UInt<1>("h00")) node T_5015 = or(T_5014, csr.io.interrupt) io.imem.resp.ready := T_5015 node T_5017 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_5018 = and(mem_reg_valid, T_5017) node T_5019 = and(T_5018, mem_wrong_npc) node T_5020 = and(mem_ctrl.branch, mem_br_taken) node T_5021 = or(T_5020, mem_ctrl.jalr) node T_5022 = or(T_5021, mem_ctrl.jal) node T_5023 = and(T_5019, T_5022) node T_5025 = eq(take_pc_wb, UInt<1>("h00")) node T_5026 = and(T_5023, T_5025) io.imem.btb_update.valid := T_5026 node T_5027 = or(mem_ctrl.jal, mem_ctrl.jalr) io.imem.btb_update.bits.isJump := T_5027 node T_5028 = bits(mem_reg_inst, 19, 15) node T_5031 = and(T_5028, UInt<5>("h019")) node T_5032 = eq(UInt<1>("h01"), T_5031) node T_5033 = and(mem_ctrl.jalr, T_5032) io.imem.btb_update.bits.isReturn := T_5033 io.imem.btb_update.bits.pc := mem_reg_pc io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := mem_reg_pc io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit io.imem.btb_update.bits.prediction.bits <> mem_reg_btb_resp node T_5034 = and(mem_reg_valid, mem_ctrl.branch) node T_5036 = eq(take_pc_wb, UInt<1>("h00")) node T_5037 = and(T_5034, T_5036) io.imem.bht_update.valid := T_5037 io.imem.bht_update.bits.pc := mem_reg_pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.prediction <> io.imem.btb_update.bits.prediction node T_5038 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) node T_5040 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_5041 = and(T_5038, T_5040) node T_5043 = eq(take_pc_wb, UInt<1>("h00")) node T_5044 = and(T_5041, T_5043) io.imem.ras_update.valid := T_5044 io.imem.ras_update.bits.returnAddr := mem_int_wdata node T_5045 = bit(mem_waddr, 0) node T_5046 = and(mem_ctrl.wxd, T_5045) io.imem.ras_update.bits.isCall := T_5046 io.imem.ras_update.bits.isReturn := io.imem.btb_update.bits.isReturn io.imem.ras_update.bits.prediction <> io.imem.btb_update.bits.prediction node T_5048 = eq(ctrl_killd, UInt<1>("h00")) node T_5049 = and(T_5048, id_ctrl.fp) io.fpu.valid := T_5049 io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := io.imem.resp.bits.data[0] io.fpu.fromint_data := T_4287 node T_5050 = and(dmem_resp_valid, dmem_resp_fpu) io.fpu.dmem_resp_val := T_5050 io.fpu.dmem_resp_data := io.dmem.resp.bits.data_word_bypass io.fpu.dmem_resp_type := io.dmem.resp.bits.typ io.fpu.dmem_resp_tag := dmem_resp_waddr node T_5051 = and(ex_reg_valid, ex_ctrl.mem) io.dmem.req.valid := T_5051 node T_5052 = or(killm_common, mem_xcpt) io.dmem.req.bits.kill := T_5052 io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.typ := ex_ctrl.mem_type io.dmem.req.bits.phys := UInt<1>("h00") node T_5054 = shr(T_4287, 38) node T_5055 = bits(alu.io.adder_out, 39, 38) node T_5057 = eq(T_5054, UInt<1>("h00")) node T_5059 = eq(T_5054, UInt<1>("h01")) node T_5060 = or(T_5057, T_5059) node T_5062 = neq(T_5055, UInt<1>("h00")) node T_5063 = asSInt(T_5054) node T_5065 = eq(T_5063, asSInt(UInt<1>("h01"))) node T_5066 = asSInt(T_5054) node T_5068 = eq(T_5066, asSInt(UInt<2>("h02"))) node T_5069 = or(T_5065, T_5068) node T_5070 = asSInt(T_5055) node T_5072 = eq(T_5070, asSInt(UInt<1>("h01"))) node T_5073 = bit(T_5055, 0) node T_5074 = mux(T_5069, T_5072, T_5073) node T_5075 = mux(T_5060, T_5062, T_5074) node T_5076 = bits(alu.io.adder_out, 38, 0) node T_5077 = cat(T_5075, T_5076) io.dmem.req.bits.addr := T_5077 node T_5078 = cat(ex_waddr, ex_ctrl.fp) io.dmem.req.bits.tag := T_5078 node T_5079 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) io.dmem.req.bits.data := T_5079 io.dmem.invalidate_lr := wb_xcpt io.rocc.cmd.valid := wb_rocc_val node T_5081 = neq(csr.io.status.xs, UInt<1>("h00")) node T_5082 = and(wb_xcpt, T_5081) io.rocc.exception := T_5082 node T_5084 = neq(csr.io.status.prv, UInt<1>("h00")) io.rocc.s := T_5084 wire T_5103 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} T_5103.opcode := UInt<1>("h00") T_5103.rd := UInt<1>("h00") T_5103.xs2 := UInt<1>("h00") T_5103.xs1 := UInt<1>("h00") T_5103.xd := UInt<1>("h00") T_5103.rs1 := UInt<1>("h00") T_5103.rs2 := UInt<1>("h00") T_5103.funct := UInt<1>("h00") node T_5120 = bits(wb_reg_inst, 6, 0) T_5103.opcode := T_5120 node T_5121 = bits(wb_reg_inst, 11, 7) T_5103.rd := T_5121 node T_5122 = bits(wb_reg_inst, 12, 12) T_5103.xs2 := T_5122 node T_5123 = bits(wb_reg_inst, 13, 13) T_5103.xs1 := T_5123 node T_5124 = bits(wb_reg_inst, 14, 14) T_5103.xd := T_5124 node T_5125 = bits(wb_reg_inst, 19, 15) T_5103.rs1 := T_5125 node T_5126 = bits(wb_reg_inst, 24, 20) T_5103.rs2 := T_5126 node T_5127 = bits(wb_reg_inst, 31, 25) T_5103.funct := T_5127 io.rocc.cmd.bits.inst <> T_5103 io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 node T_5128 = bits(csr.io.time, 32, 0) node T_5130 = mux(rf_wen, rf_waddr, UInt<1>("h00")) node T_5131 = bits(wb_reg_inst, 19, 15) reg T_5132 : UInt, clock, reset T_5132 := T_4287 reg T_5133 : UInt, clock, reset T_5133 := T_5132 node T_5134 = bits(wb_reg_inst, 24, 20) reg T_5135 : UInt, clock, reset T_5135 := T_4290 reg T_5136 : UInt, clock, reset T_5136 := T_5135 module HellaCacheArbiter : input clock : Clock input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} io.mem.invalidate_lr := UInt<1>("h00") io.mem.req.bits.data := UInt<1>("h00") io.mem.req.bits.phys := UInt<1>("h00") io.mem.req.bits.kill := UInt<1>("h00") io.mem.req.bits.typ := UInt<1>("h00") io.mem.req.bits.cmd := UInt<1>("h00") io.mem.req.bits.tag := UInt<1>("h00") io.mem.req.bits.addr := UInt<1>("h00") io.mem.req.valid := UInt<1>("h00") io.requestor[0].ordered := UInt<1>("h00") io.requestor[0].xcpt.pf.st := UInt<1>("h00") io.requestor[0].xcpt.pf.ld := UInt<1>("h00") io.requestor[0].xcpt.ma.st := UInt<1>("h00") io.requestor[0].xcpt.ma.ld := UInt<1>("h00") io.requestor[0].replay_next.bits := UInt<1>("h00") io.requestor[0].replay_next.valid := UInt<1>("h00") io.requestor[0].resp.bits.store_data := UInt<1>("h00") io.requestor[0].resp.bits.data_word_bypass := UInt<1>("h00") io.requestor[0].resp.bits.has_data := UInt<1>("h00") io.requestor[0].resp.bits.replay := UInt<1>("h00") io.requestor[0].resp.bits.nack := UInt<1>("h00") io.requestor[0].resp.bits.data := UInt<1>("h00") io.requestor[0].resp.bits.typ := UInt<1>("h00") io.requestor[0].resp.bits.cmd := UInt<1>("h00") io.requestor[0].resp.bits.tag := UInt<1>("h00") io.requestor[0].resp.bits.addr := UInt<1>("h00") io.requestor[0].resp.valid := UInt<1>("h00") io.requestor[0].req.ready := UInt<1>("h00") io.requestor[1].ordered := UInt<1>("h00") io.requestor[1].xcpt.pf.st := UInt<1>("h00") io.requestor[1].xcpt.pf.ld := UInt<1>("h00") io.requestor[1].xcpt.ma.st := UInt<1>("h00") io.requestor[1].xcpt.ma.ld := UInt<1>("h00") io.requestor[1].replay_next.bits := UInt<1>("h00") io.requestor[1].replay_next.valid := UInt<1>("h00") io.requestor[1].resp.bits.store_data := UInt<1>("h00") io.requestor[1].resp.bits.data_word_bypass := UInt<1>("h00") io.requestor[1].resp.bits.has_data := UInt<1>("h00") io.requestor[1].resp.bits.replay := UInt<1>("h00") io.requestor[1].resp.bits.nack := UInt<1>("h00") io.requestor[1].resp.bits.data := UInt<1>("h00") io.requestor[1].resp.bits.typ := UInt<1>("h00") io.requestor[1].resp.bits.cmd := UInt<1>("h00") io.requestor[1].resp.bits.tag := UInt<1>("h00") io.requestor[1].resp.bits.addr := UInt<1>("h00") io.requestor[1].resp.valid := UInt<1>("h00") io.requestor[1].req.ready := UInt<1>("h00") reg T_1238 : UInt<1>, clock, reset T_1238 := io.requestor[0].req.valid reg T_1239 : UInt<1>, clock, reset T_1239 := io.requestor[1].req.valid node T_1240 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) io.mem.req.valid := T_1240 io.requestor[0].req.ready := io.mem.req.ready node T_1242 = eq(io.requestor[0].req.valid, UInt<1>("h00")) node T_1243 = and(io.requestor[0].req.ready, T_1242) io.requestor[1].req.ready := T_1243 io.mem.req.bits <> io.requestor[1].req.bits node T_1245 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01")) io.mem.req.bits.tag := T_1245 when io.requestor[0].req.valid : io.mem.req.bits.cmd := io.requestor[0].req.bits.cmd io.mem.req.bits.typ := io.requestor[0].req.bits.typ io.mem.req.bits.addr := io.requestor[0].req.bits.addr io.mem.req.bits.phys := io.requestor[0].req.bits.phys node T_1247 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00")) io.mem.req.bits.tag := T_1247 skip when T_1238 : io.mem.req.bits.kill := io.requestor[0].req.bits.kill io.mem.req.bits.data := io.requestor[0].req.bits.data skip node T_1248 = bits(io.mem.resp.bits.tag, 0, 0) node T_1250 = eq(T_1248, UInt<1>("h00")) node T_1251 = and(io.mem.resp.valid, T_1250) io.requestor[0].resp.valid := T_1251 io.requestor[0].xcpt <> io.mem.xcpt io.requestor[0].ordered := io.mem.ordered io.requestor[0].resp.bits <> io.mem.resp.bits node T_1252 = shr(io.mem.resp.bits.tag, 1) io.requestor[0].resp.bits.tag := T_1252 node T_1253 = and(io.mem.resp.bits.nack, T_1250) io.requestor[0].resp.bits.nack := T_1253 node T_1254 = and(io.mem.resp.bits.replay, T_1250) io.requestor[0].resp.bits.replay := T_1254 node T_1255 = bits(io.mem.replay_next.bits, 0, 0) node T_1257 = eq(T_1255, UInt<1>("h00")) node T_1258 = and(io.mem.replay_next.valid, T_1257) io.requestor[0].replay_next.valid := T_1258 node T_1259 = shr(io.mem.replay_next.bits, 1) io.requestor[0].replay_next.bits := T_1259 node T_1260 = bits(io.mem.resp.bits.tag, 0, 0) node T_1262 = eq(T_1260, UInt<1>("h01")) node T_1263 = and(io.mem.resp.valid, T_1262) io.requestor[1].resp.valid := T_1263 io.requestor[1].xcpt <> io.mem.xcpt io.requestor[1].ordered := io.mem.ordered io.requestor[1].resp.bits <> io.mem.resp.bits node T_1264 = shr(io.mem.resp.bits.tag, 1) io.requestor[1].resp.bits.tag := T_1264 node T_1265 = and(io.mem.resp.bits.nack, T_1262) io.requestor[1].resp.bits.nack := T_1265 node T_1266 = and(io.mem.resp.bits.replay, T_1262) io.requestor[1].resp.bits.replay := T_1266 node T_1267 = bits(io.mem.replay_next.bits, 0, 0) node T_1269 = eq(T_1267, UInt<1>("h01")) node T_1270 = and(io.mem.replay_next.valid, T_1269) io.requestor[1].replay_next.valid := T_1270 node T_1271 = shr(io.mem.replay_next.bits, 1) io.requestor[1].replay_next.bits := T_1271 module FPUDecoder : input clock : Clock input reset : UInt<1> output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} io.sigs.wflags := UInt<1>("h00") io.sigs.round := UInt<1>("h00") io.sigs.sqrt := UInt<1>("h00") io.sigs.div := UInt<1>("h00") io.sigs.fma := UInt<1>("h00") io.sigs.fastpipe := UInt<1>("h00") io.sigs.toint := UInt<1>("h00") io.sigs.fromint := UInt<1>("h00") io.sigs.single := UInt<1>("h00") io.sigs.swap23 := UInt<1>("h00") io.sigs.swap12 := UInt<1>("h00") io.sigs.ren3 := UInt<1>("h00") io.sigs.ren2 := UInt<1>("h00") io.sigs.ren1 := UInt<1>("h00") io.sigs.wen := UInt<1>("h00") io.sigs.ldst := UInt<1>("h00") io.sigs.cmd := UInt<1>("h00") node T_42 = and(io.inst, UInt<32>("h04")) node T_44 = eq(T_42, UInt<32>("h04")) node T_46 = and(io.inst, UInt<32>("h08000010")) node T_48 = eq(T_46, UInt<32>("h08000010")) node T_50 = or(UInt<1>("h00"), T_44) node T_51 = or(T_50, T_48) node T_53 = and(io.inst, UInt<32>("h08")) node T_55 = eq(T_53, UInt<32>("h08")) node T_57 = and(io.inst, UInt<32>("h010000010")) node T_59 = eq(T_57, UInt<32>("h010000010")) node T_61 = or(UInt<1>("h00"), T_55) node T_62 = or(T_61, T_59) node T_64 = and(io.inst, UInt<32>("h040")) node T_66 = eq(T_64, UInt<32>("h00")) node T_68 = and(io.inst, UInt<32>("h020000000")) node T_70 = eq(T_68, UInt<32>("h020000000")) node T_72 = or(UInt<1>("h00"), T_66) node T_73 = or(T_72, T_70) node T_75 = and(io.inst, UInt<32>("h040000000")) node T_77 = eq(T_75, UInt<32>("h040000000")) node T_79 = or(UInt<1>("h00"), T_66) node T_80 = or(T_79, T_77) node T_82 = and(io.inst, UInt<32>("h010")) node T_84 = eq(T_82, UInt<32>("h00")) node T_86 = or(UInt<1>("h00"), T_84) node T_87 = cat(T_62, T_51) node T_88 = cat(T_73, T_87) node T_89 = cat(T_80, T_88) node T_90 = cat(T_86, T_89) node T_92 = or(UInt<1>("h00"), T_66) node T_94 = and(io.inst, UInt<32>("h080000020")) node T_96 = eq(T_94, UInt<32>("h00")) node T_98 = and(io.inst, UInt<32>("h030")) node T_100 = eq(T_98, UInt<32>("h00")) node T_102 = and(io.inst, UInt<32>("h010000020")) node T_104 = eq(T_102, UInt<32>("h010000000")) node T_106 = or(UInt<1>("h00"), T_96) node T_107 = or(T_106, T_100) node T_108 = or(T_107, T_104) node T_110 = and(io.inst, UInt<32>("h080000004")) node T_112 = eq(T_110, UInt<32>("h00")) node T_114 = and(io.inst, UInt<32>("h010000004")) node T_116 = eq(T_114, UInt<32>("h00")) node T_118 = and(io.inst, UInt<32>("h050")) node T_120 = eq(T_118, UInt<32>("h040")) node T_122 = or(UInt<1>("h00"), T_112) node T_123 = or(T_122, T_116) node T_124 = or(T_123, T_120) node T_126 = and(io.inst, UInt<32>("h040000004")) node T_128 = eq(T_126, UInt<32>("h00")) node T_130 = and(io.inst, UInt<32>("h020")) node T_132 = eq(T_130, UInt<32>("h020")) node T_134 = or(UInt<1>("h00"), T_128) node T_135 = or(T_134, T_132) node T_136 = or(T_135, T_120) node T_138 = or(UInt<1>("h00"), T_120) node T_140 = and(io.inst, UInt<32>("h050000010")) node T_142 = eq(T_140, UInt<32>("h050000010")) node T_144 = or(UInt<1>("h00"), T_66) node T_145 = or(T_144, T_142) node T_147 = and(io.inst, UInt<32>("h030000010")) node T_149 = eq(T_147, UInt<32>("h010")) node T_151 = or(UInt<1>("h00"), T_149) node T_153 = and(io.inst, UInt<32>("h01040")) node T_155 = eq(T_153, UInt<32>("h00")) node T_157 = and(io.inst, UInt<32>("h02000040")) node T_159 = eq(T_157, UInt<32>("h040")) node T_161 = or(UInt<1>("h00"), T_155) node T_162 = or(T_161, T_159) node T_164 = and(io.inst, UInt<32>("h090000010")) node T_166 = eq(T_164, UInt<32>("h090000010")) node T_168 = or(UInt<1>("h00"), T_166) node T_170 = and(io.inst, UInt<32>("h090000010")) node T_172 = eq(T_170, UInt<32>("h080000010")) node T_174 = or(UInt<1>("h00"), T_132) node T_175 = or(T_174, T_172) node T_177 = and(io.inst, UInt<32>("h0a0000010")) node T_179 = eq(T_177, UInt<32>("h020000010")) node T_181 = and(io.inst, UInt<32>("h0d0000010")) node T_183 = eq(T_181, UInt<32>("h040000010")) node T_185 = or(UInt<1>("h00"), T_179) node T_186 = or(T_185, T_183) node T_188 = and(io.inst, UInt<32>("h070000004")) node T_190 = eq(T_188, UInt<32>("h00")) node T_192 = and(io.inst, UInt<32>("h068000004")) node T_194 = eq(T_192, UInt<32>("h00")) node T_196 = or(UInt<1>("h00"), T_190) node T_197 = or(T_196, T_194) node T_198 = or(T_197, T_120) node T_200 = and(io.inst, UInt<32>("h058000010")) node T_202 = eq(T_200, UInt<32>("h018000010")) node T_204 = or(UInt<1>("h00"), T_202) node T_206 = and(io.inst, UInt<32>("h0d0000010")) node T_208 = eq(T_206, UInt<32>("h050000010")) node T_210 = or(UInt<1>("h00"), T_208) node T_212 = and(io.inst, UInt<32>("h020000004")) node T_214 = eq(T_212, UInt<32>("h00")) node T_216 = and(io.inst, UInt<32>("h040002000")) node T_218 = eq(T_216, UInt<32>("h040000000")) node T_220 = or(UInt<1>("h00"), T_214) node T_221 = or(T_220, T_120) node T_222 = or(T_221, T_218) node T_224 = and(io.inst, UInt<32>("h08002000")) node T_226 = eq(T_224, UInt<32>("h08000000")) node T_228 = and(io.inst, UInt<32>("h0c0000004")) node T_230 = eq(T_228, UInt<32>("h080000000")) node T_232 = or(UInt<1>("h00"), T_214) node T_233 = or(T_232, T_120) node T_234 = or(T_233, T_226) node T_235 = or(T_234, T_230) io.sigs.cmd := T_90 io.sigs.ldst := T_92 io.sigs.wen := T_108 io.sigs.ren1 := T_124 io.sigs.ren2 := T_136 io.sigs.ren3 := T_138 io.sigs.swap12 := T_145 io.sigs.swap23 := T_151 io.sigs.single := T_162 io.sigs.fromint := T_168 io.sigs.toint := T_175 io.sigs.fastpipe := T_186 io.sigs.fma := T_198 io.sigs.div := T_204 io.sigs.sqrt := T_210 io.sigs.round := T_222 io.sigs.wflags := T_235 module mulAddSubRecodedFloatN : input clock : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags := UInt<1>("h00") io.out := UInt<1>("h00") node signA = bit(io.a, 32) node expA = bits(io.a, 31, 23) node fractA = bits(io.a, 22, 0) node T_15 = bits(expA, 8, 6) node isZeroA = eq(T_15, UInt<1>("h00")) node T_18 = bits(expA, 8, 7) node isSpecialA = eq(T_18, UInt<2>("h03")) node T_21 = bit(expA, 6) node T_23 = eq(T_21, UInt<1>("h00")) node isInfA = and(isSpecialA, T_23) node T_25 = bit(expA, 6) node isNaNA = and(isSpecialA, T_25) node T_27 = bit(fractA, 22) node T_29 = eq(T_27, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_29) node T_32 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_32, fractA) node signB = bit(io.b, 32) node expB = bits(io.b, 31, 23) node fractB = bits(io.b, 22, 0) node T_37 = bits(expB, 8, 6) node isZeroB = eq(T_37, UInt<1>("h00")) node T_40 = bits(expB, 8, 7) node isSpecialB = eq(T_40, UInt<2>("h03")) node T_43 = bit(expB, 6) node T_45 = eq(T_43, UInt<1>("h00")) node isInfB = and(isSpecialB, T_45) node T_47 = bit(expB, 6) node isNaNB = and(isSpecialB, T_47) node T_49 = bit(fractB, 22) node T_51 = eq(T_49, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_51) node T_54 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_54, fractB) node T_56 = bit(io.c, 32) node T_57 = bit(io.op, 0) node opSignC = xor(T_56, T_57) node expC = bits(io.c, 31, 23) node fractC = bits(io.c, 22, 0) node T_61 = bits(expC, 8, 6) node isZeroC = eq(T_61, UInt<1>("h00")) node T_64 = bits(expC, 8, 7) node isSpecialC = eq(T_64, UInt<2>("h03")) node T_67 = bit(expC, 6) node T_69 = eq(T_67, UInt<1>("h00")) node isInfC = and(isSpecialC, T_69) node T_71 = bit(expC, 6) node isNaNC = and(isSpecialC, T_71) node T_73 = bit(fractC, 22) node T_75 = eq(T_73, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_75) node T_78 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_78, fractC) node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) node T_92 = xor(signA, signB) node T_93 = bit(io.op, 1) node signProd = xor(T_92, T_93) node isZeroProd = or(isZeroA, isZeroB) node T_96 = bit(expB, 8) node T_98 = eq(T_96, UInt<1>("h00")) node T_100 = subw(UInt<3>("h00"), T_98) node T_101 = bits(expB, 7, 0) node T_102 = cat(T_100, T_101) node T_103 = addw(T_102, expA) node sExpAlignedProd = addw(T_103, UInt<5>("h01b")) node doSubMags = xor(signProd, opSignC) node sNatCAlignDist = subw(sExpAlignedProd, expC) node T_108 = bit(sNatCAlignDist, 10) node CAlignDist_floor = or(isZeroProd, T_108) node T_110 = bits(sNatCAlignDist, 9, 0) node T_112 = eq(T_110, UInt<1>("h00")) node CAlignDist_0 = or(CAlignDist_floor, T_112) node T_115 = eq(isZeroC, UInt<1>("h00")) node T_116 = bits(sNatCAlignDist, 9, 0) node T_118 = lt(T_116, UInt<5>("h019")) node T_119 = or(CAlignDist_floor, T_118) node isCDominant = and(T_115, T_119) node T_122 = bits(sNatCAlignDist, 9, 0) node T_124 = lt(T_122, UInt<7>("h04a")) node T_126 = mux(T_124, sNatCAlignDist, UInt<7>("h04a")) node T_127 = mux(CAlignDist_floor, UInt<1>("h00"), T_126) node CAlignDist = bits(T_127, 6, 0) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) node T_131 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) node T_132 = bits(T_131, 77, 54) node T_133 = bits(T_132, 15, 0) node T_136 = shl(UInt<8>("h0ff"), 8) node T_137 = xor(UInt<16>("h0ffff"), T_136) node T_138 = shr(T_133, 8) node T_139 = and(T_138, T_137) node T_140 = bits(T_133, 7, 0) node T_141 = shl(T_140, 8) node T_142 = not(T_137) node T_143 = and(T_141, T_142) node T_144 = or(T_139, T_143) node T_145 = bits(T_137, 11, 0) node T_146 = shl(T_145, 4) node T_147 = xor(T_137, T_146) node T_148 = shr(T_144, 4) node T_149 = and(T_148, T_147) node T_150 = bits(T_144, 11, 0) node T_151 = shl(T_150, 4) node T_152 = not(T_147) node T_153 = and(T_151, T_152) node T_154 = or(T_149, T_153) node T_155 = bits(T_147, 13, 0) node T_156 = shl(T_155, 2) node T_157 = xor(T_147, T_156) node T_158 = shr(T_154, 2) node T_159 = and(T_158, T_157) node T_160 = bits(T_154, 13, 0) node T_161 = shl(T_160, 2) node T_162 = not(T_157) node T_163 = and(T_161, T_162) node T_164 = or(T_159, T_163) node T_165 = bits(T_157, 14, 0) node T_166 = shl(T_165, 1) node T_167 = xor(T_157, T_166) node T_168 = shr(T_164, 1) node T_169 = and(T_168, T_167) node T_170 = bits(T_164, 14, 0) node T_171 = shl(T_170, 1) node T_172 = not(T_167) node T_173 = and(T_171, T_172) node T_174 = or(T_169, T_173) node T_175 = bits(T_132, 23, 16) node T_178 = shl(UInt<4>("h0f"), 4) node T_179 = xor(UInt<8>("h0ff"), T_178) node T_180 = shr(T_175, 4) node T_181 = and(T_180, T_179) node T_182 = bits(T_175, 3, 0) node T_183 = shl(T_182, 4) node T_184 = not(T_179) node T_185 = and(T_183, T_184) node T_186 = or(T_181, T_185) node T_187 = bits(T_179, 5, 0) node T_188 = shl(T_187, 2) node T_189 = xor(T_179, T_188) node T_190 = shr(T_186, 2) node T_191 = and(T_190, T_189) node T_192 = bits(T_186, 5, 0) node T_193 = shl(T_192, 2) node T_194 = not(T_189) node T_195 = and(T_193, T_194) node T_196 = or(T_191, T_195) node T_197 = bits(T_189, 6, 0) node T_198 = shl(T_197, 1) node T_199 = xor(T_189, T_198) node T_200 = shr(T_196, 1) node T_201 = and(T_200, T_199) node T_202 = bits(T_196, 6, 0) node T_203 = shl(T_202, 1) node T_204 = not(T_199) node T_205 = and(T_203, T_204) node T_206 = or(T_201, T_205) node CExtraMask = cat(T_174, T_206) node T_208 = not(sigC) node negSigC = mux(doSubMags, T_208, sigC) node T_211 = subw(UInt<50>("h00"), doSubMags) node T_212 = cat(negSigC, T_211) node T_213 = cat(doSubMags, T_212) node T_214 = asSInt(T_213) node T_215 = dshr(T_214, CAlignDist) node T_216 = and(sigC, CExtraMask) node T_218 = neq(T_216, UInt<1>("h00")) node T_219 = xor(T_218, doSubMags) node T_220 = asUInt(T_215) node T_221 = cat(T_220, T_219) node alignedNegSigC = bits(T_221, 74, 0) node T_223 = mul(sigA, sigB) node T_224 = shl(T_223, 1) node sigSum = addw(T_224, alignedNegSigC) node T_227 = bits(sigSum, 50, 1) node T_228 = xor(UInt<50>("h00"), T_227) node T_229 = or(UInt<50>("h00"), T_227) node T_230 = shl(T_229, 1) node T_231 = xor(T_228, T_230) node T_232 = bit(T_231, 49) node T_234 = bit(T_231, 48) node T_236 = bit(T_231, 47) node T_238 = bit(T_231, 46) node T_240 = bit(T_231, 45) node T_242 = bit(T_231, 44) node T_244 = bit(T_231, 43) node T_246 = bit(T_231, 42) node T_248 = bit(T_231, 41) node T_250 = bit(T_231, 40) node T_252 = bit(T_231, 39) node T_254 = bit(T_231, 38) node T_256 = bit(T_231, 37) node T_258 = bit(T_231, 36) node T_260 = bit(T_231, 35) node T_262 = bit(T_231, 34) node T_264 = bit(T_231, 33) node T_266 = bit(T_231, 32) node T_268 = bit(T_231, 31) node T_270 = bit(T_231, 30) node T_272 = bit(T_231, 29) node T_274 = bit(T_231, 28) node T_276 = bit(T_231, 27) node T_278 = bit(T_231, 26) node T_280 = bit(T_231, 25) node T_282 = bit(T_231, 24) node T_284 = bit(T_231, 23) node T_286 = bit(T_231, 22) node T_288 = bit(T_231, 21) node T_290 = bit(T_231, 20) node T_292 = bit(T_231, 19) node T_294 = bit(T_231, 18) node T_296 = bit(T_231, 17) node T_298 = bit(T_231, 16) node T_300 = bit(T_231, 15) node T_302 = bit(T_231, 14) node T_304 = bit(T_231, 13) node T_306 = bit(T_231, 12) node T_308 = bit(T_231, 11) node T_310 = bit(T_231, 10) node T_312 = bit(T_231, 9) node T_314 = bit(T_231, 8) node T_316 = bit(T_231, 7) node T_318 = bit(T_231, 6) node T_320 = bit(T_231, 5) node T_322 = bit(T_231, 4) node T_324 = bit(T_231, 3) node T_326 = bit(T_231, 2) node T_328 = bit(T_231, 1) node T_330 = bit(T_231, 0) node T_332 = mux(T_328, UInt<7>("h048"), UInt<7>("h049")) node T_333 = mux(T_326, UInt<7>("h047"), T_332) node T_334 = mux(T_324, UInt<7>("h046"), T_333) node T_335 = mux(T_322, UInt<7>("h045"), T_334) node T_336 = mux(T_320, UInt<7>("h044"), T_335) node T_337 = mux(T_318, UInt<7>("h043"), T_336) node T_338 = mux(T_316, UInt<7>("h042"), T_337) node T_339 = mux(T_314, UInt<7>("h041"), T_338) node T_340 = mux(T_312, UInt<7>("h040"), T_339) node T_341 = mux(T_310, UInt<7>("h03f"), T_340) node T_342 = mux(T_308, UInt<7>("h03e"), T_341) node T_343 = mux(T_306, UInt<7>("h03d"), T_342) node T_344 = mux(T_304, UInt<7>("h03c"), T_343) node T_345 = mux(T_302, UInt<7>("h03b"), T_344) node T_346 = mux(T_300, UInt<7>("h03a"), T_345) node T_347 = mux(T_298, UInt<7>("h039"), T_346) node T_348 = mux(T_296, UInt<7>("h038"), T_347) node T_349 = mux(T_294, UInt<7>("h037"), T_348) node T_350 = mux(T_292, UInt<7>("h036"), T_349) node T_351 = mux(T_290, UInt<7>("h035"), T_350) node T_352 = mux(T_288, UInt<7>("h034"), T_351) node T_353 = mux(T_286, UInt<7>("h033"), T_352) node T_354 = mux(T_284, UInt<7>("h032"), T_353) node T_355 = mux(T_282, UInt<7>("h031"), T_354) node T_356 = mux(T_280, UInt<7>("h030"), T_355) node T_357 = mux(T_278, UInt<7>("h02f"), T_356) node T_358 = mux(T_276, UInt<7>("h02e"), T_357) node T_359 = mux(T_274, UInt<7>("h02d"), T_358) node T_360 = mux(T_272, UInt<7>("h02c"), T_359) node T_361 = mux(T_270, UInt<7>("h02b"), T_360) node T_362 = mux(T_268, UInt<7>("h02a"), T_361) node T_363 = mux(T_266, UInt<7>("h029"), T_362) node T_364 = mux(T_264, UInt<7>("h028"), T_363) node T_365 = mux(T_262, UInt<7>("h027"), T_364) node T_366 = mux(T_260, UInt<7>("h026"), T_365) node T_367 = mux(T_258, UInt<7>("h025"), T_366) node T_368 = mux(T_256, UInt<7>("h024"), T_367) node T_369 = mux(T_254, UInt<7>("h023"), T_368) node T_370 = mux(T_252, UInt<7>("h022"), T_369) node T_371 = mux(T_250, UInt<7>("h021"), T_370) node T_372 = mux(T_248, UInt<7>("h020"), T_371) node T_373 = mux(T_246, UInt<7>("h01f"), T_372) node T_374 = mux(T_244, UInt<7>("h01e"), T_373) node T_375 = mux(T_242, UInt<7>("h01d"), T_374) node T_376 = mux(T_240, UInt<7>("h01c"), T_375) node T_377 = mux(T_238, UInt<7>("h01b"), T_376) node T_378 = mux(T_236, UInt<7>("h01a"), T_377) node T_379 = mux(T_234, UInt<7>("h019"), T_378) node estNormPos_dist = mux(T_232, UInt<7>("h018"), T_379) node T_381 = bits(sigSum, 33, 18) node T_383 = neq(T_381, UInt<1>("h00")) node T_384 = bits(sigSum, 17, 0) node T_386 = neq(T_384, UInt<1>("h00")) node firstReduceSigSum = cat(T_383, T_386) node notSigSum = not(sigSum) node T_389 = bits(notSigSum, 33, 18) node T_391 = neq(T_389, UInt<1>("h00")) node T_392 = bits(notSigSum, 17, 0) node T_394 = neq(T_392, UInt<1>("h00")) node firstReduceNotSigSum = cat(T_391, T_394) node T_396 = or(CAlignDist_0, doSubMags) node T_398 = subw(CAlignDist, UInt<1>("h01")) node T_399 = bits(T_398, 4, 0) node CDom_estNormDist = mux(T_396, CAlignDist, T_399) node T_401 = not(doSubMags) node T_402 = bit(CDom_estNormDist, 4) node T_403 = not(T_402) node T_404 = and(T_401, T_403) node T_405 = asSInt(T_404) node T_406 = bits(sigSum, 74, 34) node T_408 = neq(firstReduceSigSum, UInt<1>("h00")) node T_409 = cat(T_406, T_408) node T_410 = asSInt(T_409) node T_411 = and(T_405, T_410) node T_412 = not(doSubMags) node T_413 = bit(CDom_estNormDist, 4) node T_414 = and(T_412, T_413) node T_415 = asSInt(T_414) node T_416 = bits(sigSum, 58, 18) node T_417 = bit(firstReduceSigSum, 0) node T_418 = cat(T_416, T_417) node T_419 = asSInt(T_418) node T_420 = and(T_415, T_419) node T_421 = or(T_411, T_420) node T_422 = bit(CDom_estNormDist, 4) node T_423 = not(T_422) node T_424 = and(doSubMags, T_423) node T_425 = asSInt(T_424) node T_426 = bits(notSigSum, 74, 34) node T_428 = neq(firstReduceNotSigSum, UInt<1>("h00")) node T_429 = cat(T_426, T_428) node T_430 = asSInt(T_429) node T_431 = and(T_425, T_430) node T_432 = or(T_421, T_431) node T_433 = bit(CDom_estNormDist, 4) node T_434 = and(doSubMags, T_433) node T_435 = asSInt(T_434) node T_436 = bits(notSigSum, 58, 18) node T_437 = bit(firstReduceNotSigSum, 0) node T_438 = cat(T_436, T_437) node T_439 = asSInt(T_438) node T_440 = and(T_435, T_439) node T_441 = or(T_432, T_440) node CDom_firstNormAbsSigSum = asUInt(T_441) node T_443 = bits(sigSum, 50, 18) node T_444 = bit(firstReduceNotSigSum, 0) node T_445 = not(T_444) node T_446 = bit(firstReduceSigSum, 0) node T_447 = mux(doSubMags, T_445, T_446) node T_448 = cat(T_443, T_447) node T_449 = bits(sigSum, 42, 1) node T_450 = bit(estNormPos_dist, 5) node T_451 = bit(estNormPos_dist, 4) node T_452 = bits(sigSum, 26, 1) node T_454 = subw(UInt<16>("h00"), doSubMags) node T_455 = cat(T_452, T_454) node T_456 = mux(T_451, T_455, T_449) node T_457 = bit(estNormPos_dist, 4) node T_458 = bits(sigSum, 10, 1) node T_460 = subw(UInt<32>("h00"), doSubMags) node T_461 = cat(T_458, T_460) node T_462 = mux(T_457, T_448, T_461) node notCDom_pos_firstNormAbsSigSum = mux(T_450, T_456, T_462) node T_464 = bits(notSigSum, 49, 18) node T_465 = bit(firstReduceNotSigSum, 0) node T_466 = cat(T_464, T_465) node T_467 = bits(notSigSum, 42, 1) node T_468 = bit(estNormPos_dist, 5) node T_469 = bit(estNormPos_dist, 4) node T_470 = bits(notSigSum, 27, 1) node T_471 = shl(T_470, 16) node T_472 = mux(T_469, T_471, T_467) node T_473 = bit(estNormPos_dist, 4) node T_474 = bits(notSigSum, 11, 1) node T_475 = shl(T_474, 32) node T_476 = mux(T_473, T_466, T_475) node notCDom_neg_cFirstNormAbsSigSum = mux(T_468, T_472, T_476) node notCDom_signSigSum = bit(sigSum, 51) node T_479 = not(isZeroC) node T_480 = and(doSubMags, T_479) node doNegSignSum = mux(isCDominant, T_480, notCDom_signSigSum) node T_482 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) node estNormDist = mux(isCDominant, CDom_estNormDist, T_482) node T_484 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) node T_485 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_484, T_485) node T_487 = not(isCDominant) node T_488 = not(notCDom_signSigSum) node T_489 = and(T_487, T_488) node doIncrSig = and(T_489, doSubMags) node estNormDist_5 = bits(estNormDist, 3, 0) node normTo2ShiftDist = not(estNormDist_5) node T_494 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) node T_495 = bits(T_494, 15, 1) node T_496 = bits(T_495, 7, 0) node T_499 = shl(UInt<4>("h0f"), 4) node T_500 = xor(UInt<8>("h0ff"), T_499) node T_501 = shr(T_496, 4) node T_502 = and(T_501, T_500) node T_503 = bits(T_496, 3, 0) node T_504 = shl(T_503, 4) node T_505 = not(T_500) node T_506 = and(T_504, T_505) node T_507 = or(T_502, T_506) node T_508 = bits(T_500, 5, 0) node T_509 = shl(T_508, 2) node T_510 = xor(T_500, T_509) node T_511 = shr(T_507, 2) node T_512 = and(T_511, T_510) node T_513 = bits(T_507, 5, 0) node T_514 = shl(T_513, 2) node T_515 = not(T_510) node T_516 = and(T_514, T_515) node T_517 = or(T_512, T_516) node T_518 = bits(T_510, 6, 0) node T_519 = shl(T_518, 1) node T_520 = xor(T_510, T_519) node T_521 = shr(T_517, 1) node T_522 = and(T_521, T_520) node T_523 = bits(T_517, 6, 0) node T_524 = shl(T_523, 1) node T_525 = not(T_520) node T_526 = and(T_524, T_525) node T_527 = or(T_522, T_526) node T_528 = bits(T_495, 14, 8) node T_529 = bits(T_528, 3, 0) node T_530 = bits(T_529, 1, 0) node T_531 = bits(T_530, 0, 0) node T_532 = bits(T_530, 1, 1) node T_533 = cat(T_531, T_532) node T_534 = bits(T_529, 3, 2) node T_535 = bits(T_534, 0, 0) node T_536 = bits(T_534, 1, 1) node T_537 = cat(T_535, T_536) node T_538 = cat(T_533, T_537) node T_539 = bits(T_528, 6, 4) node T_540 = bits(T_539, 1, 0) node T_541 = bits(T_540, 0, 0) node T_542 = bits(T_540, 1, 1) node T_543 = cat(T_541, T_542) node T_544 = bits(T_539, 2, 2) node T_545 = cat(T_543, T_544) node T_546 = cat(T_538, T_545) node T_547 = cat(T_527, T_546) node absSigSumExtraMask = cat(T_547, UInt<1>("h01")) node T_550 = bits(cFirstNormAbsSigSum, 42, 1) node T_551 = dshr(T_550, normTo2ShiftDist) node T_552 = bits(cFirstNormAbsSigSum, 15, 0) node T_553 = not(T_552) node T_554 = and(T_553, absSigSumExtraMask) node T_556 = eq(T_554, UInt<1>("h00")) node T_557 = bits(cFirstNormAbsSigSum, 15, 0) node T_558 = and(T_557, absSigSumExtraMask) node T_560 = neq(T_558, UInt<1>("h00")) node T_561 = mux(doIncrSig, T_556, T_560) node T_562 = cat(T_551, T_561) node sigX3 = bits(T_562, 27, 0) node T_564 = bits(sigX3, 27, 26) node sigX3Shift1 = eq(T_564, UInt<1>("h00")) node sExpX3 = subw(sExpSum, estNormDist) node T_568 = bits(sigX3, 27, 25) node isZeroY = eq(T_568, UInt<1>("h00")) node T_571 = not(isZeroY) node T_572 = xor(signProd, doNegSignSum) node signY = and(T_571, T_572) node sExpX3_13 = bits(sExpX3, 9, 0) node T_575 = bit(sExpX3, 10) node T_577 = subw(UInt<27>("h00"), T_575) node T_578 = not(sExpX3_13) node T_580 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_578) node T_581 = bits(T_580, 131, 107) node T_582 = bits(T_581, 15, 0) node T_585 = shl(UInt<8>("h0ff"), 8) node T_586 = xor(UInt<16>("h0ffff"), T_585) node T_587 = shr(T_582, 8) node T_588 = and(T_587, T_586) node T_589 = bits(T_582, 7, 0) node T_590 = shl(T_589, 8) node T_591 = not(T_586) node T_592 = and(T_590, T_591) node T_593 = or(T_588, T_592) node T_594 = bits(T_586, 11, 0) node T_595 = shl(T_594, 4) node T_596 = xor(T_586, T_595) node T_597 = shr(T_593, 4) node T_598 = and(T_597, T_596) node T_599 = bits(T_593, 11, 0) node T_600 = shl(T_599, 4) node T_601 = not(T_596) node T_602 = and(T_600, T_601) node T_603 = or(T_598, T_602) node T_604 = bits(T_596, 13, 0) node T_605 = shl(T_604, 2) node T_606 = xor(T_596, T_605) node T_607 = shr(T_603, 2) node T_608 = and(T_607, T_606) node T_609 = bits(T_603, 13, 0) node T_610 = shl(T_609, 2) node T_611 = not(T_606) node T_612 = and(T_610, T_611) node T_613 = or(T_608, T_612) node T_614 = bits(T_606, 14, 0) node T_615 = shl(T_614, 1) node T_616 = xor(T_606, T_615) node T_617 = shr(T_613, 1) node T_618 = and(T_617, T_616) node T_619 = bits(T_613, 14, 0) node T_620 = shl(T_619, 1) node T_621 = not(T_616) node T_622 = and(T_620, T_621) node T_623 = or(T_618, T_622) node T_624 = bits(T_581, 24, 16) node T_625 = bits(T_624, 7, 0) node T_628 = shl(UInt<4>("h0f"), 4) node T_629 = xor(UInt<8>("h0ff"), T_628) node T_630 = shr(T_625, 4) node T_631 = and(T_630, T_629) node T_632 = bits(T_625, 3, 0) node T_633 = shl(T_632, 4) node T_634 = not(T_629) node T_635 = and(T_633, T_634) node T_636 = or(T_631, T_635) node T_637 = bits(T_629, 5, 0) node T_638 = shl(T_637, 2) node T_639 = xor(T_629, T_638) node T_640 = shr(T_636, 2) node T_641 = and(T_640, T_639) node T_642 = bits(T_636, 5, 0) node T_643 = shl(T_642, 2) node T_644 = not(T_639) node T_645 = and(T_643, T_644) node T_646 = or(T_641, T_645) node T_647 = bits(T_639, 6, 0) node T_648 = shl(T_647, 1) node T_649 = xor(T_639, T_648) node T_650 = shr(T_646, 1) node T_651 = and(T_650, T_649) node T_652 = bits(T_646, 6, 0) node T_653 = shl(T_652, 1) node T_654 = not(T_649) node T_655 = and(T_653, T_654) node T_656 = or(T_651, T_655) node T_657 = bits(T_624, 8, 8) node T_658 = cat(T_656, T_657) node T_659 = cat(T_623, T_658) node T_660 = bit(sigX3, 26) node T_661 = or(T_659, T_660) node T_663 = cat(T_661, UInt<2>("h03")) node roundMask = or(T_577, T_663) node T_665 = shr(roundMask, 1) node T_666 = not(T_665) node roundPosMask = and(T_666, roundMask) node T_668 = and(sigX3, roundPosMask) node roundPosBit = neq(T_668, UInt<1>("h00")) node T_671 = shr(roundMask, 1) node T_672 = and(sigX3, T_671) node anyRoundExtra = neq(T_672, UInt<1>("h00")) node T_675 = not(sigX3) node T_676 = shr(roundMask, 1) node T_677 = and(T_675, T_676) node allRoundExtra = eq(T_677, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) node T_683 = not(doIncrSig) node T_684 = and(T_683, roundingMode_nearest_even) node T_685 = and(T_684, roundPosBit) node T_686 = and(T_685, anyRoundExtra) node T_687 = not(doIncrSig) node T_688 = and(T_687, roundDirectUp) node T_689 = and(T_688, anyRound) node T_690 = or(T_686, T_689) node T_691 = and(doIncrSig, allRound) node T_692 = or(T_690, T_691) node T_693 = and(doIncrSig, roundingMode_nearest_even) node T_694 = and(T_693, roundPosBit) node T_695 = or(T_692, T_694) node T_696 = and(doIncrSig, roundDirectUp) node roundUp = or(T_695, T_696) node T_698 = not(roundPosBit) node T_699 = and(roundingMode_nearest_even, T_698) node T_700 = and(T_699, allRoundExtra) node T_701 = and(roundingMode_nearest_even, roundPosBit) node T_702 = not(anyRoundExtra) node T_703 = and(T_701, T_702) node roundEven = mux(doIncrSig, T_700, T_703) node T_705 = not(allRound) node roundInexact = mux(doIncrSig, T_705, anyRound) node T_707 = or(sigX3, roundMask) node T_708 = shr(T_707, 2) node T_710 = addw(T_708, UInt<1>("h01")) node roundUp_sigY3 = bits(T_710, 25, 0) node T_712 = not(roundUp) node T_713 = not(roundEven) node T_714 = and(T_712, T_713) node T_715 = not(roundMask) node T_716 = and(sigX3, T_715) node T_717 = shr(T_716, 2) node T_719 = mux(T_714, T_717, UInt<1>("h00")) node T_721 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) node T_722 = or(T_719, T_721) node T_723 = shr(roundMask, 1) node T_724 = not(T_723) node T_725 = and(roundUp_sigY3, T_724) node T_727 = mux(roundEven, T_725, UInt<1>("h00")) node sigY3 = or(T_722, T_727) node T_729 = bit(sigY3, 25) node T_731 = addw(sExpX3, UInt<1>("h01")) node T_733 = mux(T_729, T_731, UInt<1>("h00")) node T_734 = bit(sigY3, 24) node T_736 = mux(T_734, sExpX3, UInt<1>("h00")) node T_737 = or(T_733, T_736) node T_738 = bits(sigY3, 25, 24) node T_740 = eq(T_738, UInt<1>("h00")) node T_742 = subw(sExpX3, UInt<1>("h01")) node T_744 = mux(T_740, T_742, UInt<1>("h00")) node sExpY = or(T_737, T_744) node expY = bits(sExpY, 8, 0) node T_747 = bits(sigY3, 22, 0) node T_748 = bits(sigY3, 23, 1) node fractY = mux(sigX3Shift1, T_747, T_748) node T_750 = bits(sExpY, 9, 7) node overflowY = eq(T_750, UInt<2>("h03")) node T_753 = bit(sExpY, 9) node T_754 = bits(sExpY, 8, 0) node T_756 = lt(T_754, UInt<7>("h06b")) node totalUnderflowY = or(T_753, T_756) node T_758 = bit(sExpX3, 10) node T_761 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) node T_762 = leq(sExpX3_13, T_761) node T_763 = or(T_758, T_762) node underflowY = and(roundInexact, T_763) node T_765 = and(roundingMode_min, signY) node T_766 = or(roundingMode_nearest_even, T_765) node T_767 = not(signY) node T_768 = and(roundingMode_max, T_767) node overflowY_roundMagUp = or(T_766, T_768) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(isZeroProd, isZeroC) node T_773 = not(addSpecial) node T_774 = not(notSpecial_addZeros) node commonCase = and(T_773, T_774) node T_776 = and(isInfA, isZeroB) node T_777 = and(isZeroA, isInfB) node T_778 = or(T_776, T_777) node T_779 = not(isNaNA) node T_780 = not(isNaNB) node T_781 = and(T_779, T_780) node T_782 = or(isInfA, isInfB) node T_783 = and(T_781, T_782) node T_784 = and(T_783, isInfC) node T_785 = and(T_784, doSubMags) node notSigNaN_invalid = or(T_778, T_785) node T_787 = or(isSigNaNA, isSigNaNB) node T_788 = or(T_787, isSigNaNC) node invalid = or(T_788, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) node T_792 = and(commonCase, roundInexact) node inexact = or(overflow, T_792) node T_794 = or(notSpecial_addZeros, isZeroY) node notSpecial_isZeroOut = or(T_794, totalUnderflowY) node T_796 = not(overflowY_roundMagUp) node isSatOut = and(overflow, T_796) node T_798 = or(isInfA, isInfB) node T_799 = or(T_798, isInfC) node T_800 = and(overflow, overflowY_roundMagUp) node notNaN_isInfOut = or(T_799, T_800) node T_802 = or(isNaNA, isNaNB) node T_803 = or(T_802, isNaNC) node isNaNOut = or(T_803, notSigNaN_invalid) node T_806 = eq(doSubMags, UInt<1>("h00")) node T_807 = and(T_806, opSignC) node T_809 = and(isNaNOut, UInt<1>("h01")) node T_810 = or(T_807, T_809) node T_812 = eq(isSpecialC, UInt<1>("h00")) node T_813 = and(mulSpecial, T_812) node T_814 = and(T_813, signProd) node T_815 = or(T_810, T_814) node T_817 = eq(mulSpecial, UInt<1>("h00")) node T_818 = and(T_817, isSpecialC) node T_819 = and(T_818, opSignC) node T_820 = or(T_815, T_819) node T_822 = eq(mulSpecial, UInt<1>("h00")) node T_823 = and(T_822, notSpecial_addZeros) node T_824 = and(T_823, doSubMags) node T_826 = and(T_824, UInt<1>("h00")) node T_827 = or(T_820, T_826) node T_828 = and(commonCase, signY) node signOut = or(T_827, T_828) node T_832 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) node T_833 = not(T_832) node T_834 = and(expY, T_833) node T_837 = mux(isSatOut, UInt<8>("h080"), UInt<9>("h00")) node T_838 = not(T_837) node T_839 = and(T_834, T_838) node T_842 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) node T_843 = not(T_842) node T_844 = and(T_839, T_843) node T_847 = mux(isSatOut, UInt<9>("h017f"), UInt<9>("h00")) node T_848 = or(T_844, T_847) node T_851 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) node T_852 = or(T_848, T_851) node T_855 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) node expOut = or(T_852, T_855) node T_857 = or(isNaNOut, isSatOut) node T_859 = subw(UInt<23>("h00"), T_857) node fractOut = or(fractY, T_859) node T_861 = cat(expOut, fractOut) node T_862 = cat(signOut, T_861) io.out := T_862 node T_864 = cat(invalid, UInt<1>("h00")) node T_865 = cat(underflow, inexact) node T_866 = cat(overflow, T_865) node T_867 = cat(T_864, T_866) io.exceptionFlags := T_867 module FPUFMAPipe : input clock : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.valid := UInt<1>("h00") node one = shl(UInt<1>("h01"), 31) node T_136 = bit(io.in.bits.in1, 32) node T_137 = bit(io.in.bits.in2, 32) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 32) reg valid : UInt<1>, clock, reset valid := io.in.valid reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset when io.in.valid : in <> io.in.bits node T_187 = bit(io.in.bits.cmd, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) node T_190 = bit(io.in.bits.cmd, 0) node T_191 = cat(T_189, T_190) in.cmd := T_191 when io.in.bits.swap23 : in.in2 := one skip node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) node T_194 = eq(T_192, UInt<1>("h00")) when T_194 : in.in3 := zero skip skip inst fma of mulAddSubRecodedFloatN fma.io.roundingMode := UInt<1>("h00") fma.io.c := UInt<1>("h00") fma.io.b := UInt<1>("h00") fma.io.a := UInt<1>("h00") fma.io.op := UInt<1>("h00") fma.clock := clock fma.reset := reset fma.io.op := in.cmd fma.io.roundingMode := in.rm fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 wire res : {data : UInt<65>, exc : UInt<5>} res.exc := UInt<1>("h00") res.data := UInt<1>("h00") node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_211 = cat(T_210, fma.io.out) res.data := T_211 res.exc := fma.io.exceptionFlags reg T_214 : UInt<1>, clock, reset onreset T_214 := UInt<1>("h00") T_214 := valid reg T_215 : {data : UInt<65>, exc : UInt<5>}, clock, reset when valid : T_215 <> res skip wire T_226 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_226.bits.exc := UInt<1>("h00") T_226.bits.data := UInt<1>("h00") T_226.valid := UInt<1>("h00") T_226.valid := T_214 T_226.bits <> T_215 io.out <> T_226 module mulAddSubRecodedFloatN_101 : input clock : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags := UInt<1>("h00") io.out := UInt<1>("h00") node signA = bit(io.a, 64) node expA = bits(io.a, 63, 52) node fractA = bits(io.a, 51, 0) node T_15 = bits(expA, 11, 9) node isZeroA = eq(T_15, UInt<1>("h00")) node T_18 = bits(expA, 11, 10) node isSpecialA = eq(T_18, UInt<2>("h03")) node T_21 = bit(expA, 9) node T_23 = eq(T_21, UInt<1>("h00")) node isInfA = and(isSpecialA, T_23) node T_25 = bit(expA, 9) node isNaNA = and(isSpecialA, T_25) node T_27 = bit(fractA, 51) node T_29 = eq(T_27, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_29) node T_32 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_32, fractA) node signB = bit(io.b, 64) node expB = bits(io.b, 63, 52) node fractB = bits(io.b, 51, 0) node T_37 = bits(expB, 11, 9) node isZeroB = eq(T_37, UInt<1>("h00")) node T_40 = bits(expB, 11, 10) node isSpecialB = eq(T_40, UInt<2>("h03")) node T_43 = bit(expB, 9) node T_45 = eq(T_43, UInt<1>("h00")) node isInfB = and(isSpecialB, T_45) node T_47 = bit(expB, 9) node isNaNB = and(isSpecialB, T_47) node T_49 = bit(fractB, 51) node T_51 = eq(T_49, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_51) node T_54 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_54, fractB) node T_56 = bit(io.c, 64) node T_57 = bit(io.op, 0) node opSignC = xor(T_56, T_57) node expC = bits(io.c, 63, 52) node fractC = bits(io.c, 51, 0) node T_61 = bits(expC, 11, 9) node isZeroC = eq(T_61, UInt<1>("h00")) node T_64 = bits(expC, 11, 10) node isSpecialC = eq(T_64, UInt<2>("h03")) node T_67 = bit(expC, 9) node T_69 = eq(T_67, UInt<1>("h00")) node isInfC = and(isSpecialC, T_69) node T_71 = bit(expC, 9) node isNaNC = and(isSpecialC, T_71) node T_73 = bit(fractC, 51) node T_75 = eq(T_73, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_75) node T_78 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_78, fractC) node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) node T_84 = xor(signA, signB) node T_85 = bit(io.op, 1) node signProd = xor(T_84, T_85) node isZeroProd = or(isZeroA, isZeroB) node T_88 = bit(expB, 11) node T_90 = eq(T_88, UInt<1>("h00")) node T_92 = subw(UInt<3>("h00"), T_90) node T_93 = bits(expB, 10, 0) node T_94 = cat(T_92, T_93) node T_95 = addw(T_94, expA) node sExpAlignedProd = addw(T_95, UInt<6>("h038")) node doSubMags = xor(signProd, opSignC) node sNatCAlignDist = subw(sExpAlignedProd, expC) node T_100 = bit(sNatCAlignDist, 13) node CAlignDist_floor = or(isZeroProd, T_100) node T_102 = bits(sNatCAlignDist, 12, 0) node T_104 = eq(T_102, UInt<1>("h00")) node CAlignDist_0 = or(CAlignDist_floor, T_104) node T_107 = eq(isZeroC, UInt<1>("h00")) node T_108 = bits(sNatCAlignDist, 12, 0) node T_110 = lt(T_108, UInt<6>("h036")) node T_111 = or(CAlignDist_floor, T_110) node isCDominant = and(T_107, T_111) node T_114 = bits(sNatCAlignDist, 12, 0) node T_116 = lt(T_114, UInt<8>("h0a1")) node T_118 = mux(T_116, sNatCAlignDist, UInt<8>("h0a1")) node T_119 = mux(CAlignDist_floor, UInt<1>("h00"), T_118) node CAlignDist = bits(T_119, 7, 0) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) node T_123 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) node T_124 = bits(T_123, 147, 95) node T_125 = bits(T_124, 31, 0) node T_128 = shl(UInt<16>("h0ffff"), 16) node T_129 = xor(UInt<32>("h0ffffffff"), T_128) node T_130 = shr(T_125, 16) node T_131 = and(T_130, T_129) node T_132 = bits(T_125, 15, 0) node T_133 = shl(T_132, 16) node T_134 = not(T_129) node T_135 = and(T_133, T_134) node T_136 = or(T_131, T_135) node T_137 = bits(T_129, 23, 0) node T_138 = shl(T_137, 8) node T_139 = xor(T_129, T_138) node T_140 = shr(T_136, 8) node T_141 = and(T_140, T_139) node T_142 = bits(T_136, 23, 0) node T_143 = shl(T_142, 8) node T_144 = not(T_139) node T_145 = and(T_143, T_144) node T_146 = or(T_141, T_145) node T_147 = bits(T_139, 27, 0) node T_148 = shl(T_147, 4) node T_149 = xor(T_139, T_148) node T_150 = shr(T_146, 4) node T_151 = and(T_150, T_149) node T_152 = bits(T_146, 27, 0) node T_153 = shl(T_152, 4) node T_154 = not(T_149) node T_155 = and(T_153, T_154) node T_156 = or(T_151, T_155) node T_157 = bits(T_149, 29, 0) node T_158 = shl(T_157, 2) node T_159 = xor(T_149, T_158) node T_160 = shr(T_156, 2) node T_161 = and(T_160, T_159) node T_162 = bits(T_156, 29, 0) node T_163 = shl(T_162, 2) node T_164 = not(T_159) node T_165 = and(T_163, T_164) node T_166 = or(T_161, T_165) node T_167 = bits(T_159, 30, 0) node T_168 = shl(T_167, 1) node T_169 = xor(T_159, T_168) node T_170 = shr(T_166, 1) node T_171 = and(T_170, T_169) node T_172 = bits(T_166, 30, 0) node T_173 = shl(T_172, 1) node T_174 = not(T_169) node T_175 = and(T_173, T_174) node T_176 = or(T_171, T_175) node T_177 = bits(T_124, 52, 32) node T_178 = bits(T_177, 15, 0) node T_181 = shl(UInt<8>("h0ff"), 8) node T_182 = xor(UInt<16>("h0ffff"), T_181) node T_183 = shr(T_178, 8) node T_184 = and(T_183, T_182) node T_185 = bits(T_178, 7, 0) node T_186 = shl(T_185, 8) node T_187 = not(T_182) node T_188 = and(T_186, T_187) node T_189 = or(T_184, T_188) node T_190 = bits(T_182, 11, 0) node T_191 = shl(T_190, 4) node T_192 = xor(T_182, T_191) node T_193 = shr(T_189, 4) node T_194 = and(T_193, T_192) node T_195 = bits(T_189, 11, 0) node T_196 = shl(T_195, 4) node T_197 = not(T_192) node T_198 = and(T_196, T_197) node T_199 = or(T_194, T_198) node T_200 = bits(T_192, 13, 0) node T_201 = shl(T_200, 2) node T_202 = xor(T_192, T_201) node T_203 = shr(T_199, 2) node T_204 = and(T_203, T_202) node T_205 = bits(T_199, 13, 0) node T_206 = shl(T_205, 2) node T_207 = not(T_202) node T_208 = and(T_206, T_207) node T_209 = or(T_204, T_208) node T_210 = bits(T_202, 14, 0) node T_211 = shl(T_210, 1) node T_212 = xor(T_202, T_211) node T_213 = shr(T_209, 1) node T_214 = and(T_213, T_212) node T_215 = bits(T_209, 14, 0) node T_216 = shl(T_215, 1) node T_217 = not(T_212) node T_218 = and(T_216, T_217) node T_219 = or(T_214, T_218) node T_220 = bits(T_177, 20, 16) node T_221 = bits(T_220, 3, 0) node T_222 = bits(T_221, 1, 0) node T_223 = bits(T_222, 0, 0) node T_224 = bits(T_222, 1, 1) node T_225 = cat(T_223, T_224) node T_226 = bits(T_221, 3, 2) node T_227 = bits(T_226, 0, 0) node T_228 = bits(T_226, 1, 1) node T_229 = cat(T_227, T_228) node T_230 = cat(T_225, T_229) node T_231 = bits(T_220, 4, 4) node T_232 = cat(T_230, T_231) node T_233 = cat(T_219, T_232) node CExtraMask = cat(T_176, T_233) node T_235 = not(sigC) node negSigC = mux(doSubMags, T_235, sigC) node T_238 = subw(UInt<108>("h00"), doSubMags) node T_239 = cat(negSigC, T_238) node T_240 = cat(doSubMags, T_239) node T_241 = asSInt(T_240) node T_242 = dshr(T_241, CAlignDist) node T_243 = and(sigC, CExtraMask) node T_245 = neq(T_243, UInt<1>("h00")) node T_246 = xor(T_245, doSubMags) node T_247 = asUInt(T_242) node T_248 = cat(T_247, T_246) node alignedNegSigC = bits(T_248, 161, 0) node T_250 = mul(sigA, sigB) node T_251 = shl(T_250, 1) node sigSum = addw(T_251, alignedNegSigC) node T_254 = bits(sigSum, 108, 1) node T_255 = xor(UInt<108>("h00"), T_254) node T_256 = or(UInt<108>("h00"), T_254) node T_257 = shl(T_256, 1) node T_258 = xor(T_255, T_257) node T_259 = bit(T_258, 107) node T_261 = bit(T_258, 106) node T_263 = bit(T_258, 105) node T_265 = bit(T_258, 104) node T_267 = bit(T_258, 103) node T_269 = bit(T_258, 102) node T_271 = bit(T_258, 101) node T_273 = bit(T_258, 100) node T_275 = bit(T_258, 99) node T_277 = bit(T_258, 98) node T_279 = bit(T_258, 97) node T_281 = bit(T_258, 96) node T_283 = bit(T_258, 95) node T_285 = bit(T_258, 94) node T_287 = bit(T_258, 93) node T_289 = bit(T_258, 92) node T_291 = bit(T_258, 91) node T_293 = bit(T_258, 90) node T_295 = bit(T_258, 89) node T_297 = bit(T_258, 88) node T_299 = bit(T_258, 87) node T_301 = bit(T_258, 86) node T_303 = bit(T_258, 85) node T_305 = bit(T_258, 84) node T_307 = bit(T_258, 83) node T_309 = bit(T_258, 82) node T_311 = bit(T_258, 81) node T_313 = bit(T_258, 80) node T_315 = bit(T_258, 79) node T_317 = bit(T_258, 78) node T_319 = bit(T_258, 77) node T_321 = bit(T_258, 76) node T_323 = bit(T_258, 75) node T_325 = bit(T_258, 74) node T_327 = bit(T_258, 73) node T_329 = bit(T_258, 72) node T_331 = bit(T_258, 71) node T_333 = bit(T_258, 70) node T_335 = bit(T_258, 69) node T_337 = bit(T_258, 68) node T_339 = bit(T_258, 67) node T_341 = bit(T_258, 66) node T_343 = bit(T_258, 65) node T_345 = bit(T_258, 64) node T_347 = bit(T_258, 63) node T_349 = bit(T_258, 62) node T_351 = bit(T_258, 61) node T_353 = bit(T_258, 60) node T_355 = bit(T_258, 59) node T_357 = bit(T_258, 58) node T_359 = bit(T_258, 57) node T_361 = bit(T_258, 56) node T_363 = bit(T_258, 55) node T_365 = bit(T_258, 54) node T_367 = bit(T_258, 53) node T_369 = bit(T_258, 52) node T_371 = bit(T_258, 51) node T_373 = bit(T_258, 50) node T_375 = bit(T_258, 49) node T_377 = bit(T_258, 48) node T_379 = bit(T_258, 47) node T_381 = bit(T_258, 46) node T_383 = bit(T_258, 45) node T_385 = bit(T_258, 44) node T_387 = bit(T_258, 43) node T_389 = bit(T_258, 42) node T_391 = bit(T_258, 41) node T_393 = bit(T_258, 40) node T_395 = bit(T_258, 39) node T_397 = bit(T_258, 38) node T_399 = bit(T_258, 37) node T_401 = bit(T_258, 36) node T_403 = bit(T_258, 35) node T_405 = bit(T_258, 34) node T_407 = bit(T_258, 33) node T_409 = bit(T_258, 32) node T_411 = bit(T_258, 31) node T_413 = bit(T_258, 30) node T_415 = bit(T_258, 29) node T_417 = bit(T_258, 28) node T_419 = bit(T_258, 27) node T_421 = bit(T_258, 26) node T_423 = bit(T_258, 25) node T_425 = bit(T_258, 24) node T_427 = bit(T_258, 23) node T_429 = bit(T_258, 22) node T_431 = bit(T_258, 21) node T_433 = bit(T_258, 20) node T_435 = bit(T_258, 19) node T_437 = bit(T_258, 18) node T_439 = bit(T_258, 17) node T_441 = bit(T_258, 16) node T_443 = bit(T_258, 15) node T_445 = bit(T_258, 14) node T_447 = bit(T_258, 13) node T_449 = bit(T_258, 12) node T_451 = bit(T_258, 11) node T_453 = bit(T_258, 10) node T_455 = bit(T_258, 9) node T_457 = bit(T_258, 8) node T_459 = bit(T_258, 7) node T_461 = bit(T_258, 6) node T_463 = bit(T_258, 5) node T_465 = bit(T_258, 4) node T_467 = bit(T_258, 3) node T_469 = bit(T_258, 2) node T_471 = bit(T_258, 1) node T_473 = bit(T_258, 0) node T_475 = mux(T_471, UInt<8>("h09f"), UInt<8>("h0a0")) node T_476 = mux(T_469, UInt<8>("h09e"), T_475) node T_477 = mux(T_467, UInt<8>("h09d"), T_476) node T_478 = mux(T_465, UInt<8>("h09c"), T_477) node T_479 = mux(T_463, UInt<8>("h09b"), T_478) node T_480 = mux(T_461, UInt<8>("h09a"), T_479) node T_481 = mux(T_459, UInt<8>("h099"), T_480) node T_482 = mux(T_457, UInt<8>("h098"), T_481) node T_483 = mux(T_455, UInt<8>("h097"), T_482) node T_484 = mux(T_453, UInt<8>("h096"), T_483) node T_485 = mux(T_451, UInt<8>("h095"), T_484) node T_486 = mux(T_449, UInt<8>("h094"), T_485) node T_487 = mux(T_447, UInt<8>("h093"), T_486) node T_488 = mux(T_445, UInt<8>("h092"), T_487) node T_489 = mux(T_443, UInt<8>("h091"), T_488) node T_490 = mux(T_441, UInt<8>("h090"), T_489) node T_491 = mux(T_439, UInt<8>("h08f"), T_490) node T_492 = mux(T_437, UInt<8>("h08e"), T_491) node T_493 = mux(T_435, UInt<8>("h08d"), T_492) node T_494 = mux(T_433, UInt<8>("h08c"), T_493) node T_495 = mux(T_431, UInt<8>("h08b"), T_494) node T_496 = mux(T_429, UInt<8>("h08a"), T_495) node T_497 = mux(T_427, UInt<8>("h089"), T_496) node T_498 = mux(T_425, UInt<8>("h088"), T_497) node T_499 = mux(T_423, UInt<8>("h087"), T_498) node T_500 = mux(T_421, UInt<8>("h086"), T_499) node T_501 = mux(T_419, UInt<8>("h085"), T_500) node T_502 = mux(T_417, UInt<8>("h084"), T_501) node T_503 = mux(T_415, UInt<8>("h083"), T_502) node T_504 = mux(T_413, UInt<8>("h082"), T_503) node T_505 = mux(T_411, UInt<8>("h081"), T_504) node T_506 = mux(T_409, UInt<8>("h080"), T_505) node T_507 = mux(T_407, UInt<8>("h07f"), T_506) node T_508 = mux(T_405, UInt<8>("h07e"), T_507) node T_509 = mux(T_403, UInt<8>("h07d"), T_508) node T_510 = mux(T_401, UInt<8>("h07c"), T_509) node T_511 = mux(T_399, UInt<8>("h07b"), T_510) node T_512 = mux(T_397, UInt<8>("h07a"), T_511) node T_513 = mux(T_395, UInt<8>("h079"), T_512) node T_514 = mux(T_393, UInt<8>("h078"), T_513) node T_515 = mux(T_391, UInt<8>("h077"), T_514) node T_516 = mux(T_389, UInt<8>("h076"), T_515) node T_517 = mux(T_387, UInt<8>("h075"), T_516) node T_518 = mux(T_385, UInt<8>("h074"), T_517) node T_519 = mux(T_383, UInt<8>("h073"), T_518) node T_520 = mux(T_381, UInt<8>("h072"), T_519) node T_521 = mux(T_379, UInt<8>("h071"), T_520) node T_522 = mux(T_377, UInt<8>("h070"), T_521) node T_523 = mux(T_375, UInt<8>("h06f"), T_522) node T_524 = mux(T_373, UInt<8>("h06e"), T_523) node T_525 = mux(T_371, UInt<8>("h06d"), T_524) node T_526 = mux(T_369, UInt<8>("h06c"), T_525) node T_527 = mux(T_367, UInt<8>("h06b"), T_526) node T_528 = mux(T_365, UInt<8>("h06a"), T_527) node T_529 = mux(T_363, UInt<8>("h069"), T_528) node T_530 = mux(T_361, UInt<8>("h068"), T_529) node T_531 = mux(T_359, UInt<8>("h067"), T_530) node T_532 = mux(T_357, UInt<8>("h066"), T_531) node T_533 = mux(T_355, UInt<8>("h065"), T_532) node T_534 = mux(T_353, UInt<8>("h064"), T_533) node T_535 = mux(T_351, UInt<8>("h063"), T_534) node T_536 = mux(T_349, UInt<8>("h062"), T_535) node T_537 = mux(T_347, UInt<8>("h061"), T_536) node T_538 = mux(T_345, UInt<8>("h060"), T_537) node T_539 = mux(T_343, UInt<8>("h05f"), T_538) node T_540 = mux(T_341, UInt<8>("h05e"), T_539) node T_541 = mux(T_339, UInt<8>("h05d"), T_540) node T_542 = mux(T_337, UInt<8>("h05c"), T_541) node T_543 = mux(T_335, UInt<8>("h05b"), T_542) node T_544 = mux(T_333, UInt<8>("h05a"), T_543) node T_545 = mux(T_331, UInt<8>("h059"), T_544) node T_546 = mux(T_329, UInt<8>("h058"), T_545) node T_547 = mux(T_327, UInt<8>("h057"), T_546) node T_548 = mux(T_325, UInt<8>("h056"), T_547) node T_549 = mux(T_323, UInt<8>("h055"), T_548) node T_550 = mux(T_321, UInt<8>("h054"), T_549) node T_551 = mux(T_319, UInt<8>("h053"), T_550) node T_552 = mux(T_317, UInt<8>("h052"), T_551) node T_553 = mux(T_315, UInt<8>("h051"), T_552) node T_554 = mux(T_313, UInt<8>("h050"), T_553) node T_555 = mux(T_311, UInt<8>("h04f"), T_554) node T_556 = mux(T_309, UInt<8>("h04e"), T_555) node T_557 = mux(T_307, UInt<8>("h04d"), T_556) node T_558 = mux(T_305, UInt<8>("h04c"), T_557) node T_559 = mux(T_303, UInt<8>("h04b"), T_558) node T_560 = mux(T_301, UInt<8>("h04a"), T_559) node T_561 = mux(T_299, UInt<8>("h049"), T_560) node T_562 = mux(T_297, UInt<8>("h048"), T_561) node T_563 = mux(T_295, UInt<8>("h047"), T_562) node T_564 = mux(T_293, UInt<8>("h046"), T_563) node T_565 = mux(T_291, UInt<8>("h045"), T_564) node T_566 = mux(T_289, UInt<8>("h044"), T_565) node T_567 = mux(T_287, UInt<8>("h043"), T_566) node T_568 = mux(T_285, UInt<8>("h042"), T_567) node T_569 = mux(T_283, UInt<8>("h041"), T_568) node T_570 = mux(T_281, UInt<8>("h040"), T_569) node T_571 = mux(T_279, UInt<8>("h03f"), T_570) node T_572 = mux(T_277, UInt<8>("h03e"), T_571) node T_573 = mux(T_275, UInt<8>("h03d"), T_572) node T_574 = mux(T_273, UInt<8>("h03c"), T_573) node T_575 = mux(T_271, UInt<8>("h03b"), T_574) node T_576 = mux(T_269, UInt<8>("h03a"), T_575) node T_577 = mux(T_267, UInt<8>("h039"), T_576) node T_578 = mux(T_265, UInt<8>("h038"), T_577) node T_579 = mux(T_263, UInt<8>("h037"), T_578) node T_580 = mux(T_261, UInt<8>("h036"), T_579) node estNormPos_dist = mux(T_259, UInt<8>("h035"), T_580) node T_582 = bits(sigSum, 75, 44) node T_584 = neq(T_582, UInt<1>("h00")) node T_585 = bits(sigSum, 43, 0) node T_587 = neq(T_585, UInt<1>("h00")) node firstReduceSigSum = cat(T_584, T_587) node notSigSum = not(sigSum) node T_590 = bits(notSigSum, 75, 44) node T_592 = neq(T_590, UInt<1>("h00")) node T_593 = bits(notSigSum, 43, 0) node T_595 = neq(T_593, UInt<1>("h00")) node firstReduceNotSigSum = cat(T_592, T_595) node T_597 = or(CAlignDist_0, doSubMags) node T_599 = subw(CAlignDist, UInt<1>("h01")) node T_600 = bits(T_599, 5, 0) node CDom_estNormDist = mux(T_597, CAlignDist, T_600) node T_602 = not(doSubMags) node T_603 = bit(CDom_estNormDist, 5) node T_604 = not(T_603) node T_605 = and(T_602, T_604) node T_606 = asSInt(T_605) node T_607 = bits(sigSum, 161, 76) node T_609 = neq(firstReduceSigSum, UInt<1>("h00")) node T_610 = cat(T_607, T_609) node T_611 = asSInt(T_610) node T_612 = and(T_606, T_611) node T_613 = not(doSubMags) node T_614 = bit(CDom_estNormDist, 5) node T_615 = and(T_613, T_614) node T_616 = asSInt(T_615) node T_617 = bits(sigSum, 129, 44) node T_618 = bit(firstReduceSigSum, 0) node T_619 = cat(T_617, T_618) node T_620 = asSInt(T_619) node T_621 = and(T_616, T_620) node T_622 = or(T_612, T_621) node T_623 = bit(CDom_estNormDist, 5) node T_624 = not(T_623) node T_625 = and(doSubMags, T_624) node T_626 = asSInt(T_625) node T_627 = bits(notSigSum, 161, 76) node T_629 = neq(firstReduceNotSigSum, UInt<1>("h00")) node T_630 = cat(T_627, T_629) node T_631 = asSInt(T_630) node T_632 = and(T_626, T_631) node T_633 = or(T_622, T_632) node T_634 = bit(CDom_estNormDist, 5) node T_635 = and(doSubMags, T_634) node T_636 = asSInt(T_635) node T_637 = bits(notSigSum, 129, 44) node T_638 = bit(firstReduceNotSigSum, 0) node T_639 = cat(T_637, T_638) node T_640 = asSInt(T_639) node T_641 = and(T_636, T_640) node T_642 = or(T_633, T_641) node CDom_firstNormAbsSigSum = asUInt(T_642) node T_644 = bits(sigSum, 108, 44) node T_645 = bit(firstReduceNotSigSum, 0) node T_646 = not(T_645) node T_647 = bit(firstReduceSigSum, 0) node T_648 = mux(doSubMags, T_646, T_647) node T_649 = cat(T_644, T_648) node T_650 = bits(sigSum, 97, 1) node T_651 = bit(estNormPos_dist, 4) node T_652 = bits(sigSum, 1, 1) node T_654 = subw(UInt<86>("h00"), doSubMags) node T_655 = cat(T_652, T_654) node T_656 = mux(T_651, T_649, T_655) node T_657 = bits(sigSum, 97, 12) node T_658 = bits(notSigSum, 11, 1) node T_660 = eq(T_658, UInt<1>("h00")) node T_661 = bits(sigSum, 11, 1) node T_663 = neq(T_661, UInt<1>("h00")) node T_664 = mux(doSubMags, T_660, T_663) node T_665 = cat(T_657, T_664) node T_666 = bit(estNormPos_dist, 6) node T_667 = bit(estNormPos_dist, 5) node T_668 = bits(sigSum, 65, 1) node T_670 = subw(UInt<22>("h00"), doSubMags) node T_671 = cat(T_668, T_670) node T_672 = mux(T_667, T_671, T_665) node T_673 = bit(estNormPos_dist, 5) node T_674 = bits(sigSum, 33, 1) node T_676 = subw(UInt<54>("h00"), doSubMags) node T_677 = cat(T_674, T_676) node T_678 = mux(T_673, T_656, T_677) node notCDom_pos_firstNormAbsSigSum = mux(T_666, T_672, T_678) node T_680 = bits(notSigSum, 107, 44) node T_681 = bit(firstReduceNotSigSum, 0) node T_682 = cat(T_680, T_681) node T_683 = bits(notSigSum, 97, 1) node T_684 = bit(estNormPos_dist, 4) node T_685 = bits(notSigSum, 2, 1) node T_686 = shl(T_685, 86) node T_687 = mux(T_684, T_682, T_686) node T_688 = bits(notSigSum, 98, 12) node T_689 = bits(notSigSum, 11, 1) node T_691 = neq(T_689, UInt<1>("h00")) node T_692 = cat(T_688, T_691) node T_693 = bit(estNormPos_dist, 6) node T_694 = bit(estNormPos_dist, 5) node T_695 = bits(notSigSum, 66, 1) node T_696 = shl(T_695, 22) node T_697 = mux(T_694, T_696, T_692) node T_698 = bit(estNormPos_dist, 5) node T_699 = bits(notSigSum, 34, 1) node T_700 = shl(T_699, 54) node T_701 = mux(T_698, T_687, T_700) node notCDom_neg_cFirstNormAbsSigSum = mux(T_693, T_697, T_701) node notCDom_signSigSum = bit(sigSum, 109) node T_704 = not(isZeroC) node T_705 = and(doSubMags, T_704) node doNegSignSum = mux(isCDominant, T_705, notCDom_signSigSum) node T_707 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) node estNormDist = mux(isCDominant, CDom_estNormDist, T_707) node T_709 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) node T_710 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_709, T_710) node T_712 = not(isCDominant) node T_713 = not(notCDom_signSigSum) node T_714 = and(T_712, T_713) node doIncrSig = and(T_714, doSubMags) node estNormDist_5 = bits(estNormDist, 4, 0) node normTo2ShiftDist = not(estNormDist_5) node T_719 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) node T_720 = bits(T_719, 31, 1) node T_721 = bits(T_720, 15, 0) node T_724 = shl(UInt<8>("h0ff"), 8) node T_725 = xor(UInt<16>("h0ffff"), T_724) node T_726 = shr(T_721, 8) node T_727 = and(T_726, T_725) node T_728 = bits(T_721, 7, 0) node T_729 = shl(T_728, 8) node T_730 = not(T_725) node T_731 = and(T_729, T_730) node T_732 = or(T_727, T_731) node T_733 = bits(T_725, 11, 0) node T_734 = shl(T_733, 4) node T_735 = xor(T_725, T_734) node T_736 = shr(T_732, 4) node T_737 = and(T_736, T_735) node T_738 = bits(T_732, 11, 0) node T_739 = shl(T_738, 4) node T_740 = not(T_735) node T_741 = and(T_739, T_740) node T_742 = or(T_737, T_741) node T_743 = bits(T_735, 13, 0) node T_744 = shl(T_743, 2) node T_745 = xor(T_735, T_744) node T_746 = shr(T_742, 2) node T_747 = and(T_746, T_745) node T_748 = bits(T_742, 13, 0) node T_749 = shl(T_748, 2) node T_750 = not(T_745) node T_751 = and(T_749, T_750) node T_752 = or(T_747, T_751) node T_753 = bits(T_745, 14, 0) node T_754 = shl(T_753, 1) node T_755 = xor(T_745, T_754) node T_756 = shr(T_752, 1) node T_757 = and(T_756, T_755) node T_758 = bits(T_752, 14, 0) node T_759 = shl(T_758, 1) node T_760 = not(T_755) node T_761 = and(T_759, T_760) node T_762 = or(T_757, T_761) node T_763 = bits(T_720, 30, 16) node T_764 = bits(T_763, 7, 0) node T_767 = shl(UInt<4>("h0f"), 4) node T_768 = xor(UInt<8>("h0ff"), T_767) node T_769 = shr(T_764, 4) node T_770 = and(T_769, T_768) node T_771 = bits(T_764, 3, 0) node T_772 = shl(T_771, 4) node T_773 = not(T_768) node T_774 = and(T_772, T_773) node T_775 = or(T_770, T_774) node T_776 = bits(T_768, 5, 0) node T_777 = shl(T_776, 2) node T_778 = xor(T_768, T_777) node T_779 = shr(T_775, 2) node T_780 = and(T_779, T_778) node T_781 = bits(T_775, 5, 0) node T_782 = shl(T_781, 2) node T_783 = not(T_778) node T_784 = and(T_782, T_783) node T_785 = or(T_780, T_784) node T_786 = bits(T_778, 6, 0) node T_787 = shl(T_786, 1) node T_788 = xor(T_778, T_787) node T_789 = shr(T_785, 1) node T_790 = and(T_789, T_788) node T_791 = bits(T_785, 6, 0) node T_792 = shl(T_791, 1) node T_793 = not(T_788) node T_794 = and(T_792, T_793) node T_795 = or(T_790, T_794) node T_796 = bits(T_763, 14, 8) node T_797 = bits(T_796, 3, 0) node T_798 = bits(T_797, 1, 0) node T_799 = bits(T_798, 0, 0) node T_800 = bits(T_798, 1, 1) node T_801 = cat(T_799, T_800) node T_802 = bits(T_797, 3, 2) node T_803 = bits(T_802, 0, 0) node T_804 = bits(T_802, 1, 1) node T_805 = cat(T_803, T_804) node T_806 = cat(T_801, T_805) node T_807 = bits(T_796, 6, 4) node T_808 = bits(T_807, 1, 0) node T_809 = bits(T_808, 0, 0) node T_810 = bits(T_808, 1, 1) node T_811 = cat(T_809, T_810) node T_812 = bits(T_807, 2, 2) node T_813 = cat(T_811, T_812) node T_814 = cat(T_806, T_813) node T_815 = cat(T_795, T_814) node T_816 = cat(T_762, T_815) node absSigSumExtraMask = cat(T_816, UInt<1>("h01")) node T_819 = bits(cFirstNormAbsSigSum, 87, 1) node T_820 = dshr(T_819, normTo2ShiftDist) node T_821 = bits(cFirstNormAbsSigSum, 31, 0) node T_822 = not(T_821) node T_823 = and(T_822, absSigSumExtraMask) node T_825 = eq(T_823, UInt<1>("h00")) node T_826 = bits(cFirstNormAbsSigSum, 31, 0) node T_827 = and(T_826, absSigSumExtraMask) node T_829 = neq(T_827, UInt<1>("h00")) node T_830 = mux(doIncrSig, T_825, T_829) node T_831 = cat(T_820, T_830) node sigX3 = bits(T_831, 56, 0) node T_833 = bits(sigX3, 56, 55) node sigX3Shift1 = eq(T_833, UInt<1>("h00")) node sExpX3 = subw(sExpSum, estNormDist) node T_837 = bits(sigX3, 56, 54) node isZeroY = eq(T_837, UInt<1>("h00")) node T_840 = not(isZeroY) node T_841 = xor(signProd, doNegSignSum) node signY = and(T_840, T_841) node sExpX3_13 = bits(sExpX3, 12, 0) node T_844 = bit(sExpX3, 13) node T_846 = subw(UInt<56>("h00"), T_844) node T_847 = not(sExpX3_13) node T_849 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_847) node T_850 = bits(T_849, 1027, 974) node T_851 = bits(T_850, 31, 0) node T_854 = shl(UInt<16>("h0ffff"), 16) node T_855 = xor(UInt<32>("h0ffffffff"), T_854) node T_856 = shr(T_851, 16) node T_857 = and(T_856, T_855) node T_858 = bits(T_851, 15, 0) node T_859 = shl(T_858, 16) node T_860 = not(T_855) node T_861 = and(T_859, T_860) node T_862 = or(T_857, T_861) node T_863 = bits(T_855, 23, 0) node T_864 = shl(T_863, 8) node T_865 = xor(T_855, T_864) node T_866 = shr(T_862, 8) node T_867 = and(T_866, T_865) node T_868 = bits(T_862, 23, 0) node T_869 = shl(T_868, 8) node T_870 = not(T_865) node T_871 = and(T_869, T_870) node T_872 = or(T_867, T_871) node T_873 = bits(T_865, 27, 0) node T_874 = shl(T_873, 4) node T_875 = xor(T_865, T_874) node T_876 = shr(T_872, 4) node T_877 = and(T_876, T_875) node T_878 = bits(T_872, 27, 0) node T_879 = shl(T_878, 4) node T_880 = not(T_875) node T_881 = and(T_879, T_880) node T_882 = or(T_877, T_881) node T_883 = bits(T_875, 29, 0) node T_884 = shl(T_883, 2) node T_885 = xor(T_875, T_884) node T_886 = shr(T_882, 2) node T_887 = and(T_886, T_885) node T_888 = bits(T_882, 29, 0) node T_889 = shl(T_888, 2) node T_890 = not(T_885) node T_891 = and(T_889, T_890) node T_892 = or(T_887, T_891) node T_893 = bits(T_885, 30, 0) node T_894 = shl(T_893, 1) node T_895 = xor(T_885, T_894) node T_896 = shr(T_892, 1) node T_897 = and(T_896, T_895) node T_898 = bits(T_892, 30, 0) node T_899 = shl(T_898, 1) node T_900 = not(T_895) node T_901 = and(T_899, T_900) node T_902 = or(T_897, T_901) node T_903 = bits(T_850, 53, 32) node T_904 = bits(T_903, 15, 0) node T_907 = shl(UInt<8>("h0ff"), 8) node T_908 = xor(UInt<16>("h0ffff"), T_907) node T_909 = shr(T_904, 8) node T_910 = and(T_909, T_908) node T_911 = bits(T_904, 7, 0) node T_912 = shl(T_911, 8) node T_913 = not(T_908) node T_914 = and(T_912, T_913) node T_915 = or(T_910, T_914) node T_916 = bits(T_908, 11, 0) node T_917 = shl(T_916, 4) node T_918 = xor(T_908, T_917) node T_919 = shr(T_915, 4) node T_920 = and(T_919, T_918) node T_921 = bits(T_915, 11, 0) node T_922 = shl(T_921, 4) node T_923 = not(T_918) node T_924 = and(T_922, T_923) node T_925 = or(T_920, T_924) node T_926 = bits(T_918, 13, 0) node T_927 = shl(T_926, 2) node T_928 = xor(T_918, T_927) node T_929 = shr(T_925, 2) node T_930 = and(T_929, T_928) node T_931 = bits(T_925, 13, 0) node T_932 = shl(T_931, 2) node T_933 = not(T_928) node T_934 = and(T_932, T_933) node T_935 = or(T_930, T_934) node T_936 = bits(T_928, 14, 0) node T_937 = shl(T_936, 1) node T_938 = xor(T_928, T_937) node T_939 = shr(T_935, 1) node T_940 = and(T_939, T_938) node T_941 = bits(T_935, 14, 0) node T_942 = shl(T_941, 1) node T_943 = not(T_938) node T_944 = and(T_942, T_943) node T_945 = or(T_940, T_944) node T_946 = bits(T_903, 21, 16) node T_947 = bits(T_946, 3, 0) node T_948 = bits(T_947, 1, 0) node T_949 = bits(T_948, 0, 0) node T_950 = bits(T_948, 1, 1) node T_951 = cat(T_949, T_950) node T_952 = bits(T_947, 3, 2) node T_953 = bits(T_952, 0, 0) node T_954 = bits(T_952, 1, 1) node T_955 = cat(T_953, T_954) node T_956 = cat(T_951, T_955) node T_957 = bits(T_946, 5, 4) node T_958 = bits(T_957, 0, 0) node T_959 = bits(T_957, 1, 1) node T_960 = cat(T_958, T_959) node T_961 = cat(T_956, T_960) node T_962 = cat(T_945, T_961) node T_963 = cat(T_902, T_962) node T_964 = bit(sigX3, 55) node T_965 = or(T_963, T_964) node T_967 = cat(T_965, UInt<2>("h03")) node roundMask = or(T_846, T_967) node T_969 = shr(roundMask, 1) node T_970 = not(T_969) node roundPosMask = and(T_970, roundMask) node T_972 = and(sigX3, roundPosMask) node roundPosBit = neq(T_972, UInt<1>("h00")) node T_975 = shr(roundMask, 1) node T_976 = and(sigX3, T_975) node anyRoundExtra = neq(T_976, UInt<1>("h00")) node T_979 = not(sigX3) node T_980 = shr(roundMask, 1) node T_981 = and(T_979, T_980) node allRoundExtra = eq(T_981, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) node T_987 = not(doIncrSig) node T_988 = and(T_987, roundingMode_nearest_even) node T_989 = and(T_988, roundPosBit) node T_990 = and(T_989, anyRoundExtra) node T_991 = not(doIncrSig) node T_992 = and(T_991, roundDirectUp) node T_993 = and(T_992, anyRound) node T_994 = or(T_990, T_993) node T_995 = and(doIncrSig, allRound) node T_996 = or(T_994, T_995) node T_997 = and(doIncrSig, roundingMode_nearest_even) node T_998 = and(T_997, roundPosBit) node T_999 = or(T_996, T_998) node T_1000 = and(doIncrSig, roundDirectUp) node roundUp = or(T_999, T_1000) node T_1002 = not(roundPosBit) node T_1003 = and(roundingMode_nearest_even, T_1002) node T_1004 = and(T_1003, allRoundExtra) node T_1005 = and(roundingMode_nearest_even, roundPosBit) node T_1006 = not(anyRoundExtra) node T_1007 = and(T_1005, T_1006) node roundEven = mux(doIncrSig, T_1004, T_1007) node T_1009 = not(allRound) node roundInexact = mux(doIncrSig, T_1009, anyRound) node T_1011 = or(sigX3, roundMask) node T_1012 = shr(T_1011, 2) node T_1014 = addw(T_1012, UInt<1>("h01")) node roundUp_sigY3 = bits(T_1014, 54, 0) node T_1016 = not(roundUp) node T_1017 = not(roundEven) node T_1018 = and(T_1016, T_1017) node T_1019 = not(roundMask) node T_1020 = and(sigX3, T_1019) node T_1021 = shr(T_1020, 2) node T_1023 = mux(T_1018, T_1021, UInt<1>("h00")) node T_1025 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) node T_1026 = or(T_1023, T_1025) node T_1027 = shr(roundMask, 1) node T_1028 = not(T_1027) node T_1029 = and(roundUp_sigY3, T_1028) node T_1031 = mux(roundEven, T_1029, UInt<1>("h00")) node sigY3 = or(T_1026, T_1031) node T_1033 = bit(sigY3, 54) node T_1035 = addw(sExpX3, UInt<1>("h01")) node T_1037 = mux(T_1033, T_1035, UInt<1>("h00")) node T_1038 = bit(sigY3, 53) node T_1040 = mux(T_1038, sExpX3, UInt<1>("h00")) node T_1041 = or(T_1037, T_1040) node T_1042 = bits(sigY3, 54, 53) node T_1044 = eq(T_1042, UInt<1>("h00")) node T_1046 = subw(sExpX3, UInt<1>("h01")) node T_1048 = mux(T_1044, T_1046, UInt<1>("h00")) node sExpY = or(T_1041, T_1048) node expY = bits(sExpY, 11, 0) node T_1051 = bits(sigY3, 51, 0) node T_1052 = bits(sigY3, 52, 1) node fractY = mux(sigX3Shift1, T_1051, T_1052) node T_1054 = bits(sExpY, 12, 10) node overflowY = eq(T_1054, UInt<2>("h03")) node T_1057 = bit(sExpY, 12) node T_1058 = bits(sExpY, 11, 0) node T_1060 = lt(T_1058, UInt<10>("h03ce")) node totalUnderflowY = or(T_1057, T_1060) node T_1062 = bit(sExpX3, 13) node T_1065 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) node T_1066 = leq(sExpX3_13, T_1065) node T_1067 = or(T_1062, T_1066) node underflowY = and(roundInexact, T_1067) node T_1069 = and(roundingMode_min, signY) node T_1070 = or(roundingMode_nearest_even, T_1069) node T_1071 = not(signY) node T_1072 = and(roundingMode_max, T_1071) node overflowY_roundMagUp = or(T_1070, T_1072) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(isZeroProd, isZeroC) node T_1077 = not(addSpecial) node T_1078 = not(notSpecial_addZeros) node commonCase = and(T_1077, T_1078) node T_1080 = and(isInfA, isZeroB) node T_1081 = and(isZeroA, isInfB) node T_1082 = or(T_1080, T_1081) node T_1083 = not(isNaNA) node T_1084 = not(isNaNB) node T_1085 = and(T_1083, T_1084) node T_1086 = or(isInfA, isInfB) node T_1087 = and(T_1085, T_1086) node T_1088 = and(T_1087, isInfC) node T_1089 = and(T_1088, doSubMags) node notSigNaN_invalid = or(T_1082, T_1089) node T_1091 = or(isSigNaNA, isSigNaNB) node T_1092 = or(T_1091, isSigNaNC) node invalid = or(T_1092, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) node T_1096 = and(commonCase, roundInexact) node inexact = or(overflow, T_1096) node T_1098 = or(notSpecial_addZeros, isZeroY) node notSpecial_isZeroOut = or(T_1098, totalUnderflowY) node T_1100 = not(overflowY_roundMagUp) node isSatOut = and(overflow, T_1100) node T_1102 = or(isInfA, isInfB) node T_1103 = or(T_1102, isInfC) node T_1104 = and(overflow, overflowY_roundMagUp) node notNaN_isInfOut = or(T_1103, T_1104) node T_1106 = or(isNaNA, isNaNB) node T_1107 = or(T_1106, isNaNC) node isNaNOut = or(T_1107, notSigNaN_invalid) node T_1110 = eq(doSubMags, UInt<1>("h00")) node T_1111 = and(T_1110, opSignC) node T_1113 = and(isNaNOut, UInt<1>("h01")) node T_1114 = or(T_1111, T_1113) node T_1116 = eq(isSpecialC, UInt<1>("h00")) node T_1117 = and(mulSpecial, T_1116) node T_1118 = and(T_1117, signProd) node T_1119 = or(T_1114, T_1118) node T_1121 = eq(mulSpecial, UInt<1>("h00")) node T_1122 = and(T_1121, isSpecialC) node T_1123 = and(T_1122, opSignC) node T_1124 = or(T_1119, T_1123) node T_1126 = eq(mulSpecial, UInt<1>("h00")) node T_1127 = and(T_1126, notSpecial_addZeros) node T_1128 = and(T_1127, doSubMags) node T_1130 = and(T_1128, UInt<1>("h00")) node T_1131 = or(T_1124, T_1130) node T_1132 = and(commonCase, signY) node signOut = or(T_1131, T_1132) node T_1136 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) node T_1137 = not(T_1136) node T_1138 = and(expY, T_1137) node T_1141 = mux(isSatOut, UInt<11>("h0400"), UInt<12>("h00")) node T_1142 = not(T_1141) node T_1143 = and(T_1138, T_1142) node T_1146 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) node T_1147 = not(T_1146) node T_1148 = and(T_1143, T_1147) node T_1151 = mux(isSatOut, UInt<12>("h0bff"), UInt<12>("h00")) node T_1152 = or(T_1148, T_1151) node T_1155 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) node T_1156 = or(T_1152, T_1155) node T_1159 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) node expOut = or(T_1156, T_1159) node T_1161 = or(isNaNOut, isSatOut) node T_1163 = subw(UInt<52>("h00"), T_1161) node fractOut = or(fractY, T_1163) node T_1165 = cat(expOut, fractOut) node T_1166 = cat(signOut, T_1165) io.out := T_1166 node T_1168 = cat(invalid, UInt<1>("h00")) node T_1169 = cat(underflow, inexact) node T_1170 = cat(overflow, T_1169) node T_1171 = cat(T_1168, T_1170) io.exceptionFlags := T_1171 module FPUFMAPipe_100 : input clock : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.valid := UInt<1>("h00") node one = shl(UInt<1>("h01"), 63) node T_136 = bit(io.in.bits.in1, 64) node T_137 = bit(io.in.bits.in2, 64) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 64) reg valid : UInt<1>, clock, reset valid := io.in.valid reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset when io.in.valid : in <> io.in.bits node T_187 = bit(io.in.bits.cmd, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) node T_190 = bit(io.in.bits.cmd, 0) node T_191 = cat(T_189, T_190) in.cmd := T_191 when io.in.bits.swap23 : in.in2 := one skip node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) node T_194 = eq(T_192, UInt<1>("h00")) when T_194 : in.in3 := zero skip skip inst fma of mulAddSubRecodedFloatN_101 fma.io.roundingMode := UInt<1>("h00") fma.io.c := UInt<1>("h00") fma.io.b := UInt<1>("h00") fma.io.a := UInt<1>("h00") fma.io.op := UInt<1>("h00") fma.clock := clock fma.reset := reset fma.io.op := in.cmd fma.io.roundingMode := in.rm fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 wire res : {data : UInt<65>, exc : UInt<5>} res.exc := UInt<1>("h00") res.data := UInt<1>("h00") node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_211 = cat(T_210, fma.io.out) res.data := T_211 res.exc := fma.io.exceptionFlags reg T_214 : UInt<1>, clock, reset onreset T_214 := UInt<1>("h00") T_214 := valid reg T_215 : {data : UInt<65>, exc : UInt<5>}, clock, reset when valid : T_215 <> res skip reg T_220 : UInt<1>, clock, reset onreset T_220 := UInt<1>("h00") T_220 := T_214 reg T_221 : {data : UInt<65>, exc : UInt<5>}, clock, reset when T_214 : T_221 <> T_215 skip wire T_232 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_232.bits.exc := UInt<1>("h00") T_232.bits.data := UInt<1>("h00") T_232.valid := UInt<1>("h00") T_232.valid := T_220 T_232.bits <> T_221 io.out <> T_232 module recodedFloatNCompare : input clock : Clock input reset : UInt<1> output io : {flip a : UInt<65>, flip b : UInt<65>, a_eq_b : UInt<1>, a_lt_b : UInt<1>, a_eq_b_invalid : UInt<1>, a_lt_b_invalid : UInt<1>} io.a_lt_b_invalid := UInt<1>("h00") io.a_eq_b_invalid := UInt<1>("h00") io.a_lt_b := UInt<1>("h00") io.a_eq_b := UInt<1>("h00") node signA = bit(io.a, 64) node magA = bits(io.a, 63, 0) node codeA = bits(io.a, 63, 61) node isZeroA = eq(codeA, UInt<1>("h00")) node isInfA = eq(codeA, UInt<3>("h06")) node isNaNA = eq(codeA, UInt<3>("h07")) node T_20 = bit(io.a, 51) node T_22 = eq(T_20, UInt<1>("h00")) node isSignalingNaNA = and(isNaNA, T_22) node signB = bit(io.b, 64) node magB = bits(io.b, 63, 0) node codeB = bits(io.b, 63, 61) node isZeroB = eq(codeB, UInt<1>("h00")) node isInfB = eq(codeB, UInt<3>("h06")) node isNaNB = eq(codeB, UInt<3>("h07")) node T_33 = bit(io.b, 51) node T_35 = eq(T_33, UInt<1>("h00")) node isSignalingNaNB = and(isNaNB, T_35) node signEqual = eq(signA, signB) node T_38 = eq(magA, magB) node T_39 = and(isInfA, isInfB) node T_40 = or(T_38, T_39) node T_41 = and(isZeroA, isZeroB) node magEqual = or(T_40, T_41) node T_43 = lt(magA, magB) node T_45 = eq(isInfA, UInt<1>("h00")) node T_46 = and(T_43, T_45) node T_48 = eq(isZeroB, UInt<1>("h00")) node magLess = and(T_46, T_48) node T_50 = or(isSignalingNaNA, isSignalingNaNB) io.a_eq_b_invalid := T_50 node T_51 = or(isNaNA, isNaNB) io.a_lt_b_invalid := T_51 node T_53 = eq(isNaNA, UInt<1>("h00")) node T_54 = and(T_53, magEqual) node T_55 = or(isZeroA, signEqual) node T_56 = and(T_54, T_55) io.a_eq_b := T_56 node T_58 = eq(io.a_lt_b_invalid, UInt<1>("h00")) node T_59 = or(magLess, magEqual) node T_61 = eq(T_59, UInt<1>("h00")) node T_62 = and(signA, T_61) node T_63 = and(isZeroA, isZeroB) node T_65 = eq(T_63, UInt<1>("h00")) node T_66 = mux(signA, T_65, magLess) node T_67 = mux(signB, T_62, T_66) node T_68 = and(T_58, T_67) io.a_lt_b := T_68 module FPToInt : input clock : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} io.out.bits.exc := UInt<1>("h00") io.out.bits.toint := UInt<1>("h00") io.out.bits.store := UInt<1>("h00") io.out.bits.lt := UInt<1>("h00") io.out.valid := UInt<1>("h00") io.as_double.in3 := UInt<1>("h00") io.as_double.in2 := UInt<1>("h00") io.as_double.in1 := UInt<1>("h00") io.as_double.typ := UInt<1>("h00") io.as_double.rm := UInt<1>("h00") io.as_double.wflags := UInt<1>("h00") io.as_double.round := UInt<1>("h00") io.as_double.sqrt := UInt<1>("h00") io.as_double.div := UInt<1>("h00") io.as_double.fma := UInt<1>("h00") io.as_double.fastpipe := UInt<1>("h00") io.as_double.toint := UInt<1>("h00") io.as_double.fromint := UInt<1>("h00") io.as_double.single := UInt<1>("h00") io.as_double.swap23 := UInt<1>("h00") io.as_double.swap12 := UInt<1>("h00") io.as_double.ren3 := UInt<1>("h00") io.as_double.ren2 := UInt<1>("h00") io.as_double.ren1 := UInt<1>("h00") io.as_double.wen := UInt<1>("h00") io.as_double.ldst := UInt<1>("h00") io.as_double.cmd := UInt<1>("h00") reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset reg valid : UInt<1>, clock, reset valid := io.in.valid when io.in.valid : in <> io.in.bits node T_234 = eq(io.in.bits.ldst, UInt<1>("h00")) node T_235 = and(io.in.bits.single, T_234) node T_238 = and(io.in.bits.cmd, UInt<4>("h0c")) node T_239 = eq(UInt<4>("h0c"), T_238) node T_241 = eq(T_239, UInt<1>("h00")) node T_242 = and(T_235, T_241) when T_242 : node T_244 = bit(io.in.bits.in1, 32) node T_245 = bits(io.in.bits.in1, 22, 0) node T_246 = bits(io.in.bits.in1, 31, 23) node T_247 = bits(io.in.bits.in1, 31, 29) node T_248 = bits(io.in.bits.in1, 30, 23) node T_249 = not(T_247) node T_251 = eq(T_249, UInt<1>("h00")) node T_252 = bit(T_245, 22) node T_254 = eq(T_252, UInt<1>("h00")) node T_255 = and(T_251, T_254) node T_257 = lt(T_247, UInt<1>("h01")) node T_259 = lt(T_247, UInt<3>("h04")) node T_261 = cat(UInt<3>("h07"), T_248) node T_263 = lt(T_247, UInt<3>("h06")) node T_265 = cat(UInt<4>("h08"), T_248) node T_267 = lt(T_247, UInt<3>("h07")) node T_270 = mux(T_267, UInt<12>("h0c00"), UInt<12>("h0e00")) node T_271 = mux(T_263, T_265, T_270) node T_272 = mux(T_259, T_261, T_271) node T_273 = mux(T_257, T_248, T_272) node T_275 = subw(UInt<52>("h00"), T_251) node T_276 = shl(T_245, 29) node T_277 = or(T_275, T_276) node T_278 = cat(T_273, T_277) node T_279 = cat(T_244, T_278) node T_280 = shl(T_255, 4) in.in1 := T_279 node T_282 = bit(io.in.bits.in2, 32) node T_283 = bits(io.in.bits.in2, 22, 0) node T_284 = bits(io.in.bits.in2, 31, 23) node T_285 = bits(io.in.bits.in2, 31, 29) node T_286 = bits(io.in.bits.in2, 30, 23) node T_287 = not(T_285) node T_289 = eq(T_287, UInt<1>("h00")) node T_290 = bit(T_283, 22) node T_292 = eq(T_290, UInt<1>("h00")) node T_293 = and(T_289, T_292) node T_295 = lt(T_285, UInt<1>("h01")) node T_297 = lt(T_285, UInt<3>("h04")) node T_299 = cat(UInt<3>("h07"), T_286) node T_301 = lt(T_285, UInt<3>("h06")) node T_303 = cat(UInt<4>("h08"), T_286) node T_305 = lt(T_285, UInt<3>("h07")) node T_308 = mux(T_305, UInt<12>("h0c00"), UInt<12>("h0e00")) node T_309 = mux(T_301, T_303, T_308) node T_310 = mux(T_297, T_299, T_309) node T_311 = mux(T_295, T_286, T_310) node T_313 = subw(UInt<52>("h00"), T_289) node T_314 = shl(T_283, 29) node T_315 = or(T_313, T_314) node T_316 = cat(T_311, T_315) node T_317 = cat(T_282, T_316) node T_318 = shl(T_293, 4) in.in2 := T_317 skip skip node T_319 = bit(in.in1, 32) node T_320 = bits(in.in1, 31, 23) node T_321 = bits(in.in1, 22, 0) node T_322 = bits(T_320, 6, 0) node T_324 = lt(T_322, UInt<2>("h02")) node T_325 = bits(T_320, 8, 6) node T_327 = eq(T_325, UInt<1>("h01")) node T_328 = bits(T_320, 8, 7) node T_330 = eq(T_328, UInt<1>("h01")) node T_331 = and(T_330, T_324) node T_332 = or(T_327, T_331) node T_333 = bits(T_320, 8, 7) node T_335 = eq(T_333, UInt<1>("h01")) node T_337 = eq(T_324, UInt<1>("h00")) node T_338 = and(T_335, T_337) node T_339 = bits(T_320, 8, 7) node T_341 = eq(T_339, UInt<2>("h02")) node T_342 = or(T_338, T_341) node T_343 = bits(T_320, 8, 7) node T_345 = eq(T_343, UInt<2>("h03")) node T_346 = bit(T_320, 6) node T_347 = and(T_345, T_346) node T_349 = bits(T_320, 4, 0) node T_350 = subw(UInt<2>("h02"), T_349) node T_352 = cat(UInt<1>("h01"), T_321) node T_353 = dshr(T_352, T_350) node T_354 = bits(T_353, 22, 0) node T_355 = bits(T_320, 7, 0) node T_357 = subw(T_355, UInt<8>("h081")) node T_359 = subw(UInt<8>("h00"), T_345) node T_360 = mux(T_342, T_357, T_359) node T_361 = or(T_342, T_347) node T_363 = mux(T_332, T_354, UInt<1>("h00")) node T_364 = mux(T_361, T_321, T_363) node T_365 = cat(T_360, T_364) node unrec_s = cat(T_319, T_365) node T_367 = bit(in.in1, 64) node T_368 = bits(in.in1, 63, 52) node T_369 = bits(in.in1, 51, 0) node T_370 = bits(T_368, 9, 0) node T_372 = lt(T_370, UInt<2>("h02")) node T_373 = bits(T_368, 11, 9) node T_375 = eq(T_373, UInt<1>("h01")) node T_376 = bits(T_368, 11, 10) node T_378 = eq(T_376, UInt<1>("h01")) node T_379 = and(T_378, T_372) node T_380 = or(T_375, T_379) node T_381 = bits(T_368, 11, 10) node T_383 = eq(T_381, UInt<1>("h01")) node T_385 = eq(T_372, UInt<1>("h00")) node T_386 = and(T_383, T_385) node T_387 = bits(T_368, 11, 10) node T_389 = eq(T_387, UInt<2>("h02")) node T_390 = or(T_386, T_389) node T_391 = bits(T_368, 11, 10) node T_393 = eq(T_391, UInt<2>("h03")) node T_394 = bit(T_368, 9) node T_395 = and(T_393, T_394) node T_397 = bits(T_368, 5, 0) node T_398 = subw(UInt<2>("h02"), T_397) node T_400 = cat(UInt<1>("h01"), T_369) node T_401 = dshr(T_400, T_398) node T_402 = bits(T_401, 51, 0) node T_403 = bits(T_368, 10, 0) node T_405 = subw(T_403, UInt<11>("h0401")) node T_407 = subw(UInt<11>("h00"), T_393) node T_408 = mux(T_390, T_405, T_407) node T_409 = or(T_390, T_395) node T_411 = mux(T_380, T_402, UInt<1>("h00")) node T_412 = mux(T_409, T_369, T_411) node T_413 = cat(T_408, T_412) node unrec_d = cat(T_367, T_413) node T_415 = bit(unrec_s, 31) node T_417 = subw(UInt<32>("h00"), T_415) node T_418 = cat(T_417, unrec_s) node unrec_out = mux(in.single, T_418, unrec_d) node T_420 = bit(in.in1, 32) node T_421 = bits(in.in1, 31, 23) node T_422 = bits(in.in1, 22, 0) node T_423 = bits(T_421, 8, 6) node T_424 = bits(T_423, 2, 1) node T_426 = eq(T_424, UInt<2>("h03")) node T_427 = bits(T_421, 6, 0) node T_429 = lt(T_427, UInt<2>("h02")) node T_431 = eq(T_423, UInt<1>("h01")) node T_433 = eq(T_424, UInt<1>("h01")) node T_434 = and(T_433, T_429) node T_435 = or(T_431, T_434) node T_437 = eq(T_424, UInt<1>("h01")) node T_439 = eq(T_429, UInt<1>("h00")) node T_440 = and(T_437, T_439) node T_442 = eq(T_424, UInt<2>("h02")) node T_443 = or(T_440, T_442) node T_445 = eq(T_423, UInt<1>("h00")) node T_446 = bit(T_421, 6) node T_448 = eq(T_446, UInt<1>("h00")) node T_449 = and(T_426, T_448) node T_450 = not(T_423) node T_452 = eq(T_450, UInt<1>("h00")) node T_453 = bit(T_422, 22) node T_455 = eq(T_453, UInt<1>("h00")) node T_456 = and(T_452, T_455) node T_457 = bit(T_422, 22) node T_458 = and(T_452, T_457) node T_460 = eq(T_420, UInt<1>("h00")) node T_461 = and(T_449, T_460) node T_463 = eq(T_420, UInt<1>("h00")) node T_464 = and(T_443, T_463) node T_466 = eq(T_420, UInt<1>("h00")) node T_467 = and(T_435, T_466) node T_469 = eq(T_420, UInt<1>("h00")) node T_470 = and(T_445, T_469) node T_471 = and(T_445, T_420) node T_472 = and(T_435, T_420) node T_473 = and(T_443, T_420) node T_474 = and(T_449, T_420) node T_475 = cat(T_458, T_456) node T_476 = cat(T_464, T_467) node T_477 = cat(T_461, T_476) node T_478 = cat(T_475, T_477) node T_479 = cat(T_470, T_471) node T_480 = cat(T_473, T_474) node T_481 = cat(T_472, T_480) node T_482 = cat(T_479, T_481) node classify_s = cat(T_478, T_482) node T_484 = bit(in.in1, 64) node T_485 = bits(in.in1, 63, 52) node T_486 = bits(in.in1, 51, 0) node T_487 = bits(T_485, 11, 9) node T_488 = bits(T_487, 2, 1) node T_490 = eq(T_488, UInt<2>("h03")) node T_491 = bits(T_485, 9, 0) node T_493 = lt(T_491, UInt<2>("h02")) node T_495 = eq(T_487, UInt<1>("h01")) node T_497 = eq(T_488, UInt<1>("h01")) node T_498 = and(T_497, T_493) node T_499 = or(T_495, T_498) node T_501 = eq(T_488, UInt<1>("h01")) node T_503 = eq(T_493, UInt<1>("h00")) node T_504 = and(T_501, T_503) node T_506 = eq(T_488, UInt<2>("h02")) node T_507 = or(T_504, T_506) node T_509 = eq(T_487, UInt<1>("h00")) node T_510 = bit(T_485, 9) node T_512 = eq(T_510, UInt<1>("h00")) node T_513 = and(T_490, T_512) node T_514 = not(T_487) node T_516 = eq(T_514, UInt<1>("h00")) node T_517 = bit(T_486, 51) node T_519 = eq(T_517, UInt<1>("h00")) node T_520 = and(T_516, T_519) node T_521 = bit(T_486, 51) node T_522 = and(T_516, T_521) node T_524 = eq(T_484, UInt<1>("h00")) node T_525 = and(T_513, T_524) node T_527 = eq(T_484, UInt<1>("h00")) node T_528 = and(T_507, T_527) node T_530 = eq(T_484, UInt<1>("h00")) node T_531 = and(T_499, T_530) node T_533 = eq(T_484, UInt<1>("h00")) node T_534 = and(T_509, T_533) node T_535 = and(T_509, T_484) node T_536 = and(T_499, T_484) node T_537 = and(T_507, T_484) node T_538 = and(T_513, T_484) node T_539 = cat(T_522, T_520) node T_540 = cat(T_528, T_531) node T_541 = cat(T_525, T_540) node T_542 = cat(T_539, T_541) node T_543 = cat(T_534, T_535) node T_544 = cat(T_537, T_538) node T_545 = cat(T_536, T_544) node T_546 = cat(T_543, T_545) node classify_d = cat(T_542, T_546) node classify_out = mux(in.single, classify_s, classify_d) inst dcmp of recodedFloatNCompare dcmp.io.b := UInt<1>("h00") dcmp.io.a := UInt<1>("h00") dcmp.clock := clock dcmp.reset := reset dcmp.io.a := in.in1 dcmp.io.b := in.in2 node T_552 = not(in.rm) node T_553 = cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b) node T_554 = and(T_552, T_553) node dcmp_out = neq(T_554, UInt<1>("h00")) node T_557 = not(in.rm) node T_558 = cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid) node T_559 = and(T_557, T_558) node T_561 = neq(T_559, UInt<1>("h00")) node dcmp_exc = shl(T_561, 4) node T_564 = xor(in.typ, UInt<1>("h01")) node T_565 = bit(in.in1, 64) node T_566 = bits(in.in1, 63, 52) node T_567 = bits(in.in1, 51, 0) node T_568 = bits(T_566, 10, 0) node T_569 = not(T_568) node T_571 = eq(T_569, UInt<1>("h00")) node T_573 = eq(T_571, UInt<1>("h00")) node T_574 = bit(T_566, 11) node T_576 = eq(T_574, UInt<1>("h00")) node T_577 = bits(T_566, 11, 9) node T_579 = eq(T_577, UInt<1>("h00")) node T_580 = bits(T_566, 11, 10) node T_581 = not(T_580) node T_583 = eq(T_581, UInt<1>("h00")) node T_585 = bits(T_566, 5, 0) node T_586 = mux(T_576, UInt<1>("h00"), T_585) node T_588 = eq(T_576, UInt<1>("h00")) node T_589 = cat(T_588, T_567) node T_590 = dshl(T_589, T_586) node T_591 = bits(T_590, 115, 52) node T_592 = bits(T_590, 52, 51) node T_593 = bits(T_590, 50, 0) node T_595 = neq(T_593, UInt<1>("h00")) node T_596 = cat(T_592, T_595) node T_597 = bits(T_596, 1, 0) node T_599 = neq(T_597, UInt<1>("h00")) node T_601 = eq(T_573, UInt<1>("h00")) node T_602 = and(T_601, T_599) node T_603 = bits(T_596, 2, 1) node T_604 = not(T_603) node T_606 = eq(T_604, UInt<1>("h00")) node T_607 = bits(T_596, 1, 0) node T_608 = not(T_607) node T_610 = eq(T_608, UInt<1>("h00")) node T_611 = or(T_606, T_610) node T_612 = mux(T_576, T_602, T_611) node T_614 = eq(T_579, UInt<1>("h00")) node T_615 = mux(T_576, T_614, T_599) node T_616 = eq(in.rm, UInt<2>("h00")) node T_617 = eq(in.rm, UInt<2>("h02")) node T_618 = and(T_565, T_615) node T_619 = eq(in.rm, UInt<2>("h03")) node T_621 = eq(T_565, UInt<1>("h00")) node T_622 = and(T_621, T_615) node T_624 = mux(T_619, T_622, UInt<1>("h00")) node T_625 = mux(T_617, T_618, T_624) node T_626 = mux(T_616, T_612, T_625) node T_627 = not(T_591) node T_628 = mux(T_565, T_627, T_591) node T_629 = xor(T_626, T_565) node T_631 = addw(T_628, UInt<1>("h01")) node T_632 = mux(T_629, T_631, T_628) node T_633 = asSInt(T_632) node T_634 = not(T_591) node T_636 = eq(T_634, UInt<1>("h00")) node T_637 = and(T_626, T_636) node T_639 = eq(T_565, UInt<1>("h00")) node T_640 = and(T_639, T_637) node T_642 = eq(T_565, UInt<1>("h00")) node T_643 = or(T_642, T_626) node T_645 = neq(T_591, UInt<1>("h00")) node T_646 = or(T_643, T_645) node T_647 = bits(T_566, 10, 0) node T_648 = eq(T_564, UInt<2>("h00")) node T_649 = and(T_565, T_626) node T_651 = eq(T_647, UInt<5>("h01f")) node T_653 = geq(T_647, UInt<6>("h020")) node T_654 = mux(T_651, T_637, T_653) node T_655 = or(T_565, T_654) node T_656 = mux(T_576, T_649, T_655) node T_657 = eq(T_564, UInt<2>("h01")) node T_660 = eq(T_647, UInt<5>("h01e")) node T_662 = eq(T_647, UInt<5>("h01f")) node T_664 = geq(T_647, UInt<6>("h020")) node T_665 = mux(T_662, T_646, T_664) node T_666 = mux(T_660, T_640, T_665) node T_667 = mux(T_576, UInt<1>("h00"), T_666) node T_668 = eq(T_564, UInt<2>("h02")) node T_669 = and(T_565, T_626) node T_671 = eq(T_647, UInt<6>("h03f")) node T_673 = geq(T_647, UInt<7>("h040")) node T_674 = mux(T_671, T_637, T_673) node T_675 = or(T_565, T_674) node T_676 = mux(T_576, T_669, T_675) node T_679 = eq(T_647, UInt<6>("h03e")) node T_681 = eq(T_647, UInt<6>("h03f")) node T_683 = geq(T_647, UInt<7>("h040")) node T_684 = mux(T_681, T_646, T_683) node T_685 = mux(T_679, T_640, T_684) node T_686 = mux(T_576, UInt<1>("h00"), T_685) node T_687 = mux(T_668, T_676, T_686) node T_688 = mux(T_657, T_667, T_687) node T_689 = mux(T_648, T_656, T_688) node T_690 = or(T_583, T_689) node T_691 = eq(T_564, UInt<2>("h03")) node T_692 = and(T_691, T_565) node T_694 = eq(T_564, UInt<2>("h01")) node T_695 = and(T_694, T_565) node T_697 = eq(T_564, UInt<2>("h03")) node T_699 = eq(T_565, UInt<1>("h00")) node T_700 = and(T_697, T_699) node T_702 = eq(T_564, UInt<2>("h01")) node T_704 = eq(T_565, UInt<1>("h00")) node T_705 = and(T_702, T_704) node T_708 = mux(T_705, asSInt(UInt<32>("h07fffffff")), asSInt(UInt<1>("h01"))) node T_709 = mux(T_700, asSInt(UInt<64>("h07fffffffffffffff")), T_708) node T_710 = mux(T_695, asSInt(UInt<32>("h080000000")), T_709) node T_711 = mux(T_692, asSInt(UInt<64>("h08000000000000000")), T_710) node T_713 = eq(T_690, UInt<1>("h00")) node T_714 = and(T_599, T_713) node T_715 = mux(T_690, T_711, T_633) node T_717 = cat(UInt<3>("h00"), T_714) node T_718 = cat(T_690, T_717) node T_719 = bit(in.rm, 0) node T_720 = mux(T_719, classify_out, unrec_out) io.out.bits.toint := T_720 io.out.bits.store := unrec_out io.out.bits.exc := UInt<1>("h00") node T_724 = and(in.cmd, UInt<4>("h0c")) node T_725 = eq(UInt<3>("h04"), T_724) when T_725 : io.out.bits.toint := dcmp_out io.out.bits.exc := dcmp_exc skip node T_728 = and(in.cmd, UInt<4>("h0c")) node T_729 = eq(UInt<4>("h08"), T_728) when T_729 : node T_730 = bit(in.typ, 1) node T_731 = bits(T_715, 31, 0) node T_732 = asSInt(T_731) node T_733 = mux(T_730, T_715, T_732) node T_734 = asUInt(T_733) io.out.bits.toint := T_734 io.out.bits.exc := T_718 skip io.out.valid := valid io.out.bits.lt := dcmp.io.a_lt_b io.as_double <> in module IntToFP : input clock : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.valid := UInt<1>("h00") reg T_136 : UInt<1>, clock, reset onreset T_136 := UInt<1>("h00") T_136 := io.in.valid reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset when io.in.valid : T_137 <> io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} in.bits.in3 := UInt<1>("h00") in.bits.in2 := UInt<1>("h00") in.bits.in1 := UInt<1>("h00") in.bits.typ := UInt<1>("h00") in.bits.rm := UInt<1>("h00") in.bits.wflags := UInt<1>("h00") in.bits.round := UInt<1>("h00") in.bits.sqrt := UInt<1>("h00") in.bits.div := UInt<1>("h00") in.bits.fma := UInt<1>("h00") in.bits.fastpipe := UInt<1>("h00") in.bits.toint := UInt<1>("h00") in.bits.fromint := UInt<1>("h00") in.bits.single := UInt<1>("h00") in.bits.swap23 := UInt<1>("h00") in.bits.swap12 := UInt<1>("h00") in.bits.ren3 := UInt<1>("h00") in.bits.ren2 := UInt<1>("h00") in.bits.ren1 := UInt<1>("h00") in.bits.wen := UInt<1>("h00") in.bits.ldst := UInt<1>("h00") in.bits.cmd := UInt<1>("h00") in.valid := UInt<1>("h00") in.valid := T_136 in.bits <> T_137 wire mux : {data : UInt<65>, exc : UInt<5>} mux.exc := UInt<1>("h00") mux.data := UInt<1>("h00") mux.exc := UInt<1>("h00") node T_288 = bit(in.bits.in1, 63) node T_289 = bits(in.bits.in1, 62, 52) node T_290 = bits(in.bits.in1, 51, 0) node T_292 = eq(T_289, UInt<1>("h00")) node T_294 = eq(T_290, UInt<1>("h00")) node T_295 = and(T_292, T_294) node T_297 = eq(T_294, UInt<1>("h00")) node T_298 = and(T_292, T_297) node T_299 = shl(T_290, 12) node T_300 = bit(T_299, 63) node T_302 = bit(T_299, 62) node T_304 = bit(T_299, 61) node T_306 = bit(T_299, 60) node T_308 = bit(T_299, 59) node T_310 = bit(T_299, 58) node T_312 = bit(T_299, 57) node T_314 = bit(T_299, 56) node T_316 = bit(T_299, 55) node T_318 = bit(T_299, 54) node T_320 = bit(T_299, 53) node T_322 = bit(T_299, 52) node T_324 = bit(T_299, 51) node T_326 = bit(T_299, 50) node T_328 = bit(T_299, 49) node T_330 = bit(T_299, 48) node T_332 = bit(T_299, 47) node T_334 = bit(T_299, 46) node T_336 = bit(T_299, 45) node T_338 = bit(T_299, 44) node T_340 = bit(T_299, 43) node T_342 = bit(T_299, 42) node T_344 = bit(T_299, 41) node T_346 = bit(T_299, 40) node T_348 = bit(T_299, 39) node T_350 = bit(T_299, 38) node T_352 = bit(T_299, 37) node T_354 = bit(T_299, 36) node T_356 = bit(T_299, 35) node T_358 = bit(T_299, 34) node T_360 = bit(T_299, 33) node T_362 = bit(T_299, 32) node T_364 = bit(T_299, 31) node T_366 = bit(T_299, 30) node T_368 = bit(T_299, 29) node T_370 = bit(T_299, 28) node T_372 = bit(T_299, 27) node T_374 = bit(T_299, 26) node T_376 = bit(T_299, 25) node T_378 = bit(T_299, 24) node T_380 = bit(T_299, 23) node T_382 = bit(T_299, 22) node T_384 = bit(T_299, 21) node T_386 = bit(T_299, 20) node T_388 = bit(T_299, 19) node T_390 = bit(T_299, 18) node T_392 = bit(T_299, 17) node T_394 = bit(T_299, 16) node T_396 = bit(T_299, 15) node T_398 = bit(T_299, 14) node T_400 = bit(T_299, 13) node T_402 = bit(T_299, 12) node T_404 = bit(T_299, 11) node T_406 = bit(T_299, 10) node T_408 = bit(T_299, 9) node T_410 = bit(T_299, 8) node T_412 = bit(T_299, 7) node T_414 = bit(T_299, 6) node T_416 = bit(T_299, 5) node T_418 = bit(T_299, 4) node T_420 = bit(T_299, 3) node T_422 = bit(T_299, 2) node T_424 = bit(T_299, 1) node T_425 = shl(T_424, 0) node T_426 = mux(T_422, UInt<2>("h02"), T_425) node T_427 = mux(T_420, UInt<2>("h03"), T_426) node T_428 = mux(T_418, UInt<3>("h04"), T_427) node T_429 = mux(T_416, UInt<3>("h05"), T_428) node T_430 = mux(T_414, UInt<3>("h06"), T_429) node T_431 = mux(T_412, UInt<3>("h07"), T_430) node T_432 = mux(T_410, UInt<4>("h08"), T_431) node T_433 = mux(T_408, UInt<4>("h09"), T_432) node T_434 = mux(T_406, UInt<4>("h0a"), T_433) node T_435 = mux(T_404, UInt<4>("h0b"), T_434) node T_436 = mux(T_402, UInt<4>("h0c"), T_435) node T_437 = mux(T_400, UInt<4>("h0d"), T_436) node T_438 = mux(T_398, UInt<4>("h0e"), T_437) node T_439 = mux(T_396, UInt<4>("h0f"), T_438) node T_440 = mux(T_394, UInt<5>("h010"), T_439) node T_441 = mux(T_392, UInt<5>("h011"), T_440) node T_442 = mux(T_390, UInt<5>("h012"), T_441) node T_443 = mux(T_388, UInt<5>("h013"), T_442) node T_444 = mux(T_386, UInt<5>("h014"), T_443) node T_445 = mux(T_384, UInt<5>("h015"), T_444) node T_446 = mux(T_382, UInt<5>("h016"), T_445) node T_447 = mux(T_380, UInt<5>("h017"), T_446) node T_448 = mux(T_378, UInt<5>("h018"), T_447) node T_449 = mux(T_376, UInt<5>("h019"), T_448) node T_450 = mux(T_374, UInt<5>("h01a"), T_449) node T_451 = mux(T_372, UInt<5>("h01b"), T_450) node T_452 = mux(T_370, UInt<5>("h01c"), T_451) node T_453 = mux(T_368, UInt<5>("h01d"), T_452) node T_454 = mux(T_366, UInt<5>("h01e"), T_453) node T_455 = mux(T_364, UInt<5>("h01f"), T_454) node T_456 = mux(T_362, UInt<6>("h020"), T_455) node T_457 = mux(T_360, UInt<6>("h021"), T_456) node T_458 = mux(T_358, UInt<6>("h022"), T_457) node T_459 = mux(T_356, UInt<6>("h023"), T_458) node T_460 = mux(T_354, UInt<6>("h024"), T_459) node T_461 = mux(T_352, UInt<6>("h025"), T_460) node T_462 = mux(T_350, UInt<6>("h026"), T_461) node T_463 = mux(T_348, UInt<6>("h027"), T_462) node T_464 = mux(T_346, UInt<6>("h028"), T_463) node T_465 = mux(T_344, UInt<6>("h029"), T_464) node T_466 = mux(T_342, UInt<6>("h02a"), T_465) node T_467 = mux(T_340, UInt<6>("h02b"), T_466) node T_468 = mux(T_338, UInt<6>("h02c"), T_467) node T_469 = mux(T_336, UInt<6>("h02d"), T_468) node T_470 = mux(T_334, UInt<6>("h02e"), T_469) node T_471 = mux(T_332, UInt<6>("h02f"), T_470) node T_472 = mux(T_330, UInt<6>("h030"), T_471) node T_473 = mux(T_328, UInt<6>("h031"), T_472) node T_474 = mux(T_326, UInt<6>("h032"), T_473) node T_475 = mux(T_324, UInt<6>("h033"), T_474) node T_476 = mux(T_322, UInt<6>("h034"), T_475) node T_477 = mux(T_320, UInt<6>("h035"), T_476) node T_478 = mux(T_318, UInt<6>("h036"), T_477) node T_479 = mux(T_316, UInt<6>("h037"), T_478) node T_480 = mux(T_314, UInt<6>("h038"), T_479) node T_481 = mux(T_312, UInt<6>("h039"), T_480) node T_482 = mux(T_310, UInt<6>("h03a"), T_481) node T_483 = mux(T_308, UInt<6>("h03b"), T_482) node T_484 = mux(T_306, UInt<6>("h03c"), T_483) node T_485 = mux(T_304, UInt<6>("h03d"), T_484) node T_486 = mux(T_302, UInt<6>("h03e"), T_485) node T_487 = mux(T_300, UInt<6>("h03f"), T_486) node T_488 = not(T_487) node T_489 = dshl(T_299, T_488) node T_492 = subw(UInt<6>("h00"), UInt<1>("h01")) node T_493 = not(T_488) node T_494 = cat(T_492, T_493) node T_495 = bits(T_489, 62, 11) node T_497 = mux(T_294, UInt<1>("h00"), T_494) node T_498 = mux(T_292, T_497, T_289) node T_503 = mux(T_298, UInt<2>("h02"), UInt<1>("h01")) node T_504 = or(UInt<11>("h0400"), T_503) node T_505 = mux(T_295, UInt<1>("h00"), T_504) node T_506 = addw(T_498, T_505) node T_507 = bits(T_506, 11, 10) node T_508 = not(T_507) node T_510 = eq(T_508, UInt<1>("h00")) node T_512 = eq(T_294, UInt<1>("h00")) node T_513 = and(T_510, T_512) node T_514 = shl(T_513, 9) node T_515 = or(T_506, T_514) node T_516 = mux(T_292, T_495, T_290) node T_517 = cat(T_515, T_516) node T_518 = cat(T_288, T_517) mux.data := T_518 when in.bits.single : node T_520 = bit(in.bits.in1, 31) node T_521 = bits(in.bits.in1, 30, 23) node T_522 = bits(in.bits.in1, 22, 0) node T_524 = eq(T_521, UInt<1>("h00")) node T_526 = eq(T_522, UInt<1>("h00")) node T_527 = and(T_524, T_526) node T_529 = eq(T_526, UInt<1>("h00")) node T_530 = and(T_524, T_529) node T_531 = shl(T_522, 9) node T_532 = bit(T_531, 31) node T_534 = bit(T_531, 30) node T_536 = bit(T_531, 29) node T_538 = bit(T_531, 28) node T_540 = bit(T_531, 27) node T_542 = bit(T_531, 26) node T_544 = bit(T_531, 25) node T_546 = bit(T_531, 24) node T_548 = bit(T_531, 23) node T_550 = bit(T_531, 22) node T_552 = bit(T_531, 21) node T_554 = bit(T_531, 20) node T_556 = bit(T_531, 19) node T_558 = bit(T_531, 18) node T_560 = bit(T_531, 17) node T_562 = bit(T_531, 16) node T_564 = bit(T_531, 15) node T_566 = bit(T_531, 14) node T_568 = bit(T_531, 13) node T_570 = bit(T_531, 12) node T_572 = bit(T_531, 11) node T_574 = bit(T_531, 10) node T_576 = bit(T_531, 9) node T_578 = bit(T_531, 8) node T_580 = bit(T_531, 7) node T_582 = bit(T_531, 6) node T_584 = bit(T_531, 5) node T_586 = bit(T_531, 4) node T_588 = bit(T_531, 3) node T_590 = bit(T_531, 2) node T_592 = bit(T_531, 1) node T_593 = shl(T_592, 0) node T_594 = mux(T_590, UInt<2>("h02"), T_593) node T_595 = mux(T_588, UInt<2>("h03"), T_594) node T_596 = mux(T_586, UInt<3>("h04"), T_595) node T_597 = mux(T_584, UInt<3>("h05"), T_596) node T_598 = mux(T_582, UInt<3>("h06"), T_597) node T_599 = mux(T_580, UInt<3>("h07"), T_598) node T_600 = mux(T_578, UInt<4>("h08"), T_599) node T_601 = mux(T_576, UInt<4>("h09"), T_600) node T_602 = mux(T_574, UInt<4>("h0a"), T_601) node T_603 = mux(T_572, UInt<4>("h0b"), T_602) node T_604 = mux(T_570, UInt<4>("h0c"), T_603) node T_605 = mux(T_568, UInt<4>("h0d"), T_604) node T_606 = mux(T_566, UInt<4>("h0e"), T_605) node T_607 = mux(T_564, UInt<4>("h0f"), T_606) node T_608 = mux(T_562, UInt<5>("h010"), T_607) node T_609 = mux(T_560, UInt<5>("h011"), T_608) node T_610 = mux(T_558, UInt<5>("h012"), T_609) node T_611 = mux(T_556, UInt<5>("h013"), T_610) node T_612 = mux(T_554, UInt<5>("h014"), T_611) node T_613 = mux(T_552, UInt<5>("h015"), T_612) node T_614 = mux(T_550, UInt<5>("h016"), T_613) node T_615 = mux(T_548, UInt<5>("h017"), T_614) node T_616 = mux(T_546, UInt<5>("h018"), T_615) node T_617 = mux(T_544, UInt<5>("h019"), T_616) node T_618 = mux(T_542, UInt<5>("h01a"), T_617) node T_619 = mux(T_540, UInt<5>("h01b"), T_618) node T_620 = mux(T_538, UInt<5>("h01c"), T_619) node T_621 = mux(T_536, UInt<5>("h01d"), T_620) node T_622 = mux(T_534, UInt<5>("h01e"), T_621) node T_623 = mux(T_532, UInt<5>("h01f"), T_622) node T_624 = not(T_623) node T_625 = dshl(T_531, T_624) node T_628 = subw(UInt<4>("h00"), UInt<1>("h01")) node T_629 = not(T_624) node T_630 = cat(T_628, T_629) node T_631 = bits(T_625, 30, 8) node T_633 = mux(T_526, UInt<1>("h00"), T_630) node T_634 = mux(T_524, T_633, T_521) node T_639 = mux(T_530, UInt<2>("h02"), UInt<1>("h01")) node T_640 = or(UInt<8>("h080"), T_639) node T_641 = mux(T_527, UInt<1>("h00"), T_640) node T_642 = addw(T_634, T_641) node T_643 = bits(T_642, 8, 7) node T_644 = not(T_643) node T_646 = eq(T_644, UInt<1>("h00")) node T_648 = eq(T_526, UInt<1>("h00")) node T_649 = and(T_646, T_648) node T_650 = shl(T_649, 6) node T_651 = or(T_642, T_650) node T_652 = mux(T_524, T_631, T_522) node T_653 = cat(T_651, T_652) node T_654 = cat(T_520, T_653) node T_655 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_656 = cat(T_655, T_654) mux.data := T_656 skip node T_659 = and(in.bits.cmd, UInt<3>("h04")) node T_660 = eq(UInt<1>("h00"), T_659) when T_660 : when in.bits.single : node T_661 = bits(in.bits.in1, 63, 0) node T_663 = xor(in.bits.typ, UInt<1>("h01")) node T_664 = eq(T_663, UInt<2>("h01")) node T_665 = bit(T_661, 31) node T_666 = eq(T_663, UInt<2>("h03")) node T_667 = bit(T_661, 63) node T_669 = mux(T_666, T_667, UInt<1>("h00")) node T_670 = mux(T_664, T_665, T_669) node T_672 = subw(UInt<1>("h00"), T_661) node T_673 = mux(T_670, T_672, T_661) node T_674 = eq(T_663, UInt<2>("h03")) node T_675 = eq(T_663, UInt<2>("h02")) node T_676 = or(T_674, T_675) node T_677 = bits(T_673, 31, 0) node T_678 = mux(T_676, T_673, T_677) node T_679 = bit(T_678, 63) node T_681 = bit(T_678, 62) node T_683 = bit(T_678, 61) node T_685 = bit(T_678, 60) node T_687 = bit(T_678, 59) node T_689 = bit(T_678, 58) node T_691 = bit(T_678, 57) node T_693 = bit(T_678, 56) node T_695 = bit(T_678, 55) node T_697 = bit(T_678, 54) node T_699 = bit(T_678, 53) node T_701 = bit(T_678, 52) node T_703 = bit(T_678, 51) node T_705 = bit(T_678, 50) node T_707 = bit(T_678, 49) node T_709 = bit(T_678, 48) node T_711 = bit(T_678, 47) node T_713 = bit(T_678, 46) node T_715 = bit(T_678, 45) node T_717 = bit(T_678, 44) node T_719 = bit(T_678, 43) node T_721 = bit(T_678, 42) node T_723 = bit(T_678, 41) node T_725 = bit(T_678, 40) node T_727 = bit(T_678, 39) node T_729 = bit(T_678, 38) node T_731 = bit(T_678, 37) node T_733 = bit(T_678, 36) node T_735 = bit(T_678, 35) node T_737 = bit(T_678, 34) node T_739 = bit(T_678, 33) node T_741 = bit(T_678, 32) node T_743 = bit(T_678, 31) node T_745 = bit(T_678, 30) node T_747 = bit(T_678, 29) node T_749 = bit(T_678, 28) node T_751 = bit(T_678, 27) node T_753 = bit(T_678, 26) node T_755 = bit(T_678, 25) node T_757 = bit(T_678, 24) node T_759 = bit(T_678, 23) node T_761 = bit(T_678, 22) node T_763 = bit(T_678, 21) node T_765 = bit(T_678, 20) node T_767 = bit(T_678, 19) node T_769 = bit(T_678, 18) node T_771 = bit(T_678, 17) node T_773 = bit(T_678, 16) node T_775 = bit(T_678, 15) node T_777 = bit(T_678, 14) node T_779 = bit(T_678, 13) node T_781 = bit(T_678, 12) node T_783 = bit(T_678, 11) node T_785 = bit(T_678, 10) node T_787 = bit(T_678, 9) node T_789 = bit(T_678, 8) node T_791 = bit(T_678, 7) node T_793 = bit(T_678, 6) node T_795 = bit(T_678, 5) node T_797 = bit(T_678, 4) node T_799 = bit(T_678, 3) node T_801 = bit(T_678, 2) node T_803 = bit(T_678, 1) node T_804 = shl(T_803, 0) node T_805 = mux(T_801, UInt<2>("h02"), T_804) node T_806 = mux(T_799, UInt<2>("h03"), T_805) node T_807 = mux(T_797, UInt<3>("h04"), T_806) node T_808 = mux(T_795, UInt<3>("h05"), T_807) node T_809 = mux(T_793, UInt<3>("h06"), T_808) node T_810 = mux(T_791, UInt<3>("h07"), T_809) node T_811 = mux(T_789, UInt<4>("h08"), T_810) node T_812 = mux(T_787, UInt<4>("h09"), T_811) node T_813 = mux(T_785, UInt<4>("h0a"), T_812) node T_814 = mux(T_783, UInt<4>("h0b"), T_813) node T_815 = mux(T_781, UInt<4>("h0c"), T_814) node T_816 = mux(T_779, UInt<4>("h0d"), T_815) node T_817 = mux(T_777, UInt<4>("h0e"), T_816) node T_818 = mux(T_775, UInt<4>("h0f"), T_817) node T_819 = mux(T_773, UInt<5>("h010"), T_818) node T_820 = mux(T_771, UInt<5>("h011"), T_819) node T_821 = mux(T_769, UInt<5>("h012"), T_820) node T_822 = mux(T_767, UInt<5>("h013"), T_821) node T_823 = mux(T_765, UInt<5>("h014"), T_822) node T_824 = mux(T_763, UInt<5>("h015"), T_823) node T_825 = mux(T_761, UInt<5>("h016"), T_824) node T_826 = mux(T_759, UInt<5>("h017"), T_825) node T_827 = mux(T_757, UInt<5>("h018"), T_826) node T_828 = mux(T_755, UInt<5>("h019"), T_827) node T_829 = mux(T_753, UInt<5>("h01a"), T_828) node T_830 = mux(T_751, UInt<5>("h01b"), T_829) node T_831 = mux(T_749, UInt<5>("h01c"), T_830) node T_832 = mux(T_747, UInt<5>("h01d"), T_831) node T_833 = mux(T_745, UInt<5>("h01e"), T_832) node T_834 = mux(T_743, UInt<5>("h01f"), T_833) node T_835 = mux(T_741, UInt<6>("h020"), T_834) node T_836 = mux(T_739, UInt<6>("h021"), T_835) node T_837 = mux(T_737, UInt<6>("h022"), T_836) node T_838 = mux(T_735, UInt<6>("h023"), T_837) node T_839 = mux(T_733, UInt<6>("h024"), T_838) node T_840 = mux(T_731, UInt<6>("h025"), T_839) node T_841 = mux(T_729, UInt<6>("h026"), T_840) node T_842 = mux(T_727, UInt<6>("h027"), T_841) node T_843 = mux(T_725, UInt<6>("h028"), T_842) node T_844 = mux(T_723, UInt<6>("h029"), T_843) node T_845 = mux(T_721, UInt<6>("h02a"), T_844) node T_846 = mux(T_719, UInt<6>("h02b"), T_845) node T_847 = mux(T_717, UInt<6>("h02c"), T_846) node T_848 = mux(T_715, UInt<6>("h02d"), T_847) node T_849 = mux(T_713, UInt<6>("h02e"), T_848) node T_850 = mux(T_711, UInt<6>("h02f"), T_849) node T_851 = mux(T_709, UInt<6>("h030"), T_850) node T_852 = mux(T_707, UInt<6>("h031"), T_851) node T_853 = mux(T_705, UInt<6>("h032"), T_852) node T_854 = mux(T_703, UInt<6>("h033"), T_853) node T_855 = mux(T_701, UInt<6>("h034"), T_854) node T_856 = mux(T_699, UInt<6>("h035"), T_855) node T_857 = mux(T_697, UInt<6>("h036"), T_856) node T_858 = mux(T_695, UInt<6>("h037"), T_857) node T_859 = mux(T_693, UInt<6>("h038"), T_858) node T_860 = mux(T_691, UInt<6>("h039"), T_859) node T_861 = mux(T_689, UInt<6>("h03a"), T_860) node T_862 = mux(T_687, UInt<6>("h03b"), T_861) node T_863 = mux(T_685, UInt<6>("h03c"), T_862) node T_864 = mux(T_683, UInt<6>("h03d"), T_863) node T_865 = mux(T_681, UInt<6>("h03e"), T_864) node T_866 = mux(T_679, UInt<6>("h03f"), T_865) node T_867 = not(T_866) node T_868 = dshl(T_678, T_867) node T_870 = bits(T_868, 40, 39) node T_871 = bits(T_868, 38, 0) node T_873 = neq(T_871, UInt<1>("h00")) node T_874 = cat(T_870, T_873) node T_875 = bits(T_874, 1, 0) node T_877 = neq(T_875, UInt<1>("h00")) node T_878 = eq(in.bits.rm, UInt<2>("h00")) node T_879 = bits(T_874, 2, 1) node T_880 = not(T_879) node T_882 = eq(T_880, UInt<1>("h00")) node T_883 = bits(T_874, 1, 0) node T_884 = not(T_883) node T_886 = eq(T_884, UInt<1>("h00")) node T_887 = or(T_882, T_886) node T_888 = eq(in.bits.rm, UInt<2>("h02")) node T_889 = and(T_670, T_877) node T_890 = eq(in.bits.rm, UInt<2>("h03")) node T_892 = eq(T_670, UInt<1>("h00")) node T_893 = and(T_892, T_877) node T_895 = mux(T_890, T_893, UInt<1>("h00")) node T_896 = mux(T_888, T_889, T_895) node T_897 = mux(T_878, T_887, T_896) node T_898 = bits(T_868, 63, 40) node T_900 = cat(UInt<1>("h00"), T_898) node T_902 = addw(T_900, UInt<1>("h01")) node T_903 = mux(T_897, T_902, T_900) node T_906 = not(T_867) node T_908 = cat(UInt<1>("h00"), T_906) node T_910 = cat(UInt<1>("h00"), T_908) node T_911 = bit(T_903, 24) node T_912 = addw(T_910, T_911) node T_913 = bit(T_868, 63) node T_915 = bits(T_912, 7, 0) node T_916 = mux(UInt<1>("h00"), UInt<8>("h080"), T_915) node T_917 = cat(T_913, T_916) node T_918 = or(UInt<1>("h00"), UInt<1>("h00")) node T_919 = or(T_877, T_918) node T_920 = bits(T_903, 22, 0) node T_921 = cat(T_917, T_920) node T_922 = cat(T_670, T_921) node T_925 = cat(UInt<2>("h00"), T_918) node T_926 = cat(UInt<1>("h00"), T_919) node T_927 = cat(T_925, T_926) node T_929 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_930 = cat(T_929, T_922) mux.data := T_930 mux.exc := T_927 skip else : node T_931 = bits(in.bits.in1, 63, 0) node T_933 = xor(in.bits.typ, UInt<1>("h01")) node T_934 = eq(T_933, UInt<2>("h01")) node T_935 = bit(T_931, 31) node T_936 = eq(T_933, UInt<2>("h03")) node T_937 = bit(T_931, 63) node T_939 = mux(T_936, T_937, UInt<1>("h00")) node T_940 = mux(T_934, T_935, T_939) node T_942 = subw(UInt<1>("h00"), T_931) node T_943 = mux(T_940, T_942, T_931) node T_944 = eq(T_933, UInt<2>("h03")) node T_945 = eq(T_933, UInt<2>("h02")) node T_946 = or(T_944, T_945) node T_947 = bits(T_943, 31, 0) node T_948 = mux(T_946, T_943, T_947) node T_949 = bit(T_948, 63) node T_951 = bit(T_948, 62) node T_953 = bit(T_948, 61) node T_955 = bit(T_948, 60) node T_957 = bit(T_948, 59) node T_959 = bit(T_948, 58) node T_961 = bit(T_948, 57) node T_963 = bit(T_948, 56) node T_965 = bit(T_948, 55) node T_967 = bit(T_948, 54) node T_969 = bit(T_948, 53) node T_971 = bit(T_948, 52) node T_973 = bit(T_948, 51) node T_975 = bit(T_948, 50) node T_977 = bit(T_948, 49) node T_979 = bit(T_948, 48) node T_981 = bit(T_948, 47) node T_983 = bit(T_948, 46) node T_985 = bit(T_948, 45) node T_987 = bit(T_948, 44) node T_989 = bit(T_948, 43) node T_991 = bit(T_948, 42) node T_993 = bit(T_948, 41) node T_995 = bit(T_948, 40) node T_997 = bit(T_948, 39) node T_999 = bit(T_948, 38) node T_1001 = bit(T_948, 37) node T_1003 = bit(T_948, 36) node T_1005 = bit(T_948, 35) node T_1007 = bit(T_948, 34) node T_1009 = bit(T_948, 33) node T_1011 = bit(T_948, 32) node T_1013 = bit(T_948, 31) node T_1015 = bit(T_948, 30) node T_1017 = bit(T_948, 29) node T_1019 = bit(T_948, 28) node T_1021 = bit(T_948, 27) node T_1023 = bit(T_948, 26) node T_1025 = bit(T_948, 25) node T_1027 = bit(T_948, 24) node T_1029 = bit(T_948, 23) node T_1031 = bit(T_948, 22) node T_1033 = bit(T_948, 21) node T_1035 = bit(T_948, 20) node T_1037 = bit(T_948, 19) node T_1039 = bit(T_948, 18) node T_1041 = bit(T_948, 17) node T_1043 = bit(T_948, 16) node T_1045 = bit(T_948, 15) node T_1047 = bit(T_948, 14) node T_1049 = bit(T_948, 13) node T_1051 = bit(T_948, 12) node T_1053 = bit(T_948, 11) node T_1055 = bit(T_948, 10) node T_1057 = bit(T_948, 9) node T_1059 = bit(T_948, 8) node T_1061 = bit(T_948, 7) node T_1063 = bit(T_948, 6) node T_1065 = bit(T_948, 5) node T_1067 = bit(T_948, 4) node T_1069 = bit(T_948, 3) node T_1071 = bit(T_948, 2) node T_1073 = bit(T_948, 1) node T_1074 = shl(T_1073, 0) node T_1075 = mux(T_1071, UInt<2>("h02"), T_1074) node T_1076 = mux(T_1069, UInt<2>("h03"), T_1075) node T_1077 = mux(T_1067, UInt<3>("h04"), T_1076) node T_1078 = mux(T_1065, UInt<3>("h05"), T_1077) node T_1079 = mux(T_1063, UInt<3>("h06"), T_1078) node T_1080 = mux(T_1061, UInt<3>("h07"), T_1079) node T_1081 = mux(T_1059, UInt<4>("h08"), T_1080) node T_1082 = mux(T_1057, UInt<4>("h09"), T_1081) node T_1083 = mux(T_1055, UInt<4>("h0a"), T_1082) node T_1084 = mux(T_1053, UInt<4>("h0b"), T_1083) node T_1085 = mux(T_1051, UInt<4>("h0c"), T_1084) node T_1086 = mux(T_1049, UInt<4>("h0d"), T_1085) node T_1087 = mux(T_1047, UInt<4>("h0e"), T_1086) node T_1088 = mux(T_1045, UInt<4>("h0f"), T_1087) node T_1089 = mux(T_1043, UInt<5>("h010"), T_1088) node T_1090 = mux(T_1041, UInt<5>("h011"), T_1089) node T_1091 = mux(T_1039, UInt<5>("h012"), T_1090) node T_1092 = mux(T_1037, UInt<5>("h013"), T_1091) node T_1093 = mux(T_1035, UInt<5>("h014"), T_1092) node T_1094 = mux(T_1033, UInt<5>("h015"), T_1093) node T_1095 = mux(T_1031, UInt<5>("h016"), T_1094) node T_1096 = mux(T_1029, UInt<5>("h017"), T_1095) node T_1097 = mux(T_1027, UInt<5>("h018"), T_1096) node T_1098 = mux(T_1025, UInt<5>("h019"), T_1097) node T_1099 = mux(T_1023, UInt<5>("h01a"), T_1098) node T_1100 = mux(T_1021, UInt<5>("h01b"), T_1099) node T_1101 = mux(T_1019, UInt<5>("h01c"), T_1100) node T_1102 = mux(T_1017, UInt<5>("h01d"), T_1101) node T_1103 = mux(T_1015, UInt<5>("h01e"), T_1102) node T_1104 = mux(T_1013, UInt<5>("h01f"), T_1103) node T_1105 = mux(T_1011, UInt<6>("h020"), T_1104) node T_1106 = mux(T_1009, UInt<6>("h021"), T_1105) node T_1107 = mux(T_1007, UInt<6>("h022"), T_1106) node T_1108 = mux(T_1005, UInt<6>("h023"), T_1107) node T_1109 = mux(T_1003, UInt<6>("h024"), T_1108) node T_1110 = mux(T_1001, UInt<6>("h025"), T_1109) node T_1111 = mux(T_999, UInt<6>("h026"), T_1110) node T_1112 = mux(T_997, UInt<6>("h027"), T_1111) node T_1113 = mux(T_995, UInt<6>("h028"), T_1112) node T_1114 = mux(T_993, UInt<6>("h029"), T_1113) node T_1115 = mux(T_991, UInt<6>("h02a"), T_1114) node T_1116 = mux(T_989, UInt<6>("h02b"), T_1115) node T_1117 = mux(T_987, UInt<6>("h02c"), T_1116) node T_1118 = mux(T_985, UInt<6>("h02d"), T_1117) node T_1119 = mux(T_983, UInt<6>("h02e"), T_1118) node T_1120 = mux(T_981, UInt<6>("h02f"), T_1119) node T_1121 = mux(T_979, UInt<6>("h030"), T_1120) node T_1122 = mux(T_977, UInt<6>("h031"), T_1121) node T_1123 = mux(T_975, UInt<6>("h032"), T_1122) node T_1124 = mux(T_973, UInt<6>("h033"), T_1123) node T_1125 = mux(T_971, UInt<6>("h034"), T_1124) node T_1126 = mux(T_969, UInt<6>("h035"), T_1125) node T_1127 = mux(T_967, UInt<6>("h036"), T_1126) node T_1128 = mux(T_965, UInt<6>("h037"), T_1127) node T_1129 = mux(T_963, UInt<6>("h038"), T_1128) node T_1130 = mux(T_961, UInt<6>("h039"), T_1129) node T_1131 = mux(T_959, UInt<6>("h03a"), T_1130) node T_1132 = mux(T_957, UInt<6>("h03b"), T_1131) node T_1133 = mux(T_955, UInt<6>("h03c"), T_1132) node T_1134 = mux(T_953, UInt<6>("h03d"), T_1133) node T_1135 = mux(T_951, UInt<6>("h03e"), T_1134) node T_1136 = mux(T_949, UInt<6>("h03f"), T_1135) node T_1137 = not(T_1136) node T_1138 = dshl(T_948, T_1137) node T_1140 = bits(T_1138, 11, 10) node T_1141 = bits(T_1138, 9, 0) node T_1143 = neq(T_1141, UInt<1>("h00")) node T_1144 = cat(T_1140, T_1143) node T_1145 = bits(T_1144, 1, 0) node T_1147 = neq(T_1145, UInt<1>("h00")) node T_1148 = eq(in.bits.rm, UInt<2>("h00")) node T_1149 = bits(T_1144, 2, 1) node T_1150 = not(T_1149) node T_1152 = eq(T_1150, UInt<1>("h00")) node T_1153 = bits(T_1144, 1, 0) node T_1154 = not(T_1153) node T_1156 = eq(T_1154, UInt<1>("h00")) node T_1157 = or(T_1152, T_1156) node T_1158 = eq(in.bits.rm, UInt<2>("h02")) node T_1159 = and(T_940, T_1147) node T_1160 = eq(in.bits.rm, UInt<2>("h03")) node T_1162 = eq(T_940, UInt<1>("h00")) node T_1163 = and(T_1162, T_1147) node T_1165 = mux(T_1160, T_1163, UInt<1>("h00")) node T_1166 = mux(T_1158, T_1159, T_1165) node T_1167 = mux(T_1148, T_1157, T_1166) node T_1168 = bits(T_1138, 63, 11) node T_1170 = cat(UInt<1>("h00"), T_1168) node T_1172 = addw(T_1170, UInt<1>("h01")) node T_1173 = mux(T_1167, T_1172, T_1170) node T_1176 = not(T_1137) node T_1178 = cat(UInt<4>("h00"), T_1176) node T_1180 = cat(UInt<1>("h00"), T_1178) node T_1181 = bit(T_1173, 53) node T_1182 = addw(T_1180, T_1181) node T_1183 = bit(T_1138, 63) node T_1185 = bits(T_1182, 10, 0) node T_1186 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_1185) node T_1187 = cat(T_1183, T_1186) node T_1188 = or(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = or(T_1147, T_1188) node T_1190 = bits(T_1173, 51, 0) node T_1191 = cat(T_1187, T_1190) node T_1192 = cat(T_940, T_1191) node T_1195 = cat(UInt<2>("h00"), T_1188) node T_1196 = cat(UInt<1>("h00"), T_1189) node T_1197 = cat(T_1195, T_1196) mux.data := T_1192 mux.exc := T_1197 skip skip reg T_1200 : UInt<1>, clock, reset onreset T_1200 := UInt<1>("h00") T_1200 := in.valid reg T_1201 : {data : UInt<65>, exc : UInt<5>}, clock, reset when in.valid : T_1201 <> mux skip reg T_1206 : UInt<1>, clock, reset onreset T_1206 := UInt<1>("h00") T_1206 := T_1200 reg T_1207 : {data : UInt<65>, exc : UInt<5>}, clock, reset when T_1200 : T_1207 <> T_1201 skip wire T_1218 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_1218.bits.exc := UInt<1>("h00") T_1218.bits.data := UInt<1>("h00") T_1218.valid := UInt<1>("h00") T_1218.valid := T_1206 T_1218.bits <> T_1207 io.out <> T_1218 module FPToFP : input clock : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} io.out.bits.exc := UInt<1>("h00") io.out.bits.data := UInt<1>("h00") io.out.valid := UInt<1>("h00") reg T_137 : UInt<1>, clock, reset onreset T_137 := UInt<1>("h00") T_137 := io.in.valid reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset when io.in.valid : T_138 <> io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} in.bits.in3 := UInt<1>("h00") in.bits.in2 := UInt<1>("h00") in.bits.in1 := UInt<1>("h00") in.bits.typ := UInt<1>("h00") in.bits.rm := UInt<1>("h00") in.bits.wflags := UInt<1>("h00") in.bits.round := UInt<1>("h00") in.bits.sqrt := UInt<1>("h00") in.bits.div := UInt<1>("h00") in.bits.fma := UInt<1>("h00") in.bits.fastpipe := UInt<1>("h00") in.bits.toint := UInt<1>("h00") in.bits.fromint := UInt<1>("h00") in.bits.single := UInt<1>("h00") in.bits.swap23 := UInt<1>("h00") in.bits.swap12 := UInt<1>("h00") in.bits.ren3 := UInt<1>("h00") in.bits.ren2 := UInt<1>("h00") in.bits.ren1 := UInt<1>("h00") in.bits.wen := UInt<1>("h00") in.bits.ldst := UInt<1>("h00") in.bits.cmd := UInt<1>("h00") in.valid := UInt<1>("h00") in.valid := T_137 in.bits <> T_138 node T_282 = and(in.bits.cmd, UInt<3>("h05")) node isSgnj = eq(UInt<3>("h04"), T_282) node T_284 = and(in.bits.single, isSgnj) node T_285 = bit(in.bits.rm, 1) node T_287 = eq(T_284, UInt<1>("h00")) node T_288 = or(T_285, T_287) node T_289 = bit(in.bits.in1, 32) node T_290 = bit(in.bits.rm, 0) node T_291 = mux(T_288, T_289, T_290) node T_292 = bit(in.bits.in2, 32) node T_293 = and(T_284, T_292) node sign_s = xor(T_291, T_293) node T_296 = eq(in.bits.single, UInt<1>("h00")) node T_297 = and(T_296, isSgnj) node T_298 = bit(in.bits.rm, 1) node T_300 = eq(T_297, UInt<1>("h00")) node T_301 = or(T_298, T_300) node T_302 = bit(in.bits.in1, 64) node T_303 = bit(in.bits.rm, 0) node T_304 = mux(T_301, T_302, T_303) node T_305 = bit(in.bits.in2, 64) node T_306 = and(T_297, T_305) node sign_d = xor(T_304, T_306) node T_308 = bits(in.bits.in1, 63, 33) node T_309 = bits(in.bits.in1, 31, 0) node T_310 = cat(sign_d, T_308) node T_311 = cat(sign_s, T_309) node fsgnj = cat(T_310, T_311) node T_313 = bit(in.bits.in1, 32) node T_314 = bits(in.bits.in1, 22, 0) node T_315 = bits(in.bits.in1, 31, 23) node T_316 = bits(in.bits.in1, 31, 29) node T_317 = bits(in.bits.in1, 30, 23) node T_318 = not(T_316) node T_320 = eq(T_318, UInt<1>("h00")) node T_321 = bit(T_314, 22) node T_323 = eq(T_321, UInt<1>("h00")) node T_324 = and(T_320, T_323) node T_326 = lt(T_316, UInt<1>("h01")) node T_328 = lt(T_316, UInt<3>("h04")) node T_330 = cat(UInt<3>("h07"), T_317) node T_332 = lt(T_316, UInt<3>("h06")) node T_334 = cat(UInt<4>("h08"), T_317) node T_336 = lt(T_316, UInt<3>("h07")) node T_339 = mux(T_336, UInt<12>("h0c00"), UInt<12>("h0e00")) node T_340 = mux(T_332, T_334, T_339) node T_341 = mux(T_328, T_330, T_340) node T_342 = mux(T_326, T_317, T_341) node T_344 = subw(UInt<52>("h00"), T_320) node T_345 = shl(T_314, 29) node T_346 = or(T_344, T_345) node T_347 = cat(T_342, T_346) node T_348 = cat(T_313, T_347) node T_349 = shl(T_324, 4) node T_350 = bit(in.bits.in1, 64) node T_351 = bits(in.bits.in1, 51, 0) node T_352 = bits(in.bits.in1, 63, 52) node T_353 = bits(in.bits.in1, 63, 61) node T_354 = bits(in.bits.in1, 62, 52) node T_355 = not(T_353) node T_357 = eq(T_355, UInt<1>("h00")) node T_358 = bit(T_351, 51) node T_360 = eq(T_358, UInt<1>("h00")) node T_361 = and(T_357, T_360) node T_366 = neq(T_353, UInt<1>("h00")) node T_368 = eq(T_366, UInt<1>("h00")) node T_369 = bits(T_353, 2, 1) node T_370 = not(T_369) node T_372 = eq(T_370, UInt<1>("h00")) node T_373 = or(T_368, T_372) node T_374 = geq(T_352, UInt<11>("h076a")) node T_375 = leq(T_352, UInt<11>("h0781")) node T_376 = and(T_374, T_375) node T_377 = lt(T_352, UInt<11>("h076a")) node T_379 = eq(T_373, UInt<1>("h00")) node T_380 = and(T_377, T_379) node T_381 = gt(T_352, UInt<12>("h087f")) node T_383 = eq(T_373, UInt<1>("h00")) node T_384 = and(T_381, T_383) node T_386 = addw(UInt<11>("h0781"), UInt<1>("h01")) node T_387 = subw(T_386, T_352) node T_389 = mux(T_376, T_387, UInt<1>("h00")) node T_390 = bits(T_389, 4, 0) node T_392 = bits(T_351, 51, 28) node T_394 = cat(T_392, UInt<24>("h00")) node T_395 = cat(UInt<1>("h01"), T_394) node T_396 = dshr(T_395, T_390) node T_397 = bits(T_396, 23, 0) node T_399 = neq(T_397, UInt<1>("h00")) node T_400 = bits(T_351, 27, 0) node T_402 = neq(T_400, UInt<1>("h00")) node T_403 = or(T_399, T_402) node T_404 = bits(T_396, 25, 24) node T_405 = cat(T_404, T_403) node T_406 = bits(T_405, 1, 0) node T_408 = neq(T_406, UInt<1>("h00")) node T_410 = eq(T_373, UInt<1>("h00")) node T_411 = and(T_408, T_410) node T_412 = eq(in.bits.rm, UInt<2>("h00")) node T_413 = bits(T_405, 1, 0) node T_414 = not(T_413) node T_416 = eq(T_414, UInt<1>("h00")) node T_417 = bits(T_405, 2, 1) node T_418 = not(T_417) node T_420 = eq(T_418, UInt<1>("h00")) node T_421 = or(T_416, T_420) node T_422 = eq(in.bits.rm, UInt<2>("h02")) node T_423 = and(T_350, T_411) node T_424 = eq(in.bits.rm, UInt<2>("h03")) node T_426 = eq(T_350, UInt<1>("h00")) node T_427 = and(T_426, T_411) node T_429 = mux(T_424, T_427, UInt<1>("h00")) node T_430 = mux(T_422, T_423, T_429) node T_431 = mux(T_412, T_421, T_430) node T_433 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_434 = cat(T_433, T_433) node T_435 = cat(T_434, T_434) node T_436 = cat(T_435, T_435) node T_437 = cat(T_435, T_436) node T_438 = cat(UInt<1>("h01"), T_437) node T_439 = dshl(T_438, T_390) node T_440 = bits(T_439, 24, 0) node T_442 = bits(T_351, 51, 29) node T_443 = cat(UInt<2>("h01"), T_442) node T_444 = not(T_440) node T_445 = or(T_443, T_444) node T_447 = addw(T_445, UInt<1>("h01")) node T_448 = mux(T_431, T_447, T_445) node T_449 = and(T_448, T_440) node T_450 = bits(T_352, 8, 0) node T_452 = addw(T_450, UInt<9>("h0100")) node T_453 = bit(T_449, 24) node T_455 = addw(T_452, UInt<1>("h01")) node T_456 = mux(T_453, T_455, T_452) node T_457 = eq(in.bits.rm, UInt<2>("h02")) node T_458 = and(T_457, T_350) node T_459 = eq(in.bits.rm, UInt<2>("h03")) node T_461 = eq(T_350, UInt<1>("h00")) node T_462 = and(T_459, T_461) node T_463 = or(T_458, T_462) node T_464 = eq(in.bits.rm, UInt<2>("h00")) node T_465 = or(T_463, T_464) node T_467 = eq(T_465, UInt<1>("h00")) node T_469 = subw(UInt<23>("h00"), T_467) node T_472 = mux(T_465, UInt<9>("h0180"), UInt<9>("h017f")) node T_476 = mux(T_463, UInt<7>("h06b"), UInt<1>("h00")) node T_477 = shl(T_353, 6) node T_478 = mux(T_380, T_476, T_456) node T_479 = mux(T_384, T_472, T_478) node T_480 = mux(T_373, T_477, T_479) node T_482 = subw(UInt<23>("h00"), T_357) node T_483 = bits(T_449, 22, 0) node T_484 = mux(T_380, UInt<1>("h00"), T_483) node T_485 = mux(T_384, T_469, T_484) node T_486 = mux(T_373, T_482, T_485) node T_487 = cat(T_480, T_486) node T_488 = cat(T_350, T_487) node T_489 = and(T_376, T_411) node T_490 = or(T_380, T_489) node T_491 = eq(T_352, UInt<12>("h087f")) node T_492 = bit(T_449, 24) node T_493 = and(T_491, T_492) node T_494 = or(T_384, T_493) node T_496 = or(T_411, T_384) node T_497 = or(T_496, T_380) node T_498 = cat(T_361, UInt<1>("h00")) node T_499 = cat(T_490, T_497) node T_500 = cat(T_494, T_499) node T_501 = cat(T_498, T_500) node T_502 = bits(in.bits.in1, 31, 29) node T_503 = not(T_502) node T_505 = eq(T_503, UInt<1>("h00")) node T_506 = bits(in.bits.in1, 63, 61) node T_507 = not(T_506) node T_509 = eq(T_507, UInt<1>("h00")) node isnan1 = mux(in.bits.single, T_505, T_509) node T_511 = bits(in.bits.in2, 31, 29) node T_512 = not(T_511) node T_514 = eq(T_512, UInt<1>("h00")) node T_515 = bits(in.bits.in2, 63, 61) node T_516 = not(T_515) node T_518 = eq(T_516, UInt<1>("h00")) node isnan2 = mux(in.bits.single, T_514, T_518) node T_520 = bit(in.bits.in1, 22) node T_521 = bit(in.bits.in1, 51) node T_522 = mux(in.bits.single, T_520, T_521) node T_523 = not(T_522) node issnan1 = and(isnan1, T_523) node T_525 = bit(in.bits.in2, 22) node T_526 = bit(in.bits.in2, 51) node T_527 = mux(in.bits.single, T_525, T_526) node T_528 = not(T_527) node issnan2 = and(isnan2, T_528) node T_530 = or(issnan1, issnan2) node minmax_exc = cat(T_530, UInt<4>("h00")) node isMax = bit(in.bits.rm, 0) node T_534 = neq(isMax, io.lt) node T_536 = eq(isnan1, UInt<1>("h00")) node T_537 = and(T_534, T_536) node isLHS = or(isnan2, T_537) wire mux : {data : UInt<65>, exc : UInt<5>} mux.exc := UInt<1>("h00") mux.data := UInt<1>("h00") mux.exc := minmax_exc mux.data := in.bits.in2 when isSgnj : mux.exc := UInt<1>("h00") skip node T_548 = or(isSgnj, isLHS) when T_548 : mux.data := fsgnj skip node T_551 = and(in.bits.cmd, UInt<3>("h04")) node T_552 = eq(UInt<1>("h00"), T_551) when T_552 : when in.bits.single : node T_554 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_555 = cat(T_554, T_488) mux.data := T_555 mux.exc := T_501 skip else : mux.data := T_348 mux.exc := T_349 skip skip reg T_558 : UInt<1>, clock, reset onreset T_558 := UInt<1>("h00") T_558 := in.valid reg T_559 : {data : UInt<65>, exc : UInt<5>}, clock, reset when in.valid : T_559 <> mux skip wire T_570 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_570.bits.exc := UInt<1>("h00") T_570.bits.data := UInt<1>("h00") T_570.valid := UInt<1>("h00") T_570.valid := T_558 T_570.bits <> T_559 io.out <> T_570 module divSqrtRecodedFloat64_mulAddZ31 : input clock : Clock input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} io.mulAddC_2 := UInt<1>("h00") io.mulAddB_0 := UInt<1>("h00") io.latchMulAddB_0 := UInt<1>("h00") io.mulAddA_0 := UInt<1>("h00") io.latchMulAddA_0 := UInt<1>("h00") io.usingMulAdd := UInt<1>("h00") io.exceptionFlags := UInt<1>("h00") io.out := UInt<1>("h00") io.outValid_sqrt := UInt<1>("h00") io.outValid_div := UInt<1>("h00") io.inReady_sqrt := UInt<1>("h00") io.inReady_div := UInt<1>("h00") reg valid_PA : UInt<1>, clock, reset onreset valid_PA := UInt<1>("h00") reg sqrtOp_PA : UInt<1>, clock, reset reg sign_PA : UInt<1>, clock, reset reg specialCodeB_PA : UInt<3>, clock, reset reg fractB_51_PA : UInt<1>, clock, reset reg roundingMode_PA : UInt<2>, clock, reset reg specialCodeA_PA : UInt<3>, clock, reset reg fractA_51_PA : UInt<1>, clock, reset reg exp_PA : UInt<14>, clock, reset reg fractB_other_PA : UInt<51>, clock, reset reg fractA_other_PA : UInt<51>, clock, reset reg valid_PB : UInt<1>, clock, reset onreset valid_PB := UInt<1>("h00") reg sqrtOp_PB : UInt<1>, clock, reset reg sign_PB : UInt<1>, clock, reset reg specialCodeA_PB : UInt<3>, clock, reset reg fractA_51_PB : UInt<1>, clock, reset reg specialCodeB_PB : UInt<3>, clock, reset reg fractB_51_PB : UInt<1>, clock, reset reg roundingMode_PB : UInt<2>, clock, reset reg exp_PB : UInt<14>, clock, reset reg fractA_0_PB : UInt<1>, clock, reset reg fractB_other_PB : UInt<51>, clock, reset reg valid_PC : UInt<1>, clock, reset onreset valid_PC := UInt<1>("h00") reg sqrtOp_PC : UInt<1>, clock, reset reg sign_PC : UInt<1>, clock, reset reg specialCodeA_PC : UInt<3>, clock, reset reg fractA_51_PC : UInt<1>, clock, reset reg specialCodeB_PC : UInt<3>, clock, reset reg fractB_51_PC : UInt<1>, clock, reset reg roundingMode_PC : UInt<2>, clock, reset reg exp_PC : UInt<14>, clock, reset reg fractA_0_PC : UInt<1>, clock, reset reg fractB_other_PC : UInt<51>, clock, reset reg cycleNum_A : UInt<3>, clock, reset onreset cycleNum_A := UInt<3>("h00") reg cycleNum_B : UInt<4>, clock, reset onreset cycleNum_B := UInt<4>("h00") reg cycleNum_C : UInt<3>, clock, reset onreset cycleNum_C := UInt<3>("h00") reg cycleNum_E : UInt<3>, clock, reset onreset cycleNum_E := UInt<3>("h00") reg fractR0_A : UInt<9>, clock, reset reg hiSqrR0_A_sqrt : UInt<10>, clock, reset reg partNegSigma0_A : UInt<21>, clock, reset reg nextMulAdd9A_A : UInt<9>, clock, reset reg nextMulAdd9B_A : UInt<9>, clock, reset reg ER1_B_sqrt : UInt<17>, clock, reset reg ESqrR1_B_sqrt : UInt<32>, clock, reset reg sigX1_B : UInt<58>, clock, reset reg sqrSigma1_C : UInt<33>, clock, reset reg sigXN_C : UInt<58>, clock, reset reg u_C_sqrt : UInt<31>, clock, reset reg E_E_div : UInt<1>, clock, reset reg sigT_E : UInt<53>, clock, reset reg extraT_E : UInt<1>, clock, reset reg isNegRemT_E : UInt<1>, clock, reset reg trueEqX_E1 : UInt<1>, clock, reset wire ready_PA : UInt<1> ready_PA := UInt<1>("h00") wire ready_PB : UInt<1> ready_PB := UInt<1>("h00") wire ready_PC : UInt<1> ready_PC := UInt<1>("h00") wire leaving_PA : UInt<1> leaving_PA := UInt<1>("h00") wire leaving_PB : UInt<1> leaving_PB := UInt<1>("h00") wire leaving_PC : UInt<1> leaving_PC := UInt<1>("h00") wire cyc_B10_sqrt : UInt<1> cyc_B10_sqrt := UInt<1>("h00") wire cyc_B9_sqrt : UInt<1> cyc_B9_sqrt := UInt<1>("h00") wire cyc_B8_sqrt : UInt<1> cyc_B8_sqrt := UInt<1>("h00") wire cyc_B7_sqrt : UInt<1> cyc_B7_sqrt := UInt<1>("h00") wire cyc_B6 : UInt<1> cyc_B6 := UInt<1>("h00") wire cyc_B5 : UInt<1> cyc_B5 := UInt<1>("h00") wire cyc_B4 : UInt<1> cyc_B4 := UInt<1>("h00") wire cyc_B3 : UInt<1> cyc_B3 := UInt<1>("h00") wire cyc_B2 : UInt<1> cyc_B2 := UInt<1>("h00") wire cyc_B1 : UInt<1> cyc_B1 := UInt<1>("h00") wire cyc_B6_div : UInt<1> cyc_B6_div := UInt<1>("h00") wire cyc_B5_div : UInt<1> cyc_B5_div := UInt<1>("h00") wire cyc_B4_div : UInt<1> cyc_B4_div := UInt<1>("h00") wire cyc_B3_div : UInt<1> cyc_B3_div := UInt<1>("h00") wire cyc_B2_div : UInt<1> cyc_B2_div := UInt<1>("h00") wire cyc_B1_div : UInt<1> cyc_B1_div := UInt<1>("h00") wire cyc_B6_sqrt : UInt<1> cyc_B6_sqrt := UInt<1>("h00") wire cyc_B5_sqrt : UInt<1> cyc_B5_sqrt := UInt<1>("h00") wire cyc_B4_sqrt : UInt<1> cyc_B4_sqrt := UInt<1>("h00") wire cyc_B3_sqrt : UInt<1> cyc_B3_sqrt := UInt<1>("h00") wire cyc_B2_sqrt : UInt<1> cyc_B2_sqrt := UInt<1>("h00") wire cyc_B1_sqrt : UInt<1> cyc_B1_sqrt := UInt<1>("h00") wire cyc_C5 : UInt<1> cyc_C5 := UInt<1>("h00") wire cyc_C4 : UInt<1> cyc_C4 := UInt<1>("h00") wire valid_normalCase_leaving_PB : UInt<1> valid_normalCase_leaving_PB := UInt<1>("h00") wire cyc_C2 : UInt<1> cyc_C2 := UInt<1>("h00") wire cyc_C1 : UInt<1> cyc_C1 := UInt<1>("h00") wire cyc_E4 : UInt<1> cyc_E4 := UInt<1>("h00") wire cyc_E3 : UInt<1> cyc_E3 := UInt<1>("h00") wire cyc_E2 : UInt<1> cyc_E2 := UInt<1>("h00") wire cyc_E1 : UInt<1> cyc_E1 := UInt<1>("h00") wire zSigma1_B4 : UInt zSigma1_B4 := UInt<1>("h00") wire sigXNU_B3_CX : UInt sigXNU_B3_CX := UInt<1>("h00") wire zComplSigT_C1_sqrt : UInt zComplSigT_C1_sqrt := UInt<1>("h00") wire zComplSigT_C1 : UInt zComplSigT_C1 := UInt<1>("h00") node T_251 = not(cyc_B6_sqrt) node T_252 = and(ready_PA, T_251) node T_253 = not(cyc_B5_sqrt) node T_254 = and(T_252, T_253) node T_255 = not(cyc_B4_sqrt) node T_256 = and(T_254, T_255) node T_257 = not(cyc_B3) node T_258 = and(T_256, T_257) node T_259 = not(cyc_B2) node T_260 = and(T_258, T_259) node T_261 = not(cyc_B1_sqrt) node T_262 = and(T_260, T_261) node T_263 = not(cyc_C5) node T_264 = and(T_262, T_263) node T_265 = not(cyc_C4) node T_266 = and(T_264, T_265) io.inReady_div := T_266 node T_267 = not(cyc_B6_sqrt) node T_268 = and(ready_PA, T_267) node T_269 = not(cyc_B5_sqrt) node T_270 = and(T_268, T_269) node T_271 = not(cyc_B4_sqrt) node T_272 = and(T_270, T_271) node T_273 = not(cyc_B2_div) node T_274 = and(T_272, T_273) node T_275 = not(cyc_B1_sqrt) node T_276 = and(T_274, T_275) io.inReady_sqrt := T_276 node T_277 = and(io.inReady_div, io.inValid) node T_278 = not(io.sqrtOp) node cyc_S_div = and(T_277, T_278) node T_280 = and(io.inReady_sqrt, io.inValid) node cyc_S_sqrt = and(T_280, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) node signA_S = bit(io.a, 64) node expA_S = bits(io.a, 63, 52) node fractA_S = bits(io.a, 51, 0) node specialCodeA_S = bits(expA_S, 11, 9) node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) node T_289 = bits(specialCodeA_S, 2, 1) node isSpecialA_S = eq(T_289, UInt<2>("h03")) node signB_S = bit(io.b, 64) node expB_S = bits(io.b, 63, 52) node fractB_S = bits(io.b, 51, 0) node specialCodeB_S = bits(expB_S, 11, 9) node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) node T_298 = bits(specialCodeB_S, 2, 1) node isSpecialB_S = eq(T_298, UInt<2>("h03")) node T_301 = xor(signA_S, signB_S) node sign_S = mux(io.sqrtOp, signB_S, T_301) node T_303 = not(isSpecialA_S) node T_304 = not(isSpecialB_S) node T_305 = and(T_303, T_304) node T_306 = not(isZeroA_S) node T_307 = and(T_305, T_306) node T_308 = not(isZeroB_S) node normalCase_S_div = and(T_307, T_308) node T_310 = not(isSpecialB_S) node T_311 = not(isZeroB_S) node T_312 = and(T_310, T_311) node T_313 = not(signB_S) node normalCase_S_sqrt = and(T_312, T_313) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) node T_319 = not(ready_PB) node T_320 = or(valid_PA, T_319) node T_321 = and(cyc_S, T_320) node entering_PA = or(entering_PA_normalCase, T_321) node T_323 = not(normalCase_S) node T_324 = and(cyc_S, T_323) node T_325 = not(valid_PA) node T_326 = and(T_324, T_325) node T_327 = not(valid_PB) node T_328 = not(ready_PC) node T_329 = and(T_327, T_328) node T_330 = or(leaving_PB, T_329) node entering_PB_S = and(T_326, T_330) node T_332 = not(normalCase_S) node T_333 = and(cyc_S, T_332) node T_334 = not(valid_PA) node T_335 = and(T_333, T_334) node T_336 = not(valid_PB) node T_337 = and(T_335, T_336) node entering_PC_S = and(T_337, ready_PC) node T_339 = or(entering_PA, leaving_PA) when T_339 : valid_PA := entering_PA skip when entering_PA : sqrtOp_PA := io.sqrtOp sign_PA := sign_S specialCodeB_PA := specialCodeB_S node T_340 = bit(fractB_S, 51) fractB_51_PA := T_340 roundingMode_PA := io.roundingMode skip node T_341 = not(io.sqrtOp) node T_342 = and(entering_PA, T_341) when T_342 : specialCodeA_PA := specialCodeA_S node T_343 = bit(fractA_S, 51) fractA_51_PA := T_343 skip when entering_PA_normalCase : node T_344 = bit(expB_S, 11) node T_346 = subw(UInt<3>("h00"), T_344) node T_347 = bits(expB_S, 10, 0) node T_348 = not(T_347) node T_349 = cat(T_346, T_348) node T_350 = addw(expA_S, T_349) node T_351 = mux(io.sqrtOp, expB_S, T_350) exp_PA := T_351 node T_352 = bits(fractB_S, 50, 0) fractB_other_PA := T_352 skip when entering_PA_normalCase_div : node T_353 = bits(fractA_S, 50, 0) fractA_other_PA := T_353 skip node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) node T_356 = bits(specialCodeA_PA, 2, 1) node isSpecialA_PA = eq(T_356, UInt<2>("h03")) node T_360 = cat(fractA_51_PA, fractA_other_PA) node sigA_PA = cat(UInt<1>("h01"), T_360) node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) node T_364 = bits(specialCodeB_PA, 2, 1) node isSpecialB_PA = eq(T_364, UInt<2>("h03")) node T_368 = cat(fractB_51_PA, fractB_other_PA) node sigB_PA = cat(UInt<1>("h01"), T_368) node T_370 = not(isSpecialB_PA) node T_371 = not(isZeroB_PA) node T_372 = and(T_370, T_371) node T_373 = not(sign_PA) node T_374 = and(T_372, T_373) node T_375 = not(isSpecialA_PA) node T_376 = not(isSpecialB_PA) node T_377 = and(T_375, T_376) node T_378 = not(isZeroA_PA) node T_379 = and(T_377, T_378) node T_380 = not(isZeroB_PA) node T_381 = and(T_379, T_380) node normalCase_PA = mux(sqrtOp_PA, T_374, T_381) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) node T_385 = and(valid_PA, valid_leaving_PA) leaving_PA := T_385 node T_386 = not(valid_PA) node T_387 = or(T_386, valid_leaving_PA) ready_PA := T_387 node T_388 = and(valid_PA, normalCase_PA) node entering_PB_normalCase = and(T_388, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) node T_391 = or(entering_PB, leaving_PB) when T_391 : valid_PB := entering_PB skip when entering_PB : node T_392 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) sqrtOp_PB := T_392 node T_393 = mux(valid_PA, sign_PA, sign_S) sign_PB := T_393 node T_394 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) specialCodeA_PB := T_394 node T_395 = bit(fractA_S, 51) node T_396 = mux(valid_PA, fractA_51_PA, T_395) fractA_51_PB := T_396 node T_397 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) specialCodeB_PB := T_397 node T_398 = bit(fractB_S, 51) node T_399 = mux(valid_PA, fractB_51_PA, T_398) fractB_51_PB := T_399 node T_400 = mux(valid_PA, roundingMode_PA, io.roundingMode) roundingMode_PB := T_400 skip when entering_PB_normalCase : exp_PB := exp_PA node T_401 = bit(fractA_other_PA, 0) fractA_0_PB := T_401 fractB_other_PB := fractB_other_PA skip node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) node T_404 = bits(specialCodeA_PB, 2, 1) node isSpecialA_PB = eq(T_404, UInt<2>("h03")) node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) node T_409 = bits(specialCodeB_PB, 2, 1) node isSpecialB_PB = eq(T_409, UInt<2>("h03")) node T_412 = not(isSpecialB_PB) node T_413 = not(isZeroB_PB) node T_414 = and(T_412, T_413) node T_415 = not(sign_PB) node T_416 = and(T_414, T_415) node T_417 = not(isSpecialA_PB) node T_418 = not(isSpecialB_PB) node T_419 = and(T_417, T_418) node T_420 = not(isZeroA_PB) node T_421 = and(T_419, T_420) node T_422 = not(isZeroB_PB) node T_423 = and(T_421, T_422) node normalCase_PB = mux(sqrtOp_PB, T_416, T_423) node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) node T_426 = and(valid_PB, valid_leaving_PB) leaving_PB := T_426 node T_427 = not(valid_PB) node T_428 = or(T_427, valid_leaving_PB) ready_PB := T_428 node T_429 = and(valid_PB, normalCase_PB) node entering_PC_normalCase = and(T_429, valid_normalCase_leaving_PB) node entering_PC = or(entering_PC_S, leaving_PB) node T_432 = or(entering_PC, leaving_PC) when T_432 : valid_PC := entering_PC skip when entering_PC : node T_433 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) sqrtOp_PC := T_433 node T_434 = mux(valid_PB, sign_PB, sign_S) sign_PC := T_434 node T_435 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) specialCodeA_PC := T_435 node T_436 = bit(fractA_S, 51) node T_437 = mux(valid_PB, fractA_51_PB, T_436) fractA_51_PC := T_437 node T_438 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) specialCodeB_PC := T_438 node T_439 = bit(fractB_S, 51) node T_440 = mux(valid_PB, fractB_51_PB, T_439) fractB_51_PC := T_440 node T_441 = mux(valid_PB, roundingMode_PB, io.roundingMode) roundingMode_PC := T_441 skip when entering_PC_normalCase : exp_PC := exp_PB fractA_0_PC := fractA_0_PB fractB_other_PC := fractB_other_PB skip node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) node T_444 = bits(specialCodeA_PC, 2, 1) node isSpecialA_PC = eq(T_444, UInt<2>("h03")) node T_447 = bit(specialCodeA_PC, 0) node T_448 = not(T_447) node isInfA_PC = and(isSpecialA_PC, T_448) node T_450 = bit(specialCodeA_PC, 0) node isNaNA_PC = and(isSpecialA_PC, T_450) node T_452 = not(fractA_51_PC) node isSigNaNA_PC = and(isNaNA_PC, T_452) node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) node T_456 = bits(specialCodeB_PC, 2, 1) node isSpecialB_PC = eq(T_456, UInt<2>("h03")) node T_459 = bit(specialCodeB_PC, 0) node T_460 = not(T_459) node isInfB_PC = and(isSpecialB_PC, T_460) node T_462 = bit(specialCodeB_PC, 0) node isNaNB_PC = and(isSpecialB_PC, T_462) node T_464 = not(fractB_51_PC) node isSigNaNB_PC = and(isNaNB_PC, T_464) node T_467 = cat(fractB_51_PC, fractB_other_PC) node sigB_PC = cat(UInt<1>("h01"), T_467) node T_469 = not(isSpecialB_PC) node T_470 = not(isZeroB_PC) node T_471 = and(T_469, T_470) node T_472 = not(sign_PC) node T_473 = and(T_471, T_472) node T_474 = not(isSpecialA_PC) node T_475 = not(isSpecialB_PC) node T_476 = and(T_474, T_475) node T_477 = not(isZeroA_PC) node T_478 = and(T_476, T_477) node T_479 = not(isZeroB_PC) node T_480 = and(T_478, T_479) node normalCase_PC = mux(sqrtOp_PC, T_473, T_480) node expP2_PC = addw(exp_PC, UInt<2>("h02")) node T_484 = bit(exp_PC, 0) node T_485 = bits(expP2_PC, 13, 1) node T_487 = cat(T_485, UInt<1>("h00")) node T_488 = bits(exp_PC, 13, 1) node T_490 = cat(T_488, UInt<1>("h01")) node expP1_PC = mux(T_484, T_487, T_490) node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) node T_498 = not(roundMagUp_PC) node T_499 = not(roundingMode_near_even_PC) node roundMagDown_PC = and(T_498, T_499) node T_501 = not(normalCase_PC) node valid_leaving_PC = or(T_501, cyc_E1) node T_503 = and(valid_PC, valid_leaving_PC) leaving_PC := T_503 node T_504 = not(valid_PC) node T_505 = or(T_504, valid_leaving_PC) ready_PC := T_505 node T_506 = not(sqrtOp_PC) node T_507 = and(leaving_PC, T_506) io.outValid_div := T_507 node T_508 = and(leaving_PC, sqrtOp_PC) io.outValid_sqrt := T_508 node T_510 = neq(cycleNum_A, UInt<1>("h00")) node T_511 = or(entering_PA_normalCase, T_510) when T_511 : node T_514 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) node T_517 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) node T_518 = or(T_514, T_517) node T_519 = not(entering_PA_normalCase) node T_521 = subw(cycleNum_A, UInt<1>("h01")) node T_523 = mux(T_519, T_521, UInt<1>("h00")) node T_524 = or(T_518, T_523) cycleNum_A := T_524 skip node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) node T_538 = not(sqrtOp_PA) node cyc_A3_div = and(cyc_A3, T_538) node T_540 = not(sqrtOp_PA) node cyc_A2_div = and(cyc_A2, T_540) node T_542 = not(sqrtOp_PA) node cyc_A1_div = and(cyc_A1, T_542) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) node T_548 = neq(cycleNum_B, UInt<1>("h00")) node T_549 = or(cyc_A1, T_548) when T_549 : node T_552 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) node T_554 = subw(cycleNum_B, UInt<1>("h01")) node T_555 = mux(cyc_A1, T_552, T_554) cycleNum_B := T_555 skip node T_557 = eq(cycleNum_B, UInt<4>("h0a")) cyc_B10_sqrt := T_557 node T_559 = eq(cycleNum_B, UInt<4>("h09")) cyc_B9_sqrt := T_559 node T_561 = eq(cycleNum_B, UInt<4>("h08")) cyc_B8_sqrt := T_561 node T_563 = eq(cycleNum_B, UInt<3>("h07")) cyc_B7_sqrt := T_563 node T_565 = eq(cycleNum_B, UInt<3>("h06")) cyc_B6 := T_565 node T_567 = eq(cycleNum_B, UInt<3>("h05")) cyc_B5 := T_567 node T_569 = eq(cycleNum_B, UInt<3>("h04")) cyc_B4 := T_569 node T_571 = eq(cycleNum_B, UInt<2>("h03")) cyc_B3 := T_571 node T_573 = eq(cycleNum_B, UInt<2>("h02")) cyc_B2 := T_573 node T_575 = eq(cycleNum_B, UInt<1>("h01")) cyc_B1 := T_575 node T_576 = and(cyc_B6, valid_PA) node T_577 = not(sqrtOp_PA) node T_578 = and(T_576, T_577) cyc_B6_div := T_578 node T_579 = and(cyc_B5, valid_PA) node T_580 = not(sqrtOp_PA) node T_581 = and(T_579, T_580) cyc_B5_div := T_581 node T_582 = and(cyc_B4, valid_PA) node T_583 = not(sqrtOp_PA) node T_584 = and(T_582, T_583) cyc_B4_div := T_584 node T_585 = not(sqrtOp_PB) node T_586 = and(cyc_B3, T_585) cyc_B3_div := T_586 node T_587 = not(sqrtOp_PB) node T_588 = and(cyc_B2, T_587) cyc_B2_div := T_588 node T_589 = not(sqrtOp_PB) node T_590 = and(cyc_B1, T_589) cyc_B1_div := T_590 node T_591 = and(cyc_B6, valid_PB) node T_592 = and(T_591, sqrtOp_PB) cyc_B6_sqrt := T_592 node T_593 = and(cyc_B5, valid_PB) node T_594 = and(T_593, sqrtOp_PB) cyc_B5_sqrt := T_594 node T_595 = and(cyc_B4, valid_PB) node T_596 = and(T_595, sqrtOp_PB) cyc_B4_sqrt := T_596 node T_597 = and(cyc_B3, sqrtOp_PB) cyc_B3_sqrt := T_597 node T_598 = and(cyc_B2, sqrtOp_PB) cyc_B2_sqrt := T_598 node T_599 = and(cyc_B1, sqrtOp_PB) cyc_B1_sqrt := T_599 node T_601 = neq(cycleNum_C, UInt<1>("h00")) node T_602 = or(cyc_B1, T_601) when T_602 : node T_605 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) node T_607 = subw(cycleNum_C, UInt<1>("h01")) node T_608 = mux(cyc_B1, T_605, T_607) cycleNum_C := T_608 skip node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) node T_612 = eq(cycleNum_C, UInt<3>("h05")) cyc_C5 := T_612 node T_614 = eq(cycleNum_C, UInt<3>("h04")) cyc_C4 := T_614 node T_616 = eq(cycleNum_C, UInt<2>("h03")) valid_normalCase_leaving_PB := T_616 node T_618 = eq(cycleNum_C, UInt<2>("h02")) cyc_C2 := T_618 node T_620 = eq(cycleNum_C, UInt<1>("h01")) cyc_C1 := T_620 node T_621 = not(sqrtOp_PB) node cyc_C5_div = and(cyc_C5, T_621) node T_623 = not(sqrtOp_PB) node cyc_C4_div = and(cyc_C4, T_623) node T_625 = not(sqrtOp_PB) node cyc_C3_div = and(valid_normalCase_leaving_PB, T_625) node T_627 = not(sqrtOp_PC) node cyc_C2_div = and(cyc_C2, T_627) node T_629 = not(sqrtOp_PC) node cyc_C1_div = and(cyc_C1, T_629) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) node T_637 = neq(cycleNum_E, UInt<1>("h00")) node T_638 = or(cyc_C1, T_637) when T_638 : node T_641 = subw(cycleNum_E, UInt<1>("h01")) node T_642 = mux(cyc_C1, UInt<3>("h04"), T_641) cycleNum_E := T_642 skip node T_644 = eq(cycleNum_E, UInt<3>("h04")) cyc_E4 := T_644 node T_646 = eq(cycleNum_E, UInt<2>("h03")) cyc_E3 := T_646 node T_648 = eq(cycleNum_E, UInt<2>("h02")) cyc_E2 := T_648 node T_650 = eq(cycleNum_E, UInt<1>("h01")) cyc_E1 := T_650 node T_651 = not(sqrtOp_PC) node cyc_E4_div = and(cyc_E4, T_651) node T_653 = not(sqrtOp_PC) node cyc_E3_div = and(cyc_E3, T_653) node T_655 = not(sqrtOp_PC) node cyc_E2_div = and(cyc_E2, T_655) node T_657 = not(sqrtOp_PC) node cyc_E1_div = and(cyc_E1, T_657) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) node T_665 = bits(fractB_S, 51, 49) node T_667 = eq(T_665, UInt<1>("h00")) node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_667) node T_669 = bits(fractB_S, 51, 49) node T_671 = eq(T_669, UInt<1>("h01")) node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_671) node T_673 = bits(fractB_S, 51, 49) node T_675 = eq(T_673, UInt<2>("h02")) node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_675) node T_677 = bits(fractB_S, 51, 49) node T_679 = eq(T_677, UInt<2>("h03")) node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_679) node T_681 = bits(fractB_S, 51, 49) node T_683 = eq(T_681, UInt<3>("h04")) node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_683) node T_685 = bits(fractB_S, 51, 49) node T_687 = eq(T_685, UInt<3>("h05")) node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_687) node T_689 = bits(fractB_S, 51, 49) node T_691 = eq(T_689, UInt<3>("h06")) node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_691) node T_693 = bits(fractB_S, 51, 49) node T_695 = eq(T_693, UInt<3>("h07")) node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_695) node T_699 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) node T_702 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) node T_703 = or(T_699, T_702) node T_706 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) node T_707 = or(T_703, T_706) node T_710 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) node T_711 = or(T_707, T_710) node T_714 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) node T_715 = or(T_711, T_714) node T_718 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) node T_719 = or(T_715, T_718) node T_722 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) node T_723 = or(T_719, T_722) node T_726 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) node zK1_A4_div = or(T_723, T_726) node T_729 = not(UInt<12>("h0fe3")) node T_731 = mux(zLinPiece_0_A4_div, T_729, UInt<1>("h00")) node T_733 = not(UInt<12>("h0c5d")) node T_735 = mux(zLinPiece_1_A4_div, T_733, UInt<1>("h00")) node T_736 = or(T_731, T_735) node T_738 = not(UInt<12>("h098a")) node T_740 = mux(zLinPiece_2_A4_div, T_738, UInt<1>("h00")) node T_741 = or(T_736, T_740) node T_743 = not(UInt<12>("h0739")) node T_745 = mux(zLinPiece_3_A4_div, T_743, UInt<1>("h00")) node T_746 = or(T_741, T_745) node T_748 = not(UInt<12>("h054b")) node T_750 = mux(zLinPiece_4_A4_div, T_748, UInt<1>("h00")) node T_751 = or(T_746, T_750) node T_753 = not(UInt<12>("h03a9")) node T_755 = mux(zLinPiece_5_A4_div, T_753, UInt<1>("h00")) node T_756 = or(T_751, T_755) node T_758 = not(UInt<12>("h0242")) node T_760 = mux(zLinPiece_6_A4_div, T_758, UInt<1>("h00")) node T_761 = or(T_756, T_760) node T_763 = not(UInt<12>("h010b")) node T_765 = mux(zLinPiece_7_A4_div, T_763, UInt<1>("h00")) node zComplFractK0_A4_div = or(T_761, T_765) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) node T_769 = bit(expB_S, 0) node T_770 = not(T_769) node T_771 = and(entering_PA_normalCase_sqrt, T_770) node T_772 = bit(fractB_S, 51) node T_773 = not(T_772) node zQuadPiece_0_A7_sqrt = and(T_771, T_773) node T_775 = bit(expB_S, 0) node T_776 = not(T_775) node T_777 = and(entering_PA_normalCase_sqrt, T_776) node T_778 = bit(fractB_S, 51) node zQuadPiece_1_A7_sqrt = and(T_777, T_778) node T_780 = bit(expB_S, 0) node T_781 = and(entering_PA_normalCase_sqrt, T_780) node T_782 = bit(fractB_S, 51) node T_783 = not(T_782) node zQuadPiece_2_A7_sqrt = and(T_781, T_783) node T_785 = bit(expB_S, 0) node T_786 = and(entering_PA_normalCase_sqrt, T_785) node T_787 = bit(fractB_S, 51) node zQuadPiece_3_A7_sqrt = and(T_786, T_787) node T_791 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) node T_794 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) node T_795 = or(T_791, T_794) node T_798 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) node T_799 = or(T_795, T_798) node T_802 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) node zK2_A7_sqrt = or(T_799, T_802) node T_805 = not(UInt<10>("h03d0")) node T_807 = mux(zQuadPiece_0_A7_sqrt, T_805, UInt<1>("h00")) node T_809 = not(UInt<10>("h0220")) node T_811 = mux(zQuadPiece_1_A7_sqrt, T_809, UInt<1>("h00")) node T_812 = or(T_807, T_811) node T_814 = not(UInt<10>("h02b2")) node T_816 = mux(zQuadPiece_2_A7_sqrt, T_814, UInt<1>("h00")) node T_817 = or(T_812, T_816) node T_819 = not(UInt<10>("h0181")) node T_821 = mux(zQuadPiece_3_A7_sqrt, T_819, UInt<1>("h00")) node zComplK1_A7_sqrt = or(T_817, T_821) node T_823 = bit(exp_PA, 0) node T_824 = not(T_823) node T_825 = and(cyc_A6_sqrt, T_824) node T_826 = bit(sigB_PA, 51) node T_827 = not(T_826) node zQuadPiece_0_A6_sqrt = and(T_825, T_827) node T_829 = bit(exp_PA, 0) node T_830 = not(T_829) node T_831 = and(cyc_A6_sqrt, T_830) node T_832 = bit(sigB_PA, 51) node zQuadPiece_1_A6_sqrt = and(T_831, T_832) node T_834 = bit(exp_PA, 0) node T_835 = and(cyc_A6_sqrt, T_834) node T_836 = bit(sigB_PA, 51) node T_837 = not(T_836) node zQuadPiece_2_A6_sqrt = and(T_835, T_837) node T_839 = bit(exp_PA, 0) node T_840 = and(cyc_A6_sqrt, T_839) node T_841 = bit(sigB_PA, 51) node zQuadPiece_3_A6_sqrt = and(T_840, T_841) node T_844 = not(UInt<13>("h01fe5")) node T_846 = mux(zQuadPiece_0_A6_sqrt, T_844, UInt<1>("h00")) node T_848 = not(UInt<13>("h01435")) node T_850 = mux(zQuadPiece_1_A6_sqrt, T_848, UInt<1>("h00")) node T_851 = or(T_846, T_850) node T_853 = not(UInt<13>("h0d2c")) node T_855 = mux(zQuadPiece_2_A6_sqrt, T_853, UInt<1>("h00")) node T_856 = or(T_851, T_855) node T_858 = not(UInt<13>("h04e8")) node T_860 = mux(zQuadPiece_3_A6_sqrt, T_858, UInt<1>("h00")) node zComplFractK0_A6_sqrt = or(T_856, T_860) node T_862 = bits(zFractB_A4_div, 48, 40) node T_863 = or(T_862, zK2_A7_sqrt) node T_864 = not(cyc_S) node T_866 = mux(T_864, nextMulAdd9A_A, UInt<1>("h00")) node mulAdd9A_A = or(T_863, T_866) node T_868 = bits(zFractB_A7_sqrt, 50, 42) node T_869 = or(zK1_A4_div, T_868) node T_870 = not(cyc_S) node T_872 = mux(T_870, nextMulAdd9B_A, UInt<1>("h00")) node mulAdd9B_A = or(T_869, T_872) node T_874 = shl(zComplK1_A7_sqrt, 10) node T_876 = subw(UInt<6>("h00"), cyc_A6_sqrt) node T_877 = cat(zComplFractK0_A6_sqrt, T_876) node T_878 = cat(cyc_A6_sqrt, T_877) node T_879 = or(T_874, T_878) node T_881 = subw(UInt<8>("h00"), entering_PA_normalCase_div) node T_882 = cat(zComplFractK0_A4_div, T_881) node T_883 = cat(entering_PA_normalCase_div, T_882) node T_884 = or(T_879, T_883) node T_886 = shl(fractR0_A, 10) node T_887 = addw(UInt<20>("h040000"), T_886) node T_889 = mux(cyc_A5_sqrt, T_887, UInt<1>("h00")) node T_890 = or(T_884, T_889) node T_891 = bit(hiSqrR0_A_sqrt, 9) node T_892 = not(T_891) node T_893 = and(cyc_A4_sqrt, T_892) node T_896 = mux(T_893, UInt<11>("h0400"), UInt<1>("h00")) node T_897 = or(T_890, T_896) node T_898 = bit(hiSqrR0_A_sqrt, 9) node T_899 = and(cyc_A4_sqrt, T_898) node T_900 = or(T_899, cyc_A3_div) node T_901 = bits(sigB_PA, 46, 26) node T_903 = addw(T_901, UInt<11>("h0400")) node T_905 = mux(T_900, T_903, UInt<1>("h00")) node T_906 = or(T_897, T_905) node T_907 = or(cyc_A3_sqrt, cyc_A2) node T_909 = mux(T_907, partNegSigma0_A, UInt<1>("h00")) node T_910 = or(T_906, T_909) node T_911 = shl(fractR0_A, 16) node T_913 = mux(cyc_A1_sqrt, T_911, UInt<1>("h00")) node T_914 = or(T_910, T_913) node T_915 = shl(fractR0_A, 15) node T_917 = mux(cyc_A1_div, T_915, UInt<1>("h00")) node mulAdd9C_A = or(T_914, T_917) node T_919 = mul(mulAdd9A_A, mulAdd9B_A) node T_921 = bits(mulAdd9C_A, 17, 0) node T_922 = cat(UInt<1>("h00"), T_921) node loMulAdd9Out_A = addw(T_919, T_922) node T_924 = bit(loMulAdd9Out_A, 18) node T_925 = bits(mulAdd9C_A, 24, 18) node T_927 = addw(T_925, UInt<1>("h01")) node T_928 = bits(mulAdd9C_A, 24, 18) node T_929 = mux(T_924, T_927, T_928) node T_930 = bits(loMulAdd9Out_A, 17, 0) node mulAdd9Out_A = cat(T_929, T_930) node T_932 = bit(mulAdd9Out_A, 19) node T_933 = and(cyc_A6_sqrt, T_932) node T_934 = not(mulAdd9Out_A) node T_935 = shr(T_934, 10) node T_937 = mux(T_933, T_935, UInt<1>("h00")) node zFractR0_A6_sqrt = bits(T_937, 8, 0) node T_939 = bit(exp_PA, 0) node T_940 = shl(mulAdd9Out_A, 1) node sqrR0_A5_sqrt = mux(T_939, T_940, mulAdd9Out_A) node T_942 = bit(mulAdd9Out_A, 20) node T_943 = and(entering_PA_normalCase_div, T_942) node T_944 = not(mulAdd9Out_A) node T_945 = shr(T_944, 11) node T_947 = mux(T_943, T_945, UInt<1>("h00")) node zFractR0_A4_div = bits(T_947, 8, 0) node T_949 = bit(mulAdd9Out_A, 11) node T_950 = and(cyc_A2, T_949) node T_951 = not(mulAdd9Out_A) node T_952 = shr(T_951, 2) node T_954 = mux(T_950, T_952, UInt<1>("h00")) node zSigma0_A2 = bits(T_954, 8, 0) node T_956 = shr(mulAdd9Out_A, 10) node T_957 = shr(mulAdd9Out_A, 9) node T_958 = mux(sqrtOp_PA, T_956, T_957) node fractR1_A1 = bits(T_958, 14, 0) node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) node T_962 = bit(exp_PA, 0) node T_963 = shl(r1_A1, 1) node ER1_A1_sqrt = mux(T_962, T_963, r1_A1) node T_965 = or(cyc_A6_sqrt, entering_PA_normalCase_div) when T_965 : node T_966 = or(zFractR0_A6_sqrt, zFractR0_A4_div) fractR0_A := T_966 skip when cyc_A5_sqrt : node T_967 = shr(sqrR0_A5_sqrt, 10) hiSqrR0_A_sqrt := T_967 skip node T_968 = or(cyc_A4_sqrt, cyc_A3) when T_968 : node T_969 = shr(mulAdd9Out_A, 9) node T_970 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_969) node T_971 = bits(T_970, 20, 0) partNegSigma0_A := T_971 skip node T_972 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node T_973 = or(T_972, cyc_A5_sqrt) node T_974 = or(T_973, cyc_A4) node T_975 = or(T_974, cyc_A3) node T_976 = or(T_975, cyc_A2) when T_976 : node T_977 = not(mulAdd9Out_A) node T_978 = shr(T_977, 11) node T_980 = mux(entering_PA_normalCase_sqrt, T_978, UInt<1>("h00")) node T_981 = or(T_980, zFractR0_A6_sqrt) node T_982 = bits(sigB_PA, 43, 35) node T_984 = mux(cyc_A4_sqrt, T_982, UInt<1>("h00")) node T_985 = or(T_981, T_984) node T_986 = bits(zFractB_A4_div, 43, 35) node T_987 = or(T_985, T_986) node T_988 = or(cyc_A5_sqrt, cyc_A3) node T_989 = bits(sigB_PA, 52, 44) node T_991 = mux(T_988, T_989, UInt<1>("h00")) node T_992 = or(T_987, T_991) node T_993 = or(T_992, zSigma0_A2) nextMulAdd9A_A := T_993 skip node T_994 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node T_995 = or(T_994, cyc_A5_sqrt) node T_996 = or(T_995, cyc_A4) node T_997 = or(T_996, cyc_A2) when T_997 : node T_998 = bits(zFractB_A7_sqrt, 50, 42) node T_999 = or(T_998, zFractR0_A6_sqrt) node T_1000 = bits(sqrR0_A5_sqrt, 9, 1) node T_1002 = mux(cyc_A5_sqrt, T_1000, UInt<1>("h00")) node T_1003 = or(T_999, T_1002) node T_1004 = or(T_1003, zFractR0_A4_div) node T_1005 = bits(hiSqrR0_A_sqrt, 8, 0) node T_1007 = mux(cyc_A4_sqrt, T_1005, UInt<1>("h00")) node T_1008 = or(T_1004, T_1007) node T_1010 = bits(fractR0_A, 8, 1) node T_1011 = cat(UInt<1>("h01"), T_1010) node T_1013 = mux(cyc_A2, T_1011, UInt<1>("h00")) node T_1014 = or(T_1008, T_1013) nextMulAdd9B_A := T_1014 skip when cyc_A1_sqrt : ER1_B_sqrt := ER1_A1_sqrt skip node T_1015 = or(cyc_A1, cyc_B7_sqrt) node T_1016 = or(T_1015, cyc_B6_div) node T_1017 = or(T_1016, cyc_B4) node T_1018 = or(T_1017, cyc_B3) node T_1019 = or(T_1018, cyc_C6_sqrt) node T_1020 = or(T_1019, cyc_C4) node T_1021 = or(T_1020, cyc_C1) io.latchMulAddA_0 := T_1021 node T_1022 = shl(ER1_A1_sqrt, 36) node T_1024 = mux(cyc_A1_sqrt, T_1022, UInt<1>("h00")) node T_1025 = or(cyc_B7_sqrt, cyc_A1_div) node T_1027 = mux(T_1025, sigB_PA, UInt<1>("h00")) node T_1028 = or(T_1024, T_1027) node T_1030 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) node T_1031 = or(T_1028, T_1030) node T_1032 = bits(zSigma1_B4, 45, 12) node T_1033 = or(T_1031, T_1032) node T_1034 = or(cyc_B3, cyc_C6_sqrt) node T_1035 = bits(sigXNU_B3_CX, 57, 12) node T_1037 = mux(T_1034, T_1035, UInt<1>("h00")) node T_1038 = or(T_1033, T_1037) node T_1039 = bits(sigXN_C, 57, 25) node T_1040 = shl(T_1039, 13) node T_1042 = mux(cyc_C4_div, T_1040, UInt<1>("h00")) node T_1043 = or(T_1038, T_1042) node T_1044 = shl(u_C_sqrt, 15) node T_1046 = mux(cyc_C4_sqrt, T_1044, UInt<1>("h00")) node T_1047 = or(T_1043, T_1046) node T_1049 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) node T_1050 = or(T_1047, T_1049) node T_1051 = or(T_1050, zComplSigT_C1_sqrt) io.mulAddA_0 := T_1051 node T_1052 = or(cyc_A1, cyc_B7_sqrt) node T_1053 = or(T_1052, cyc_B6_sqrt) node T_1054 = or(T_1053, cyc_B4) node T_1055 = or(T_1054, cyc_C6_sqrt) node T_1056 = or(T_1055, cyc_C4) node T_1057 = or(T_1056, cyc_C1) io.latchMulAddB_0 := T_1057 node T_1058 = shl(r1_A1, 36) node T_1060 = mux(cyc_A1, T_1058, UInt<1>("h00")) node T_1061 = shl(ESqrR1_B_sqrt, 19) node T_1063 = mux(cyc_B7_sqrt, T_1061, UInt<1>("h00")) node T_1064 = or(T_1060, T_1063) node T_1065 = shl(ER1_B_sqrt, 36) node T_1067 = mux(cyc_B6_sqrt, T_1065, UInt<1>("h00")) node T_1068 = or(T_1064, T_1067) node T_1069 = or(T_1068, zSigma1_B4) node T_1070 = bits(sqrSigma1_C, 30, 1) node T_1072 = mux(cyc_C6_sqrt, T_1070, UInt<1>("h00")) node T_1073 = or(T_1069, T_1072) node T_1075 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) node T_1076 = or(T_1073, T_1075) node T_1077 = or(T_1076, zComplSigT_C1) io.mulAddB_0 := T_1077 node T_1078 = or(cyc_A4, cyc_A3_div) node T_1079 = or(T_1078, cyc_A1_div) node T_1080 = or(T_1079, cyc_B10_sqrt) node T_1081 = or(T_1080, cyc_B9_sqrt) node T_1082 = or(T_1081, cyc_B7_sqrt) node T_1083 = or(T_1082, cyc_B6) node T_1084 = or(T_1083, cyc_B5_sqrt) node T_1085 = or(T_1084, cyc_B3_sqrt) node T_1086 = or(T_1085, cyc_B2_div) node T_1087 = or(T_1086, cyc_B1_sqrt) node T_1088 = or(T_1087, cyc_C4) node T_1089 = or(cyc_A3, cyc_A2_div) node T_1090 = or(T_1089, cyc_B9_sqrt) node T_1091 = or(T_1090, cyc_B8_sqrt) node T_1092 = or(T_1091, cyc_B6) node T_1093 = or(T_1092, cyc_B5) node T_1094 = or(T_1093, cyc_B4_sqrt) node T_1095 = or(T_1094, cyc_B2_sqrt) node T_1096 = or(T_1095, cyc_B1_div) node T_1097 = or(T_1096, cyc_C6_sqrt) node T_1098 = or(T_1097, valid_normalCase_leaving_PB) node T_1099 = or(cyc_A2, cyc_A1_div) node T_1100 = or(T_1099, cyc_B8_sqrt) node T_1101 = or(T_1100, cyc_B7_sqrt) node T_1102 = or(T_1101, cyc_B5) node T_1103 = or(T_1102, cyc_B4) node T_1104 = or(T_1103, cyc_B3_sqrt) node T_1105 = or(T_1104, cyc_B1_sqrt) node T_1106 = or(T_1105, cyc_C5) node T_1107 = or(T_1106, cyc_C2) node T_1108 = or(io.latchMulAddA_0, cyc_B6) node T_1109 = or(T_1108, cyc_B2_sqrt) node T_1110 = cat(T_1088, T_1098) node T_1111 = cat(T_1107, T_1109) node T_1112 = cat(T_1110, T_1111) io.usingMulAdd := T_1112 node T_1113 = shl(sigX1_B, 47) node T_1115 = mux(cyc_B1, T_1113, UInt<1>("h00")) node T_1116 = shl(sigX1_B, 46) node T_1118 = mux(cyc_C6_sqrt, T_1116, UInt<1>("h00")) node T_1119 = or(T_1115, T_1118) node T_1120 = or(cyc_C4_sqrt, cyc_C2) node T_1121 = shl(sigXN_C, 47) node T_1123 = mux(T_1120, T_1121, UInt<1>("h00")) node T_1124 = or(T_1119, T_1123) node T_1125 = not(E_E_div) node T_1126 = and(cyc_E3_div, T_1125) node T_1127 = shl(fractA_0_PC, 53) node T_1129 = mux(T_1126, T_1127, UInt<1>("h00")) node T_1130 = or(T_1124, T_1129) node T_1131 = bit(exp_PC, 0) node T_1132 = bit(sigB_PC, 0) node T_1134 = cat(T_1132, UInt<1>("h00")) node T_1135 = bit(sigB_PC, 1) node T_1136 = bit(sigB_PC, 0) node T_1137 = xor(T_1135, T_1136) node T_1138 = bit(sigB_PC, 0) node T_1139 = cat(T_1137, T_1138) node T_1140 = mux(T_1131, T_1134, T_1139) node T_1141 = not(extraT_E) node T_1143 = cat(T_1141, UInt<1>("h00")) node T_1144 = xor(T_1140, T_1143) node T_1145 = shl(T_1144, 54) node T_1147 = mux(cyc_E3_sqrt, T_1145, UInt<1>("h00")) node T_1148 = or(T_1130, T_1147) io.mulAddC_2 := T_1148 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) node T_1150 = bits(io.mulAddResult_3, 90, 45) node T_1151 = not(T_1150) node T_1153 = mux(cyc_B4, T_1151, UInt<1>("h00")) zSigma1_B4 := T_1153 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) node T_1155 = bits(io.mulAddResult_3, 104, 47) sigXNU_B3_CX := T_1155 node T_1156 = bit(io.mulAddResult_3, 104) node E_C1_div = not(T_1156) node T_1158 = not(E_C1_div) node T_1159 = and(cyc_C1_div, T_1158) node T_1160 = or(T_1159, cyc_C1_sqrt) node T_1161 = bits(io.mulAddResult_3, 104, 51) node T_1162 = not(T_1161) node T_1164 = mux(T_1160, T_1162, UInt<1>("h00")) node T_1165 = and(cyc_C1_div, E_C1_div) node T_1167 = bits(io.mulAddResult_3, 102, 50) node T_1168 = not(T_1167) node T_1169 = cat(UInt<1>("h00"), T_1168) node T_1171 = mux(T_1165, T_1169, UInt<1>("h00")) node T_1172 = or(T_1164, T_1171) zComplSigT_C1 := T_1172 node T_1173 = bits(io.mulAddResult_3, 104, 51) node T_1174 = not(T_1173) node T_1176 = mux(cyc_C1_sqrt, T_1174, UInt<1>("h00")) zComplSigT_C1_sqrt := T_1176 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : ESqrR1_B_sqrt := ESqrR1_B8_sqrt skip when cyc_B3 : sigX1_B := sigXNU_B3_CX skip when cyc_B1 : sqrSigma1_C := sqrSigma1_B1 skip node T_1179 = or(cyc_C6_sqrt, cyc_C5_div) node T_1180 = or(T_1179, cyc_C3_sqrt) when T_1180 : sigXN_C := sigXNU_B3_CX skip when cyc_C5_sqrt : node T_1181 = bits(sigXNU_B3_CX, 56, 26) u_C_sqrt := T_1181 skip when cyc_C1 : E_E_div := E_C1_div node T_1182 = bits(sigT_C1, 53, 1) sigT_E := T_1182 node T_1183 = bit(sigT_C1, 0) extraT_E := T_1183 skip when cyc_E2 : node T_1184 = bit(remT_E2, 55) node T_1185 = bit(remT_E2, 53) node T_1186 = mux(sqrtOp_PC, T_1184, T_1185) isNegRemT_E := T_1186 node T_1187 = bits(remT_E2, 53, 0) node T_1189 = eq(T_1187, UInt<1>("h00")) node T_1190 = not(sqrtOp_PC) node T_1191 = bits(remT_E2, 55, 54) node T_1193 = eq(T_1191, UInt<1>("h00")) node T_1194 = or(T_1190, T_1193) node T_1195 = and(T_1189, T_1194) trueEqX_E1 := T_1195 skip node T_1196 = not(sqrtOp_PC) node T_1197 = and(T_1196, E_E_div) node T_1199 = mux(T_1197, exp_PC, UInt<1>("h00")) node T_1200 = not(sqrtOp_PC) node T_1201 = not(E_E_div) node T_1202 = and(T_1200, T_1201) node T_1204 = mux(T_1202, expP1_PC, UInt<1>("h00")) node T_1205 = or(T_1199, T_1204) node T_1206 = shr(exp_PC, 1) node T_1208 = addw(T_1206, UInt<12>("h0400")) node T_1210 = mux(sqrtOp_PC, T_1208, UInt<1>("h00")) node sExpX_E = or(T_1205, T_1210) node posExpX_E = bits(sExpX_E, 12, 0) node T_1213 = bits(posExpX_E, 12, 6) node posExpX_0001111_E = eq(T_1213, UInt<7>("h0f")) node T_1216 = bit(posExpX_E, 5) node T_1217 = not(T_1216) node posExpX_00011110_E = and(posExpX_0001111_E, T_1217) node T_1219 = bit(posExpX_E, 4) node T_1220 = not(T_1219) node posExpX_000111100_E = and(posExpX_00011110_E, T_1220) node T_1222 = bits(sExpX_E, 2, 0) node exp3X_lt_001_E = lt(T_1222, UInt<3>("h01")) node T_1225 = bits(sExpX_E, 2, 0) node exp3X_lt_010_E = lt(T_1225, UInt<3>("h02")) node T_1228 = bits(sExpX_E, 2, 0) node exp3X_lt_011_E = lt(T_1228, UInt<3>("h03")) node T_1231 = bits(sExpX_E, 2, 0) node exp3X_lt_100_E = lt(T_1231, UInt<3>("h04")) node T_1234 = bits(sExpX_E, 2, 0) node exp3X_lt_101_E = lt(T_1234, UInt<3>("h05")) node T_1237 = bits(sExpX_E, 2, 0) node exp3X_lt_110_E = lt(T_1237, UInt<3>("h06")) node T_1240 = bits(sExpX_E, 2, 0) node exp3X_lt_111_E = lt(T_1240, UInt<3>("h07")) node T_1243 = bits(sExpX_E, 4, 3) node exp5X_lt_01000_E = eq(T_1243, UInt<2>("h00")) node T_1246 = bits(sExpX_E, 4, 3) node exp5X_01_E = eq(T_1246, UInt<2>("h01")) node T_1249 = bits(sExpX_E, 4, 3) node exp5X_10_E = eq(T_1249, UInt<2>("h02")) node exp5X_lt_00001_E = and(exp5X_lt_01000_E, exp3X_lt_001_E) node exp5X_lt_00010_E = and(exp5X_lt_01000_E, exp3X_lt_010_E) node exp5X_lt_00011_E = and(exp5X_lt_01000_E, exp3X_lt_011_E) node exp5X_lt_00100_E = and(exp5X_lt_01000_E, exp3X_lt_100_E) node exp5X_lt_00101_E = and(exp5X_lt_01000_E, exp3X_lt_101_E) node exp5X_lt_00110_E = and(exp5X_lt_01000_E, exp3X_lt_110_E) node exp5X_lt_00111_E = and(exp5X_lt_01000_E, exp3X_lt_111_E) node T_1259 = and(exp5X_01_E, exp3X_lt_001_E) node exp5X_lt_01001_E = or(exp5X_lt_01000_E, T_1259) node T_1261 = and(exp5X_01_E, exp3X_lt_010_E) node exp5X_lt_01010_E = or(exp5X_lt_01000_E, T_1261) node T_1263 = and(exp5X_01_E, exp3X_lt_011_E) node exp5X_lt_01011_E = or(exp5X_lt_01000_E, T_1263) node T_1265 = and(exp5X_01_E, exp3X_lt_100_E) node exp5X_lt_01100_E = or(exp5X_lt_01000_E, T_1265) node T_1267 = and(exp5X_01_E, exp3X_lt_101_E) node exp5X_lt_01101_E = or(exp5X_lt_01000_E, T_1267) node T_1269 = and(exp5X_01_E, exp3X_lt_110_E) node exp5X_lt_01110_E = or(exp5X_lt_01000_E, T_1269) node T_1271 = and(exp5X_01_E, exp3X_lt_111_E) node exp5X_lt_01111_E = or(exp5X_lt_01000_E, T_1271) node T_1273 = bit(sExpX_E, 4) node exp5X_lt_10000_E = not(T_1273) node T_1275 = bit(sExpX_E, 4) node T_1276 = not(T_1275) node T_1277 = and(exp5X_10_E, exp3X_lt_001_E) node exp5X_lt_10001_E = or(T_1276, T_1277) node T_1279 = bit(sExpX_E, 4) node T_1280 = not(T_1279) node T_1281 = and(exp5X_10_E, exp3X_lt_010_E) node exp5X_lt_10010_E = or(T_1280, T_1281) node T_1283 = bit(sExpX_E, 4) node T_1284 = not(T_1283) node T_1285 = and(exp5X_10_E, exp3X_lt_011_E) node exp5X_lt_10011_E = or(T_1284, T_1285) node T_1287 = bit(sExpX_E, 4) node T_1288 = not(T_1287) node T_1289 = and(exp5X_10_E, exp3X_lt_100_E) node exp5X_lt_10100_E = or(T_1288, T_1289) node T_1291 = bit(sExpX_E, 4) node T_1292 = not(T_1291) node T_1293 = and(exp5X_10_E, exp3X_lt_101_E) node exp5X_lt_10101_E = or(T_1292, T_1293) node T_1295 = bit(sExpX_E, 4) node T_1296 = not(T_1295) node T_1297 = and(exp5X_10_E, exp3X_lt_110_E) node exp5X_lt_10110_E = or(T_1296, T_1297) node T_1299 = bit(sExpX_E, 4) node T_1300 = not(T_1299) node T_1301 = and(exp5X_10_E, exp3X_lt_111_E) node exp5X_lt_10111_E = or(T_1300, T_1301) node T_1303 = bits(sExpX_E, 4, 3) node exp5X_lt_11000_E = neq(T_1303, UInt<2>("h03")) node exp5X_lt_11001_E = or(exp5X_lt_11000_E, exp3X_lt_001_E) node exp5X_lt_11010_E = or(exp5X_lt_11000_E, exp3X_lt_010_E) node exp5X_lt_11011_E = or(exp5X_lt_11000_E, exp3X_lt_011_E) node exp5X_lt_11100_E = or(exp5X_lt_11000_E, exp3X_lt_100_E) node exp5X_lt_11101_E = or(exp5X_lt_11000_E, exp3X_lt_101_E) node exp5X_lt_11110_E = or(exp5X_lt_11000_E, exp3X_lt_110_E) node exp5X_lt_11111_E = or(exp5X_lt_11000_E, exp3X_lt_111_E) node T_1313 = bits(sExpX_E, 3, 0) node T_1315 = lt(T_1313, UInt<4>("h0e")) node T_1316 = and(posExpX_000111100_E, T_1315) node T_1317 = bits(sExpX_E, 3, 0) node T_1319 = lt(T_1317, UInt<4>("h0f")) node T_1320 = and(posExpX_000111100_E, T_1319) node T_1321 = and(posExpX_00011110_E, exp5X_lt_10001_E) node T_1322 = and(posExpX_00011110_E, exp5X_lt_10010_E) node T_1323 = and(posExpX_00011110_E, exp5X_lt_10011_E) node T_1324 = and(posExpX_00011110_E, exp5X_lt_10100_E) node T_1325 = and(posExpX_00011110_E, exp5X_lt_10101_E) node T_1326 = and(posExpX_00011110_E, exp5X_lt_10110_E) node T_1327 = and(posExpX_00011110_E, exp5X_lt_10111_E) node T_1328 = and(posExpX_00011110_E, exp5X_lt_11000_E) node T_1329 = and(posExpX_00011110_E, exp5X_lt_11001_E) node T_1330 = and(posExpX_00011110_E, exp5X_lt_11010_E) node T_1331 = and(posExpX_00011110_E, exp5X_lt_11011_E) node T_1332 = and(posExpX_00011110_E, exp5X_lt_11100_E) node T_1333 = and(posExpX_00011110_E, exp5X_lt_11101_E) node T_1334 = and(posExpX_00011110_E, exp5X_lt_11110_E) node T_1335 = and(posExpX_00011110_E, exp5X_lt_11111_E) node T_1336 = bit(sExpX_E, 5) node T_1337 = not(T_1336) node T_1338 = or(T_1337, exp5X_lt_00001_E) node T_1339 = and(posExpX_0001111_E, T_1338) node T_1340 = bit(sExpX_E, 5) node T_1341 = not(T_1340) node T_1342 = or(T_1341, exp5X_lt_00010_E) node T_1343 = and(posExpX_0001111_E, T_1342) node T_1344 = bit(sExpX_E, 5) node T_1345 = not(T_1344) node T_1346 = or(T_1345, exp5X_lt_00011_E) node T_1347 = and(posExpX_0001111_E, T_1346) node T_1348 = bit(sExpX_E, 5) node T_1349 = not(T_1348) node T_1350 = or(T_1349, exp5X_lt_00100_E) node T_1351 = and(posExpX_0001111_E, T_1350) node T_1352 = bit(sExpX_E, 5) node T_1353 = not(T_1352) node T_1354 = or(T_1353, exp5X_lt_00101_E) node T_1355 = and(posExpX_0001111_E, T_1354) node T_1356 = bit(sExpX_E, 5) node T_1357 = not(T_1356) node T_1358 = or(T_1357, exp5X_lt_00110_E) node T_1359 = and(posExpX_0001111_E, T_1358) node T_1360 = bit(sExpX_E, 5) node T_1361 = not(T_1360) node T_1362 = or(T_1361, exp5X_lt_00111_E) node T_1363 = and(posExpX_0001111_E, T_1362) node T_1364 = bit(sExpX_E, 5) node T_1365 = not(T_1364) node T_1366 = or(T_1365, exp5X_lt_01000_E) node T_1367 = and(posExpX_0001111_E, T_1366) node T_1368 = bit(sExpX_E, 5) node T_1369 = not(T_1368) node T_1370 = or(T_1369, exp5X_lt_01001_E) node T_1371 = and(posExpX_0001111_E, T_1370) node T_1372 = bit(sExpX_E, 5) node T_1373 = not(T_1372) node T_1374 = or(T_1373, exp5X_lt_01010_E) node T_1375 = and(posExpX_0001111_E, T_1374) node T_1376 = bit(sExpX_E, 5) node T_1377 = not(T_1376) node T_1378 = or(T_1377, exp5X_lt_01011_E) node T_1379 = and(posExpX_0001111_E, T_1378) node T_1380 = bit(sExpX_E, 5) node T_1381 = not(T_1380) node T_1382 = or(T_1381, exp5X_lt_01100_E) node T_1383 = and(posExpX_0001111_E, T_1382) node T_1384 = bit(sExpX_E, 5) node T_1385 = not(T_1384) node T_1386 = or(T_1385, exp5X_lt_01101_E) node T_1387 = and(posExpX_0001111_E, T_1386) node T_1388 = bit(sExpX_E, 5) node T_1389 = not(T_1388) node T_1390 = or(T_1389, exp5X_lt_01110_E) node T_1391 = and(posExpX_0001111_E, T_1390) node T_1392 = bit(sExpX_E, 5) node T_1393 = not(T_1392) node T_1394 = or(T_1393, exp5X_lt_01111_E) node T_1395 = and(posExpX_0001111_E, T_1394) node T_1396 = bit(sExpX_E, 5) node T_1397 = not(T_1396) node T_1398 = or(T_1397, exp5X_lt_10000_E) node T_1399 = and(posExpX_0001111_E, T_1398) node T_1400 = bit(sExpX_E, 5) node T_1401 = not(T_1400) node T_1402 = or(T_1401, exp5X_lt_10001_E) node T_1403 = and(posExpX_0001111_E, T_1402) node T_1404 = bit(sExpX_E, 5) node T_1405 = not(T_1404) node T_1406 = or(T_1405, exp5X_lt_10010_E) node T_1407 = and(posExpX_0001111_E, T_1406) node T_1408 = bit(sExpX_E, 5) node T_1409 = not(T_1408) node T_1410 = or(T_1409, exp5X_lt_10011_E) node T_1411 = and(posExpX_0001111_E, T_1410) node T_1412 = bit(sExpX_E, 5) node T_1413 = not(T_1412) node T_1414 = or(T_1413, exp5X_lt_10100_E) node T_1415 = and(posExpX_0001111_E, T_1414) node T_1416 = bit(sExpX_E, 5) node T_1417 = not(T_1416) node T_1418 = or(T_1417, exp5X_lt_10101_E) node T_1419 = and(posExpX_0001111_E, T_1418) node T_1420 = bit(sExpX_E, 5) node T_1421 = not(T_1420) node T_1422 = or(T_1421, exp5X_lt_10110_E) node T_1423 = and(posExpX_0001111_E, T_1422) node T_1424 = bit(sExpX_E, 5) node T_1425 = not(T_1424) node T_1426 = or(T_1425, exp5X_lt_10111_E) node T_1427 = and(posExpX_0001111_E, T_1426) node T_1428 = bit(sExpX_E, 5) node T_1429 = not(T_1428) node T_1430 = or(T_1429, exp5X_lt_11000_E) node T_1431 = and(posExpX_0001111_E, T_1430) node T_1432 = bit(sExpX_E, 5) node T_1433 = not(T_1432) node T_1434 = or(T_1433, exp5X_lt_11001_E) node T_1435 = and(posExpX_0001111_E, T_1434) node T_1436 = bit(sExpX_E, 5) node T_1437 = not(T_1436) node T_1438 = or(T_1437, exp5X_lt_11010_E) node T_1439 = and(posExpX_0001111_E, T_1438) node T_1440 = bit(sExpX_E, 5) node T_1441 = not(T_1440) node T_1442 = or(T_1441, exp5X_lt_11011_E) node T_1443 = and(posExpX_0001111_E, T_1442) node T_1444 = bit(sExpX_E, 5) node T_1445 = not(T_1444) node T_1446 = or(T_1445, exp5X_lt_11100_E) node T_1447 = and(posExpX_0001111_E, T_1446) node T_1448 = bit(sExpX_E, 5) node T_1449 = not(T_1448) node T_1450 = or(T_1449, exp5X_lt_11101_E) node T_1451 = and(posExpX_0001111_E, T_1450) node T_1452 = bit(sExpX_E, 5) node T_1453 = not(T_1452) node T_1454 = or(T_1453, exp5X_lt_11110_E) node T_1455 = and(posExpX_0001111_E, T_1454) node T_1456 = bit(sExpX_E, 5) node T_1457 = not(T_1456) node T_1458 = or(T_1457, exp5X_lt_11111_E) node T_1459 = and(posExpX_0001111_E, T_1458) node T_1461 = lt(posExpX_E, UInt<13>("h0401")) node T_1463 = lt(posExpX_E, UInt<13>("h0402")) node T_1464 = cat(T_1320, posExpX_000111100_E) node T_1465 = cat(T_1316, T_1464) node T_1466 = cat(T_1322, T_1323) node T_1467 = cat(T_1321, T_1466) node T_1468 = cat(T_1465, T_1467) node T_1469 = cat(T_1325, T_1326) node T_1470 = cat(T_1324, T_1469) node T_1471 = cat(T_1327, T_1328) node T_1472 = cat(T_1329, T_1330) node T_1473 = cat(T_1471, T_1472) node T_1474 = cat(T_1470, T_1473) node T_1475 = cat(T_1468, T_1474) node T_1476 = cat(T_1332, T_1333) node T_1477 = cat(T_1331, T_1476) node T_1478 = cat(T_1335, posExpX_00011110_E) node T_1479 = cat(T_1334, T_1478) node T_1480 = cat(T_1477, T_1479) node T_1481 = cat(T_1343, T_1347) node T_1482 = cat(T_1339, T_1481) node T_1483 = cat(T_1351, T_1355) node T_1484 = cat(T_1359, T_1363) node T_1485 = cat(T_1483, T_1484) node T_1486 = cat(T_1482, T_1485) node T_1487 = cat(T_1480, T_1486) node T_1488 = cat(T_1475, T_1487) node T_1489 = cat(T_1371, T_1375) node T_1490 = cat(T_1367, T_1489) node T_1491 = cat(T_1383, T_1387) node T_1492 = cat(T_1379, T_1491) node T_1493 = cat(T_1490, T_1492) node T_1494 = cat(T_1395, T_1399) node T_1495 = cat(T_1391, T_1494) node T_1496 = cat(T_1403, T_1407) node T_1497 = cat(T_1411, T_1415) node T_1498 = cat(T_1496, T_1497) node T_1499 = cat(T_1495, T_1498) node T_1500 = cat(T_1493, T_1499) node T_1501 = cat(T_1423, T_1427) node T_1502 = cat(T_1419, T_1501) node T_1503 = cat(T_1431, T_1435) node T_1504 = cat(T_1439, T_1443) node T_1505 = cat(T_1503, T_1504) node T_1506 = cat(T_1502, T_1505) node T_1507 = cat(T_1451, T_1455) node T_1508 = cat(T_1447, T_1507) node T_1509 = cat(T_1459, posExpX_0001111_E) node T_1510 = cat(T_1461, T_1463) node T_1511 = cat(T_1509, T_1510) node T_1512 = cat(T_1508, T_1511) node T_1513 = cat(T_1506, T_1512) node T_1514 = cat(T_1500, T_1513) node roundMask_E = cat(T_1488, T_1514) node T_1517 = cat(UInt<1>("h00"), roundMask_E) node T_1518 = not(T_1517) node T_1520 = cat(roundMask_E, UInt<1>("h01")) node incrPosMask_E = and(T_1518, T_1520) node T_1522 = shr(incrPosMask_E, 1) node T_1523 = and(sigT_E, T_1522) node hiRoundPosBitT_E = neq(T_1523, UInt<1>("h00")) node T_1526 = shr(roundMask_E, 1) node T_1527 = and(sigT_E, T_1526) node all0sHiRoundExtraT_E = eq(T_1527, UInt<1>("h00")) node T_1530 = not(sigT_E) node T_1531 = shr(roundMask_E, 1) node T_1532 = and(T_1530, T_1531) node all1sHiRoundExtraT_E = eq(T_1532, UInt<1>("h00")) node T_1535 = bit(roundMask_E, 0) node T_1536 = not(T_1535) node T_1537 = or(T_1536, hiRoundPosBitT_E) node all1sHiRoundT_E = and(T_1537, all1sHiRoundExtraT_E) node T_1540 = addw(UInt<54>("h00"), sigT_E) node sigAdjT_E = addw(T_1540, roundMagUp_PC) node T_1543 = not(roundMask_E) node T_1544 = cat(UInt<1>("h01"), T_1543) node sigY0_E = and(sigAdjT_E, T_1544) node T_1547 = cat(UInt<1>("h00"), roundMask_E) node T_1548 = or(sigAdjT_E, T_1547) node sigY1_E = addw(T_1548, UInt<1>("h01")) node T_1551 = not(isNegRemT_E) node T_1552 = not(trueEqX_E1) node T_1553 = and(T_1551, T_1552) node trueLtX_E1 = mux(sqrtOp_PC, T_1553, isNegRemT_E) node T_1555 = bit(roundMask_E, 0) node T_1556 = not(trueLtX_E1) node T_1557 = and(T_1555, T_1556) node T_1558 = and(T_1557, all1sHiRoundExtraT_E) node T_1559 = and(T_1558, extraT_E) node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1559) node T_1561 = not(trueEqX_E1) node T_1562 = not(extraT_E) node T_1563 = or(T_1561, T_1562) node T_1564 = not(all1sHiRoundExtraT_E) node anyRoundExtra_E1 = or(T_1563, T_1564) node T_1566 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) node T_1567 = not(anyRoundExtra_E1) node T_1568 = and(T_1566, T_1567) node roundEvenMask_E1 = mux(T_1568, incrPosMask_E, UInt<1>("h00")) node T_1571 = and(roundMagDown_PC, extraT_E) node T_1572 = not(trueLtX_E1) node T_1573 = and(T_1571, T_1572) node T_1574 = and(T_1573, all1sHiRoundT_E) node T_1575 = not(trueLtX_E1) node T_1576 = and(extraT_E, T_1575) node T_1577 = not(trueEqX_E1) node T_1578 = and(T_1576, T_1577) node T_1579 = not(all1sHiRoundT_E) node T_1580 = or(T_1578, T_1579) node T_1581 = and(roundMagUp_PC, T_1580) node T_1582 = or(T_1574, T_1581) node T_1583 = not(trueLtX_E1) node T_1584 = or(extraT_E, T_1583) node T_1585 = bit(roundMask_E, 0) node T_1586 = not(T_1585) node T_1587 = and(T_1584, T_1586) node T_1588 = or(hiRoundPosBitT_E, T_1587) node T_1589 = not(trueLtX_E1) node T_1590 = and(extraT_E, T_1589) node T_1591 = and(T_1590, all1sHiRoundExtraT_E) node T_1592 = or(T_1588, T_1591) node T_1593 = and(roundingMode_near_even_PC, T_1592) node T_1594 = or(T_1582, T_1593) node T_1595 = mux(T_1594, sigY1_E, sigY0_E) node T_1596 = not(roundEvenMask_E1) node sigY_E1 = and(T_1595, T_1596) node fractY_E1 = bits(sigY_E1, 51, 0) node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) node T_1600 = bit(sigY_E1, 53) node T_1601 = not(T_1600) node T_1603 = mux(T_1601, sExpX_E, UInt<1>("h00")) node T_1604 = bit(sigY_E1, 53) node T_1605 = not(sqrtOp_PC) node T_1606 = and(T_1604, T_1605) node T_1607 = and(T_1606, E_E_div) node T_1609 = mux(T_1607, expP1_PC, UInt<1>("h00")) node T_1610 = or(T_1603, T_1609) node T_1611 = bit(sigY_E1, 53) node T_1612 = not(sqrtOp_PC) node T_1613 = and(T_1611, T_1612) node T_1614 = not(E_E_div) node T_1615 = and(T_1613, T_1614) node T_1617 = mux(T_1615, expP2_PC, UInt<1>("h00")) node T_1618 = or(T_1610, T_1617) node T_1619 = bit(sigY_E1, 53) node T_1620 = and(T_1619, sqrtOp_PC) node T_1621 = shr(expP2_PC, 1) node T_1623 = addw(T_1621, UInt<12>("h0400")) node T_1625 = mux(T_1620, T_1623, UInt<1>("h00")) node sExpY_E1 = or(T_1618, T_1625) node expY_E1 = bits(sExpY_E1, 11, 0) node T_1628 = bit(sExpY_E1, 13) node T_1629 = not(T_1628) node T_1631 = bits(sExpY_E1, 12, 10) node T_1632 = leq(UInt<3>("h03"), T_1631) node overflowY_E1 = and(T_1629, T_1632) node T_1634 = bit(sExpY_E1, 13) node T_1635 = bits(sExpY_E1, 12, 0) node T_1637 = lt(T_1635, UInt<13>("h03ce")) node totalUnderflowY_E1 = or(T_1634, T_1637) node T_1640 = leq(posExpX_E, UInt<13>("h0401")) node T_1641 = and(T_1640, inexactY_E1) node underflowY_E1 = or(totalUnderflowY_E1, T_1641) node T_1643 = not(isNaNB_PC) node T_1644 = not(isZeroB_PC) node T_1645 = and(T_1643, T_1644) node T_1646 = and(T_1645, sign_PC) node T_1647 = and(isZeroA_PC, isZeroB_PC) node T_1648 = and(isInfA_PC, isInfB_PC) node T_1649 = or(T_1647, T_1648) node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1646, T_1649) node T_1651 = not(sqrtOp_PC) node T_1652 = and(T_1651, isSigNaNA_PC) node T_1653 = or(T_1652, isSigNaNB_PC) node invalid_PC = or(T_1653, notSigNaN_invalid_PC) node T_1655 = not(sqrtOp_PC) node T_1656 = not(isSpecialA_PC) node T_1657 = and(T_1655, T_1656) node T_1658 = not(isZeroA_PC) node T_1659 = and(T_1657, T_1658) node infinity_PC = and(T_1659, isZeroB_PC) node overflow_E1 = and(normalCase_PC, overflowY_E1) node underflow_E1 = and(normalCase_PC, underflowY_E1) node T_1663 = or(overflow_E1, underflow_E1) node T_1664 = and(normalCase_PC, inexactY_E1) node inexact_E1 = or(T_1663, T_1664) node T_1666 = or(isZeroA_PC, isInfB_PC) node T_1667 = not(roundMagUp_PC) node T_1668 = and(totalUnderflowY_E1, T_1667) node T_1669 = or(T_1666, T_1668) node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1669) node T_1671 = and(normalCase_PC, totalUnderflowY_E1) node pegMinFiniteMagOut_E1 = and(T_1671, roundMagUp_PC) node T_1673 = not(overflowY_roundMagUp_PC) node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1673) node T_1675 = or(isInfA_PC, isZeroB_PC) node T_1676 = and(overflow_E1, overflowY_roundMagUp_PC) node T_1677 = or(T_1675, T_1676) node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1677) node T_1679 = not(sqrtOp_PC) node T_1680 = and(T_1679, isNaNA_PC) node T_1681 = or(T_1680, isNaNB_PC) node isNaNOut_PC = or(T_1681, notSigNaN_invalid_PC) node T_1683 = and(isZeroB_PC, sign_PC) node T_1684 = mux(sqrtOp_PC, T_1683, sign_PC) node signOut_PC = or(isNaNOut_PC, T_1684) node T_1687 = not(UInt<12>("h01ff")) node T_1689 = mux(notSpecial_isZeroOut_E1, T_1687, UInt<1>("h00")) node T_1690 = not(T_1689) node T_1691 = and(expY_E1, T_1690) node T_1693 = not(UInt<12>("h03ce")) node T_1695 = mux(pegMinFiniteMagOut_E1, T_1693, UInt<1>("h00")) node T_1696 = not(T_1695) node T_1697 = and(T_1691, T_1696) node T_1699 = not(UInt<12>("h0bff")) node T_1701 = mux(pegMaxFiniteMagOut_E1, T_1699, UInt<1>("h00")) node T_1702 = not(T_1701) node T_1703 = and(T_1697, T_1702) node T_1705 = not(UInt<12>("h0dff")) node T_1707 = mux(notNaN_isInfOut_E1, T_1705, UInt<1>("h00")) node T_1708 = not(T_1707) node T_1709 = and(T_1703, T_1708) node T_1712 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) node T_1713 = or(T_1709, T_1712) node T_1716 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) node T_1717 = or(T_1713, T_1716) node T_1720 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) node T_1721 = or(T_1717, T_1720) node T_1724 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) node expOut_E1 = or(T_1721, T_1724) node T_1726 = and(totalUnderflowY_E1, roundMagUp_PC) node T_1728 = mux(T_1726, UInt<1>("h00"), fractY_E1) node T_1729 = or(isNaNOut_PC, pegMaxFiniteMagOut_E1) node T_1732 = mux(T_1729, UInt<52>("h0fffffffffffff"), UInt<1>("h00")) node fractOut_E1 = or(T_1728, T_1732) node T_1734 = cat(expOut_E1, fractOut_E1) node T_1735 = cat(signOut_PC, T_1734) io.out := T_1735 node T_1736 = cat(invalid_PC, infinity_PC) node T_1737 = cat(underflow_E1, inexact_E1) node T_1738 = cat(overflow_E1, T_1737) node T_1739 = cat(T_1736, T_1738) io.exceptionFlags := T_1739 module mul54 : input clock : Clock input reset : UInt<1> output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} io.result_s3 := UInt<1>("h00") reg val_s1 : UInt<1>, clock, reset reg val_s2 : UInt<1>, clock, reset reg reg_a_s1 : UInt<54>, clock, reset reg reg_b_s1 : UInt<54>, clock, reset reg reg_a_s2 : UInt<54>, clock, reset reg reg_b_s2 : UInt<54>, clock, reset reg reg_result_s3 : UInt<105>, clock, reset val_s1 := io.val_s0 val_s2 := val_s1 when io.val_s0 : when io.latch_a_s0 : reg_a_s1 := io.a_s0 skip when io.latch_b_s0 : reg_b_s1 := io.b_s0 skip skip when val_s1 : reg_a_s2 := reg_a_s1 reg_b_s2 := reg_b_s1 skip when val_s2 : node T_25 = mul(reg_a_s2, reg_b_s2) node T_26 = addw(T_25, io.c_s2) reg_result_s3 := T_26 skip io.result_s3 := reg_result_s3 module divSqrtRecodedFloat64 : input clock : Clock input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags := UInt<1>("h00") io.out := UInt<1>("h00") io.outValid_sqrt := UInt<1>("h00") io.outValid_div := UInt<1>("h00") io.inReady_sqrt := UInt<1>("h00") io.inReady_div := UInt<1>("h00") inst ds of divSqrtRecodedFloat64_mulAddZ31 ds.io.mulAddResult_3 := UInt<1>("h00") ds.io.roundingMode := UInt<1>("h00") ds.io.b := UInt<1>("h00") ds.io.a := UInt<1>("h00") ds.io.sqrtOp := UInt<1>("h00") ds.io.inValid := UInt<1>("h00") ds.clock := clock ds.reset := reset io.inReady_div := ds.io.inReady_div io.inReady_sqrt := ds.io.inReady_sqrt ds.io.inValid := io.inValid ds.io.sqrtOp := io.sqrtOp ds.io.a := io.a ds.io.b := io.b ds.io.roundingMode := io.roundingMode io.outValid_div := ds.io.outValid_div io.outValid_sqrt := ds.io.outValid_sqrt io.out := ds.io.out io.exceptionFlags := ds.io.exceptionFlags inst mul of mul54 mul.io.c_s2 := UInt<1>("h00") mul.io.b_s0 := UInt<1>("h00") mul.io.latch_b_s0 := UInt<1>("h00") mul.io.a_s0 := UInt<1>("h00") mul.io.latch_a_s0 := UInt<1>("h00") mul.io.val_s0 := UInt<1>("h00") mul.clock := clock mul.reset := reset node T_29 = bit(ds.io.usingMulAdd, 0) mul.io.val_s0 := T_29 mul.io.latch_a_s0 := ds.io.latchMulAddA_0 mul.io.a_s0 := ds.io.mulAddA_0 mul.io.latch_b_s0 := ds.io.latchMulAddB_0 mul.io.b_s0 := ds.io.mulAddB_0 mul.io.c_s2 := ds.io.mulAddC_2 ds.io.mulAddResult_3 := mul.io.result_s3 module FPU : input clock : Clock input reset : UInt<1> output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>} io.sboard_clra := UInt<1>("h00") io.sboard_clr := UInt<1>("h00") io.sboard_set := UInt<1>("h00") io.dec.wflags := UInt<1>("h00") io.dec.round := UInt<1>("h00") io.dec.sqrt := UInt<1>("h00") io.dec.div := UInt<1>("h00") io.dec.fma := UInt<1>("h00") io.dec.fastpipe := UInt<1>("h00") io.dec.toint := UInt<1>("h00") io.dec.fromint := UInt<1>("h00") io.dec.single := UInt<1>("h00") io.dec.swap23 := UInt<1>("h00") io.dec.swap12 := UInt<1>("h00") io.dec.ren3 := UInt<1>("h00") io.dec.ren2 := UInt<1>("h00") io.dec.ren1 := UInt<1>("h00") io.dec.wen := UInt<1>("h00") io.dec.ldst := UInt<1>("h00") io.dec.cmd := UInt<1>("h00") io.illegal_rm := UInt<1>("h00") io.nack_mem := UInt<1>("h00") io.fcsr_rdy := UInt<1>("h00") io.toint_data := UInt<1>("h00") io.store_data := UInt<1>("h00") io.fcsr_flags.bits := UInt<1>("h00") io.fcsr_flags.valid := UInt<1>("h00") reg ex_reg_valid : UInt<1>, clock, reset onreset ex_reg_valid := UInt<1>("h00") ex_reg_valid := io.valid reg ex_reg_inst : UInt<32>, clock, reset when io.valid : ex_reg_inst := io.inst skip node T_68 = eq(io.killx, UInt<1>("h00")) node T_69 = and(ex_reg_valid, T_68) reg mem_reg_valid : UInt<1>, clock, reset onreset mem_reg_valid := UInt<1>("h00") mem_reg_valid := T_69 reg mem_reg_inst : UInt<32>, clock, reset when ex_reg_valid : mem_reg_inst := ex_reg_inst skip node killm = or(io.killm, io.nack_mem) node T_75 = eq(killm, UInt<1>("h00")) node T_76 = and(mem_reg_valid, T_75) reg wb_reg_valid : UInt<1>, clock, reset onreset wb_reg_valid := UInt<1>("h00") wb_reg_valid := T_76 inst fp_decoder of FPUDecoder fp_decoder.io.inst := UInt<1>("h00") fp_decoder.clock := clock fp_decoder.reset := reset fp_decoder.io.inst := io.inst reg ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset when io.valid : ex_ctrl <> fp_decoder.io.sigs skip reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset when ex_reg_valid : mem_ctrl <> ex_ctrl skip reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset when mem_reg_valid : wb_ctrl <> mem_ctrl skip reg load_wb : UInt<1>, clock, reset load_wb := io.dmem_resp_val node T_136 = eq(io.dmem_resp_type, UInt<3>("h02")) node T_137 = eq(io.dmem_resp_type, UInt<3>("h06")) node T_138 = or(T_136, T_137) reg load_wb_single : UInt<1>, clock, reset when io.dmem_resp_val : load_wb_single := T_138 skip reg load_wb_data : UInt<64>, clock, reset when io.dmem_resp_val : load_wb_data := io.dmem_resp_data skip reg load_wb_tag : UInt<5>, clock, reset when io.dmem_resp_val : load_wb_tag := io.dmem_resp_tag skip node T_142 = bit(load_wb_data, 31) node T_143 = bits(load_wb_data, 30, 23) node T_144 = bits(load_wb_data, 22, 0) node T_146 = eq(T_143, UInt<1>("h00")) node T_148 = eq(T_144, UInt<1>("h00")) node T_149 = and(T_146, T_148) node T_151 = eq(T_148, UInt<1>("h00")) node T_152 = and(T_146, T_151) node T_153 = shl(T_144, 9) node T_154 = bit(T_153, 31) node T_156 = bit(T_153, 30) node T_158 = bit(T_153, 29) node T_160 = bit(T_153, 28) node T_162 = bit(T_153, 27) node T_164 = bit(T_153, 26) node T_166 = bit(T_153, 25) node T_168 = bit(T_153, 24) node T_170 = bit(T_153, 23) node T_172 = bit(T_153, 22) node T_174 = bit(T_153, 21) node T_176 = bit(T_153, 20) node T_178 = bit(T_153, 19) node T_180 = bit(T_153, 18) node T_182 = bit(T_153, 17) node T_184 = bit(T_153, 16) node T_186 = bit(T_153, 15) node T_188 = bit(T_153, 14) node T_190 = bit(T_153, 13) node T_192 = bit(T_153, 12) node T_194 = bit(T_153, 11) node T_196 = bit(T_153, 10) node T_198 = bit(T_153, 9) node T_200 = bit(T_153, 8) node T_202 = bit(T_153, 7) node T_204 = bit(T_153, 6) node T_206 = bit(T_153, 5) node T_208 = bit(T_153, 4) node T_210 = bit(T_153, 3) node T_212 = bit(T_153, 2) node T_214 = bit(T_153, 1) node T_215 = shl(T_214, 0) node T_216 = mux(T_212, UInt<2>("h02"), T_215) node T_217 = mux(T_210, UInt<2>("h03"), T_216) node T_218 = mux(T_208, UInt<3>("h04"), T_217) node T_219 = mux(T_206, UInt<3>("h05"), T_218) node T_220 = mux(T_204, UInt<3>("h06"), T_219) node T_221 = mux(T_202, UInt<3>("h07"), T_220) node T_222 = mux(T_200, UInt<4>("h08"), T_221) node T_223 = mux(T_198, UInt<4>("h09"), T_222) node T_224 = mux(T_196, UInt<4>("h0a"), T_223) node T_225 = mux(T_194, UInt<4>("h0b"), T_224) node T_226 = mux(T_192, UInt<4>("h0c"), T_225) node T_227 = mux(T_190, UInt<4>("h0d"), T_226) node T_228 = mux(T_188, UInt<4>("h0e"), T_227) node T_229 = mux(T_186, UInt<4>("h0f"), T_228) node T_230 = mux(T_184, UInt<5>("h010"), T_229) node T_231 = mux(T_182, UInt<5>("h011"), T_230) node T_232 = mux(T_180, UInt<5>("h012"), T_231) node T_233 = mux(T_178, UInt<5>("h013"), T_232) node T_234 = mux(T_176, UInt<5>("h014"), T_233) node T_235 = mux(T_174, UInt<5>("h015"), T_234) node T_236 = mux(T_172, UInt<5>("h016"), T_235) node T_237 = mux(T_170, UInt<5>("h017"), T_236) node T_238 = mux(T_168, UInt<5>("h018"), T_237) node T_239 = mux(T_166, UInt<5>("h019"), T_238) node T_240 = mux(T_164, UInt<5>("h01a"), T_239) node T_241 = mux(T_162, UInt<5>("h01b"), T_240) node T_242 = mux(T_160, UInt<5>("h01c"), T_241) node T_243 = mux(T_158, UInt<5>("h01d"), T_242) node T_244 = mux(T_156, UInt<5>("h01e"), T_243) node T_245 = mux(T_154, UInt<5>("h01f"), T_244) node T_246 = not(T_245) node T_247 = dshl(T_153, T_246) node T_250 = subw(UInt<4>("h00"), UInt<1>("h01")) node T_251 = not(T_246) node T_252 = cat(T_250, T_251) node T_253 = bits(T_247, 30, 8) node T_255 = mux(T_148, UInt<1>("h00"), T_252) node T_256 = mux(T_146, T_255, T_143) node T_261 = mux(T_152, UInt<2>("h02"), UInt<1>("h01")) node T_262 = or(UInt<8>("h080"), T_261) node T_263 = mux(T_149, UInt<1>("h00"), T_262) node T_264 = addw(T_256, T_263) node T_265 = bits(T_264, 8, 7) node T_266 = not(T_265) node T_268 = eq(T_266, UInt<1>("h00")) node T_270 = eq(T_148, UInt<1>("h00")) node T_271 = and(T_268, T_270) node T_272 = shl(T_271, 6) node T_273 = or(T_264, T_272) node T_274 = mux(T_146, T_253, T_144) node T_275 = cat(T_273, T_274) node rec_s = cat(T_142, T_275) node T_277 = bit(load_wb_data, 63) node T_278 = bits(load_wb_data, 62, 52) node T_279 = bits(load_wb_data, 51, 0) node T_281 = eq(T_278, UInt<1>("h00")) node T_283 = eq(T_279, UInt<1>("h00")) node T_284 = and(T_281, T_283) node T_286 = eq(T_283, UInt<1>("h00")) node T_287 = and(T_281, T_286) node T_288 = shl(T_279, 12) node T_289 = bit(T_288, 63) node T_291 = bit(T_288, 62) node T_293 = bit(T_288, 61) node T_295 = bit(T_288, 60) node T_297 = bit(T_288, 59) node T_299 = bit(T_288, 58) node T_301 = bit(T_288, 57) node T_303 = bit(T_288, 56) node T_305 = bit(T_288, 55) node T_307 = bit(T_288, 54) node T_309 = bit(T_288, 53) node T_311 = bit(T_288, 52) node T_313 = bit(T_288, 51) node T_315 = bit(T_288, 50) node T_317 = bit(T_288, 49) node T_319 = bit(T_288, 48) node T_321 = bit(T_288, 47) node T_323 = bit(T_288, 46) node T_325 = bit(T_288, 45) node T_327 = bit(T_288, 44) node T_329 = bit(T_288, 43) node T_331 = bit(T_288, 42) node T_333 = bit(T_288, 41) node T_335 = bit(T_288, 40) node T_337 = bit(T_288, 39) node T_339 = bit(T_288, 38) node T_341 = bit(T_288, 37) node T_343 = bit(T_288, 36) node T_345 = bit(T_288, 35) node T_347 = bit(T_288, 34) node T_349 = bit(T_288, 33) node T_351 = bit(T_288, 32) node T_353 = bit(T_288, 31) node T_355 = bit(T_288, 30) node T_357 = bit(T_288, 29) node T_359 = bit(T_288, 28) node T_361 = bit(T_288, 27) node T_363 = bit(T_288, 26) node T_365 = bit(T_288, 25) node T_367 = bit(T_288, 24) node T_369 = bit(T_288, 23) node T_371 = bit(T_288, 22) node T_373 = bit(T_288, 21) node T_375 = bit(T_288, 20) node T_377 = bit(T_288, 19) node T_379 = bit(T_288, 18) node T_381 = bit(T_288, 17) node T_383 = bit(T_288, 16) node T_385 = bit(T_288, 15) node T_387 = bit(T_288, 14) node T_389 = bit(T_288, 13) node T_391 = bit(T_288, 12) node T_393 = bit(T_288, 11) node T_395 = bit(T_288, 10) node T_397 = bit(T_288, 9) node T_399 = bit(T_288, 8) node T_401 = bit(T_288, 7) node T_403 = bit(T_288, 6) node T_405 = bit(T_288, 5) node T_407 = bit(T_288, 4) node T_409 = bit(T_288, 3) node T_411 = bit(T_288, 2) node T_413 = bit(T_288, 1) node T_414 = shl(T_413, 0) node T_415 = mux(T_411, UInt<2>("h02"), T_414) node T_416 = mux(T_409, UInt<2>("h03"), T_415) node T_417 = mux(T_407, UInt<3>("h04"), T_416) node T_418 = mux(T_405, UInt<3>("h05"), T_417) node T_419 = mux(T_403, UInt<3>("h06"), T_418) node T_420 = mux(T_401, UInt<3>("h07"), T_419) node T_421 = mux(T_399, UInt<4>("h08"), T_420) node T_422 = mux(T_397, UInt<4>("h09"), T_421) node T_423 = mux(T_395, UInt<4>("h0a"), T_422) node T_424 = mux(T_393, UInt<4>("h0b"), T_423) node T_425 = mux(T_391, UInt<4>("h0c"), T_424) node T_426 = mux(T_389, UInt<4>("h0d"), T_425) node T_427 = mux(T_387, UInt<4>("h0e"), T_426) node T_428 = mux(T_385, UInt<4>("h0f"), T_427) node T_429 = mux(T_383, UInt<5>("h010"), T_428) node T_430 = mux(T_381, UInt<5>("h011"), T_429) node T_431 = mux(T_379, UInt<5>("h012"), T_430) node T_432 = mux(T_377, UInt<5>("h013"), T_431) node T_433 = mux(T_375, UInt<5>("h014"), T_432) node T_434 = mux(T_373, UInt<5>("h015"), T_433) node T_435 = mux(T_371, UInt<5>("h016"), T_434) node T_436 = mux(T_369, UInt<5>("h017"), T_435) node T_437 = mux(T_367, UInt<5>("h018"), T_436) node T_438 = mux(T_365, UInt<5>("h019"), T_437) node T_439 = mux(T_363, UInt<5>("h01a"), T_438) node T_440 = mux(T_361, UInt<5>("h01b"), T_439) node T_441 = mux(T_359, UInt<5>("h01c"), T_440) node T_442 = mux(T_357, UInt<5>("h01d"), T_441) node T_443 = mux(T_355, UInt<5>("h01e"), T_442) node T_444 = mux(T_353, UInt<5>("h01f"), T_443) node T_445 = mux(T_351, UInt<6>("h020"), T_444) node T_446 = mux(T_349, UInt<6>("h021"), T_445) node T_447 = mux(T_347, UInt<6>("h022"), T_446) node T_448 = mux(T_345, UInt<6>("h023"), T_447) node T_449 = mux(T_343, UInt<6>("h024"), T_448) node T_450 = mux(T_341, UInt<6>("h025"), T_449) node T_451 = mux(T_339, UInt<6>("h026"), T_450) node T_452 = mux(T_337, UInt<6>("h027"), T_451) node T_453 = mux(T_335, UInt<6>("h028"), T_452) node T_454 = mux(T_333, UInt<6>("h029"), T_453) node T_455 = mux(T_331, UInt<6>("h02a"), T_454) node T_456 = mux(T_329, UInt<6>("h02b"), T_455) node T_457 = mux(T_327, UInt<6>("h02c"), T_456) node T_458 = mux(T_325, UInt<6>("h02d"), T_457) node T_459 = mux(T_323, UInt<6>("h02e"), T_458) node T_460 = mux(T_321, UInt<6>("h02f"), T_459) node T_461 = mux(T_319, UInt<6>("h030"), T_460) node T_462 = mux(T_317, UInt<6>("h031"), T_461) node T_463 = mux(T_315, UInt<6>("h032"), T_462) node T_464 = mux(T_313, UInt<6>("h033"), T_463) node T_465 = mux(T_311, UInt<6>("h034"), T_464) node T_466 = mux(T_309, UInt<6>("h035"), T_465) node T_467 = mux(T_307, UInt<6>("h036"), T_466) node T_468 = mux(T_305, UInt<6>("h037"), T_467) node T_469 = mux(T_303, UInt<6>("h038"), T_468) node T_470 = mux(T_301, UInt<6>("h039"), T_469) node T_471 = mux(T_299, UInt<6>("h03a"), T_470) node T_472 = mux(T_297, UInt<6>("h03b"), T_471) node T_473 = mux(T_295, UInt<6>("h03c"), T_472) node T_474 = mux(T_293, UInt<6>("h03d"), T_473) node T_475 = mux(T_291, UInt<6>("h03e"), T_474) node T_476 = mux(T_289, UInt<6>("h03f"), T_475) node T_477 = not(T_476) node T_478 = dshl(T_288, T_477) node T_481 = subw(UInt<6>("h00"), UInt<1>("h01")) node T_482 = not(T_477) node T_483 = cat(T_481, T_482) node T_484 = bits(T_478, 62, 11) node T_486 = mux(T_283, UInt<1>("h00"), T_483) node T_487 = mux(T_281, T_486, T_278) node T_492 = mux(T_287, UInt<2>("h02"), UInt<1>("h01")) node T_493 = or(UInt<11>("h0400"), T_492) node T_494 = mux(T_284, UInt<1>("h00"), T_493) node T_495 = addw(T_487, T_494) node T_496 = bits(T_495, 11, 10) node T_497 = not(T_496) node T_499 = eq(T_497, UInt<1>("h00")) node T_501 = eq(T_283, UInt<1>("h00")) node T_502 = and(T_499, T_501) node T_503 = shl(T_502, 9) node T_504 = or(T_495, T_503) node T_505 = mux(T_281, T_484, T_279) node T_506 = cat(T_504, T_505) node rec_d = cat(T_277, T_506) node T_509 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_510 = cat(T_509, rec_s) node load_wb_data_recoded = mux(load_wb_single, T_510, rec_d) cmem regfile : UInt<65>[32], clock when load_wb : infer accessor T_515 = regfile[load_wb_tag] T_515 := load_wb_data_recoded skip reg ex_ra1 : UInt, clock, reset reg ex_ra2 : UInt, clock, reset reg ex_ra3 : UInt, clock, reset when io.valid : when fp_decoder.io.sigs.ren1 : node T_523 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) when T_523 : node T_524 = bits(io.inst, 19, 15) ex_ra1 := T_524 skip when fp_decoder.io.sigs.swap12 : node T_525 = bits(io.inst, 19, 15) ex_ra2 := T_525 skip skip when fp_decoder.io.sigs.ren2 : when fp_decoder.io.sigs.swap12 : node T_526 = bits(io.inst, 24, 20) ex_ra1 := T_526 skip when fp_decoder.io.sigs.swap23 : node T_527 = bits(io.inst, 24, 20) ex_ra3 := T_527 skip node T_529 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) node T_531 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) node T_532 = and(T_529, T_531) when T_532 : node T_533 = bits(io.inst, 24, 20) ex_ra2 := T_533 skip skip when fp_decoder.io.sigs.ren3 : node T_534 = bits(io.inst, 31, 27) ex_ra3 := T_534 skip skip infer accessor ex_rs1 = regfile[ex_ra1] infer accessor ex_rs2 = regfile[ex_ra2] infer accessor ex_rs3 = regfile[ex_ra3] node T_538 = bits(ex_reg_inst, 14, 12) node T_540 = eq(T_538, UInt<3>("h07")) node T_541 = bits(ex_reg_inst, 14, 12) node ex_rm = mux(T_540, io.fcsr_rm, T_541) wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} req.in3 := UInt<1>("h00") req.in2 := UInt<1>("h00") req.in1 := UInt<1>("h00") req.typ := UInt<1>("h00") req.rm := UInt<1>("h00") req.wflags := UInt<1>("h00") req.round := UInt<1>("h00") req.sqrt := UInt<1>("h00") req.div := UInt<1>("h00") req.fma := UInt<1>("h00") req.fastpipe := UInt<1>("h00") req.toint := UInt<1>("h00") req.fromint := UInt<1>("h00") req.single := UInt<1>("h00") req.swap23 := UInt<1>("h00") req.swap12 := UInt<1>("h00") req.ren3 := UInt<1>("h00") req.ren2 := UInt<1>("h00") req.ren1 := UInt<1>("h00") req.wen := UInt<1>("h00") req.ldst := UInt<1>("h00") req.cmd := UInt<1>("h00") req <> ex_ctrl req.rm := ex_rm req.in1 := ex_rs1 req.in2 := ex_rs2 req.in3 := ex_rs3 node T_611 = bits(ex_reg_inst, 21, 20) req.typ := T_611 inst sfma of FPUFMAPipe sfma.io.in.bits.in3 := UInt<1>("h00") sfma.io.in.bits.in2 := UInt<1>("h00") sfma.io.in.bits.in1 := UInt<1>("h00") sfma.io.in.bits.typ := UInt<1>("h00") sfma.io.in.bits.rm := UInt<1>("h00") sfma.io.in.bits.wflags := UInt<1>("h00") sfma.io.in.bits.round := UInt<1>("h00") sfma.io.in.bits.sqrt := UInt<1>("h00") sfma.io.in.bits.div := UInt<1>("h00") sfma.io.in.bits.fma := UInt<1>("h00") sfma.io.in.bits.fastpipe := UInt<1>("h00") sfma.io.in.bits.toint := UInt<1>("h00") sfma.io.in.bits.fromint := UInt<1>("h00") sfma.io.in.bits.single := UInt<1>("h00") sfma.io.in.bits.swap23 := UInt<1>("h00") sfma.io.in.bits.swap12 := UInt<1>("h00") sfma.io.in.bits.ren3 := UInt<1>("h00") sfma.io.in.bits.ren2 := UInt<1>("h00") sfma.io.in.bits.ren1 := UInt<1>("h00") sfma.io.in.bits.wen := UInt<1>("h00") sfma.io.in.bits.ldst := UInt<1>("h00") sfma.io.in.bits.cmd := UInt<1>("h00") sfma.io.in.valid := UInt<1>("h00") sfma.clock := clock sfma.reset := reset node T_636 = and(ex_reg_valid, ex_ctrl.fma) node T_637 = and(T_636, ex_ctrl.single) sfma.io.in.valid := T_637 sfma.io.in.bits <> req inst dfma of FPUFMAPipe_100 dfma.io.in.bits.in3 := UInt<1>("h00") dfma.io.in.bits.in2 := UInt<1>("h00") dfma.io.in.bits.in1 := UInt<1>("h00") dfma.io.in.bits.typ := UInt<1>("h00") dfma.io.in.bits.rm := UInt<1>("h00") dfma.io.in.bits.wflags := UInt<1>("h00") dfma.io.in.bits.round := UInt<1>("h00") dfma.io.in.bits.sqrt := UInt<1>("h00") dfma.io.in.bits.div := UInt<1>("h00") dfma.io.in.bits.fma := UInt<1>("h00") dfma.io.in.bits.fastpipe := UInt<1>("h00") dfma.io.in.bits.toint := UInt<1>("h00") dfma.io.in.bits.fromint := UInt<1>("h00") dfma.io.in.bits.single := UInt<1>("h00") dfma.io.in.bits.swap23 := UInt<1>("h00") dfma.io.in.bits.swap12 := UInt<1>("h00") dfma.io.in.bits.ren3 := UInt<1>("h00") dfma.io.in.bits.ren2 := UInt<1>("h00") dfma.io.in.bits.ren1 := UInt<1>("h00") dfma.io.in.bits.wen := UInt<1>("h00") dfma.io.in.bits.ldst := UInt<1>("h00") dfma.io.in.bits.cmd := UInt<1>("h00") dfma.io.in.valid := UInt<1>("h00") dfma.clock := clock dfma.reset := reset node T_662 = and(ex_reg_valid, ex_ctrl.fma) node T_664 = eq(ex_ctrl.single, UInt<1>("h00")) node T_665 = and(T_662, T_664) dfma.io.in.valid := T_665 dfma.io.in.bits <> req inst fpiu of FPToInt fpiu.io.in.bits.in3 := UInt<1>("h00") fpiu.io.in.bits.in2 := UInt<1>("h00") fpiu.io.in.bits.in1 := UInt<1>("h00") fpiu.io.in.bits.typ := UInt<1>("h00") fpiu.io.in.bits.rm := UInt<1>("h00") fpiu.io.in.bits.wflags := UInt<1>("h00") fpiu.io.in.bits.round := UInt<1>("h00") fpiu.io.in.bits.sqrt := UInt<1>("h00") fpiu.io.in.bits.div := UInt<1>("h00") fpiu.io.in.bits.fma := UInt<1>("h00") fpiu.io.in.bits.fastpipe := UInt<1>("h00") fpiu.io.in.bits.toint := UInt<1>("h00") fpiu.io.in.bits.fromint := UInt<1>("h00") fpiu.io.in.bits.single := UInt<1>("h00") fpiu.io.in.bits.swap23 := UInt<1>("h00") fpiu.io.in.bits.swap12 := UInt<1>("h00") fpiu.io.in.bits.ren3 := UInt<1>("h00") fpiu.io.in.bits.ren2 := UInt<1>("h00") fpiu.io.in.bits.ren1 := UInt<1>("h00") fpiu.io.in.bits.wen := UInt<1>("h00") fpiu.io.in.bits.ldst := UInt<1>("h00") fpiu.io.in.bits.cmd := UInt<1>("h00") fpiu.io.in.valid := UInt<1>("h00") fpiu.clock := clock fpiu.reset := reset node T_690 = or(ex_ctrl.toint, ex_ctrl.div) node T_691 = or(T_690, ex_ctrl.sqrt) node T_694 = and(ex_ctrl.cmd, UInt<4>("h0d")) node T_695 = eq(UInt<3>("h05"), T_694) node T_696 = or(T_691, T_695) node T_697 = and(ex_reg_valid, T_696) fpiu.io.in.valid := T_697 fpiu.io.in.bits <> req io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint inst ifpu of IntToFP ifpu.io.in.bits.in3 := UInt<1>("h00") ifpu.io.in.bits.in2 := UInt<1>("h00") ifpu.io.in.bits.in1 := UInt<1>("h00") ifpu.io.in.bits.typ := UInt<1>("h00") ifpu.io.in.bits.rm := UInt<1>("h00") ifpu.io.in.bits.wflags := UInt<1>("h00") ifpu.io.in.bits.round := UInt<1>("h00") ifpu.io.in.bits.sqrt := UInt<1>("h00") ifpu.io.in.bits.div := UInt<1>("h00") ifpu.io.in.bits.fma := UInt<1>("h00") ifpu.io.in.bits.fastpipe := UInt<1>("h00") ifpu.io.in.bits.toint := UInt<1>("h00") ifpu.io.in.bits.fromint := UInt<1>("h00") ifpu.io.in.bits.single := UInt<1>("h00") ifpu.io.in.bits.swap23 := UInt<1>("h00") ifpu.io.in.bits.swap12 := UInt<1>("h00") ifpu.io.in.bits.ren3 := UInt<1>("h00") ifpu.io.in.bits.ren2 := UInt<1>("h00") ifpu.io.in.bits.ren1 := UInt<1>("h00") ifpu.io.in.bits.wen := UInt<1>("h00") ifpu.io.in.bits.ldst := UInt<1>("h00") ifpu.io.in.bits.cmd := UInt<1>("h00") ifpu.io.in.valid := UInt<1>("h00") ifpu.clock := clock ifpu.reset := reset node T_722 = and(ex_reg_valid, ex_ctrl.fromint) ifpu.io.in.valid := T_722 ifpu.io.in.bits <> req ifpu.io.in.bits.in1 := io.fromint_data inst fpmu of FPToFP fpmu.io.lt := UInt<1>("h00") fpmu.io.in.bits.in3 := UInt<1>("h00") fpmu.io.in.bits.in2 := UInt<1>("h00") fpmu.io.in.bits.in1 := UInt<1>("h00") fpmu.io.in.bits.typ := UInt<1>("h00") fpmu.io.in.bits.rm := UInt<1>("h00") fpmu.io.in.bits.wflags := UInt<1>("h00") fpmu.io.in.bits.round := UInt<1>("h00") fpmu.io.in.bits.sqrt := UInt<1>("h00") fpmu.io.in.bits.div := UInt<1>("h00") fpmu.io.in.bits.fma := UInt<1>("h00") fpmu.io.in.bits.fastpipe := UInt<1>("h00") fpmu.io.in.bits.toint := UInt<1>("h00") fpmu.io.in.bits.fromint := UInt<1>("h00") fpmu.io.in.bits.single := UInt<1>("h00") fpmu.io.in.bits.swap23 := UInt<1>("h00") fpmu.io.in.bits.swap12 := UInt<1>("h00") fpmu.io.in.bits.ren3 := UInt<1>("h00") fpmu.io.in.bits.ren2 := UInt<1>("h00") fpmu.io.in.bits.ren1 := UInt<1>("h00") fpmu.io.in.bits.wen := UInt<1>("h00") fpmu.io.in.bits.ldst := UInt<1>("h00") fpmu.io.in.bits.cmd := UInt<1>("h00") fpmu.io.in.valid := UInt<1>("h00") fpmu.clock := clock fpmu.reset := reset node T_748 = and(ex_reg_valid, ex_ctrl.fastpipe) fpmu.io.in.valid := T_748 fpmu.io.in.bits <> req fpmu.io.lt := fpiu.io.out.bits.lt reg divSqrt_wen : UInt<1>, clock, reset divSqrt_wen := UInt<1>("h00") wire divSqrt_inReady : UInt<1> divSqrt_inReady := UInt<1>("h00") reg divSqrt_waddr : UInt, clock, reset wire divSqrt_wdata : UInt divSqrt_wdata := UInt<1>("h00") wire divSqrt_flags : UInt divSqrt_flags := UInt<1>("h00") reg divSqrt_in_flight : UInt<1>, clock, reset onreset divSqrt_in_flight := UInt<1>("h00") node T_765 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) node T_768 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) node T_769 = and(mem_ctrl.fma, mem_ctrl.single) node T_772 = mux(T_769, UInt<1>("h01"), UInt<1>("h00")) node T_774 = eq(mem_ctrl.single, UInt<1>("h00")) node T_775 = and(mem_ctrl.fma, T_774) node T_778 = mux(T_775, UInt<2>("h02"), UInt<1>("h00")) node T_779 = or(T_765, T_768) node T_780 = or(T_779, T_772) node memLatencyMask = or(T_780, T_778) reg wen : UInt<2>, clock, reset onreset wen := UInt<2>("h00") reg winfo : UInt[2], clock, reset node T_796 = or(mem_ctrl.fma, mem_ctrl.fastpipe) node T_797 = or(T_796, mem_ctrl.fromint) node mem_wen = and(mem_reg_valid, T_797) node T_801 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) node T_804 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) node T_805 = and(ex_ctrl.fma, ex_ctrl.single) node T_808 = mux(T_805, UInt<2>("h02"), UInt<1>("h00")) node T_810 = eq(ex_ctrl.single, UInt<1>("h00")) node T_811 = and(ex_ctrl.fma, T_810) node T_814 = mux(T_811, UInt<3>("h04"), UInt<1>("h00")) node T_815 = or(T_801, T_804) node T_816 = or(T_815, T_808) node T_817 = or(T_816, T_814) node T_818 = and(memLatencyMask, T_817) node T_820 = neq(T_818, UInt<1>("h00")) node T_821 = and(mem_wen, T_820) node T_824 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) node T_827 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) node T_828 = and(ex_ctrl.fma, ex_ctrl.single) node T_831 = mux(T_828, UInt<3>("h04"), UInt<1>("h00")) node T_833 = eq(ex_ctrl.single, UInt<1>("h00")) node T_834 = and(ex_ctrl.fma, T_833) node T_837 = mux(T_834, UInt<4>("h08"), UInt<1>("h00")) node T_838 = or(T_824, T_827) node T_839 = or(T_838, T_831) node T_840 = or(T_839, T_837) node T_841 = and(wen, T_840) node T_843 = neq(T_841, UInt<1>("h00")) node T_844 = or(T_821, T_843) reg write_port_busy : UInt<1>, clock, reset when ex_reg_valid : write_port_busy := T_844 skip node T_848 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) node T_851 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) node T_852 = and(mem_ctrl.fma, mem_ctrl.single) node T_855 = mux(T_852, UInt<2>("h02"), UInt<1>("h00")) node T_857 = eq(mem_ctrl.single, UInt<1>("h00")) node T_858 = and(mem_ctrl.fma, T_857) node T_861 = mux(T_858, UInt<2>("h03"), UInt<1>("h00")) node T_862 = or(T_848, T_851) node T_863 = or(T_862, T_855) node T_864 = or(T_863, T_861) node T_865 = bits(mem_reg_inst, 11, 7) node T_866 = cat(mem_ctrl.single, T_865) node mem_winfo = cat(T_864, T_866) node T_868 = bit(wen, 1) when T_868 : winfo[0] := winfo[1] skip node T_869 = shr(wen, 1) wen := T_869 when mem_wen : node T_871 = eq(killm, UInt<1>("h00")) when T_871 : node T_872 = shr(wen, 1) node T_873 = or(T_872, memLatencyMask) wen := T_873 skip node T_875 = eq(write_port_busy, UInt<1>("h00")) node T_876 = bit(memLatencyMask, 0) node T_877 = and(T_875, T_876) when T_877 : winfo[0] := mem_winfo skip node T_879 = eq(write_port_busy, UInt<1>("h00")) node T_880 = bit(memLatencyMask, 1) node T_881 = and(T_879, T_880) when T_881 : winfo[1] := mem_winfo skip skip node T_882 = bits(winfo[0], 4, 0) node waddr = mux(divSqrt_wen, divSqrt_waddr, T_882) node wsrc = shr(winfo[0], 6) wire T_886 : UInt<65>[4] T_886[0] := fpmu.io.out.bits.data T_886[1] := ifpu.io.out.bits.data T_886[2] := sfma.io.out.bits.data T_886[3] := dfma.io.out.bits.data infer accessor T_892 = T_886[wsrc] node wdata = mux(divSqrt_wen, divSqrt_wdata, T_892) wire T_895 : UInt<5>[4] T_895[0] := fpmu.io.out.bits.exc T_895[1] := ifpu.io.out.bits.exc T_895[2] := sfma.io.out.bits.exc T_895[3] := dfma.io.out.bits.exc infer accessor wexc = T_895[wsrc] node T_902 = bit(wen, 0) node T_903 = or(T_902, divSqrt_wen) when T_903 : infer accessor T_904 = regfile[waddr] T_904 := wdata skip node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) reg wb_toint_exc : UInt<5>, clock, reset when mem_ctrl.toint : wb_toint_exc := fpiu.io.out.bits.exc skip node T_907 = or(wb_toint_valid, divSqrt_wen) node T_908 = bit(wen, 0) node T_909 = or(T_907, T_908) io.fcsr_flags.valid := T_909 node T_911 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) node T_913 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) node T_914 = or(T_911, T_913) node T_915 = bit(wen, 0) node T_917 = mux(T_915, wexc, UInt<1>("h00")) node T_918 = or(T_914, T_917) io.fcsr_flags.bits := T_918 node T_919 = or(mem_ctrl.div, mem_ctrl.sqrt) node T_920 = and(mem_reg_valid, T_919) node T_922 = eq(divSqrt_inReady, UInt<1>("h00")) node T_924 = neq(wen, UInt<1>("h00")) node T_925 = or(T_922, T_924) node units_busy = and(T_920, T_925) node T_927 = and(ex_reg_valid, ex_ctrl.wflags) node T_928 = and(mem_reg_valid, mem_ctrl.wflags) node T_929 = or(T_927, T_928) node T_930 = and(wb_reg_valid, wb_ctrl.toint) node T_931 = or(T_929, T_930) node T_933 = neq(wen, UInt<1>("h00")) node T_934 = or(T_931, T_933) node T_935 = or(T_934, divSqrt_in_flight) node T_937 = eq(T_935, UInt<1>("h00")) io.fcsr_rdy := T_937 node T_938 = or(units_busy, write_port_busy) node T_939 = or(T_938, divSqrt_in_flight) io.nack_mem := T_939 io.dec <> fp_decoder.io.sigs node T_941 = or(UInt<1>("h00"), mem_ctrl.div) node T_942 = or(T_941, mem_ctrl.sqrt) reg T_943 : UInt<1>, clock, reset T_943 := T_942 node T_944 = and(wb_reg_valid, T_943) io.sboard_set := T_944 node T_945 = bit(wen, 0) node T_947 = and(T_945, UInt<1>("h00")) node T_948 = or(divSqrt_wen, T_947) io.sboard_clr := T_948 io.sboard_clra := waddr node T_949 = bit(ex_rm, 2) node T_950 = and(T_949, ex_ctrl.round) io.illegal_rm := T_950 divSqrt_wdata := UInt<1>("h00") divSqrt_flags := UInt<1>("h00") reg T_954 : UInt<1>, clock, reset reg T_956 : UInt, clock, reset reg T_958 : UInt, clock, reset reg T_960 : UInt, clock, reset inst T_961 of divSqrtRecodedFloat64 T_961.io.roundingMode := UInt<1>("h00") T_961.io.b := UInt<1>("h00") T_961.io.a := UInt<1>("h00") T_961.io.sqrtOp := UInt<1>("h00") T_961.io.inValid := UInt<1>("h00") T_961.clock := clock T_961.reset := reset node T_967 = mux(T_961.io.sqrtOp, T_961.io.inReady_sqrt, T_961.io.inReady_div) divSqrt_inReady := T_967 node T_968 = or(T_961.io.outValid_div, T_961.io.outValid_sqrt) node T_970 = neq(wen, UInt<1>("h00")) node T_972 = eq(T_970, UInt<1>("h00")) node T_973 = and(mem_reg_valid, T_972) node T_975 = eq(divSqrt_in_flight, UInt<1>("h00")) node T_976 = and(T_973, T_975) node T_978 = eq(io.killm, UInt<1>("h00")) node T_979 = and(T_976, T_978) node T_980 = or(mem_ctrl.div, mem_ctrl.sqrt) node T_981 = and(T_979, T_980) T_961.io.inValid := T_981 T_961.io.sqrtOp := mem_ctrl.sqrt T_961.io.a := fpiu.io.as_double.in1 T_961.io.b := fpiu.io.as_double.in2 T_961.io.roundingMode := fpiu.io.as_double.rm node T_982 = and(T_961.io.inValid, divSqrt_inReady) when T_982 : divSqrt_in_flight := UInt<1>("h01") T_954 := mem_ctrl.single node T_984 = bits(mem_reg_inst, 11, 7) divSqrt_waddr := T_984 T_956 := T_961.io.roundingMode skip when T_968 : divSqrt_wen := UInt<1>("h01") T_960 := T_961.io.out divSqrt_in_flight := UInt<1>("h00") T_958 := T_961.io.exceptionFlags skip node T_987 = bit(T_960, 64) node T_988 = bits(T_960, 51, 0) node T_989 = bits(T_960, 63, 52) node T_990 = bits(T_960, 63, 61) node T_991 = bits(T_960, 62, 52) node T_992 = not(T_990) node T_994 = eq(T_992, UInt<1>("h00")) node T_995 = bit(T_988, 51) node T_997 = eq(T_995, UInt<1>("h00")) node T_998 = and(T_994, T_997) node T_1003 = neq(T_990, UInt<1>("h00")) node T_1005 = eq(T_1003, UInt<1>("h00")) node T_1006 = bits(T_990, 2, 1) node T_1007 = not(T_1006) node T_1009 = eq(T_1007, UInt<1>("h00")) node T_1010 = or(T_1005, T_1009) node T_1011 = geq(T_989, UInt<11>("h076a")) node T_1012 = leq(T_989, UInt<11>("h0781")) node T_1013 = and(T_1011, T_1012) node T_1014 = lt(T_989, UInt<11>("h076a")) node T_1016 = eq(T_1010, UInt<1>("h00")) node T_1017 = and(T_1014, T_1016) node T_1018 = gt(T_989, UInt<12>("h087f")) node T_1020 = eq(T_1010, UInt<1>("h00")) node T_1021 = and(T_1018, T_1020) node T_1023 = addw(UInt<11>("h0781"), UInt<1>("h01")) node T_1024 = subw(T_1023, T_989) node T_1026 = mux(T_1013, T_1024, UInt<1>("h00")) node T_1027 = bits(T_1026, 4, 0) node T_1029 = bits(T_988, 51, 28) node T_1031 = cat(T_1029, UInt<24>("h00")) node T_1032 = cat(UInt<1>("h01"), T_1031) node T_1033 = dshr(T_1032, T_1027) node T_1034 = bits(T_1033, 23, 0) node T_1036 = neq(T_1034, UInt<1>("h00")) node T_1037 = bits(T_988, 27, 0) node T_1039 = neq(T_1037, UInt<1>("h00")) node T_1040 = or(T_1036, T_1039) node T_1041 = bits(T_1033, 25, 24) node T_1042 = cat(T_1041, T_1040) node T_1043 = bits(T_1042, 1, 0) node T_1045 = neq(T_1043, UInt<1>("h00")) node T_1047 = eq(T_1010, UInt<1>("h00")) node T_1048 = and(T_1045, T_1047) node T_1049 = eq(ex_rm, UInt<2>("h00")) node T_1050 = bits(T_1042, 1, 0) node T_1051 = not(T_1050) node T_1053 = eq(T_1051, UInt<1>("h00")) node T_1054 = bits(T_1042, 2, 1) node T_1055 = not(T_1054) node T_1057 = eq(T_1055, UInt<1>("h00")) node T_1058 = or(T_1053, T_1057) node T_1059 = eq(ex_rm, UInt<2>("h02")) node T_1060 = and(T_987, T_1048) node T_1061 = eq(ex_rm, UInt<2>("h03")) node T_1063 = eq(T_987, UInt<1>("h00")) node T_1064 = and(T_1063, T_1048) node T_1066 = mux(T_1061, T_1064, UInt<1>("h00")) node T_1067 = mux(T_1059, T_1060, T_1066) node T_1068 = mux(T_1049, T_1058, T_1067) node T_1070 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_1071 = cat(T_1070, T_1070) node T_1072 = cat(T_1071, T_1071) node T_1073 = cat(T_1072, T_1072) node T_1074 = cat(T_1072, T_1073) node T_1075 = cat(UInt<1>("h01"), T_1074) node T_1076 = dshl(T_1075, T_1027) node T_1077 = bits(T_1076, 24, 0) node T_1079 = bits(T_988, 51, 29) node T_1080 = cat(UInt<2>("h01"), T_1079) node T_1081 = not(T_1077) node T_1082 = or(T_1080, T_1081) node T_1084 = addw(T_1082, UInt<1>("h01")) node T_1085 = mux(T_1068, T_1084, T_1082) node T_1086 = and(T_1085, T_1077) node T_1087 = bits(T_989, 8, 0) node T_1089 = addw(T_1087, UInt<9>("h0100")) node T_1090 = bit(T_1086, 24) node T_1092 = addw(T_1089, UInt<1>("h01")) node T_1093 = mux(T_1090, T_1092, T_1089) node T_1094 = eq(ex_rm, UInt<2>("h02")) node T_1095 = and(T_1094, T_987) node T_1096 = eq(ex_rm, UInt<2>("h03")) node T_1098 = eq(T_987, UInt<1>("h00")) node T_1099 = and(T_1096, T_1098) node T_1100 = or(T_1095, T_1099) node T_1101 = eq(ex_rm, UInt<2>("h00")) node T_1102 = or(T_1100, T_1101) node T_1104 = eq(T_1102, UInt<1>("h00")) node T_1106 = subw(UInt<23>("h00"), T_1104) node T_1109 = mux(T_1102, UInt<9>("h0180"), UInt<9>("h017f")) node T_1113 = mux(T_1100, UInt<7>("h06b"), UInt<1>("h00")) node T_1114 = shl(T_990, 6) node T_1115 = mux(T_1017, T_1113, T_1093) node T_1116 = mux(T_1021, T_1109, T_1115) node T_1117 = mux(T_1010, T_1114, T_1116) node T_1119 = subw(UInt<23>("h00"), T_994) node T_1120 = bits(T_1086, 22, 0) node T_1121 = mux(T_1017, UInt<1>("h00"), T_1120) node T_1122 = mux(T_1021, T_1106, T_1121) node T_1123 = mux(T_1010, T_1119, T_1122) node T_1124 = cat(T_1117, T_1123) node T_1125 = cat(T_987, T_1124) node T_1126 = and(T_1013, T_1048) node T_1127 = or(T_1017, T_1126) node T_1128 = eq(T_989, UInt<12>("h087f")) node T_1129 = bit(T_1086, 24) node T_1130 = and(T_1128, T_1129) node T_1131 = or(T_1021, T_1130) node T_1133 = or(T_1048, T_1021) node T_1134 = or(T_1133, T_1017) node T_1135 = cat(T_998, UInt<1>("h00")) node T_1136 = cat(T_1127, T_1134) node T_1137 = cat(T_1131, T_1136) node T_1138 = cat(T_1135, T_1137) node T_1139 = mux(T_954, T_1125, T_960) divSqrt_wdata := T_1139 node T_1141 = mux(T_954, T_1138, UInt<1>("h00")) node T_1142 = or(T_958, T_1141) divSqrt_flags := T_1142 module RocketTile : input clock : Clock input reset : UInt<1> output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}, uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}} io.host.debug_stats_pcr := UInt<1>("h00") io.host.ipi_rep.ready := UInt<1>("h00") io.host.ipi_req.bits := UInt<1>("h00") io.host.ipi_req.valid := UInt<1>("h00") io.host.pcr.resp.bits := UInt<1>("h00") io.host.pcr.resp.valid := UInt<1>("h00") io.host.pcr.req.ready := UInt<1>("h00") io.uncached.grant.ready := UInt<1>("h00") io.uncached.acquire.bits.union := UInt<1>("h00") io.uncached.acquire.bits.a_type := UInt<1>("h00") io.uncached.acquire.bits.is_builtin_type := UInt<1>("h00") io.uncached.acquire.bits.data := UInt<1>("h00") io.uncached.acquire.bits.addr_beat := UInt<1>("h00") io.uncached.acquire.bits.client_xact_id := UInt<1>("h00") io.uncached.acquire.bits.addr_block := UInt<1>("h00") io.uncached.acquire.valid := UInt<1>("h00") io.cached.release.bits.voluntary := UInt<1>("h00") io.cached.release.bits.r_type := UInt<1>("h00") io.cached.release.bits.data := UInt<1>("h00") io.cached.release.bits.addr_beat := UInt<1>("h00") io.cached.release.bits.client_xact_id := UInt<1>("h00") io.cached.release.bits.addr_block := UInt<1>("h00") io.cached.release.valid := UInt<1>("h00") io.cached.probe.ready := UInt<1>("h00") io.cached.grant.ready := UInt<1>("h00") io.cached.acquire.bits.union := UInt<1>("h00") io.cached.acquire.bits.a_type := UInt<1>("h00") io.cached.acquire.bits.is_builtin_type := UInt<1>("h00") io.cached.acquire.bits.data := UInt<1>("h00") io.cached.acquire.bits.addr_beat := UInt<1>("h00") io.cached.acquire.bits.client_xact_id := UInt<1>("h00") io.cached.acquire.bits.addr_block := UInt<1>("h00") io.cached.acquire.valid := UInt<1>("h00") inst icache of Frontend icache.io.mem.grant.bits.g_type := UInt<1>("h00") icache.io.mem.grant.bits.is_builtin_type := UInt<1>("h00") icache.io.mem.grant.bits.manager_xact_id := UInt<1>("h00") icache.io.mem.grant.bits.client_xact_id := UInt<1>("h00") icache.io.mem.grant.bits.data := UInt<1>("h00") icache.io.mem.grant.bits.addr_beat := UInt<1>("h00") icache.io.mem.grant.valid := UInt<1>("h00") icache.io.mem.acquire.ready := UInt<1>("h00") icache.io.ptw.invalidate := UInt<1>("h00") icache.io.ptw.status.ie := UInt<1>("h00") icache.io.ptw.status.prv := UInt<1>("h00") icache.io.ptw.status.ie1 := UInt<1>("h00") icache.io.ptw.status.prv1 := UInt<1>("h00") icache.io.ptw.status.ie2 := UInt<1>("h00") icache.io.ptw.status.prv2 := UInt<1>("h00") icache.io.ptw.status.ie3 := UInt<1>("h00") icache.io.ptw.status.prv3 := UInt<1>("h00") icache.io.ptw.status.fs := UInt<1>("h00") icache.io.ptw.status.xs := UInt<1>("h00") icache.io.ptw.status.mprv := UInt<1>("h00") icache.io.ptw.status.vm := UInt<1>("h00") icache.io.ptw.status.zero1 := UInt<1>("h00") icache.io.ptw.status.sd_rv32 := UInt<1>("h00") icache.io.ptw.status.zero2 := UInt<1>("h00") icache.io.ptw.status.sd := UInt<1>("h00") icache.io.ptw.resp.bits.pte.v := UInt<1>("h00") icache.io.ptw.resp.bits.pte.typ := UInt<1>("h00") icache.io.ptw.resp.bits.pte.r := UInt<1>("h00") icache.io.ptw.resp.bits.pte.d := UInt<1>("h00") icache.io.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") icache.io.ptw.resp.bits.pte.ppn := UInt<1>("h00") icache.io.ptw.resp.bits.error := UInt<1>("h00") icache.io.ptw.resp.valid := UInt<1>("h00") icache.io.ptw.req.ready := UInt<1>("h00") icache.io.cpu.invalidate := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.entry := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.target := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.mask := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.taken := UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.valid := UInt<1>("h00") icache.io.cpu.ras_update.bits.returnAddr := UInt<1>("h00") icache.io.cpu.ras_update.bits.isReturn := UInt<1>("h00") icache.io.cpu.ras_update.bits.isCall := UInt<1>("h00") icache.io.cpu.ras_update.valid := UInt<1>("h00") icache.io.cpu.bht_update.bits.mispredict := UInt<1>("h00") icache.io.cpu.bht_update.bits.taken := UInt<1>("h00") icache.io.cpu.bht_update.bits.pc := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.entry := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.target := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.mask := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.taken := UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.valid := UInt<1>("h00") icache.io.cpu.bht_update.valid := UInt<1>("h00") icache.io.cpu.btb_update.bits.br_pc := UInt<1>("h00") icache.io.cpu.btb_update.bits.isReturn := UInt<1>("h00") icache.io.cpu.btb_update.bits.isJump := UInt<1>("h00") icache.io.cpu.btb_update.bits.taken := UInt<1>("h00") icache.io.cpu.btb_update.bits.target := UInt<1>("h00") icache.io.cpu.btb_update.bits.pc := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.entry := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.target := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.mask := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.taken := UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.valid := UInt<1>("h00") icache.io.cpu.btb_update.valid := UInt<1>("h00") icache.io.cpu.resp.ready := UInt<1>("h00") icache.io.cpu.req.bits.pc := UInt<1>("h00") icache.io.cpu.req.valid := UInt<1>("h00") icache.clock := clock icache.reset := reset inst dcache of HellaCache dcache.io.mem.release.ready := UInt<1>("h00") dcache.io.mem.probe.bits.p_type := UInt<1>("h00") dcache.io.mem.probe.bits.addr_block := UInt<1>("h00") dcache.io.mem.probe.valid := UInt<1>("h00") dcache.io.mem.grant.bits.g_type := UInt<1>("h00") dcache.io.mem.grant.bits.is_builtin_type := UInt<1>("h00") dcache.io.mem.grant.bits.manager_xact_id := UInt<1>("h00") dcache.io.mem.grant.bits.client_xact_id := UInt<1>("h00") dcache.io.mem.grant.bits.data := UInt<1>("h00") dcache.io.mem.grant.bits.addr_beat := UInt<1>("h00") dcache.io.mem.grant.valid := UInt<1>("h00") dcache.io.mem.acquire.ready := UInt<1>("h00") dcache.io.ptw.invalidate := UInt<1>("h00") dcache.io.ptw.status.ie := UInt<1>("h00") dcache.io.ptw.status.prv := UInt<1>("h00") dcache.io.ptw.status.ie1 := UInt<1>("h00") dcache.io.ptw.status.prv1 := UInt<1>("h00") dcache.io.ptw.status.ie2 := UInt<1>("h00") dcache.io.ptw.status.prv2 := UInt<1>("h00") dcache.io.ptw.status.ie3 := UInt<1>("h00") dcache.io.ptw.status.prv3 := UInt<1>("h00") dcache.io.ptw.status.fs := UInt<1>("h00") dcache.io.ptw.status.xs := UInt<1>("h00") dcache.io.ptw.status.mprv := UInt<1>("h00") dcache.io.ptw.status.vm := UInt<1>("h00") dcache.io.ptw.status.zero1 := UInt<1>("h00") dcache.io.ptw.status.sd_rv32 := UInt<1>("h00") dcache.io.ptw.status.zero2 := UInt<1>("h00") dcache.io.ptw.status.sd := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.v := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.typ := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.r := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.d := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") dcache.io.ptw.resp.bits.pte.ppn := UInt<1>("h00") dcache.io.ptw.resp.bits.error := UInt<1>("h00") dcache.io.ptw.resp.valid := UInt<1>("h00") dcache.io.ptw.req.ready := UInt<1>("h00") dcache.io.cpu.invalidate_lr := UInt<1>("h00") dcache.io.cpu.req.bits.data := UInt<1>("h00") dcache.io.cpu.req.bits.phys := UInt<1>("h00") dcache.io.cpu.req.bits.kill := UInt<1>("h00") dcache.io.cpu.req.bits.typ := UInt<1>("h00") dcache.io.cpu.req.bits.cmd := UInt<1>("h00") dcache.io.cpu.req.bits.tag := UInt<1>("h00") dcache.io.cpu.req.bits.addr := UInt<1>("h00") dcache.io.cpu.req.valid := UInt<1>("h00") dcache.clock := clock dcache.reset := reset inst ptw of PTW ptw.io.dpath.status.ie := UInt<1>("h00") ptw.io.dpath.status.prv := UInt<1>("h00") ptw.io.dpath.status.ie1 := UInt<1>("h00") ptw.io.dpath.status.prv1 := UInt<1>("h00") ptw.io.dpath.status.ie2 := UInt<1>("h00") ptw.io.dpath.status.prv2 := UInt<1>("h00") ptw.io.dpath.status.ie3 := UInt<1>("h00") ptw.io.dpath.status.prv3 := UInt<1>("h00") ptw.io.dpath.status.fs := UInt<1>("h00") ptw.io.dpath.status.xs := UInt<1>("h00") ptw.io.dpath.status.mprv := UInt<1>("h00") ptw.io.dpath.status.vm := UInt<1>("h00") ptw.io.dpath.status.zero1 := UInt<1>("h00") ptw.io.dpath.status.sd_rv32 := UInt<1>("h00") ptw.io.dpath.status.zero2 := UInt<1>("h00") ptw.io.dpath.status.sd := UInt<1>("h00") ptw.io.dpath.invalidate := UInt<1>("h00") ptw.io.dpath.ptbr := UInt<1>("h00") ptw.io.mem.ordered := UInt<1>("h00") ptw.io.mem.xcpt.pf.st := UInt<1>("h00") ptw.io.mem.xcpt.pf.ld := UInt<1>("h00") ptw.io.mem.xcpt.ma.st := UInt<1>("h00") ptw.io.mem.xcpt.ma.ld := UInt<1>("h00") ptw.io.mem.replay_next.bits := UInt<1>("h00") ptw.io.mem.replay_next.valid := UInt<1>("h00") ptw.io.mem.resp.bits.store_data := UInt<1>("h00") ptw.io.mem.resp.bits.data_word_bypass := UInt<1>("h00") ptw.io.mem.resp.bits.has_data := UInt<1>("h00") ptw.io.mem.resp.bits.replay := UInt<1>("h00") ptw.io.mem.resp.bits.nack := UInt<1>("h00") ptw.io.mem.resp.bits.data := UInt<1>("h00") ptw.io.mem.resp.bits.typ := UInt<1>("h00") ptw.io.mem.resp.bits.cmd := UInt<1>("h00") ptw.io.mem.resp.bits.tag := UInt<1>("h00") ptw.io.mem.resp.bits.addr := UInt<1>("h00") ptw.io.mem.resp.valid := UInt<1>("h00") ptw.io.mem.req.ready := UInt<1>("h00") ptw.io.requestor[0].req.bits.fetch := UInt<1>("h00") ptw.io.requestor[0].req.bits.store := UInt<1>("h00") ptw.io.requestor[0].req.bits.prv := UInt<1>("h00") ptw.io.requestor[0].req.bits.addr := UInt<1>("h00") ptw.io.requestor[0].req.valid := UInt<1>("h00") ptw.io.requestor[1].req.bits.fetch := UInt<1>("h00") ptw.io.requestor[1].req.bits.store := UInt<1>("h00") ptw.io.requestor[1].req.bits.prv := UInt<1>("h00") ptw.io.requestor[1].req.bits.addr := UInt<1>("h00") ptw.io.requestor[1].req.valid := UInt<1>("h00") ptw.clock := clock ptw.reset := reset inst core of Rocket core.io.rocc.pptw.req.bits.fetch := UInt<1>("h00") core.io.rocc.pptw.req.bits.store := UInt<1>("h00") core.io.rocc.pptw.req.bits.prv := UInt<1>("h00") core.io.rocc.pptw.req.bits.addr := UInt<1>("h00") core.io.rocc.pptw.req.valid := UInt<1>("h00") core.io.rocc.dptw.req.bits.fetch := UInt<1>("h00") core.io.rocc.dptw.req.bits.store := UInt<1>("h00") core.io.rocc.dptw.req.bits.prv := UInt<1>("h00") core.io.rocc.dptw.req.bits.addr := UInt<1>("h00") core.io.rocc.dptw.req.valid := UInt<1>("h00") core.io.rocc.iptw.req.bits.fetch := UInt<1>("h00") core.io.rocc.iptw.req.bits.store := UInt<1>("h00") core.io.rocc.iptw.req.bits.prv := UInt<1>("h00") core.io.rocc.iptw.req.bits.addr := UInt<1>("h00") core.io.rocc.iptw.req.valid := UInt<1>("h00") core.io.rocc.dmem.grant.ready := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.union := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.data := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") core.io.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") core.io.rocc.dmem.acquire.valid := UInt<1>("h00") core.io.rocc.imem.grant.ready := UInt<1>("h00") core.io.rocc.imem.acquire.bits.union := UInt<1>("h00") core.io.rocc.imem.acquire.bits.a_type := UInt<1>("h00") core.io.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") core.io.rocc.imem.acquire.bits.data := UInt<1>("h00") core.io.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") core.io.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") core.io.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") core.io.rocc.imem.acquire.valid := UInt<1>("h00") core.io.rocc.interrupt := UInt<1>("h00") core.io.rocc.busy := UInt<1>("h00") core.io.rocc.mem.invalidate_lr := UInt<1>("h00") core.io.rocc.mem.req.bits.data := UInt<1>("h00") core.io.rocc.mem.req.bits.phys := UInt<1>("h00") core.io.rocc.mem.req.bits.kill := UInt<1>("h00") core.io.rocc.mem.req.bits.typ := UInt<1>("h00") core.io.rocc.mem.req.bits.cmd := UInt<1>("h00") core.io.rocc.mem.req.bits.tag := UInt<1>("h00") core.io.rocc.mem.req.bits.addr := UInt<1>("h00") core.io.rocc.mem.req.valid := UInt<1>("h00") core.io.rocc.resp.bits.data := UInt<1>("h00") core.io.rocc.resp.bits.rd := UInt<1>("h00") core.io.rocc.resp.valid := UInt<1>("h00") core.io.rocc.cmd.ready := UInt<1>("h00") core.io.fpu.sboard_clra := UInt<1>("h00") core.io.fpu.sboard_clr := UInt<1>("h00") core.io.fpu.sboard_set := UInt<1>("h00") core.io.fpu.dec.wflags := UInt<1>("h00") core.io.fpu.dec.round := UInt<1>("h00") core.io.fpu.dec.sqrt := UInt<1>("h00") core.io.fpu.dec.div := UInt<1>("h00") core.io.fpu.dec.fma := UInt<1>("h00") core.io.fpu.dec.fastpipe := UInt<1>("h00") core.io.fpu.dec.toint := UInt<1>("h00") core.io.fpu.dec.fromint := UInt<1>("h00") core.io.fpu.dec.single := UInt<1>("h00") core.io.fpu.dec.swap23 := UInt<1>("h00") core.io.fpu.dec.swap12 := UInt<1>("h00") core.io.fpu.dec.ren3 := UInt<1>("h00") core.io.fpu.dec.ren2 := UInt<1>("h00") core.io.fpu.dec.ren1 := UInt<1>("h00") core.io.fpu.dec.wen := UInt<1>("h00") core.io.fpu.dec.ldst := UInt<1>("h00") core.io.fpu.dec.cmd := UInt<1>("h00") core.io.fpu.illegal_rm := UInt<1>("h00") core.io.fpu.nack_mem := UInt<1>("h00") core.io.fpu.fcsr_rdy := UInt<1>("h00") core.io.fpu.toint_data := UInt<1>("h00") core.io.fpu.store_data := UInt<1>("h00") core.io.fpu.fcsr_flags.bits := UInt<1>("h00") core.io.fpu.fcsr_flags.valid := UInt<1>("h00") core.io.dmem.ordered := UInt<1>("h00") core.io.dmem.xcpt.pf.st := UInt<1>("h00") core.io.dmem.xcpt.pf.ld := UInt<1>("h00") core.io.dmem.xcpt.ma.st := UInt<1>("h00") core.io.dmem.xcpt.ma.ld := UInt<1>("h00") core.io.dmem.replay_next.bits := UInt<1>("h00") core.io.dmem.replay_next.valid := UInt<1>("h00") core.io.dmem.resp.bits.store_data := UInt<1>("h00") core.io.dmem.resp.bits.data_word_bypass := UInt<1>("h00") core.io.dmem.resp.bits.has_data := UInt<1>("h00") core.io.dmem.resp.bits.replay := UInt<1>("h00") core.io.dmem.resp.bits.nack := UInt<1>("h00") core.io.dmem.resp.bits.data := UInt<1>("h00") core.io.dmem.resp.bits.typ := UInt<1>("h00") core.io.dmem.resp.bits.cmd := UInt<1>("h00") core.io.dmem.resp.bits.tag := UInt<1>("h00") core.io.dmem.resp.bits.addr := UInt<1>("h00") core.io.dmem.resp.valid := UInt<1>("h00") core.io.dmem.req.ready := UInt<1>("h00") core.io.imem.npc := UInt<1>("h00") core.io.imem.btb_resp.bits.bht.value := UInt<1>("h00") core.io.imem.btb_resp.bits.bht.history := UInt<1>("h00") core.io.imem.btb_resp.bits.entry := UInt<1>("h00") core.io.imem.btb_resp.bits.target := UInt<1>("h00") core.io.imem.btb_resp.bits.bridx := UInt<1>("h00") core.io.imem.btb_resp.bits.mask := UInt<1>("h00") core.io.imem.btb_resp.bits.taken := UInt<1>("h00") core.io.imem.btb_resp.valid := UInt<1>("h00") core.io.imem.resp.bits.xcpt_if := UInt<1>("h00") core.io.imem.resp.bits.mask := UInt<1>("h00") core.io.imem.resp.bits.data[0] := UInt<1>("h00") core.io.imem.resp.bits.pc := UInt<1>("h00") core.io.imem.resp.valid := UInt<1>("h00") core.io.host.ipi_rep.bits := UInt<1>("h00") core.io.host.ipi_rep.valid := UInt<1>("h00") core.io.host.ipi_req.ready := UInt<1>("h00") core.io.host.pcr.resp.ready := UInt<1>("h00") core.io.host.pcr.req.bits.data := UInt<1>("h00") core.io.host.pcr.req.bits.addr := UInt<1>("h00") core.io.host.pcr.req.bits.rw := UInt<1>("h00") core.io.host.pcr.req.valid := UInt<1>("h00") core.io.host.id := UInt<1>("h00") core.io.host.reset := UInt<1>("h00") core.clock := clock core.reset := reset dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr inst dcArb of HellaCacheArbiter dcArb.io.mem.ordered := UInt<1>("h00") dcArb.io.mem.xcpt.pf.st := UInt<1>("h00") dcArb.io.mem.xcpt.pf.ld := UInt<1>("h00") dcArb.io.mem.xcpt.ma.st := UInt<1>("h00") dcArb.io.mem.xcpt.ma.ld := UInt<1>("h00") dcArb.io.mem.replay_next.bits := UInt<1>("h00") dcArb.io.mem.replay_next.valid := UInt<1>("h00") dcArb.io.mem.resp.bits.store_data := UInt<1>("h00") dcArb.io.mem.resp.bits.data_word_bypass := UInt<1>("h00") dcArb.io.mem.resp.bits.has_data := UInt<1>("h00") dcArb.io.mem.resp.bits.replay := UInt<1>("h00") dcArb.io.mem.resp.bits.nack := UInt<1>("h00") dcArb.io.mem.resp.bits.data := UInt<1>("h00") dcArb.io.mem.resp.bits.typ := UInt<1>("h00") dcArb.io.mem.resp.bits.cmd := UInt<1>("h00") dcArb.io.mem.resp.bits.tag := UInt<1>("h00") dcArb.io.mem.resp.bits.addr := UInt<1>("h00") dcArb.io.mem.resp.valid := UInt<1>("h00") dcArb.io.mem.req.ready := UInt<1>("h00") dcArb.io.requestor[0].invalidate_lr := UInt<1>("h00") dcArb.io.requestor[0].req.bits.data := UInt<1>("h00") dcArb.io.requestor[0].req.bits.phys := UInt<1>("h00") dcArb.io.requestor[0].req.bits.kill := UInt<1>("h00") dcArb.io.requestor[0].req.bits.typ := UInt<1>("h00") dcArb.io.requestor[0].req.bits.cmd := UInt<1>("h00") dcArb.io.requestor[0].req.bits.tag := UInt<1>("h00") dcArb.io.requestor[0].req.bits.addr := UInt<1>("h00") dcArb.io.requestor[0].req.valid := UInt<1>("h00") dcArb.io.requestor[1].invalidate_lr := UInt<1>("h00") dcArb.io.requestor[1].req.bits.data := UInt<1>("h00") dcArb.io.requestor[1].req.bits.phys := UInt<1>("h00") dcArb.io.requestor[1].req.bits.kill := UInt<1>("h00") dcArb.io.requestor[1].req.bits.typ := UInt<1>("h00") dcArb.io.requestor[1].req.bits.cmd := UInt<1>("h00") dcArb.io.requestor[1].req.bits.tag := UInt<1>("h00") dcArb.io.requestor[1].req.bits.addr := UInt<1>("h00") dcArb.io.requestor[1].req.valid := UInt<1>("h00") dcArb.clock := clock dcArb.reset := reset dcArb.io.requestor[0] <> ptw.io.mem dcArb.io.requestor[1] <> core.io.dmem dcache.io.cpu <> dcArb.io.mem ptw.io.requestor[0] <> icache.io.ptw ptw.io.requestor[1] <> dcache.io.ptw io.host <> core.io.host icache.io.cpu <> core.io.imem core.io.ptw <> ptw.io.dpath inst T_1190 of FPU T_1190.io.killm := UInt<1>("h00") T_1190.io.killx := UInt<1>("h00") T_1190.io.valid := UInt<1>("h00") T_1190.io.dmem_resp_data := UInt<1>("h00") T_1190.io.dmem_resp_tag := UInt<1>("h00") T_1190.io.dmem_resp_type := UInt<1>("h00") T_1190.io.dmem_resp_val := UInt<1>("h00") T_1190.io.fcsr_rm := UInt<1>("h00") T_1190.io.fromint_data := UInt<1>("h00") T_1190.io.inst := UInt<1>("h00") T_1190.clock := clock T_1190.reset := reset core.io.fpu <> T_1190.io io.cached <> dcache.io.mem io.uncached <> icache.io.mem module Queue_102 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.data := UInt<1>("h00") io.deq.bits.addr := UInt<1>("h00") io.deq.bits.rw := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2], clock reg T_53 : UInt<1>, clock, reset onreset T_53 := UInt<1>("h00") reg T_55 : UInt<1>, clock, reset onreset T_55 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_66 = and(io.enq.ready, io.enq.valid) node T_68 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_66, T_68) node T_70 = and(io.deq.ready, io.deq.valid) node T_72 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_70, T_72) when do_enq : infer accessor T_74 = ram[T_53] T_74 <> io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) node T_84 = addw(T_53, UInt<1>("h01")) node T_85 = mux(T_81, UInt<1>("h00"), T_84) T_53 := T_85 skip when do_deq : node T_87 = eq(T_55, UInt<1>("h01")) node T_89 = and(UInt<1>("h00"), T_87) node T_92 = addw(T_55, UInt<1>("h01")) node T_93 = mux(T_89, UInt<1>("h00"), T_92) T_55 := T_93 skip node T_94 = neq(do_enq, do_deq) when T_94 : maybe_full := do_enq skip node T_96 = eq(empty, UInt<1>("h00")) node T_98 = and(UInt<1>("h00"), io.enq.valid) node T_99 = or(T_96, T_98) io.deq.valid := T_99 node T_101 = eq(full, UInt<1>("h00")) node T_103 = and(UInt<1>("h00"), io.deq.ready) node T_104 = or(T_101, T_103) io.enq.ready := T_104 infer accessor T_105 = ram[T_55] wire T_113 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>} T_113 <> T_105 when maybe_flow : T_113 <> io.enq.bits skip io.deq.bits <> T_113 node ptr_diff = subw(T_53, T_55) node T_118 = and(maybe_full, ptr_match) node T_119 = cat(T_118, ptr_diff) io.count := T_119 module Queue_103 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : UInt<64>[2], clock reg T_26 : UInt<1>, clock, reset onreset T_26 := UInt<1>("h00") reg T_28 : UInt<1>, clock, reset onreset T_28 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_39 = and(io.enq.ready, io.enq.valid) node T_41 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_39, T_41) node T_43 = and(io.deq.ready, io.deq.valid) node T_45 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_43, T_45) when do_enq : infer accessor T_47 = ram[T_26] T_47 := io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) node T_54 = addw(T_26, UInt<1>("h01")) node T_55 = mux(T_51, UInt<1>("h00"), T_54) T_26 := T_55 skip when do_deq : node T_57 = eq(T_28, UInt<1>("h01")) node T_59 = and(UInt<1>("h00"), T_57) node T_62 = addw(T_28, UInt<1>("h01")) node T_63 = mux(T_59, UInt<1>("h00"), T_62) T_28 := T_63 skip node T_64 = neq(do_enq, do_deq) when T_64 : maybe_full := do_enq skip node T_66 = eq(empty, UInt<1>("h00")) node T_68 = and(UInt<1>("h00"), io.enq.valid) node T_69 = or(T_66, T_68) io.deq.valid := T_69 node T_71 = eq(full, UInt<1>("h00")) node T_73 = and(UInt<1>("h00"), io.deq.ready) node T_74 = or(T_71, T_73) io.enq.ready := T_74 infer accessor T_75 = ram[T_28] node T_76 = mux(maybe_flow, io.enq.bits, T_75) io.deq.bits := T_76 node ptr_diff = subw(T_26, T_28) node T_78 = and(maybe_full, ptr_match) node T_79 = cat(T_78, ptr_diff) io.count := T_79 module Queue_104 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : UInt<1>[2], clock reg T_26 : UInt<1>, clock, reset onreset T_26 := UInt<1>("h00") reg T_28 : UInt<1>, clock, reset onreset T_28 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_39 = and(io.enq.ready, io.enq.valid) node T_41 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_39, T_41) node T_43 = and(io.deq.ready, io.deq.valid) node T_45 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_43, T_45) when do_enq : infer accessor T_47 = ram[T_26] T_47 := io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) node T_54 = addw(T_26, UInt<1>("h01")) node T_55 = mux(T_51, UInt<1>("h00"), T_54) T_26 := T_55 skip when do_deq : node T_57 = eq(T_28, UInt<1>("h01")) node T_59 = and(UInt<1>("h00"), T_57) node T_62 = addw(T_28, UInt<1>("h01")) node T_63 = mux(T_59, UInt<1>("h00"), T_62) T_28 := T_63 skip node T_64 = neq(do_enq, do_deq) when T_64 : maybe_full := do_enq skip node T_66 = eq(empty, UInt<1>("h00")) node T_68 = and(UInt<1>("h00"), io.enq.valid) node T_69 = or(T_66, T_68) io.deq.valid := T_69 node T_71 = eq(full, UInt<1>("h00")) node T_73 = and(UInt<1>("h00"), io.deq.ready) node T_74 = or(T_71, T_73) io.enq.ready := T_74 infer accessor T_75 = ram[T_28] node T_76 = mux(maybe_flow, io.enq.bits, T_75) io.deq.bits := T_76 node ptr_diff = subw(T_26, T_28) node T_78 = and(maybe_full, ptr_match) node T_79 = cat(T_78, ptr_diff) io.count := T_79 module MultiChannelTop : input clock : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}[1], mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, last : UInt<1>, strb : UInt<16>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<6>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<6>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<128>, last : UInt<1>, id : UInt<6>, user : UInt<1>}}}} io.mmio.r.ready := UInt<1>("h00") io.mmio.ar.bits.user := UInt<1>("h00") io.mmio.ar.bits.id := UInt<1>("h00") io.mmio.ar.bits.region := UInt<1>("h00") io.mmio.ar.bits.qos := UInt<1>("h00") io.mmio.ar.bits.prot := UInt<1>("h00") io.mmio.ar.bits.cache := UInt<1>("h00") io.mmio.ar.bits.lock := UInt<1>("h00") io.mmio.ar.bits.burst := UInt<1>("h00") io.mmio.ar.bits.size := UInt<1>("h00") io.mmio.ar.bits.len := UInt<1>("h00") io.mmio.ar.bits.addr := UInt<1>("h00") io.mmio.ar.valid := UInt<1>("h00") io.mmio.b.ready := UInt<1>("h00") io.mmio.w.bits.user := UInt<1>("h00") io.mmio.w.bits.strb := UInt<1>("h00") io.mmio.w.bits.last := UInt<1>("h00") io.mmio.w.bits.data := UInt<1>("h00") io.mmio.w.valid := UInt<1>("h00") io.mmio.aw.bits.user := UInt<1>("h00") io.mmio.aw.bits.id := UInt<1>("h00") io.mmio.aw.bits.region := UInt<1>("h00") io.mmio.aw.bits.qos := UInt<1>("h00") io.mmio.aw.bits.prot := UInt<1>("h00") io.mmio.aw.bits.cache := UInt<1>("h00") io.mmio.aw.bits.lock := UInt<1>("h00") io.mmio.aw.bits.burst := UInt<1>("h00") io.mmio.aw.bits.size := UInt<1>("h00") io.mmio.aw.bits.len := UInt<1>("h00") io.mmio.aw.bits.addr := UInt<1>("h00") io.mmio.aw.valid := UInt<1>("h00") io.mem[0].r.ready := UInt<1>("h00") io.mem[0].ar.bits.user := UInt<1>("h00") io.mem[0].ar.bits.id := UInt<1>("h00") io.mem[0].ar.bits.region := UInt<1>("h00") io.mem[0].ar.bits.qos := UInt<1>("h00") io.mem[0].ar.bits.prot := UInt<1>("h00") io.mem[0].ar.bits.cache := UInt<1>("h00") io.mem[0].ar.bits.lock := UInt<1>("h00") io.mem[0].ar.bits.burst := UInt<1>("h00") io.mem[0].ar.bits.size := UInt<1>("h00") io.mem[0].ar.bits.len := UInt<1>("h00") io.mem[0].ar.bits.addr := UInt<1>("h00") io.mem[0].ar.valid := UInt<1>("h00") io.mem[0].b.ready := UInt<1>("h00") io.mem[0].w.bits.user := UInt<1>("h00") io.mem[0].w.bits.strb := UInt<1>("h00") io.mem[0].w.bits.last := UInt<1>("h00") io.mem[0].w.bits.data := UInt<1>("h00") io.mem[0].w.valid := UInt<1>("h00") io.mem[0].aw.bits.user := UInt<1>("h00") io.mem[0].aw.bits.id := UInt<1>("h00") io.mem[0].aw.bits.region := UInt<1>("h00") io.mem[0].aw.bits.qos := UInt<1>("h00") io.mem[0].aw.bits.prot := UInt<1>("h00") io.mem[0].aw.bits.cache := UInt<1>("h00") io.mem[0].aw.bits.lock := UInt<1>("h00") io.mem[0].aw.bits.burst := UInt<1>("h00") io.mem[0].aw.bits.size := UInt<1>("h00") io.mem[0].aw.bits.len := UInt<1>("h00") io.mem[0].aw.bits.addr := UInt<1>("h00") io.mem[0].aw.valid := UInt<1>("h00") io.mem_backup_ctrl.out_valid := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.out.bits := UInt<1>("h00") io.host.out.valid := UInt<1>("h00") io.host.in.ready := UInt<1>("h00") io.host.clk_edge := UInt<1>("h00") io.host.clk := UInt<1>("h00") inst uncore of Uncore uncore.io.mmio.r.bits.user := UInt<1>("h00") uncore.io.mmio.r.bits.id := UInt<1>("h00") uncore.io.mmio.r.bits.last := UInt<1>("h00") uncore.io.mmio.r.bits.data := UInt<1>("h00") uncore.io.mmio.r.bits.resp := UInt<1>("h00") uncore.io.mmio.r.valid := UInt<1>("h00") uncore.io.mmio.ar.ready := UInt<1>("h00") uncore.io.mmio.b.bits.user := UInt<1>("h00") uncore.io.mmio.b.bits.id := UInt<1>("h00") uncore.io.mmio.b.bits.resp := UInt<1>("h00") uncore.io.mmio.b.valid := UInt<1>("h00") uncore.io.mmio.w.ready := UInt<1>("h00") uncore.io.mmio.aw.ready := UInt<1>("h00") uncore.io.mem_backup_ctrl.out_ready := UInt<1>("h00") uncore.io.mem_backup_ctrl.in_valid := UInt<1>("h00") uncore.io.mem_backup_ctrl.en := UInt<1>("h00") uncore.io.htif[0].debug_stats_pcr := UInt<1>("h00") uncore.io.htif[0].ipi_rep.ready := UInt<1>("h00") uncore.io.htif[0].ipi_req.bits := UInt<1>("h00") uncore.io.htif[0].ipi_req.valid := UInt<1>("h00") uncore.io.htif[0].pcr.resp.bits := UInt<1>("h00") uncore.io.htif[0].pcr.resp.valid := UInt<1>("h00") uncore.io.htif[0].pcr.req.ready := UInt<1>("h00") uncore.io.tiles_uncached[0].grant.ready := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.valid := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.r_type := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.data := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") uncore.io.tiles_cached[0].release.valid := UInt<1>("h00") uncore.io.tiles_cached[0].probe.ready := UInt<1>("h00") uncore.io.tiles_cached[0].grant.ready := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.union := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.data := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") uncore.io.tiles_cached[0].acquire.valid := UInt<1>("h00") uncore.io.mem[0].r.bits.user := UInt<1>("h00") uncore.io.mem[0].r.bits.id := UInt<1>("h00") uncore.io.mem[0].r.bits.last := UInt<1>("h00") uncore.io.mem[0].r.bits.data := UInt<1>("h00") uncore.io.mem[0].r.bits.resp := UInt<1>("h00") uncore.io.mem[0].r.valid := UInt<1>("h00") uncore.io.mem[0].ar.ready := UInt<1>("h00") uncore.io.mem[0].b.bits.user := UInt<1>("h00") uncore.io.mem[0].b.bits.id := UInt<1>("h00") uncore.io.mem[0].b.bits.resp := UInt<1>("h00") uncore.io.mem[0].b.valid := UInt<1>("h00") uncore.io.mem[0].w.ready := UInt<1>("h00") uncore.io.mem[0].aw.ready := UInt<1>("h00") uncore.io.host.out.ready := UInt<1>("h00") uncore.io.host.in.bits := UInt<1>("h00") uncore.io.host.in.valid := UInt<1>("h00") uncore.clock := clock uncore.reset := reset inst T_893 of RocketTile T_893.io.host.ipi_rep.bits := UInt<1>("h00") T_893.io.host.ipi_rep.valid := UInt<1>("h00") T_893.io.host.ipi_req.ready := UInt<1>("h00") T_893.io.host.pcr.resp.ready := UInt<1>("h00") T_893.io.host.pcr.req.bits.data := UInt<1>("h00") T_893.io.host.pcr.req.bits.addr := UInt<1>("h00") T_893.io.host.pcr.req.bits.rw := UInt<1>("h00") T_893.io.host.pcr.req.valid := UInt<1>("h00") T_893.io.host.id := UInt<1>("h00") T_893.io.host.reset := UInt<1>("h00") T_893.io.uncached.grant.bits.g_type := UInt<1>("h00") T_893.io.uncached.grant.bits.is_builtin_type := UInt<1>("h00") T_893.io.uncached.grant.bits.manager_xact_id := UInt<1>("h00") T_893.io.uncached.grant.bits.client_xact_id := UInt<1>("h00") T_893.io.uncached.grant.bits.data := UInt<1>("h00") T_893.io.uncached.grant.bits.addr_beat := UInt<1>("h00") T_893.io.uncached.grant.valid := UInt<1>("h00") T_893.io.uncached.acquire.ready := UInt<1>("h00") T_893.io.cached.release.ready := UInt<1>("h00") T_893.io.cached.probe.bits.p_type := UInt<1>("h00") T_893.io.cached.probe.bits.addr_block := UInt<1>("h00") T_893.io.cached.probe.valid := UInt<1>("h00") T_893.io.cached.grant.bits.g_type := UInt<1>("h00") T_893.io.cached.grant.bits.is_builtin_type := UInt<1>("h00") T_893.io.cached.grant.bits.manager_xact_id := UInt<1>("h00") T_893.io.cached.grant.bits.client_xact_id := UInt<1>("h00") T_893.io.cached.grant.bits.data := UInt<1>("h00") T_893.io.cached.grant.bits.addr_beat := UInt<1>("h00") T_893.io.cached.grant.valid := UInt<1>("h00") T_893.io.cached.acquire.ready := UInt<1>("h00") T_893.clock := clock T_893.reset := uncore.io.htif[0].reset T_893.io.host.id := UInt<1>("h00") reg T_925 : UInt<1>, clock, reset T_925 := uncore.io.htif[0].reset reg T_926 : UInt<1>, clock, reset T_926 := T_925 T_893.io.host.reset := T_926 inst T_931 of Queue_102 T_931.io.deq.ready := UInt<1>("h00") T_931.io.enq.bits.data := UInt<1>("h00") T_931.io.enq.bits.addr := UInt<1>("h00") T_931.io.enq.bits.rw := UInt<1>("h00") T_931.io.enq.valid := UInt<1>("h00") T_931.clock := clock T_931.reset := reset T_931.io.enq.valid := uncore.io.htif[0].pcr.req.valid T_931.io.enq.bits <> uncore.io.htif[0].pcr.req.bits uncore.io.htif[0].pcr.req.ready := T_931.io.enq.ready T_893.io.host.pcr.req <> T_931.io.deq inst T_938 of Queue_103 T_938.io.deq.ready := UInt<1>("h00") T_938.io.enq.bits := UInt<1>("h00") T_938.io.enq.valid := UInt<1>("h00") T_938.clock := clock T_938.reset := reset T_938.io.enq.valid := T_893.io.host.pcr.resp.valid T_938.io.enq.bits := T_893.io.host.pcr.resp.bits T_893.io.host.pcr.resp.ready := T_938.io.enq.ready uncore.io.htif[0].pcr.resp <> T_938.io.deq inst T_943 of Queue_104 T_943.io.deq.ready := UInt<1>("h00") T_943.io.enq.bits := UInt<1>("h00") T_943.io.enq.valid := UInt<1>("h00") T_943.clock := clock T_943.reset := reset T_943.io.enq.valid := T_893.io.host.ipi_req.valid T_943.io.enq.bits := T_893.io.host.ipi_req.bits T_893.io.host.ipi_req.ready := T_943.io.enq.ready uncore.io.htif[0].ipi_req <> T_943.io.deq inst T_948 of Queue_104 T_948.io.deq.ready := UInt<1>("h00") T_948.io.enq.bits := UInt<1>("h00") T_948.io.enq.valid := UInt<1>("h00") T_948.clock := clock T_948.reset := reset T_948.io.enq.valid := uncore.io.htif[0].ipi_rep.valid T_948.io.enq.bits := uncore.io.htif[0].ipi_rep.bits uncore.io.htif[0].ipi_rep.ready := T_948.io.enq.ready T_893.io.host.ipi_rep <> T_948.io.deq uncore.io.htif[0].debug_stats_pcr := T_893.io.host.debug_stats_pcr uncore.io.tiles_cached[0] <> T_893.io.cached uncore.io.tiles_uncached[0] <> T_893.io.uncached io.host <> uncore.io.host io.mem <> uncore.io.mem io.mmio <> uncore.io.mmio io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl module Queue_109 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}}, count : UInt<2>} io.count := UInt<1>("h00") io.deq.bits.rw := UInt<1>("h00") io.deq.bits.tag := UInt<1>("h00") io.deq.bits.addr := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}[2], clock reg T_53 : UInt<1>, clock, reset onreset T_53 := UInt<1>("h00") reg T_55 : UInt<1>, clock, reset onreset T_55 := UInt<1>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_66 = and(io.enq.ready, io.enq.valid) node T_68 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_66, T_68) node T_70 = and(io.deq.ready, io.deq.valid) node T_72 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_70, T_72) when do_enq : infer accessor T_74 = ram[T_53] T_74 <> io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) node T_84 = addw(T_53, UInt<1>("h01")) node T_85 = mux(T_81, UInt<1>("h00"), T_84) T_53 := T_85 skip when do_deq : node T_87 = eq(T_55, UInt<1>("h01")) node T_89 = and(UInt<1>("h00"), T_87) node T_92 = addw(T_55, UInt<1>("h01")) node T_93 = mux(T_89, UInt<1>("h00"), T_92) T_55 := T_93 skip node T_94 = neq(do_enq, do_deq) when T_94 : maybe_full := do_enq skip node T_96 = eq(empty, UInt<1>("h00")) node T_98 = and(UInt<1>("h00"), io.enq.valid) node T_99 = or(T_96, T_98) io.deq.valid := T_99 node T_101 = eq(full, UInt<1>("h00")) node T_103 = and(UInt<1>("h00"), io.deq.ready) node T_104 = or(T_101, T_103) io.enq.ready := T_104 infer accessor T_105 = ram[T_55] wire T_113 : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>} T_113 <> T_105 when maybe_flow : T_113 <> io.enq.bits skip io.deq.bits <> T_113 node ptr_diff = subw(T_53, T_55) node T_118 = and(maybe_full, ptr_match) node T_119 = cat(T_118, ptr_diff) io.count := T_119 module Queue_110 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, count : UInt<3>} io.count := UInt<1>("h00") io.deq.bits.data := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {data : UInt<128>}[4], clock reg T_35 : UInt<2>, clock, reset onreset T_35 := UInt<2>("h00") reg T_37 : UInt<2>, clock, reset onreset T_37 := UInt<2>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_35, T_37) node T_42 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_42) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_48 = and(io.enq.ready, io.enq.valid) node T_50 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_48, T_50) node T_52 = and(io.deq.ready, io.deq.valid) node T_54 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_52, T_54) when do_enq : infer accessor T_56 = ram[T_35] T_56 <> io.enq.bits node T_59 = eq(T_35, UInt<2>("h03")) node T_61 = and(UInt<1>("h00"), T_59) node T_64 = addw(T_35, UInt<1>("h01")) node T_65 = mux(T_61, UInt<1>("h00"), T_64) T_35 := T_65 skip when do_deq : node T_67 = eq(T_37, UInt<2>("h03")) node T_69 = and(UInt<1>("h00"), T_67) node T_72 = addw(T_37, UInt<1>("h01")) node T_73 = mux(T_69, UInt<1>("h00"), T_72) T_37 := T_73 skip node T_74 = neq(do_enq, do_deq) when T_74 : maybe_full := do_enq skip node T_76 = eq(empty, UInt<1>("h00")) node T_78 = and(UInt<1>("h00"), io.enq.valid) node T_79 = or(T_76, T_78) io.deq.valid := T_79 node T_81 = eq(full, UInt<1>("h00")) node T_83 = and(UInt<1>("h00"), io.deq.ready) node T_84 = or(T_81, T_83) io.enq.ready := T_84 infer accessor T_85 = ram[T_37] wire T_89 : {data : UInt<128>} T_89 <> T_85 when maybe_flow : T_89 <> io.enq.bits skip io.deq.bits <> T_89 node ptr_diff = subw(T_35, T_37) node T_92 = and(maybe_full, ptr_match) node T_93 = cat(T_92, ptr_diff) io.count := T_93 module Queue_111 : input clock : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<6>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<6>}}, count : UInt<3>} io.count := UInt<1>("h00") io.deq.bits.tag := UInt<1>("h00") io.deq.bits.data := UInt<1>("h00") io.deq.valid := UInt<1>("h00") io.enq.ready := UInt<1>("h00") cmem ram : {data : UInt<128>, tag : UInt<6>}[4], clock reg T_44 : UInt<2>, clock, reset onreset T_44 := UInt<2>("h00") reg T_46 : UInt<2>, clock, reset onreset T_46 := UInt<2>("h00") reg maybe_full : UInt<1>, clock, reset onreset maybe_full := UInt<1>("h00") node ptr_match = eq(T_44, T_46) node T_51 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_51) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_57 = and(io.enq.ready, io.enq.valid) node T_59 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_57, T_59) node T_61 = and(io.deq.ready, io.deq.valid) node T_63 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_61, T_63) when do_enq : infer accessor T_65 = ram[T_44] T_65 <> io.enq.bits node T_69 = eq(T_44, UInt<2>("h03")) node T_71 = and(UInt<1>("h00"), T_69) node T_74 = addw(T_44, UInt<1>("h01")) node T_75 = mux(T_71, UInt<1>("h00"), T_74) T_44 := T_75 skip when do_deq : node T_77 = eq(T_46, UInt<2>("h03")) node T_79 = and(UInt<1>("h00"), T_77) node T_82 = addw(T_46, UInt<1>("h01")) node T_83 = mux(T_79, UInt<1>("h00"), T_82) T_46 := T_83 skip node T_84 = neq(do_enq, do_deq) when T_84 : maybe_full := do_enq skip node T_86 = eq(empty, UInt<1>("h00")) node T_88 = and(UInt<1>("h00"), io.enq.valid) node T_89 = or(T_86, T_88) io.deq.valid := T_89 node T_91 = eq(full, UInt<1>("h00")) node T_93 = and(UInt<1>("h00"), io.deq.ready) node T_94 = or(T_91, T_93) io.enq.ready := T_94 infer accessor T_95 = ram[T_46] wire T_101 : {data : UInt<128>, tag : UInt<6>} T_101 <> T_95 when maybe_flow : T_101 <> io.enq.bits skip io.deq.bits <> T_101 node ptr_diff = subw(T_44, T_46) node T_105 = and(maybe_full, ptr_match) node T_106 = cat(T_105, ptr_diff) io.count := T_106 module Top : input clock : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<6>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<6>}}}} io.mem.resp.ready := UInt<1>("h00") io.mem.req_data.bits.data := UInt<1>("h00") io.mem.req_data.valid := UInt<1>("h00") io.mem.req_cmd.bits.rw := UInt<1>("h00") io.mem.req_cmd.bits.tag := UInt<1>("h00") io.mem.req_cmd.bits.addr := UInt<1>("h00") io.mem.req_cmd.valid := UInt<1>("h00") io.mem_backup_ctrl.out_valid := UInt<1>("h00") io.host.debug_stats_pcr := UInt<1>("h00") io.host.out.bits := UInt<1>("h00") io.host.out.valid := UInt<1>("h00") io.host.in.ready := UInt<1>("h00") io.host.clk_edge := UInt<1>("h00") io.host.clk := UInt<1>("h00") inst T_77 of MultiChannelTop T_77.io.mmio.r.bits.user := UInt<1>("h00") T_77.io.mmio.r.bits.id := UInt<1>("h00") T_77.io.mmio.r.bits.last := UInt<1>("h00") T_77.io.mmio.r.bits.data := UInt<1>("h00") T_77.io.mmio.r.bits.resp := UInt<1>("h00") T_77.io.mmio.r.valid := UInt<1>("h00") T_77.io.mmio.ar.ready := UInt<1>("h00") T_77.io.mmio.b.bits.user := UInt<1>("h00") T_77.io.mmio.b.bits.id := UInt<1>("h00") T_77.io.mmio.b.bits.resp := UInt<1>("h00") T_77.io.mmio.b.valid := UInt<1>("h00") T_77.io.mmio.w.ready := UInt<1>("h00") T_77.io.mmio.aw.ready := UInt<1>("h00") T_77.io.mem[0].r.bits.user := UInt<1>("h00") T_77.io.mem[0].r.bits.id := UInt<1>("h00") T_77.io.mem[0].r.bits.last := UInt<1>("h00") T_77.io.mem[0].r.bits.data := UInt<1>("h00") T_77.io.mem[0].r.bits.resp := UInt<1>("h00") T_77.io.mem[0].r.valid := UInt<1>("h00") T_77.io.mem[0].ar.ready := UInt<1>("h00") T_77.io.mem[0].b.bits.user := UInt<1>("h00") T_77.io.mem[0].b.bits.id := UInt<1>("h00") T_77.io.mem[0].b.bits.resp := UInt<1>("h00") T_77.io.mem[0].b.valid := UInt<1>("h00") T_77.io.mem[0].w.ready := UInt<1>("h00") T_77.io.mem[0].aw.ready := UInt<1>("h00") T_77.io.mem_backup_ctrl.out_ready := UInt<1>("h00") T_77.io.mem_backup_ctrl.in_valid := UInt<1>("h00") T_77.io.mem_backup_ctrl.en := UInt<1>("h00") T_77.io.host.out.ready := UInt<1>("h00") T_77.io.host.in.bits := UInt<1>("h00") T_77.io.host.in.valid := UInt<1>("h00") T_77.clock := clock T_77.reset := reset inst T_110 of NASTIArbiter_72 T_110.io.slave.r.bits.user := UInt<1>("h00") T_110.io.slave.r.bits.id := UInt<1>("h00") T_110.io.slave.r.bits.last := UInt<1>("h00") T_110.io.slave.r.bits.data := UInt<1>("h00") T_110.io.slave.r.bits.resp := UInt<1>("h00") T_110.io.slave.r.valid := UInt<1>("h00") T_110.io.slave.ar.ready := UInt<1>("h00") T_110.io.slave.b.bits.user := UInt<1>("h00") T_110.io.slave.b.bits.id := UInt<1>("h00") T_110.io.slave.b.bits.resp := UInt<1>("h00") T_110.io.slave.b.valid := UInt<1>("h00") T_110.io.slave.w.ready := UInt<1>("h00") T_110.io.slave.aw.ready := UInt<1>("h00") T_110.io.master[0].r.ready := UInt<1>("h00") T_110.io.master[0].ar.bits.user := UInt<1>("h00") T_110.io.master[0].ar.bits.id := UInt<1>("h00") T_110.io.master[0].ar.bits.region := UInt<1>("h00") T_110.io.master[0].ar.bits.qos := UInt<1>("h00") T_110.io.master[0].ar.bits.prot := UInt<1>("h00") T_110.io.master[0].ar.bits.cache := UInt<1>("h00") T_110.io.master[0].ar.bits.lock := UInt<1>("h00") T_110.io.master[0].ar.bits.burst := UInt<1>("h00") T_110.io.master[0].ar.bits.size := UInt<1>("h00") T_110.io.master[0].ar.bits.len := UInt<1>("h00") T_110.io.master[0].ar.bits.addr := UInt<1>("h00") T_110.io.master[0].ar.valid := UInt<1>("h00") T_110.io.master[0].b.ready := UInt<1>("h00") T_110.io.master[0].w.bits.user := UInt<1>("h00") T_110.io.master[0].w.bits.strb := UInt<1>("h00") T_110.io.master[0].w.bits.last := UInt<1>("h00") T_110.io.master[0].w.bits.data := UInt<1>("h00") T_110.io.master[0].w.valid := UInt<1>("h00") T_110.io.master[0].aw.bits.user := UInt<1>("h00") T_110.io.master[0].aw.bits.id := UInt<1>("h00") T_110.io.master[0].aw.bits.region := UInt<1>("h00") T_110.io.master[0].aw.bits.qos := UInt<1>("h00") T_110.io.master[0].aw.bits.prot := UInt<1>("h00") T_110.io.master[0].aw.bits.cache := UInt<1>("h00") T_110.io.master[0].aw.bits.lock := UInt<1>("h00") T_110.io.master[0].aw.bits.burst := UInt<1>("h00") T_110.io.master[0].aw.bits.size := UInt<1>("h00") T_110.io.master[0].aw.bits.len := UInt<1>("h00") T_110.io.master[0].aw.bits.addr := UInt<1>("h00") T_110.io.master[0].aw.valid := UInt<1>("h00") T_110.clock := clock T_110.reset := reset inst T_155 of MemIONASTIIOConverter T_155.io.mem.resp.bits.tag := UInt<1>("h00") T_155.io.mem.resp.bits.data := UInt<1>("h00") T_155.io.mem.resp.valid := UInt<1>("h00") T_155.io.mem.req_data.ready := UInt<1>("h00") T_155.io.mem.req_cmd.ready := UInt<1>("h00") T_155.io.nasti.r.ready := UInt<1>("h00") T_155.io.nasti.ar.bits.user := UInt<1>("h00") T_155.io.nasti.ar.bits.id := UInt<1>("h00") T_155.io.nasti.ar.bits.region := UInt<1>("h00") T_155.io.nasti.ar.bits.qos := UInt<1>("h00") T_155.io.nasti.ar.bits.prot := UInt<1>("h00") T_155.io.nasti.ar.bits.cache := UInt<1>("h00") T_155.io.nasti.ar.bits.lock := UInt<1>("h00") T_155.io.nasti.ar.bits.burst := UInt<1>("h00") T_155.io.nasti.ar.bits.size := UInt<1>("h00") T_155.io.nasti.ar.bits.len := UInt<1>("h00") T_155.io.nasti.ar.bits.addr := UInt<1>("h00") T_155.io.nasti.ar.valid := UInt<1>("h00") T_155.io.nasti.b.ready := UInt<1>("h00") T_155.io.nasti.w.bits.user := UInt<1>("h00") T_155.io.nasti.w.bits.strb := UInt<1>("h00") T_155.io.nasti.w.bits.last := UInt<1>("h00") T_155.io.nasti.w.bits.data := UInt<1>("h00") T_155.io.nasti.w.valid := UInt<1>("h00") T_155.io.nasti.aw.bits.user := UInt<1>("h00") T_155.io.nasti.aw.bits.id := UInt<1>("h00") T_155.io.nasti.aw.bits.region := UInt<1>("h00") T_155.io.nasti.aw.bits.qos := UInt<1>("h00") T_155.io.nasti.aw.bits.prot := UInt<1>("h00") T_155.io.nasti.aw.bits.cache := UInt<1>("h00") T_155.io.nasti.aw.bits.lock := UInt<1>("h00") T_155.io.nasti.aw.bits.burst := UInt<1>("h00") T_155.io.nasti.aw.bits.size := UInt<1>("h00") T_155.io.nasti.aw.bits.len := UInt<1>("h00") T_155.io.nasti.aw.bits.addr := UInt<1>("h00") T_155.io.nasti.aw.valid := UInt<1>("h00") T_155.clock := clock T_155.reset := reset T_110.io.master <> T_77.io.mem T_155.io.nasti <> T_110.io.slave inst T_196 of Queue_109 T_196.io.deq.ready := UInt<1>("h00") T_196.io.enq.bits.rw := UInt<1>("h00") T_196.io.enq.bits.tag := UInt<1>("h00") T_196.io.enq.bits.addr := UInt<1>("h00") T_196.io.enq.valid := UInt<1>("h00") T_196.clock := clock T_196.reset := reset T_196.io.enq.valid := T_155.io.mem.req_cmd.valid T_196.io.enq.bits <> T_155.io.mem.req_cmd.bits T_155.io.mem.req_cmd.ready := T_196.io.enq.ready io.mem.req_cmd <> T_196.io.deq inst T_204 of Queue_110 T_204.io.deq.ready := UInt<1>("h00") T_204.io.enq.bits.data := UInt<1>("h00") T_204.io.enq.valid := UInt<1>("h00") T_204.clock := clock T_204.reset := reset T_204.io.enq.valid := T_155.io.mem.req_data.valid T_204.io.enq.bits <> T_155.io.mem.req_data.bits T_155.io.mem.req_data.ready := T_204.io.enq.ready io.mem.req_data <> T_204.io.deq inst T_211 of Queue_111 T_211.io.deq.ready := UInt<1>("h00") T_211.io.enq.bits.tag := UInt<1>("h00") T_211.io.enq.bits.data := UInt<1>("h00") T_211.io.enq.valid := UInt<1>("h00") T_211.clock := clock T_211.reset := reset T_211.io.enq.valid := io.mem.resp.valid T_211.io.enq.bits <> io.mem.resp.bits io.mem.resp.ready := T_211.io.enq.ready T_155.io.mem.resp <> T_211.io.deq io.mem_backup_ctrl <> T_77.io.mem_backup_ctrl io.host <> T_77.io.host inst T_216 of NASTIErrorSlave T_216.io.r.ready := UInt<1>("h00") T_216.io.ar.bits.user := UInt<1>("h00") T_216.io.ar.bits.id := UInt<1>("h00") T_216.io.ar.bits.region := UInt<1>("h00") T_216.io.ar.bits.qos := UInt<1>("h00") T_216.io.ar.bits.prot := UInt<1>("h00") T_216.io.ar.bits.cache := UInt<1>("h00") T_216.io.ar.bits.lock := UInt<1>("h00") T_216.io.ar.bits.burst := UInt<1>("h00") T_216.io.ar.bits.size := UInt<1>("h00") T_216.io.ar.bits.len := UInt<1>("h00") T_216.io.ar.bits.addr := UInt<1>("h00") T_216.io.ar.valid := UInt<1>("h00") T_216.io.b.ready := UInt<1>("h00") T_216.io.w.bits.user := UInt<1>("h00") T_216.io.w.bits.strb := UInt<1>("h00") T_216.io.w.bits.last := UInt<1>("h00") T_216.io.w.bits.data := UInt<1>("h00") T_216.io.w.valid := UInt<1>("h00") T_216.io.aw.bits.user := UInt<1>("h00") T_216.io.aw.bits.id := UInt<1>("h00") T_216.io.aw.bits.region := UInt<1>("h00") T_216.io.aw.bits.qos := UInt<1>("h00") T_216.io.aw.bits.prot := UInt<1>("h00") T_216.io.aw.bits.cache := UInt<1>("h00") T_216.io.aw.bits.lock := UInt<1>("h00") T_216.io.aw.bits.burst := UInt<1>("h00") T_216.io.aw.bits.size := UInt<1>("h00") T_216.io.aw.bits.len := UInt<1>("h00") T_216.io.aw.bits.addr := UInt<1>("h00") T_216.io.aw.valid := UInt<1>("h00") T_216.clock := clock T_216.reset := reset T_216.io <> T_77.io.mmio