circuit Top : module Htif : input clk : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.scr.resp.ready <= UInt<1>("h00") io.scr.req.bits.data <= UInt<1>("h00") io.scr.req.bits.addr <= UInt<1>("h00") io.scr.req.bits.rw <= UInt<1>("h00") io.scr.req.valid <= UInt<1>("h00") io.mem.grant.ready <= UInt<1>("h00") io.mem.acquire.bits.data <= UInt<1>("h00") io.mem.acquire.bits.union <= UInt<1>("h00") io.mem.acquire.bits.a_type <= UInt<1>("h00") io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") io.mem.acquire.bits.addr_beat <= UInt<1>("h00") io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") io.mem.acquire.bits.addr_block <= UInt<1>("h00") io.mem.acquire.valid <= UInt<1>("h00") io.cpu[0].csr.resp.ready <= UInt<1>("h00") io.cpu[0].csr.req.bits.data <= UInt<1>("h00") io.cpu[0].csr.req.bits.addr <= UInt<1>("h00") io.cpu[0].csr.req.bits.rw <= UInt<1>("h00") io.cpu[0].csr.req.valid <= UInt<1>("h00") io.cpu[0].id <= UInt<1>("h00") io.cpu[0].reset <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.out.bits <= UInt<1>("h00") io.host.out.valid <= UInt<1>("h00") io.host.in.ready <= UInt<1>("h00") io.host.clk_edge <= UInt<1>("h00") io.host.clk <= UInt<1>("h00") io.host.debug_stats_csr <= io.cpu[0].debug_stats_csr reg rx_count : UInt<15>, clk, reset, UInt<15>("h00") reg rx_shifter : UInt<64>, clk, UInt<1>("h00"), rx_shifter node T_1212 = bits(rx_shifter, 63, 16) node rx_shifter_in = cat(io.host.in.bits, T_1212) node next_cmd = bits(rx_shifter_in, 3, 0) reg cmd : UInt, clk, UInt<1>("h00"), cmd reg size : UInt, clk, UInt<1>("h00"), size reg pos : UInt, clk, UInt<1>("h00"), pos reg seqno : UInt, clk, UInt<1>("h00"), seqno reg addr : UInt, clk, UInt<1>("h00"), addr node T_1225 = and(io.host.in.valid, io.host.in.ready) when T_1225 : rx_shifter <= rx_shifter_in node T_1227 = addw(rx_count, UInt<1>("h01")) rx_count <= T_1227 node T_1229 = eq(rx_count, UInt<2>("h03")) when T_1229 : cmd <= next_cmd node T_1230 = bits(rx_shifter_in, 15, 4) size <= T_1230 node T_1231 = bits(rx_shifter_in, 15, 7) pos <= T_1231 node T_1232 = bits(rx_shifter_in, 23, 16) seqno <= T_1232 node T_1233 = bits(rx_shifter_in, 63, 24) addr <= T_1233 skip skip node rx_word_count = shr(rx_count, 2) node T_1235 = bits(rx_count, 1, 0) node T_1236 = not(T_1235) node T_1238 = eq(T_1236, UInt<1>("h00")) node rx_word_done = and(io.host.in.valid, T_1238) cmem packet_ram : UInt<64>[8] node T_1243 = and(rx_word_done, io.host.in.ready) when T_1243 : node T_1244 = bits(rx_word_count, 2, 0) node T_1246 = subw(T_1244, UInt<1>("h01")) infer mport T_1247 = packet_ram[T_1246], clk T_1247 <= rx_shifter_in skip node csr_addr = bits(addr, 11, 0) node csr_coreid = bits(addr, 21, 20) infer mport csr_wdata = packet_ram[UInt<1>("h00")], clk node T_1259 = bits(size, 2, 0) node T_1261 = neq(T_1259, UInt<1>("h00")) node T_1262 = bits(addr, 2, 0) node T_1264 = neq(T_1262, UInt<1>("h00")) node bad_mem_packet = or(T_1261, T_1264) node T_1266 = eq(cmd, UInt<1>("h00")) node T_1267 = eq(cmd, UInt<1>("h01")) node T_1268 = or(T_1266, T_1267) node T_1269 = eq(cmd, UInt<2>("h02")) node T_1270 = eq(cmd, UInt<2>("h03")) node T_1271 = or(T_1269, T_1270) node T_1273 = neq(size, UInt<1>("h01")) node T_1275 = mux(T_1271, T_1273, UInt<1>("h01")) node nack = mux(T_1268, bad_mem_packet, T_1275) reg tx_count : UInt<15>, clk, reset, UInt<15>("h00") node tx_subword_count = bits(tx_count, 1, 0) node tx_word_count = bits(tx_count, 14, 2) node T_1281 = bits(tx_word_count, 2, 0) node packet_ram_raddr = subw(T_1281, UInt<1>("h01")) node T_1284 = and(io.host.out.valid, io.host.out.ready) when T_1284 : node T_1286 = addw(tx_count, UInt<1>("h01")) tx_count <= T_1286 skip node T_1288 = eq(rx_word_count, UInt<1>("h00")) node T_1289 = neq(next_cmd, UInt<1>("h01")) node T_1290 = neq(next_cmd, UInt<2>("h03")) node T_1291 = and(T_1289, T_1290) node T_1292 = eq(rx_word_count, size) node T_1293 = bits(rx_word_count, 2, 0) node T_1295 = eq(T_1293, UInt<1>("h00")) node T_1296 = or(T_1292, T_1295) node T_1297 = mux(T_1288, T_1291, T_1296) node rx_done = and(rx_word_done, T_1297) node T_1300 = eq(nack, UInt<1>("h00")) node T_1301 = eq(cmd, UInt<1>("h00")) node T_1302 = eq(cmd, UInt<2>("h02")) node T_1303 = or(T_1301, T_1302) node T_1304 = eq(cmd, UInt<2>("h03")) node T_1305 = or(T_1303, T_1304) node T_1306 = and(T_1300, T_1305) node tx_size = mux(T_1306, size, UInt<1>("h00")) node T_1309 = not(tx_subword_count) node T_1311 = eq(T_1309, UInt<1>("h00")) node T_1312 = and(io.host.out.ready, T_1311) node T_1313 = eq(tx_word_count, tx_size) node T_1315 = gt(tx_word_count, UInt<1>("h00")) node T_1316 = not(packet_ram_raddr) node T_1318 = eq(T_1316, UInt<1>("h00")) node T_1319 = and(T_1315, T_1318) node T_1320 = or(T_1313, T_1319) node tx_done = and(T_1312, T_1320) reg state : UInt, clk, reset, UInt<1>("h00") node T_1332 = eq(state, UInt<3>("h04")) node T_1333 = and(T_1332, io.mem.acquire.ready) node T_1334 = eq(state, UInt<3>("h05")) node T_1335 = and(T_1334, io.mem.grant.valid) node T_1336 = or(T_1333, T_1335) reg cnt : UInt<2>, clk, reset, UInt<2>("h00") when T_1336 : node T_1340 = eq(cnt, UInt<2>("h03")) node T_1342 = and(UInt<1>("h00"), T_1340) node T_1345 = addw(cnt, UInt<1>("h01")) node T_1346 = mux(T_1342, UInt<1>("h00"), T_1345) cnt <= T_1346 skip node cnt_done = and(T_1336, T_1340) node T_1349 = eq(rx_word_count, UInt<1>("h00")) node rx_cmd = mux(T_1349, next_cmd, cmd) node T_1351 = eq(state, UInt<1>("h00")) node T_1352 = and(T_1351, rx_done) when T_1352 : node T_1353 = eq(rx_cmd, UInt<1>("h00")) node T_1354 = eq(rx_cmd, UInt<1>("h01")) node T_1355 = eq(rx_cmd, UInt<2>("h02")) node T_1356 = eq(rx_cmd, UInt<2>("h03")) node T_1357 = or(T_1355, T_1356) node T_1358 = mux(T_1357, UInt<1>("h01"), UInt<3>("h07")) node T_1359 = mux(T_1354, UInt<3>("h04"), T_1358) node T_1360 = mux(T_1353, UInt<2>("h03"), T_1359) state <= T_1360 skip node T_1361 = eq(state, UInt<3>("h04")) when T_1361 : when cnt_done : state <= UInt<3>("h06") skip skip node T_1362 = eq(state, UInt<2>("h03")) when T_1362 : when io.mem.acquire.ready : state <= UInt<3>("h05") skip skip node T_1363 = eq(state, UInt<3>("h06")) node T_1364 = and(T_1363, io.mem.grant.valid) when T_1364 : node T_1365 = eq(cmd, UInt<1>("h00")) node T_1367 = eq(pos, UInt<1>("h01")) node T_1368 = or(T_1365, T_1367) node T_1369 = mux(T_1368, UInt<3>("h07"), UInt<1>("h00")) state <= T_1369 node T_1371 = subw(pos, UInt<1>("h01")) pos <= T_1371 node T_1373 = addw(addr, UInt<4>("h08")) addr <= T_1373 skip node T_1374 = eq(state, UInt<3>("h05")) node T_1375 = and(T_1374, cnt_done) when T_1375 : node T_1376 = eq(cmd, UInt<1>("h00")) node T_1378 = eq(pos, UInt<1>("h01")) node T_1379 = or(T_1376, T_1378) node T_1380 = mux(T_1379, UInt<3>("h07"), UInt<1>("h00")) state <= T_1380 node T_1382 = subw(pos, UInt<1>("h01")) pos <= T_1382 node T_1384 = addw(addr, UInt<4>("h08")) addr <= T_1384 skip node T_1385 = eq(state, UInt<3>("h07")) node T_1386 = and(T_1385, tx_done) when T_1386 : node T_1387 = eq(tx_word_count, tx_size) when T_1387 : rx_count <= UInt<1>("h00") tx_count <= UInt<1>("h00") skip node T_1390 = eq(cmd, UInt<1>("h00")) node T_1392 = neq(pos, UInt<1>("h00")) node T_1393 = and(T_1390, T_1392) node T_1394 = mux(T_1393, UInt<2>("h03"), UInt<1>("h00")) state <= T_1394 skip node T_1396 = eq(state, UInt<3>("h05")) node T_1397 = and(T_1396, io.mem.grant.valid) when T_1397 : node T_1398 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00")) infer mport T_1399 = packet_ram[T_1398], clk node T_1400 = bits(io.mem.grant.bits.data, 63, 0) T_1399 <= T_1400 skip node T_1401 = cat(cnt, UInt<1>("h00")) infer mport T_1402 = packet_ram[T_1401], clk node T_1404 = eq(state, UInt<3>("h05")) node T_1405 = and(T_1404, io.mem.grant.valid) when T_1405 : node T_1406 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01")) infer mport T_1407 = packet_ram[T_1406], clk node T_1408 = bits(io.mem.grant.bits.data, 127, 64) T_1407 <= T_1408 skip node T_1409 = cat(cnt, UInt<1>("h01")) infer mport T_1410 = packet_ram[T_1409], clk node mem_req_data = cat(T_1410, T_1402) node init_addr = shr(addr, 3) node T_1413 = eq(state, UInt<2>("h03")) node T_1414 = eq(state, UInt<3>("h04")) node T_1415 = or(T_1413, T_1414) io.mem.acquire.valid <= T_1415 node T_1416 = eq(cmd, UInt<1>("h01")) node T_1444 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1450 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1451 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1452 = cat(T_1450, T_1451) node T_1454 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1455 = cat(UInt<3>("h07"), T_1454) node T_1457 = cat(T_1444, UInt<1>("h01")) node T_1459 = cat(T_1444, UInt<1>("h01")) node T_1461 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1462 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1463 = cat(T_1461, T_1462) node T_1465 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1467 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1468 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_1469 = mux(T_1468, T_1467, UInt<1>("h00")) node T_1470 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_1471 = mux(T_1470, T_1465, T_1469) node T_1472 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_1473 = mux(T_1472, T_1463, T_1471) node T_1474 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_1475 = mux(T_1474, T_1459, T_1473) node T_1476 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_1477 = mux(T_1476, T_1457, T_1475) node T_1478 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_1479 = mux(T_1478, T_1455, T_1477) node T_1480 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_1481 = mux(T_1480, T_1452, T_1479) wire T_1513 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1513.data <= UInt<1>("h00") T_1513.union <= UInt<1>("h00") T_1513.a_type <= UInt<1>("h00") T_1513.is_builtin_type <= UInt<1>("h00") T_1513.addr_beat <= UInt<1>("h00") T_1513.client_xact_id <= UInt<1>("h00") T_1513.addr_block <= UInt<1>("h00") T_1513.is_builtin_type <= UInt<1>("h01") T_1513.a_type <= UInt<3>("h03") T_1513.client_xact_id <= UInt<1>("h00") T_1513.addr_block <= init_addr T_1513.addr_beat <= cnt T_1513.data <= mem_req_data T_1513.union <= T_1481 node T_1561 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1562 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1563 = cat(T_1561, T_1562) node T_1565 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1566 = cat(UInt<3>("h07"), T_1565) node T_1568 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1570 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1572 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1573 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1574 = cat(T_1572, T_1573) node T_1576 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1578 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1579 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1580 = mux(T_1579, T_1578, UInt<1>("h00")) node T_1581 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1582 = mux(T_1581, T_1576, T_1580) node T_1583 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1584 = mux(T_1583, T_1574, T_1582) node T_1585 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1586 = mux(T_1585, T_1570, T_1584) node T_1587 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1588 = mux(T_1587, T_1568, T_1586) node T_1589 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1590 = mux(T_1589, T_1566, T_1588) node T_1591 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1592 = mux(T_1591, T_1563, T_1590) wire T_1624 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1624.data <= UInt<1>("h00") T_1624.union <= UInt<1>("h00") T_1624.a_type <= UInt<1>("h00") T_1624.is_builtin_type <= UInt<1>("h00") T_1624.addr_beat <= UInt<1>("h00") T_1624.client_xact_id <= UInt<1>("h00") T_1624.addr_block <= UInt<1>("h00") T_1624.is_builtin_type <= UInt<1>("h01") T_1624.a_type <= UInt<3>("h01") T_1624.client_xact_id <= UInt<1>("h00") T_1624.addr_block <= init_addr T_1624.addr_beat <= UInt<1>("h00") T_1624.data <= UInt<1>("h00") T_1624.union <= T_1592 wire T_1693 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1693 <- T_1624 when T_1416 : T_1693 <- T_1513 skip io.mem.acquire.bits <- T_1693 io.mem.grant.ready <= UInt<1>("h01") reg csrReadData : UInt<64>, clk, UInt<1>("h00"), csrReadData reg T_1728 : UInt<1>, clk, reset, UInt<1>("h01") node T_1730 = eq(csr_coreid, UInt<1>("h00")) node T_1731 = eq(state, UInt<1>("h01")) node T_1732 = and(T_1731, T_1730) node T_1734 = neq(csr_addr, UInt<11>("h0782")) node T_1735 = and(T_1732, T_1734) io.cpu[0].csr.req.valid <= T_1735 node T_1736 = eq(cmd, UInt<2>("h03")) io.cpu[0].csr.req.bits.rw <= T_1736 io.cpu[0].csr.req.bits.addr <= csr_addr io.cpu[0].csr.req.bits.data <= csr_wdata io.cpu[0].reset <= T_1728 node T_1737 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid) when T_1737 : state <= UInt<2>("h02") skip node T_1738 = eq(state, UInt<1>("h01")) node T_1739 = and(T_1738, T_1730) node T_1741 = eq(csr_addr, UInt<11>("h0782")) node T_1742 = and(T_1739, T_1741) when T_1742 : node T_1743 = eq(cmd, UInt<2>("h03")) when T_1743 : node T_1744 = bit(csr_wdata, 0) T_1728 <= T_1744 skip csrReadData <= T_1728 state <= UInt<3>("h07") skip io.cpu[0].csr.resp.ready <= UInt<1>("h01") node T_1746 = eq(state, UInt<2>("h02")) node T_1747 = and(T_1746, io.cpu[0].csr.resp.valid) when T_1747 : csrReadData <= io.cpu[0].csr.resp.bits state <= UInt<3>("h07") skip node T_1748 = eq(state, UInt<1>("h01")) node T_1749 = not(csr_coreid) node T_1751 = eq(T_1749, UInt<1>("h00")) node T_1752 = and(T_1748, T_1751) io.scr.req.valid <= T_1752 node T_1753 = bits(addr, 5, 0) io.scr.req.bits.addr <= T_1753 io.scr.req.bits.data <= csr_wdata node T_1754 = eq(cmd, UInt<2>("h03")) io.scr.req.bits.rw <= T_1754 io.scr.resp.ready <= UInt<1>("h01") node T_1756 = and(io.scr.req.ready, io.scr.req.valid) when T_1756 : state <= UInt<2>("h02") skip node T_1757 = eq(state, UInt<2>("h02")) node T_1758 = and(T_1757, io.scr.resp.valid) when T_1758 : csrReadData <= io.scr.resp.bits state <= UInt<3>("h07") skip node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) node T_1762 = cat(addr, seqno) node T_1763 = cat(tx_size, tx_cmd_ext) node tx_header = cat(T_1762, T_1763) node T_1766 = eq(tx_word_count, UInt<1>("h00")) node T_1767 = eq(cmd, UInt<2>("h02")) node T_1768 = eq(cmd, UInt<2>("h03")) node T_1769 = or(T_1767, T_1768) infer mport T_1770 = packet_ram[packet_ram_raddr], clk node T_1771 = mux(T_1769, csrReadData, T_1770) node tx_data = mux(T_1766, tx_header, T_1771) node T_1773 = eq(state, UInt<1>("h00")) io.host.in.ready <= T_1773 node T_1774 = eq(state, UInt<3>("h07")) io.host.out.valid <= T_1774 node T_1775 = bits(tx_count, 1, 0) node T_1777 = cat(T_1775, UInt<4>("h00")) node T_1778 = dshr(tx_data, T_1777) io.host.out.bits <= T_1778 module ClientTileLinkIOWrapper : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} io.out.release.bits.data <= UInt<1>("h00") io.out.release.bits.r_type <= UInt<1>("h00") io.out.release.bits.voluntary <= UInt<1>("h00") io.out.release.bits.client_xact_id <= UInt<1>("h00") io.out.release.bits.addr_block <= UInt<1>("h00") io.out.release.bits.addr_beat <= UInt<1>("h00") io.out.release.valid <= UInt<1>("h00") io.out.probe.ready <= UInt<1>("h00") io.out.grant.ready <= UInt<1>("h00") io.out.acquire.bits.data <= UInt<1>("h00") io.out.acquire.bits.union <= UInt<1>("h00") io.out.acquire.bits.a_type <= UInt<1>("h00") io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") io.out.acquire.bits.addr_beat <= UInt<1>("h00") io.out.acquire.bits.client_xact_id <= UInt<1>("h00") io.out.acquire.bits.addr_block <= UInt<1>("h00") io.out.acquire.valid <= UInt<1>("h00") io.in.grant.bits.data <= UInt<1>("h00") io.in.grant.bits.g_type <= UInt<1>("h00") io.in.grant.bits.is_builtin_type <= UInt<1>("h00") io.in.grant.bits.manager_xact_id <= UInt<1>("h00") io.in.grant.bits.client_xact_id <= UInt<1>("h00") io.in.grant.bits.addr_beat <= UInt<1>("h00") io.in.grant.valid <= UInt<1>("h00") io.in.acquire.ready <= UInt<1>("h00") io.out.acquire <- io.in.acquire io.in.grant <- io.out.grant io.out.probe.ready <= UInt<1>("h01") io.out.release.valid <= UInt<1>("h00") module FinishQueue : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.dst <= UInt<1>("h00") io.deq.bits.fin.manager_xact_id <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem T_877 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2] reg T_879 : UInt<1>, clk, reset, UInt<1>("h00") reg T_881 : UInt<1>, clk, reset, UInt<1>("h00") reg T_883 : UInt<1>, clk, reset, UInt<1>("h00") node T_884 = eq(T_879, T_881) node T_886 = eq(T_883, UInt<1>("h00")) node T_887 = and(T_884, T_886) node T_888 = and(T_884, T_883) node T_890 = and(UInt<1>("h00"), T_887) node T_891 = and(T_890, io.deq.ready) node T_892 = and(io.enq.ready, io.enq.valid) node T_894 = eq(T_891, UInt<1>("h00")) node T_895 = and(T_892, T_894) node T_896 = and(io.deq.ready, io.deq.valid) node T_898 = eq(T_891, UInt<1>("h00")) node T_899 = and(T_896, T_898) when T_895 : infer mport T_900 = T_877[T_879], clk T_900 <- io.enq.bits node T_997 = eq(T_879, UInt<1>("h01")) node T_999 = and(UInt<1>("h00"), T_997) node T_1002 = addw(T_879, UInt<1>("h01")) node T_1003 = mux(T_999, UInt<1>("h00"), T_1002) T_879 <= T_1003 skip when T_899 : node T_1005 = eq(T_881, UInt<1>("h01")) node T_1007 = and(UInt<1>("h00"), T_1005) node T_1010 = addw(T_881, UInt<1>("h01")) node T_1011 = mux(T_1007, UInt<1>("h00"), T_1010) T_881 <= T_1011 skip node T_1012 = neq(T_895, T_899) when T_1012 : T_883 <= T_895 skip node T_1014 = eq(T_887, UInt<1>("h00")) node T_1016 = and(UInt<1>("h00"), io.enq.valid) node T_1017 = or(T_1014, T_1016) io.deq.valid <= T_1017 node T_1019 = eq(T_888, UInt<1>("h00")) node T_1021 = and(UInt<1>("h00"), io.deq.ready) node T_1022 = or(T_1019, T_1021) io.enq.ready <= T_1022 infer mport T_1023 = T_877[T_881], clk wire T_1215 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>} T_1215 <- T_1023 when T_890 : T_1215 <- io.enq.bits skip io.deq.bits <- T_1215 node T_1311 = subw(T_879, T_881) node T_1312 = and(T_883, T_884) node T_1313 = cat(T_1312, T_1311) io.count <= T_1313 module FinishUnit : input clk : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready <= UInt<1>("h00") io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.finish.bits.header.dst <= UInt<1>("h00") io.finish.bits.header.src <= UInt<1>("h00") io.finish.valid <= UInt<1>("h00") io.refill.bits.data <= UInt<1>("h00") io.refill.bits.g_type <= UInt<1>("h00") io.refill.bits.is_builtin_type <= UInt<1>("h00") io.refill.bits.manager_xact_id <= UInt<1>("h00") io.refill.bits.client_xact_id <= UInt<1>("h00") io.refill.bits.addr_beat <= UInt<1>("h00") io.refill.valid <= UInt<1>("h00") io.grant.ready <= UInt<1>("h00") node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) node T_1188 = or(UInt<1>("h00"), T_1186) wire T_1190 : UInt<1>[2] T_1190[0] <= UInt<1>("h00") T_1190[1] <= UInt<1>("h01") node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) node T_1197 = or(UInt<1>("h00"), T_1194) node T_1198 = or(T_1197, T_1195) node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) node T_1210 = addw(T_1203, UInt<1>("h01")) node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) T_1203 <= T_1211 skip node T_1212 = and(T_1201, T_1205) node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) node T_1214 = mux(T_1200, T_1212, T_1178) inst T_1311 of FinishQueue T_1311.io.deq.ready <= UInt<1>("h00") T_1311.io.enq.bits.dst <= UInt<1>("h00") T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") T_1311.io.enq.valid <= UInt<1>("h00") T_1311.clk <= clk T_1311.reset <= reset node T_1316 = and(io.grant.ready, io.grant.valid) node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) node T_1324 = eq(T_1322, UInt<1>("h00")) node T_1325 = and(T_1319, T_1324) node T_1326 = and(T_1316, T_1325) wire T_1330 : UInt<3>[1] T_1330[0] <= UInt<3>("h05") node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) node T_1335 = or(UInt<1>("h00"), T_1333) wire T_1337 : UInt<1>[2] T_1337[0] <= UInt<1>("h00") T_1337[1] <= UInt<1>("h01") node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) node T_1344 = or(UInt<1>("h00"), T_1341) node T_1345 = or(T_1344, T_1342) node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) node T_1347 = and(UInt<1>("h01"), T_1346) node T_1349 = eq(T_1347, UInt<1>("h00")) node T_1350 = or(T_1349, T_1214) node T_1351 = and(T_1326, T_1350) T_1311.io.enq.valid <= T_1351 wire T_1377 : {manager_xact_id : UInt<4>} T_1377.manager_xact_id <= UInt<1>("h00") T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id T_1311.io.enq.bits.fin <- T_1377 T_1311.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<1>("h00") io.finish.bits.header.dst <= T_1311.io.deq.bits.dst io.finish.bits.payload <- T_1311.io.deq.bits.fin io.finish.valid <= T_1311.io.deq.valid T_1311.io.deq.ready <= io.finish.ready node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) node T_1411 = eq(T_1409, UInt<1>("h00")) node T_1412 = and(T_1406, T_1411) node T_1414 = eq(T_1412, UInt<1>("h00")) node T_1415 = or(T_1311.io.enq.ready, T_1414) node T_1416 = and(T_1415, io.grant.valid) io.refill.valid <= T_1416 io.refill.bits <- io.grant.bits.payload node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) node T_1424 = eq(T_1422, UInt<1>("h00")) node T_1425 = and(T_1419, T_1424) node T_1427 = eq(T_1425, UInt<1>("h00")) node T_1428 = or(T_1311.io.enq.ready, T_1427) node T_1429 = and(T_1428, io.refill.ready) io.grant.ready <= T_1429 io.ready <= T_1311.io.enq.ready module ClientTileLinkNetworkPort : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.network.release.bits.payload.data <= UInt<1>("h00") io.network.release.bits.payload.r_type <= UInt<1>("h00") io.network.release.bits.payload.voluntary <= UInt<1>("h00") io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") io.network.release.bits.payload.addr_block <= UInt<1>("h00") io.network.release.bits.payload.addr_beat <= UInt<1>("h00") io.network.release.bits.header.dst <= UInt<1>("h00") io.network.release.bits.header.src <= UInt<1>("h00") io.network.release.valid <= UInt<1>("h00") io.network.probe.ready <= UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.network.finish.bits.header.dst <= UInt<1>("h00") io.network.finish.bits.header.src <= UInt<1>("h00") io.network.finish.valid <= UInt<1>("h00") io.network.grant.ready <= UInt<1>("h00") io.network.acquire.bits.payload.data <= UInt<1>("h00") io.network.acquire.bits.payload.union <= UInt<1>("h00") io.network.acquire.bits.payload.a_type <= UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") io.network.acquire.bits.header.dst <= UInt<1>("h00") io.network.acquire.bits.header.src <= UInt<1>("h00") io.network.acquire.valid <= UInt<1>("h00") io.client.release.ready <= UInt<1>("h00") io.client.probe.bits.p_type <= UInt<1>("h00") io.client.probe.bits.addr_block <= UInt<1>("h00") io.client.probe.valid <= UInt<1>("h00") io.client.grant.bits.data <= UInt<1>("h00") io.client.grant.bits.g_type <= UInt<1>("h00") io.client.grant.bits.is_builtin_type <= UInt<1>("h00") io.client.grant.bits.manager_xact_id <= UInt<1>("h00") io.client.grant.bits.client_xact_id <= UInt<1>("h00") io.client.grant.bits.addr_beat <= UInt<1>("h00") io.client.grant.valid <= UInt<1>("h00") io.client.acquire.ready <= UInt<1>("h00") inst finisher of FinishUnit finisher.io.finish.ready <= UInt<1>("h00") finisher.io.refill.ready <= UInt<1>("h00") finisher.io.grant.bits.payload.data <= UInt<1>("h00") finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") finisher.io.grant.bits.header.dst <= UInt<1>("h00") finisher.io.grant.bits.header.src <= UInt<1>("h00") finisher.io.grant.valid <= UInt<1>("h00") finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} acq_with_header.bits.payload.data <= UInt<1>("h00") acq_with_header.bits.payload.union <= UInt<1>("h00") acq_with_header.bits.payload.a_type <= UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") acq_with_header.bits.payload.addr_block <= UInt<1>("h00") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.bits.header.src <= UInt<1>("h00") acq_with_header.valid <= UInt<1>("h00") acq_with_header.ready <= UInt<1>("h00") acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<1>("h00") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} rel_with_header.bits.payload.data <= UInt<1>("h00") rel_with_header.bits.payload.r_type <= UInt<1>("h00") rel_with_header.bits.payload.voluntary <= UInt<1>("h00") rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") rel_with_header.bits.payload.addr_block <= UInt<1>("h00") rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.bits.header.src <= UInt<1>("h00") rel_with_header.valid <= UInt<1>("h00") rel_with_header.ready <= UInt<1>("h00") rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<1>("h00") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type <= UInt<1>("h00") prb_without_header.bits.addr_block <= UInt<1>("h00") prb_without_header.valid <= UInt<1>("h00") prb_without_header.ready <= UInt<1>("h00") prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits node T_5014 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid <= T_5014 node T_5015 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready <= T_5015 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill module Queue : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.payload.data <= UInt<1>("h00") io.deq.bits.payload.union <= UInt<1>("h00") io.deq.bits.payload.a_type <= UInt<1>("h00") io.deq.bits.payload.is_builtin_type <= UInt<1>("h00") io.deq.bits.payload.addr_beat <= UInt<1>("h00") io.deq.bits.payload.client_xact_id <= UInt<1>("h00") io.deq.bits.payload.addr_block <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2] reg T_1160 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1162 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_1160, T_1162) node T_1167 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1167) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1173 = and(io.enq.ready, io.enq.valid) node T_1175 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1173, T_1175) node T_1177 = and(io.deq.ready, io.deq.valid) node T_1179 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1177, T_1179) when do_enq : infer mport T_1181 = ram[T_1160], clk T_1181 <- io.enq.bits node T_1309 = eq(T_1160, UInt<1>("h01")) node T_1311 = and(UInt<1>("h00"), T_1309) node T_1314 = addw(T_1160, UInt<1>("h01")) node T_1315 = mux(T_1311, UInt<1>("h00"), T_1314) T_1160 <= T_1315 skip when do_deq : node T_1317 = eq(T_1162, UInt<1>("h01")) node T_1319 = and(UInt<1>("h00"), T_1317) node T_1322 = addw(T_1162, UInt<1>("h01")) node T_1323 = mux(T_1319, UInt<1>("h00"), T_1322) T_1162 <= T_1323 skip node T_1324 = neq(do_enq, do_deq) when T_1324 : maybe_full <= do_enq skip node T_1326 = eq(empty, UInt<1>("h00")) node T_1328 = and(UInt<1>("h00"), io.enq.valid) node T_1329 = or(T_1326, T_1328) io.deq.valid <= T_1329 node T_1331 = eq(full, UInt<1>("h00")) node T_1333 = and(UInt<1>("h00"), io.deq.ready) node T_1334 = or(T_1331, T_1333) io.enq.ready <= T_1334 infer mport T_1335 = ram[T_1162], clk wire T_1589 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} T_1589 <- T_1335 when maybe_flow : T_1589 <- io.enq.bits skip io.deq.bits <- T_1589 node ptr_diff = subw(T_1160, T_1162) node T_1717 = and(maybe_full, ptr_match) node T_1718 = cat(T_1717, ptr_diff) io.count <= T_1718 module Queue_2 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.payload.p_type <= UInt<1>("h00") io.deq.bits.payload.addr_block <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2] reg T_1115 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1117 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_1115, T_1117) node T_1122 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1122) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1128 = and(io.enq.ready, io.enq.valid) node T_1130 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1128, T_1130) node T_1132 = and(io.deq.ready, io.deq.valid) node T_1134 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1132, T_1134) when do_enq : infer mport T_1136 = ram[T_1115], clk T_1136 <- io.enq.bits node T_1259 = eq(T_1115, UInt<1>("h01")) node T_1261 = and(UInt<1>("h00"), T_1259) node T_1264 = addw(T_1115, UInt<1>("h01")) node T_1265 = mux(T_1261, UInt<1>("h00"), T_1264) T_1115 <= T_1265 skip when do_deq : node T_1267 = eq(T_1117, UInt<1>("h01")) node T_1269 = and(UInt<1>("h00"), T_1267) node T_1272 = addw(T_1117, UInt<1>("h01")) node T_1273 = mux(T_1269, UInt<1>("h00"), T_1272) T_1117 <= T_1273 skip node T_1274 = neq(do_enq, do_deq) when T_1274 : maybe_full <= do_enq skip node T_1276 = eq(empty, UInt<1>("h00")) node T_1278 = and(UInt<1>("h00"), io.enq.valid) node T_1279 = or(T_1276, T_1278) io.deq.valid <= T_1279 node T_1281 = eq(full, UInt<1>("h00")) node T_1283 = and(UInt<1>("h00"), io.deq.ready) node T_1284 = or(T_1281, T_1283) io.enq.ready <= T_1284 infer mport T_1285 = ram[T_1117], clk wire T_1529 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}} T_1529 <- T_1285 when maybe_flow : T_1529 <- io.enq.bits skip io.deq.bits <- T_1529 node ptr_diff = subw(T_1115, T_1117) node T_1652 = and(maybe_full, ptr_match) node T_1653 = cat(T_1652, ptr_diff) io.count <= T_1653 module Queue_3 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.payload.data <= UInt<1>("h00") io.deq.bits.payload.r_type <= UInt<1>("h00") io.deq.bits.payload.voluntary <= UInt<1>("h00") io.deq.bits.payload.client_xact_id <= UInt<1>("h00") io.deq.bits.payload.addr_block <= UInt<1>("h00") io.deq.bits.payload.addr_beat <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2] reg T_1151 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1153 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_1151, T_1153) node T_1158 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1158) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1164 = and(io.enq.ready, io.enq.valid) node T_1166 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1164, T_1166) node T_1168 = and(io.deq.ready, io.deq.valid) node T_1170 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1168, T_1170) when do_enq : infer mport T_1172 = ram[T_1151], clk T_1172 <- io.enq.bits node T_1299 = eq(T_1151, UInt<1>("h01")) node T_1301 = and(UInt<1>("h00"), T_1299) node T_1304 = addw(T_1151, UInt<1>("h01")) node T_1305 = mux(T_1301, UInt<1>("h00"), T_1304) T_1151 <= T_1305 skip when do_deq : node T_1307 = eq(T_1153, UInt<1>("h01")) node T_1309 = and(UInt<1>("h00"), T_1307) node T_1312 = addw(T_1153, UInt<1>("h01")) node T_1313 = mux(T_1309, UInt<1>("h00"), T_1312) T_1153 <= T_1313 skip node T_1314 = neq(do_enq, do_deq) when T_1314 : maybe_full <= do_enq skip node T_1316 = eq(empty, UInt<1>("h00")) node T_1318 = and(UInt<1>("h00"), io.enq.valid) node T_1319 = or(T_1316, T_1318) io.deq.valid <= T_1319 node T_1321 = eq(full, UInt<1>("h00")) node T_1323 = and(UInt<1>("h00"), io.deq.ready) node T_1324 = or(T_1321, T_1323) io.enq.ready <= T_1324 infer mport T_1325 = ram[T_1153], clk wire T_1577 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} T_1577 <- T_1325 when maybe_flow : T_1577 <- io.enq.bits skip io.deq.bits <- T_1577 node ptr_diff = subw(T_1151, T_1153) node T_1704 = and(maybe_full, ptr_match) node T_1705 = cat(T_1704, ptr_diff) io.count <= T_1705 module Queue_4 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.payload.data <= UInt<1>("h00") io.deq.bits.payload.g_type <= UInt<1>("h00") io.deq.bits.payload.is_builtin_type <= UInt<1>("h00") io.deq.bits.payload.manager_xact_id <= UInt<1>("h00") io.deq.bits.payload.client_xact_id <= UInt<1>("h00") io.deq.bits.payload.addr_beat <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}[2] reg T_1151 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1153 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_1151, T_1153) node T_1158 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1158) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1164 = and(io.enq.ready, io.enq.valid) node T_1166 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1164, T_1166) node T_1168 = and(io.deq.ready, io.deq.valid) node T_1170 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1168, T_1170) when do_enq : infer mport T_1172 = ram[T_1151], clk T_1172 <- io.enq.bits node T_1299 = eq(T_1151, UInt<1>("h01")) node T_1301 = and(UInt<1>("h00"), T_1299) node T_1304 = addw(T_1151, UInt<1>("h01")) node T_1305 = mux(T_1301, UInt<1>("h00"), T_1304) T_1151 <= T_1305 skip when do_deq : node T_1307 = eq(T_1153, UInt<1>("h01")) node T_1309 = and(UInt<1>("h00"), T_1307) node T_1312 = addw(T_1153, UInt<1>("h01")) node T_1313 = mux(T_1309, UInt<1>("h00"), T_1312) T_1153 <= T_1313 skip node T_1314 = neq(do_enq, do_deq) when T_1314 : maybe_full <= do_enq skip node T_1316 = eq(empty, UInt<1>("h00")) node T_1318 = and(UInt<1>("h00"), io.enq.valid) node T_1319 = or(T_1316, T_1318) io.deq.valid <= T_1319 node T_1321 = eq(full, UInt<1>("h00")) node T_1323 = and(UInt<1>("h00"), io.deq.ready) node T_1324 = or(T_1321, T_1323) io.enq.ready <= T_1324 infer mport T_1325 = ram[T_1153], clk wire T_1577 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}} T_1577 <- T_1325 when maybe_flow : T_1577 <- io.enq.bits skip io.deq.bits <- T_1577 node ptr_diff = subw(T_1151, T_1153) node T_1704 = and(maybe_full, ptr_match) node T_1705 = cat(T_1704, ptr_diff) io.count <= T_1705 module Queue_5 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.payload.manager_xact_id <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2] reg T_1106 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1108 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_1106, T_1108) node T_1113 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1113) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1119 = and(io.enq.ready, io.enq.valid) node T_1121 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1119, T_1121) node T_1123 = and(io.deq.ready, io.deq.valid) node T_1125 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1123, T_1125) when do_enq : infer mport T_1127 = ram[T_1106], clk T_1127 <- io.enq.bits node T_1249 = eq(T_1106, UInt<1>("h01")) node T_1251 = and(UInt<1>("h00"), T_1249) node T_1254 = addw(T_1106, UInt<1>("h01")) node T_1255 = mux(T_1251, UInt<1>("h00"), T_1254) T_1106 <= T_1255 skip when do_deq : node T_1257 = eq(T_1108, UInt<1>("h01")) node T_1259 = and(UInt<1>("h00"), T_1257) node T_1262 = addw(T_1108, UInt<1>("h01")) node T_1263 = mux(T_1259, UInt<1>("h00"), T_1262) T_1108 <= T_1263 skip node T_1264 = neq(do_enq, do_deq) when T_1264 : maybe_full <= do_enq skip node T_1266 = eq(empty, UInt<1>("h00")) node T_1268 = and(UInt<1>("h00"), io.enq.valid) node T_1269 = or(T_1266, T_1268) io.deq.valid <= T_1269 node T_1271 = eq(full, UInt<1>("h00")) node T_1273 = and(UInt<1>("h00"), io.deq.ready) node T_1274 = or(T_1271, T_1273) io.enq.ready <= T_1274 infer mport T_1275 = ram[T_1108], clk wire T_1517 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}} T_1517 <- T_1275 when maybe_flow : T_1517 <- io.enq.bits skip io.deq.bits <- T_1517 node ptr_diff = subw(T_1106, T_1108) node T_1639 = and(maybe_full, ptr_match) node T_1640 = cat(T_1639, ptr_diff) io.count <= T_1640 module TileLinkEnqueuer : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.manager.release.bits.payload.data <= UInt<1>("h00") io.manager.release.bits.payload.r_type <= UInt<1>("h00") io.manager.release.bits.payload.voluntary <= UInt<1>("h00") io.manager.release.bits.payload.client_xact_id <= UInt<1>("h00") io.manager.release.bits.payload.addr_block <= UInt<1>("h00") io.manager.release.bits.payload.addr_beat <= UInt<1>("h00") io.manager.release.bits.header.dst <= UInt<1>("h00") io.manager.release.bits.header.src <= UInt<1>("h00") io.manager.release.valid <= UInt<1>("h00") io.manager.probe.ready <= UInt<1>("h00") io.manager.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.manager.finish.bits.header.dst <= UInt<1>("h00") io.manager.finish.bits.header.src <= UInt<1>("h00") io.manager.finish.valid <= UInt<1>("h00") io.manager.grant.ready <= UInt<1>("h00") io.manager.acquire.bits.payload.data <= UInt<1>("h00") io.manager.acquire.bits.payload.union <= UInt<1>("h00") io.manager.acquire.bits.payload.a_type <= UInt<1>("h00") io.manager.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") io.manager.acquire.bits.payload.addr_beat <= UInt<1>("h00") io.manager.acquire.bits.payload.client_xact_id <= UInt<1>("h00") io.manager.acquire.bits.payload.addr_block <= UInt<1>("h00") io.manager.acquire.bits.header.dst <= UInt<1>("h00") io.manager.acquire.bits.header.src <= UInt<1>("h00") io.manager.acquire.valid <= UInt<1>("h00") io.client.release.ready <= UInt<1>("h00") io.client.probe.bits.payload.p_type <= UInt<1>("h00") io.client.probe.bits.payload.addr_block <= UInt<1>("h00") io.client.probe.bits.header.dst <= UInt<1>("h00") io.client.probe.bits.header.src <= UInt<1>("h00") io.client.probe.valid <= UInt<1>("h00") io.client.finish.ready <= UInt<1>("h00") io.client.grant.bits.payload.data <= UInt<1>("h00") io.client.grant.bits.payload.g_type <= UInt<1>("h00") io.client.grant.bits.payload.is_builtin_type <= UInt<1>("h00") io.client.grant.bits.payload.manager_xact_id <= UInt<1>("h00") io.client.grant.bits.payload.client_xact_id <= UInt<1>("h00") io.client.grant.bits.payload.addr_beat <= UInt<1>("h00") io.client.grant.bits.header.dst <= UInt<1>("h00") io.client.grant.bits.header.src <= UInt<1>("h00") io.client.grant.valid <= UInt<1>("h00") io.client.acquire.ready <= UInt<1>("h00") inst T_7778 of Queue T_7778.io.deq.ready <= UInt<1>("h00") T_7778.io.enq.bits.payload.data <= UInt<1>("h00") T_7778.io.enq.bits.payload.union <= UInt<1>("h00") T_7778.io.enq.bits.payload.a_type <= UInt<1>("h00") T_7778.io.enq.bits.payload.is_builtin_type <= UInt<1>("h00") T_7778.io.enq.bits.payload.addr_beat <= UInt<1>("h00") T_7778.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") T_7778.io.enq.bits.payload.addr_block <= UInt<1>("h00") T_7778.io.enq.bits.header.dst <= UInt<1>("h00") T_7778.io.enq.bits.header.src <= UInt<1>("h00") T_7778.io.enq.valid <= UInt<1>("h00") T_7778.clk <= clk T_7778.reset <= reset T_7778.io.enq.valid <= io.client.acquire.valid T_7778.io.enq.bits <- io.client.acquire.bits io.client.acquire.ready <= T_7778.io.enq.ready io.manager.acquire <- T_7778.io.deq inst T_7912 of Queue_2 T_7912.io.deq.ready <= UInt<1>("h00") T_7912.io.enq.bits.payload.p_type <= UInt<1>("h00") T_7912.io.enq.bits.payload.addr_block <= UInt<1>("h00") T_7912.io.enq.bits.header.dst <= UInt<1>("h00") T_7912.io.enq.bits.header.src <= UInt<1>("h00") T_7912.io.enq.valid <= UInt<1>("h00") T_7912.clk <= clk T_7912.reset <= reset T_7912.io.enq.valid <= io.manager.probe.valid T_7912.io.enq.bits <- io.manager.probe.bits io.manager.probe.ready <= T_7912.io.enq.ready io.client.probe <- T_7912.io.deq inst T_8045 of Queue_3 T_8045.io.deq.ready <= UInt<1>("h00") T_8045.io.enq.bits.payload.data <= UInt<1>("h00") T_8045.io.enq.bits.payload.r_type <= UInt<1>("h00") T_8045.io.enq.bits.payload.voluntary <= UInt<1>("h00") T_8045.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") T_8045.io.enq.bits.payload.addr_block <= UInt<1>("h00") T_8045.io.enq.bits.payload.addr_beat <= UInt<1>("h00") T_8045.io.enq.bits.header.dst <= UInt<1>("h00") T_8045.io.enq.bits.header.src <= UInt<1>("h00") T_8045.io.enq.valid <= UInt<1>("h00") T_8045.clk <= clk T_8045.reset <= reset T_8045.io.enq.valid <= io.client.release.valid T_8045.io.enq.bits <- io.client.release.bits io.client.release.ready <= T_8045.io.enq.ready io.manager.release <- T_8045.io.deq inst T_8182 of Queue_4 T_8182.io.deq.ready <= UInt<1>("h00") T_8182.io.enq.bits.payload.data <= UInt<1>("h00") T_8182.io.enq.bits.payload.g_type <= UInt<1>("h00") T_8182.io.enq.bits.payload.is_builtin_type <= UInt<1>("h00") T_8182.io.enq.bits.payload.manager_xact_id <= UInt<1>("h00") T_8182.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") T_8182.io.enq.bits.payload.addr_beat <= UInt<1>("h00") T_8182.io.enq.bits.header.dst <= UInt<1>("h00") T_8182.io.enq.bits.header.src <= UInt<1>("h00") T_8182.io.enq.valid <= UInt<1>("h00") T_8182.clk <= clk T_8182.reset <= reset T_8182.io.enq.valid <= io.manager.grant.valid T_8182.io.enq.bits <- io.manager.grant.bits io.manager.grant.ready <= T_8182.io.enq.ready io.client.grant <- T_8182.io.deq inst T_8314 of Queue_5 T_8314.io.deq.ready <= UInt<1>("h00") T_8314.io.enq.bits.payload.manager_xact_id <= UInt<1>("h00") T_8314.io.enq.bits.header.dst <= UInt<1>("h00") T_8314.io.enq.bits.header.src <= UInt<1>("h00") T_8314.io.enq.valid <= UInt<1>("h00") T_8314.clk <= clk T_8314.reset <= reset T_8314.io.enq.valid <= io.client.finish.valid T_8314.io.enq.bits <- io.client.finish.bits io.client.finish.ready <= T_8314.io.enq.ready io.manager.finish <- T_8314.io.deq module FinishUnit_7 : input clk : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready <= UInt<1>("h00") io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.finish.bits.header.dst <= UInt<1>("h00") io.finish.bits.header.src <= UInt<1>("h00") io.finish.valid <= UInt<1>("h00") io.refill.bits.data <= UInt<1>("h00") io.refill.bits.g_type <= UInt<1>("h00") io.refill.bits.is_builtin_type <= UInt<1>("h00") io.refill.bits.manager_xact_id <= UInt<1>("h00") io.refill.bits.client_xact_id <= UInt<1>("h00") io.refill.bits.addr_beat <= UInt<1>("h00") io.refill.valid <= UInt<1>("h00") io.grant.ready <= UInt<1>("h00") node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) node T_1188 = or(UInt<1>("h00"), T_1186) wire T_1190 : UInt<1>[2] T_1190[0] <= UInt<1>("h00") T_1190[1] <= UInt<1>("h01") node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) node T_1197 = or(UInt<1>("h00"), T_1194) node T_1198 = or(T_1197, T_1195) node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) node T_1210 = addw(T_1203, UInt<1>("h01")) node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) T_1203 <= T_1211 skip node T_1212 = and(T_1201, T_1205) node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) node T_1214 = mux(T_1200, T_1212, T_1178) inst T_1311 of FinishQueue T_1311.io.deq.ready <= UInt<1>("h00") T_1311.io.enq.bits.dst <= UInt<1>("h00") T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") T_1311.io.enq.valid <= UInt<1>("h00") T_1311.clk <= clk T_1311.reset <= reset node T_1316 = and(io.grant.ready, io.grant.valid) node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) node T_1324 = eq(T_1322, UInt<1>("h00")) node T_1325 = and(T_1319, T_1324) node T_1326 = and(T_1316, T_1325) wire T_1330 : UInt<3>[1] T_1330[0] <= UInt<3>("h05") node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) node T_1335 = or(UInt<1>("h00"), T_1333) wire T_1337 : UInt<1>[2] T_1337[0] <= UInt<1>("h00") T_1337[1] <= UInt<1>("h01") node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) node T_1344 = or(UInt<1>("h00"), T_1341) node T_1345 = or(T_1344, T_1342) node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) node T_1347 = and(UInt<1>("h01"), T_1346) node T_1349 = eq(T_1347, UInt<1>("h00")) node T_1350 = or(T_1349, T_1214) node T_1351 = and(T_1326, T_1350) T_1311.io.enq.valid <= T_1351 wire T_1377 : {manager_xact_id : UInt<4>} T_1377.manager_xact_id <= UInt<1>("h00") T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id T_1311.io.enq.bits.fin <- T_1377 T_1311.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<1>("h01") io.finish.bits.header.dst <= T_1311.io.deq.bits.dst io.finish.bits.payload <- T_1311.io.deq.bits.fin io.finish.valid <= T_1311.io.deq.valid T_1311.io.deq.ready <= io.finish.ready node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) node T_1411 = eq(T_1409, UInt<1>("h00")) node T_1412 = and(T_1406, T_1411) node T_1414 = eq(T_1412, UInt<1>("h00")) node T_1415 = or(T_1311.io.enq.ready, T_1414) node T_1416 = and(T_1415, io.grant.valid) io.refill.valid <= T_1416 io.refill.bits <- io.grant.bits.payload node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) node T_1424 = eq(T_1422, UInt<1>("h00")) node T_1425 = and(T_1419, T_1424) node T_1427 = eq(T_1425, UInt<1>("h00")) node T_1428 = or(T_1311.io.enq.ready, T_1427) node T_1429 = and(T_1428, io.refill.ready) io.grant.ready <= T_1429 io.ready <= T_1311.io.enq.ready module ClientTileLinkNetworkPort_6 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.network.release.bits.payload.data <= UInt<1>("h00") io.network.release.bits.payload.r_type <= UInt<1>("h00") io.network.release.bits.payload.voluntary <= UInt<1>("h00") io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") io.network.release.bits.payload.addr_block <= UInt<1>("h00") io.network.release.bits.payload.addr_beat <= UInt<1>("h00") io.network.release.bits.header.dst <= UInt<1>("h00") io.network.release.bits.header.src <= UInt<1>("h00") io.network.release.valid <= UInt<1>("h00") io.network.probe.ready <= UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.network.finish.bits.header.dst <= UInt<1>("h00") io.network.finish.bits.header.src <= UInt<1>("h00") io.network.finish.valid <= UInt<1>("h00") io.network.grant.ready <= UInt<1>("h00") io.network.acquire.bits.payload.data <= UInt<1>("h00") io.network.acquire.bits.payload.union <= UInt<1>("h00") io.network.acquire.bits.payload.a_type <= UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") io.network.acquire.bits.header.dst <= UInt<1>("h00") io.network.acquire.bits.header.src <= UInt<1>("h00") io.network.acquire.valid <= UInt<1>("h00") io.client.release.ready <= UInt<1>("h00") io.client.probe.bits.p_type <= UInt<1>("h00") io.client.probe.bits.addr_block <= UInt<1>("h00") io.client.probe.valid <= UInt<1>("h00") io.client.grant.bits.data <= UInt<1>("h00") io.client.grant.bits.g_type <= UInt<1>("h00") io.client.grant.bits.is_builtin_type <= UInt<1>("h00") io.client.grant.bits.manager_xact_id <= UInt<1>("h00") io.client.grant.bits.client_xact_id <= UInt<1>("h00") io.client.grant.bits.addr_beat <= UInt<1>("h00") io.client.grant.valid <= UInt<1>("h00") io.client.acquire.ready <= UInt<1>("h00") inst finisher of FinishUnit_7 finisher.io.finish.ready <= UInt<1>("h00") finisher.io.refill.ready <= UInt<1>("h00") finisher.io.grant.bits.payload.data <= UInt<1>("h00") finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") finisher.io.grant.bits.header.dst <= UInt<1>("h00") finisher.io.grant.bits.header.src <= UInt<1>("h00") finisher.io.grant.valid <= UInt<1>("h00") finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} acq_with_header.bits.payload.data <= UInt<1>("h00") acq_with_header.bits.payload.union <= UInt<1>("h00") acq_with_header.bits.payload.a_type <= UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") acq_with_header.bits.payload.addr_block <= UInt<1>("h00") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.bits.header.src <= UInt<1>("h00") acq_with_header.valid <= UInt<1>("h00") acq_with_header.ready <= UInt<1>("h00") acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<1>("h01") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} rel_with_header.bits.payload.data <= UInt<1>("h00") rel_with_header.bits.payload.r_type <= UInt<1>("h00") rel_with_header.bits.payload.voluntary <= UInt<1>("h00") rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") rel_with_header.bits.payload.addr_block <= UInt<1>("h00") rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.bits.header.src <= UInt<1>("h00") rel_with_header.valid <= UInt<1>("h00") rel_with_header.ready <= UInt<1>("h00") rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<1>("h01") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type <= UInt<1>("h00") prb_without_header.bits.addr_block <= UInt<1>("h00") prb_without_header.valid <= UInt<1>("h00") prb_without_header.ready <= UInt<1>("h00") prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits node T_5014 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid <= T_5014 node T_5015 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready <= T_5015 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill module FinishUnit_16 : input clk : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} io.ready <= UInt<1>("h00") io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.finish.bits.header.dst <= UInt<1>("h00") io.finish.bits.header.src <= UInt<1>("h00") io.finish.valid <= UInt<1>("h00") io.refill.bits.data <= UInt<1>("h00") io.refill.bits.g_type <= UInt<1>("h00") io.refill.bits.is_builtin_type <= UInt<1>("h00") io.refill.bits.manager_xact_id <= UInt<1>("h00") io.refill.bits.client_xact_id <= UInt<1>("h00") io.refill.bits.addr_beat <= UInt<1>("h00") io.refill.valid <= UInt<1>("h00") io.grant.ready <= UInt<1>("h00") node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type) node T_1188 = or(UInt<1>("h00"), T_1186) wire T_1190 : UInt<1>[2] T_1190[0] <= UInt<1>("h00") T_1190[1] <= UInt<1>("h01") node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type) node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type) node T_1197 = or(UInt<1>("h00"), T_1194) node T_1198 = or(T_1197, T_1195) node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) node T_1210 = addw(T_1203, UInt<1>("h01")) node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) T_1203 <= T_1211 skip node T_1212 = and(T_1201, T_1205) node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) node T_1214 = mux(T_1200, T_1212, T_1178) inst T_1311 of FinishQueue T_1311.io.deq.ready <= UInt<1>("h00") T_1311.io.enq.bits.dst <= UInt<1>("h00") T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") T_1311.io.enq.valid <= UInt<1>("h00") T_1311.clk <= clk T_1311.reset <= reset node T_1316 = and(io.grant.ready, io.grant.valid) node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) node T_1324 = eq(T_1322, UInt<1>("h00")) node T_1325 = and(T_1319, T_1324) node T_1326 = and(T_1316, T_1325) wire T_1330 : UInt<3>[1] T_1330[0] <= UInt<3>("h05") node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) node T_1335 = or(UInt<1>("h00"), T_1333) wire T_1337 : UInt<1>[2] T_1337[0] <= UInt<1>("h00") T_1337[1] <= UInt<1>("h01") node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) node T_1344 = or(UInt<1>("h00"), T_1341) node T_1345 = or(T_1344, T_1342) node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) node T_1347 = and(UInt<1>("h01"), T_1346) node T_1349 = eq(T_1347, UInt<1>("h00")) node T_1350 = or(T_1349, T_1214) node T_1351 = and(T_1326, T_1350) T_1311.io.enq.valid <= T_1351 wire T_1377 : {manager_xact_id : UInt<4>} T_1377.manager_xact_id <= UInt<1>("h00") T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id T_1311.io.enq.bits.fin <- T_1377 T_1311.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<2>("h02") io.finish.bits.header.dst <= T_1311.io.deq.bits.dst io.finish.bits.payload <- T_1311.io.deq.bits.fin io.finish.valid <= T_1311.io.deq.valid T_1311.io.deq.ready <= io.finish.ready node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) node T_1411 = eq(T_1409, UInt<1>("h00")) node T_1412 = and(T_1406, T_1411) node T_1414 = eq(T_1412, UInt<1>("h00")) node T_1415 = or(T_1311.io.enq.ready, T_1414) node T_1416 = and(T_1415, io.grant.valid) io.refill.valid <= T_1416 io.refill.bits <- io.grant.bits.payload node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) node T_1424 = eq(T_1422, UInt<1>("h00")) node T_1425 = and(T_1419, T_1424) node T_1427 = eq(T_1425, UInt<1>("h00")) node T_1428 = or(T_1311.io.enq.ready, T_1427) node T_1429 = and(T_1428, io.refill.ready) io.grant.ready <= T_1429 io.ready <= T_1311.io.enq.ready module ClientTileLinkNetworkPort_15 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.network.release.bits.payload.data <= UInt<1>("h00") io.network.release.bits.payload.r_type <= UInt<1>("h00") io.network.release.bits.payload.voluntary <= UInt<1>("h00") io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") io.network.release.bits.payload.addr_block <= UInt<1>("h00") io.network.release.bits.payload.addr_beat <= UInt<1>("h00") io.network.release.bits.header.dst <= UInt<1>("h00") io.network.release.bits.header.src <= UInt<1>("h00") io.network.release.valid <= UInt<1>("h00") io.network.probe.ready <= UInt<1>("h00") io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.network.finish.bits.header.dst <= UInt<1>("h00") io.network.finish.bits.header.src <= UInt<1>("h00") io.network.finish.valid <= UInt<1>("h00") io.network.grant.ready <= UInt<1>("h00") io.network.acquire.bits.payload.data <= UInt<1>("h00") io.network.acquire.bits.payload.union <= UInt<1>("h00") io.network.acquire.bits.payload.a_type <= UInt<1>("h00") io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") io.network.acquire.bits.header.dst <= UInt<1>("h00") io.network.acquire.bits.header.src <= UInt<1>("h00") io.network.acquire.valid <= UInt<1>("h00") io.client.release.ready <= UInt<1>("h00") io.client.probe.bits.p_type <= UInt<1>("h00") io.client.probe.bits.addr_block <= UInt<1>("h00") io.client.probe.valid <= UInt<1>("h00") io.client.grant.bits.data <= UInt<1>("h00") io.client.grant.bits.g_type <= UInt<1>("h00") io.client.grant.bits.is_builtin_type <= UInt<1>("h00") io.client.grant.bits.manager_xact_id <= UInt<1>("h00") io.client.grant.bits.client_xact_id <= UInt<1>("h00") io.client.grant.bits.addr_beat <= UInt<1>("h00") io.client.grant.valid <= UInt<1>("h00") io.client.acquire.ready <= UInt<1>("h00") inst finisher of FinishUnit_16 finisher.io.finish.ready <= UInt<1>("h00") finisher.io.refill.ready <= UInt<1>("h00") finisher.io.grant.bits.payload.data <= UInt<1>("h00") finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") finisher.io.grant.bits.header.dst <= UInt<1>("h00") finisher.io.grant.bits.header.src <= UInt<1>("h00") finisher.io.grant.valid <= UInt<1>("h00") finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} acq_with_header.bits.payload.data <= UInt<1>("h00") acq_with_header.bits.payload.union <= UInt<1>("h00") acq_with_header.bits.payload.a_type <= UInt<1>("h00") acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") acq_with_header.bits.payload.addr_block <= UInt<1>("h00") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.bits.header.src <= UInt<1>("h00") acq_with_header.valid <= UInt<1>("h00") acq_with_header.ready <= UInt<1>("h00") acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<2>("h02") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} rel_with_header.bits.payload.data <= UInt<1>("h00") rel_with_header.bits.payload.r_type <= UInt<1>("h00") rel_with_header.bits.payload.voluntary <= UInt<1>("h00") rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") rel_with_header.bits.payload.addr_block <= UInt<1>("h00") rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.bits.header.src <= UInt<1>("h00") rel_with_header.valid <= UInt<1>("h00") rel_with_header.ready <= UInt<1>("h00") rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<2>("h02") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} prb_without_header.bits.p_type <= UInt<1>("h00") prb_without_header.bits.addr_block <= UInt<1>("h00") prb_without_header.valid <= UInt<1>("h00") prb_without_header.ready <= UInt<1>("h00") prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits node T_5014 = and(acq_with_header.valid, finisher.io.ready) io.network.acquire.valid <= T_5014 node T_5015 = and(io.network.acquire.ready, finisher.io.ready) acq_with_header.ready <= T_5015 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill module ManagerTileLinkNetworkPort : input clk : Clock input reset : UInt<1> output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.network.release.ready <= UInt<1>("h00") io.network.probe.bits.payload.p_type <= UInt<1>("h00") io.network.probe.bits.payload.addr_block <= UInt<1>("h00") io.network.probe.bits.header.dst <= UInt<1>("h00") io.network.probe.bits.header.src <= UInt<1>("h00") io.network.probe.valid <= UInt<1>("h00") io.network.finish.ready <= UInt<1>("h00") io.network.grant.bits.payload.data <= UInt<1>("h00") io.network.grant.bits.payload.g_type <= UInt<1>("h00") io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") io.network.grant.bits.header.dst <= UInt<1>("h00") io.network.grant.bits.header.src <= UInt<1>("h00") io.network.grant.valid <= UInt<1>("h00") io.network.acquire.ready <= UInt<1>("h00") io.manager.release.bits.client_id <= UInt<1>("h00") io.manager.release.bits.data <= UInt<1>("h00") io.manager.release.bits.r_type <= UInt<1>("h00") io.manager.release.bits.voluntary <= UInt<1>("h00") io.manager.release.bits.client_xact_id <= UInt<1>("h00") io.manager.release.bits.addr_block <= UInt<1>("h00") io.manager.release.bits.addr_beat <= UInt<1>("h00") io.manager.release.valid <= UInt<1>("h00") io.manager.probe.ready <= UInt<1>("h00") io.manager.finish.bits.manager_xact_id <= UInt<1>("h00") io.manager.finish.valid <= UInt<1>("h00") io.manager.grant.ready <= UInt<1>("h00") io.manager.acquire.bits.client_id <= UInt<1>("h00") io.manager.acquire.bits.data <= UInt<1>("h00") io.manager.acquire.bits.union <= UInt<1>("h00") io.manager.acquire.bits.a_type <= UInt<1>("h00") io.manager.acquire.bits.is_builtin_type <= UInt<1>("h00") io.manager.acquire.bits.addr_beat <= UInt<1>("h00") io.manager.acquire.bits.client_xact_id <= UInt<1>("h00") io.manager.acquire.bits.addr_block <= UInt<1>("h00") io.manager.acquire.valid <= UInt<1>("h00") wire T_6833 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}} T_6833.bits.payload.client_id <= UInt<1>("h00") T_6833.bits.payload.data <= UInt<1>("h00") T_6833.bits.payload.g_type <= UInt<1>("h00") T_6833.bits.payload.is_builtin_type <= UInt<1>("h00") T_6833.bits.payload.manager_xact_id <= UInt<1>("h00") T_6833.bits.payload.client_xact_id <= UInt<1>("h00") T_6833.bits.payload.addr_beat <= UInt<1>("h00") T_6833.bits.header.dst <= UInt<1>("h00") T_6833.bits.header.src <= UInt<1>("h00") T_6833.valid <= UInt<1>("h00") T_6833.ready <= UInt<1>("h00") T_6833.bits.payload <- io.manager.grant.bits T_6833.bits.header.src <= UInt<1>("h00") T_6833.bits.header.dst <= io.manager.grant.bits.client_id T_6833.valid <= io.manager.grant.valid io.manager.grant.ready <= T_6833.ready io.network.grant <- T_6833 wire T_7474 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} T_7474.bits.payload.client_id <= UInt<1>("h00") T_7474.bits.payload.p_type <= UInt<1>("h00") T_7474.bits.payload.addr_block <= UInt<1>("h00") T_7474.bits.header.dst <= UInt<1>("h00") T_7474.bits.header.src <= UInt<1>("h00") T_7474.valid <= UInt<1>("h00") T_7474.ready <= UInt<1>("h00") T_7474.bits.payload <- io.manager.probe.bits T_7474.bits.header.src <= UInt<1>("h00") T_7474.bits.header.dst <= io.manager.probe.bits.client_id T_7474.valid <= io.manager.probe.valid io.manager.probe.ready <= T_7474.ready io.network.probe <- T_7474 io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src wire T_7796 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} T_7796.bits.data <= UInt<1>("h00") T_7796.bits.union <= UInt<1>("h00") T_7796.bits.a_type <= UInt<1>("h00") T_7796.bits.is_builtin_type <= UInt<1>("h00") T_7796.bits.addr_beat <= UInt<1>("h00") T_7796.bits.client_xact_id <= UInt<1>("h00") T_7796.bits.addr_block <= UInt<1>("h00") T_7796.valid <= UInt<1>("h00") T_7796.ready <= UInt<1>("h00") T_7796.valid <= io.network.acquire.valid T_7796.bits <- io.network.acquire.bits.payload io.network.acquire.ready <= T_7796.ready io.manager.acquire <- T_7796 io.manager.release.bits.client_id <= io.network.release.bits.header.src wire T_7933 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} T_7933.bits.data <= UInt<1>("h00") T_7933.bits.r_type <= UInt<1>("h00") T_7933.bits.voluntary <= UInt<1>("h00") T_7933.bits.client_xact_id <= UInt<1>("h00") T_7933.bits.addr_block <= UInt<1>("h00") T_7933.bits.addr_beat <= UInt<1>("h00") T_7933.valid <= UInt<1>("h00") T_7933.ready <= UInt<1>("h00") T_7933.valid <= io.network.release.valid T_7933.bits <- io.network.release.bits.payload io.network.release.ready <= T_7933.ready io.manager.release <- T_7933 wire T_8057 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} T_8057.bits.manager_xact_id <= UInt<1>("h00") T_8057.valid <= UInt<1>("h00") T_8057.ready <= UInt<1>("h00") T_8057.valid <= io.network.finish.valid T_8057.bits <- io.network.finish.bits.payload io.network.finish.ready <= T_8057.ready io.manager.finish <- T_8057 module Queue_25 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<1>} io.count <= UInt<1>("h00") io.deq.bits.payload.data <= UInt<1>("h00") io.deq.bits.payload.r_type <= UInt<1>("h00") io.deq.bits.payload.voluntary <= UInt<1>("h00") io.deq.bits.payload.client_xact_id <= UInt<1>("h00") io.deq.bits.payload.addr_block <= UInt<1>("h00") io.deq.bits.payload.addr_beat <= UInt<1>("h00") io.deq.bits.header.dst <= UInt<1>("h00") io.deq.bits.header.src <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[1] reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1156 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1156) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_1162 = and(io.enq.ready, io.enq.valid) node T_1164 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_1162, T_1164) node T_1166 = and(io.deq.ready, io.deq.valid) node T_1168 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_1166, T_1168) when do_enq : infer mport T_1170 = ram[UInt<1>("h00")], clk T_1170 <- io.enq.bits skip when do_deq : skip node T_1298 = neq(do_enq, do_deq) when T_1298 : maybe_full <= do_enq skip node T_1300 = eq(empty, UInt<1>("h00")) node T_1302 = and(UInt<1>("h00"), io.enq.valid) node T_1303 = or(T_1300, T_1302) io.deq.valid <= T_1303 node T_1305 = eq(full, UInt<1>("h00")) node T_1307 = and(UInt<1>("h00"), io.deq.ready) node T_1308 = or(T_1305, T_1307) io.enq.ready <= T_1308 infer mport T_1309 = ram[UInt<1>("h00")], clk wire T_1561 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} T_1561 <- T_1309 when maybe_flow : T_1561 <- io.enq.bits skip io.deq.bits <- T_1561 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_1688 = and(maybe_full, ptr_match) node T_1689 = cat(T_1688, ptr_diff) io.count <= T_1689 module TileLinkEnqueuer_24 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} io.manager.release.bits.payload.data <= UInt<1>("h00") io.manager.release.bits.payload.r_type <= UInt<1>("h00") io.manager.release.bits.payload.voluntary <= UInt<1>("h00") io.manager.release.bits.payload.client_xact_id <= UInt<1>("h00") io.manager.release.bits.payload.addr_block <= UInt<1>("h00") io.manager.release.bits.payload.addr_beat <= UInt<1>("h00") io.manager.release.bits.header.dst <= UInt<1>("h00") io.manager.release.bits.header.src <= UInt<1>("h00") io.manager.release.valid <= UInt<1>("h00") io.manager.probe.ready <= UInt<1>("h00") io.manager.finish.bits.payload.manager_xact_id <= UInt<1>("h00") io.manager.finish.bits.header.dst <= UInt<1>("h00") io.manager.finish.bits.header.src <= UInt<1>("h00") io.manager.finish.valid <= UInt<1>("h00") io.manager.grant.ready <= UInt<1>("h00") io.manager.acquire.bits.payload.data <= UInt<1>("h00") io.manager.acquire.bits.payload.union <= UInt<1>("h00") io.manager.acquire.bits.payload.a_type <= UInt<1>("h00") io.manager.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") io.manager.acquire.bits.payload.addr_beat <= UInt<1>("h00") io.manager.acquire.bits.payload.client_xact_id <= UInt<1>("h00") io.manager.acquire.bits.payload.addr_block <= UInt<1>("h00") io.manager.acquire.bits.header.dst <= UInt<1>("h00") io.manager.acquire.bits.header.src <= UInt<1>("h00") io.manager.acquire.valid <= UInt<1>("h00") io.client.release.ready <= UInt<1>("h00") io.client.probe.bits.payload.p_type <= UInt<1>("h00") io.client.probe.bits.payload.addr_block <= UInt<1>("h00") io.client.probe.bits.header.dst <= UInt<1>("h00") io.client.probe.bits.header.src <= UInt<1>("h00") io.client.probe.valid <= UInt<1>("h00") io.client.finish.ready <= UInt<1>("h00") io.client.grant.bits.payload.data <= UInt<1>("h00") io.client.grant.bits.payload.g_type <= UInt<1>("h00") io.client.grant.bits.payload.is_builtin_type <= UInt<1>("h00") io.client.grant.bits.payload.manager_xact_id <= UInt<1>("h00") io.client.grant.bits.payload.client_xact_id <= UInt<1>("h00") io.client.grant.bits.payload.addr_beat <= UInt<1>("h00") io.client.grant.bits.header.dst <= UInt<1>("h00") io.client.grant.bits.header.src <= UInt<1>("h00") io.client.grant.valid <= UInt<1>("h00") io.client.acquire.ready <= UInt<1>("h00") io.manager.acquire <- io.client.acquire io.client.probe <- io.manager.probe inst T_7777 of Queue_25 T_7777.io.deq.ready <= UInt<1>("h00") T_7777.io.enq.bits.payload.data <= UInt<1>("h00") T_7777.io.enq.bits.payload.r_type <= UInt<1>("h00") T_7777.io.enq.bits.payload.voluntary <= UInt<1>("h00") T_7777.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") T_7777.io.enq.bits.payload.addr_block <= UInt<1>("h00") T_7777.io.enq.bits.payload.addr_beat <= UInt<1>("h00") T_7777.io.enq.bits.header.dst <= UInt<1>("h00") T_7777.io.enq.bits.header.src <= UInt<1>("h00") T_7777.io.enq.valid <= UInt<1>("h00") T_7777.clk <= clk T_7777.reset <= reset T_7777.io.enq.valid <= io.client.release.valid T_7777.io.enq.bits <- io.client.release.bits io.client.release.ready <= T_7777.io.enq.ready io.manager.release <- T_7777.io.deq io.client.grant <- io.manager.grant io.manager.finish <- io.client.finish module LockingRRArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.payload.data <= UInt<1>("h00") io.out.bits.payload.union <= UInt<1>("h00") io.out.bits.payload.a_type <= UInt<1>("h00") io.out.bits.payload.is_builtin_type <= UInt<1>("h00") io.out.bits.payload.addr_beat <= UInt<1>("h00") io.out.bits.payload.client_xact_id <= UInt<1>("h00") io.out.bits.payload.addr_block <= UInt<1>("h00") io.out.bits.header.dst <= UInt<1>("h00") io.out.bits.header.src <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") reg T_3348 : UInt<1>, clk, reset, UInt<1>("h00") reg T_3350 : UInt, clk, reset, UInt<2>("h02") wire T_3352 : UInt<2> T_3352 <= UInt<1>("h00") io.out.valid <= io.in[T_3352].valid io.out.bits <- io.in[T_3352].bits io.chosen <= T_3352 io.in[T_3352].ready <= UInt<1>("h00") reg last_grant : UInt<2>, clk, reset, UInt<2>("h00") node T_4129 = gt(UInt<1>("h00"), last_grant) node T_4130 = and(io.in[0].valid, T_4129) node T_4132 = gt(UInt<1>("h01"), last_grant) node T_4133 = and(io.in[1].valid, T_4132) node T_4135 = gt(UInt<2>("h02"), last_grant) node T_4136 = and(io.in[2].valid, T_4135) node T_4139 = or(UInt<1>("h00"), T_4130) node T_4141 = eq(T_4139, UInt<1>("h00")) node T_4143 = or(UInt<1>("h00"), T_4130) node T_4144 = or(T_4143, T_4133) node T_4146 = eq(T_4144, UInt<1>("h00")) node T_4148 = or(UInt<1>("h00"), T_4130) node T_4149 = or(T_4148, T_4133) node T_4150 = or(T_4149, T_4136) node T_4152 = eq(T_4150, UInt<1>("h00")) node T_4154 = or(UInt<1>("h00"), T_4130) node T_4155 = or(T_4154, T_4133) node T_4156 = or(T_4155, T_4136) node T_4157 = or(T_4156, io.in[0].valid) node T_4159 = eq(T_4157, UInt<1>("h00")) node T_4161 = or(UInt<1>("h00"), T_4130) node T_4162 = or(T_4161, T_4133) node T_4163 = or(T_4162, T_4136) node T_4164 = or(T_4163, io.in[0].valid) node T_4165 = or(T_4164, io.in[1].valid) node T_4167 = eq(T_4165, UInt<1>("h00")) node T_4169 = gt(UInt<1>("h00"), last_grant) node T_4170 = and(UInt<1>("h01"), T_4169) node T_4171 = or(T_4170, T_4152) node T_4173 = gt(UInt<1>("h01"), last_grant) node T_4174 = and(T_4141, T_4173) node T_4175 = or(T_4174, T_4159) node T_4177 = gt(UInt<2>("h02"), last_grant) node T_4178 = and(T_4146, T_4177) node T_4179 = or(T_4178, T_4167) node T_4181 = eq(T_3350, UInt<1>("h00")) node T_4182 = mux(T_3348, T_4181, T_4171) node T_4183 = and(T_4182, io.out.ready) io.in[0].ready <= T_4183 node T_4185 = eq(T_3350, UInt<1>("h01")) node T_4186 = mux(T_3348, T_4185, T_4175) node T_4187 = and(T_4186, io.out.ready) io.in[1].ready <= T_4187 node T_4189 = eq(T_3350, UInt<2>("h02")) node T_4190 = mux(T_3348, T_4189, T_4179) node T_4191 = and(T_4190, io.out.ready) io.in[2].ready <= T_4191 reg T_4193 : UInt<2>, clk, reset, UInt<2>("h00") node T_4195 = addw(T_4193, UInt<1>("h01")) node T_4196 = and(io.out.ready, io.out.valid) when T_4196 : node T_4198 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type) wire T_4201 : UInt<3>[1] T_4201[0] <= UInt<3>("h03") node T_4204 = eq(T_4201[0], io.out.bits.payload.a_type) node T_4206 = or(UInt<1>("h00"), T_4204) node T_4207 = and(T_4198, T_4206) when T_4207 : T_4193 <= T_4195 node T_4209 = eq(T_3348, UInt<1>("h00")) when T_4209 : T_3348 <= UInt<1>("h01") node T_4211 = and(io.in[0].ready, io.in[0].valid) node T_4212 = and(io.in[1].ready, io.in[1].valid) node T_4213 = and(io.in[2].ready, io.in[2].valid) wire T_4215 : UInt<1>[3] T_4215[0] <= T_4211 T_4215[1] <= T_4212 T_4215[2] <= T_4213 node T_4223 = mux(T_4215[1], UInt<1>("h01"), UInt<2>("h02")) node T_4224 = mux(T_4215[0], UInt<1>("h00"), T_4223) T_3350 <= T_4224 skip skip node T_4226 = eq(T_4195, UInt<1>("h00")) when T_4226 : T_3348 <= UInt<1>("h00") skip skip node T_4230 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_4232 = mux(io.in[0].valid, UInt<1>("h00"), T_4230) node T_4234 = gt(UInt<2>("h02"), last_grant) node T_4235 = and(io.in[2].valid, T_4234) node T_4237 = mux(T_4235, UInt<2>("h02"), T_4232) node T_4239 = gt(UInt<1>("h01"), last_grant) node T_4240 = and(io.in[1].valid, T_4239) node choose = mux(T_4240, UInt<1>("h01"), T_4237) node T_4243 = mux(T_3348, T_3350, choose) T_3352 <= T_4243 node T_4244 = and(io.out.ready, io.out.valid) when T_4244 : last_grant <= T_3352 skip module LockingRRArbiter_26 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.payload.data <= UInt<1>("h00") io.out.bits.payload.r_type <= UInt<1>("h00") io.out.bits.payload.voluntary <= UInt<1>("h00") io.out.bits.payload.client_xact_id <= UInt<1>("h00") io.out.bits.payload.addr_block <= UInt<1>("h00") io.out.bits.payload.addr_beat <= UInt<1>("h00") io.out.bits.header.dst <= UInt<1>("h00") io.out.bits.header.src <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") reg T_3322 : UInt<1>, clk, reset, UInt<1>("h00") reg T_3324 : UInt, clk, reset, UInt<2>("h02") wire T_3326 : UInt<2> T_3326 <= UInt<1>("h00") io.out.valid <= io.in[T_3326].valid io.out.bits <- io.in[T_3326].bits io.chosen <= T_3326 io.in[T_3326].ready <= UInt<1>("h00") reg last_grant : UInt<2>, clk, reset, UInt<2>("h00") node T_4097 = gt(UInt<1>("h00"), last_grant) node T_4098 = and(io.in[0].valid, T_4097) node T_4100 = gt(UInt<1>("h01"), last_grant) node T_4101 = and(io.in[1].valid, T_4100) node T_4103 = gt(UInt<2>("h02"), last_grant) node T_4104 = and(io.in[2].valid, T_4103) node T_4107 = or(UInt<1>("h00"), T_4098) node T_4109 = eq(T_4107, UInt<1>("h00")) node T_4111 = or(UInt<1>("h00"), T_4098) node T_4112 = or(T_4111, T_4101) node T_4114 = eq(T_4112, UInt<1>("h00")) node T_4116 = or(UInt<1>("h00"), T_4098) node T_4117 = or(T_4116, T_4101) node T_4118 = or(T_4117, T_4104) node T_4120 = eq(T_4118, UInt<1>("h00")) node T_4122 = or(UInt<1>("h00"), T_4098) node T_4123 = or(T_4122, T_4101) node T_4124 = or(T_4123, T_4104) node T_4125 = or(T_4124, io.in[0].valid) node T_4127 = eq(T_4125, UInt<1>("h00")) node T_4129 = or(UInt<1>("h00"), T_4098) node T_4130 = or(T_4129, T_4101) node T_4131 = or(T_4130, T_4104) node T_4132 = or(T_4131, io.in[0].valid) node T_4133 = or(T_4132, io.in[1].valid) node T_4135 = eq(T_4133, UInt<1>("h00")) node T_4137 = gt(UInt<1>("h00"), last_grant) node T_4138 = and(UInt<1>("h01"), T_4137) node T_4139 = or(T_4138, T_4120) node T_4141 = gt(UInt<1>("h01"), last_grant) node T_4142 = and(T_4109, T_4141) node T_4143 = or(T_4142, T_4127) node T_4145 = gt(UInt<2>("h02"), last_grant) node T_4146 = and(T_4114, T_4145) node T_4147 = or(T_4146, T_4135) node T_4149 = eq(T_3324, UInt<1>("h00")) node T_4150 = mux(T_3322, T_4149, T_4139) node T_4151 = and(T_4150, io.out.ready) io.in[0].ready <= T_4151 node T_4153 = eq(T_3324, UInt<1>("h01")) node T_4154 = mux(T_3322, T_4153, T_4143) node T_4155 = and(T_4154, io.out.ready) io.in[1].ready <= T_4155 node T_4157 = eq(T_3324, UInt<2>("h02")) node T_4158 = mux(T_3322, T_4157, T_4147) node T_4159 = and(T_4158, io.out.ready) io.in[2].ready <= T_4159 reg T_4161 : UInt<2>, clk, reset, UInt<2>("h00") node T_4163 = addw(T_4161, UInt<1>("h01")) node T_4164 = and(io.out.ready, io.out.valid) when T_4164 : wire T_4167 : UInt<2>[3] T_4167[0] <= UInt<1>("h00") T_4167[1] <= UInt<1>("h01") T_4167[2] <= UInt<2>("h02") node T_4172 = eq(T_4167[0], io.out.bits.payload.r_type) node T_4173 = eq(T_4167[1], io.out.bits.payload.r_type) node T_4174 = eq(T_4167[2], io.out.bits.payload.r_type) node T_4176 = or(UInt<1>("h00"), T_4172) node T_4177 = or(T_4176, T_4173) node T_4178 = or(T_4177, T_4174) node T_4179 = and(UInt<1>("h01"), T_4178) when T_4179 : T_4161 <= T_4163 node T_4181 = eq(T_3322, UInt<1>("h00")) when T_4181 : T_3322 <= UInt<1>("h01") node T_4183 = and(io.in[0].ready, io.in[0].valid) node T_4184 = and(io.in[1].ready, io.in[1].valid) node T_4185 = and(io.in[2].ready, io.in[2].valid) wire T_4187 : UInt<1>[3] T_4187[0] <= T_4183 T_4187[1] <= T_4184 T_4187[2] <= T_4185 node T_4195 = mux(T_4187[1], UInt<1>("h01"), UInt<2>("h02")) node T_4196 = mux(T_4187[0], UInt<1>("h00"), T_4195) T_3324 <= T_4196 skip skip node T_4198 = eq(T_4163, UInt<1>("h00")) when T_4198 : T_3322 <= UInt<1>("h00") skip skip node T_4202 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_4204 = mux(io.in[0].valid, UInt<1>("h00"), T_4202) node T_4206 = gt(UInt<2>("h02"), last_grant) node T_4207 = and(io.in[2].valid, T_4206) node T_4209 = mux(T_4207, UInt<2>("h02"), T_4204) node T_4211 = gt(UInt<1>("h01"), last_grant) node T_4212 = and(io.in[1].valid, T_4211) node choose = mux(T_4212, UInt<1>("h01"), T_4209) node T_4215 = mux(T_3322, T_3324, choose) T_3326 <= T_4215 node T_4216 = and(io.out.ready, io.out.valid) when T_4216 : last_grant <= T_3326 skip module RRArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.payload.manager_xact_id <= UInt<1>("h00") io.out.bits.header.dst <= UInt<1>("h00") io.out.bits.header.src <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") wire T_3194 : UInt<2> T_3194 <= UInt<1>("h00") io.out.valid <= io.in[T_3194].valid io.out.bits <- io.in[T_3194].bits io.chosen <= T_3194 io.in[T_3194].ready <= UInt<1>("h00") reg T_3934 : UInt<2>, clk, reset, UInt<2>("h00") node T_3935 = gt(UInt<1>("h00"), T_3934) node T_3936 = and(io.in[0].valid, T_3935) node T_3938 = gt(UInt<1>("h01"), T_3934) node T_3939 = and(io.in[1].valid, T_3938) node T_3941 = gt(UInt<2>("h02"), T_3934) node T_3942 = and(io.in[2].valid, T_3941) node T_3945 = or(UInt<1>("h00"), T_3936) node T_3947 = eq(T_3945, UInt<1>("h00")) node T_3949 = or(UInt<1>("h00"), T_3936) node T_3950 = or(T_3949, T_3939) node T_3952 = eq(T_3950, UInt<1>("h00")) node T_3954 = or(UInt<1>("h00"), T_3936) node T_3955 = or(T_3954, T_3939) node T_3956 = or(T_3955, T_3942) node T_3958 = eq(T_3956, UInt<1>("h00")) node T_3960 = or(UInt<1>("h00"), T_3936) node T_3961 = or(T_3960, T_3939) node T_3962 = or(T_3961, T_3942) node T_3963 = or(T_3962, io.in[0].valid) node T_3965 = eq(T_3963, UInt<1>("h00")) node T_3967 = or(UInt<1>("h00"), T_3936) node T_3968 = or(T_3967, T_3939) node T_3969 = or(T_3968, T_3942) node T_3970 = or(T_3969, io.in[0].valid) node T_3971 = or(T_3970, io.in[1].valid) node T_3973 = eq(T_3971, UInt<1>("h00")) node T_3975 = gt(UInt<1>("h00"), T_3934) node T_3976 = and(UInt<1>("h01"), T_3975) node T_3977 = or(T_3976, T_3958) node T_3979 = gt(UInt<1>("h01"), T_3934) node T_3980 = and(T_3947, T_3979) node T_3981 = or(T_3980, T_3965) node T_3983 = gt(UInt<2>("h02"), T_3934) node T_3984 = and(T_3952, T_3983) node T_3985 = or(T_3984, T_3973) node T_3987 = eq(UInt<2>("h02"), UInt<1>("h00")) node T_3988 = mux(UInt<1>("h00"), T_3987, T_3977) node T_3989 = and(T_3988, io.out.ready) io.in[0].ready <= T_3989 node T_3991 = eq(UInt<2>("h02"), UInt<1>("h01")) node T_3992 = mux(UInt<1>("h00"), T_3991, T_3981) node T_3993 = and(T_3992, io.out.ready) io.in[1].ready <= T_3993 node T_3995 = eq(UInt<2>("h02"), UInt<2>("h02")) node T_3996 = mux(UInt<1>("h00"), T_3995, T_3985) node T_3997 = and(T_3996, io.out.ready) io.in[2].ready <= T_3997 node T_4000 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node T_4002 = mux(io.in[0].valid, UInt<1>("h00"), T_4000) node T_4004 = gt(UInt<2>("h02"), T_3934) node T_4005 = and(io.in[2].valid, T_4004) node T_4007 = mux(T_4005, UInt<2>("h02"), T_4002) node T_4009 = gt(UInt<1>("h01"), T_3934) node T_4010 = and(io.in[1].valid, T_4009) node T_4012 = mux(T_4010, UInt<1>("h01"), T_4007) node T_4013 = mux(UInt<1>("h00"), UInt<2>("h02"), T_4012) T_3194 <= T_4013 node T_4014 = and(io.out.ready, io.out.valid) when T_4014 : T_3934 <= T_3194 skip module RocketChipTileLinkArbiter : input clk : Clock input reset : UInt<1> output io : {flip clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}[1]} io.managers[0].release.bits.client_id <= UInt<1>("h00") io.managers[0].release.bits.data <= UInt<1>("h00") io.managers[0].release.bits.r_type <= UInt<1>("h00") io.managers[0].release.bits.voluntary <= UInt<1>("h00") io.managers[0].release.bits.client_xact_id <= UInt<1>("h00") io.managers[0].release.bits.addr_block <= UInt<1>("h00") io.managers[0].release.bits.addr_beat <= UInt<1>("h00") io.managers[0].release.valid <= UInt<1>("h00") io.managers[0].probe.ready <= UInt<1>("h00") io.managers[0].finish.bits.manager_xact_id <= UInt<1>("h00") io.managers[0].finish.valid <= UInt<1>("h00") io.managers[0].grant.ready <= UInt<1>("h00") io.managers[0].acquire.bits.client_id <= UInt<1>("h00") io.managers[0].acquire.bits.data <= UInt<1>("h00") io.managers[0].acquire.bits.union <= UInt<1>("h00") io.managers[0].acquire.bits.a_type <= UInt<1>("h00") io.managers[0].acquire.bits.is_builtin_type <= UInt<1>("h00") io.managers[0].acquire.bits.addr_beat <= UInt<1>("h00") io.managers[0].acquire.bits.client_xact_id <= UInt<1>("h00") io.managers[0].acquire.bits.addr_block <= UInt<1>("h00") io.managers[0].acquire.valid <= UInt<1>("h00") io.clients[0].release.ready <= UInt<1>("h00") io.clients[0].probe.bits.p_type <= UInt<1>("h00") io.clients[0].probe.bits.addr_block <= UInt<1>("h00") io.clients[0].probe.valid <= UInt<1>("h00") io.clients[0].grant.bits.data <= UInt<1>("h00") io.clients[0].grant.bits.g_type <= UInt<1>("h00") io.clients[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.clients[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.clients[0].grant.bits.client_xact_id <= UInt<1>("h00") io.clients[0].grant.bits.addr_beat <= UInt<1>("h00") io.clients[0].grant.valid <= UInt<1>("h00") io.clients[0].acquire.ready <= UInt<1>("h00") io.clients[1].release.ready <= UInt<1>("h00") io.clients[1].probe.bits.p_type <= UInt<1>("h00") io.clients[1].probe.bits.addr_block <= UInt<1>("h00") io.clients[1].probe.valid <= UInt<1>("h00") io.clients[1].grant.bits.data <= UInt<1>("h00") io.clients[1].grant.bits.g_type <= UInt<1>("h00") io.clients[1].grant.bits.is_builtin_type <= UInt<1>("h00") io.clients[1].grant.bits.manager_xact_id <= UInt<1>("h00") io.clients[1].grant.bits.client_xact_id <= UInt<1>("h00") io.clients[1].grant.bits.addr_beat <= UInt<1>("h00") io.clients[1].grant.valid <= UInt<1>("h00") io.clients[1].acquire.ready <= UInt<1>("h00") io.clients[2].release.ready <= UInt<1>("h00") io.clients[2].probe.bits.p_type <= UInt<1>("h00") io.clients[2].probe.bits.addr_block <= UInt<1>("h00") io.clients[2].probe.valid <= UInt<1>("h00") io.clients[2].grant.bits.data <= UInt<1>("h00") io.clients[2].grant.bits.g_type <= UInt<1>("h00") io.clients[2].grant.bits.is_builtin_type <= UInt<1>("h00") io.clients[2].grant.bits.manager_xact_id <= UInt<1>("h00") io.clients[2].grant.bits.client_xact_id <= UInt<1>("h00") io.clients[2].grant.bits.addr_beat <= UInt<1>("h00") io.clients[2].grant.valid <= UInt<1>("h00") io.clients[2].acquire.ready <= UInt<1>("h00") inst T_11386 of ClientTileLinkNetworkPort T_11386.io.network.release.ready <= UInt<1>("h00") T_11386.io.network.probe.bits.payload.p_type <= UInt<1>("h00") T_11386.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") T_11386.io.network.probe.bits.header.dst <= UInt<1>("h00") T_11386.io.network.probe.bits.header.src <= UInt<1>("h00") T_11386.io.network.probe.valid <= UInt<1>("h00") T_11386.io.network.finish.ready <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.data <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.g_type <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11386.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11386.io.network.grant.bits.header.dst <= UInt<1>("h00") T_11386.io.network.grant.bits.header.src <= UInt<1>("h00") T_11386.io.network.grant.valid <= UInt<1>("h00") T_11386.io.network.acquire.ready <= UInt<1>("h00") T_11386.io.client.release.bits.data <= UInt<1>("h00") T_11386.io.client.release.bits.r_type <= UInt<1>("h00") T_11386.io.client.release.bits.voluntary <= UInt<1>("h00") T_11386.io.client.release.bits.client_xact_id <= UInt<1>("h00") T_11386.io.client.release.bits.addr_block <= UInt<1>("h00") T_11386.io.client.release.bits.addr_beat <= UInt<1>("h00") T_11386.io.client.release.valid <= UInt<1>("h00") T_11386.io.client.probe.ready <= UInt<1>("h00") T_11386.io.client.grant.ready <= UInt<1>("h00") T_11386.io.client.acquire.bits.data <= UInt<1>("h00") T_11386.io.client.acquire.bits.union <= UInt<1>("h00") T_11386.io.client.acquire.bits.a_type <= UInt<1>("h00") T_11386.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") T_11386.io.client.acquire.bits.addr_beat <= UInt<1>("h00") T_11386.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") T_11386.io.client.acquire.bits.addr_block <= UInt<1>("h00") T_11386.io.client.acquire.valid <= UInt<1>("h00") T_11386.clk <= clk T_11386.reset <= reset inst T_11421 of TileLinkEnqueuer T_11421.io.manager.release.ready <= UInt<1>("h00") T_11421.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") T_11421.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") T_11421.io.manager.probe.bits.header.dst <= UInt<1>("h00") T_11421.io.manager.probe.bits.header.src <= UInt<1>("h00") T_11421.io.manager.probe.valid <= UInt<1>("h00") T_11421.io.manager.finish.ready <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.data <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11421.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11421.io.manager.grant.bits.header.dst <= UInt<1>("h00") T_11421.io.manager.grant.bits.header.src <= UInt<1>("h00") T_11421.io.manager.grant.valid <= UInt<1>("h00") T_11421.io.manager.acquire.ready <= UInt<1>("h00") T_11421.io.client.release.bits.payload.data <= UInt<1>("h00") T_11421.io.client.release.bits.payload.r_type <= UInt<1>("h00") T_11421.io.client.release.bits.payload.voluntary <= UInt<1>("h00") T_11421.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") T_11421.io.client.release.bits.payload.addr_block <= UInt<1>("h00") T_11421.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") T_11421.io.client.release.bits.header.dst <= UInt<1>("h00") T_11421.io.client.release.bits.header.src <= UInt<1>("h00") T_11421.io.client.release.valid <= UInt<1>("h00") T_11421.io.client.probe.ready <= UInt<1>("h00") T_11421.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") T_11421.io.client.finish.bits.header.dst <= UInt<1>("h00") T_11421.io.client.finish.bits.header.src <= UInt<1>("h00") T_11421.io.client.finish.valid <= UInt<1>("h00") T_11421.io.client.grant.ready <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.data <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.union <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") T_11421.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") T_11421.io.client.acquire.bits.header.dst <= UInt<1>("h00") T_11421.io.client.acquire.bits.header.src <= UInt<1>("h00") T_11421.io.client.acquire.valid <= UInt<1>("h00") T_11421.clk <= clk T_11421.reset <= reset T_11386.io.client <- io.clients[0] T_11421.io.client <- T_11386.io.network inst T_11464 of ClientTileLinkNetworkPort_6 T_11464.io.network.release.ready <= UInt<1>("h00") T_11464.io.network.probe.bits.payload.p_type <= UInt<1>("h00") T_11464.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") T_11464.io.network.probe.bits.header.dst <= UInt<1>("h00") T_11464.io.network.probe.bits.header.src <= UInt<1>("h00") T_11464.io.network.probe.valid <= UInt<1>("h00") T_11464.io.network.finish.ready <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.data <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.g_type <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11464.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11464.io.network.grant.bits.header.dst <= UInt<1>("h00") T_11464.io.network.grant.bits.header.src <= UInt<1>("h00") T_11464.io.network.grant.valid <= UInt<1>("h00") T_11464.io.network.acquire.ready <= UInt<1>("h00") T_11464.io.client.release.bits.data <= UInt<1>("h00") T_11464.io.client.release.bits.r_type <= UInt<1>("h00") T_11464.io.client.release.bits.voluntary <= UInt<1>("h00") T_11464.io.client.release.bits.client_xact_id <= UInt<1>("h00") T_11464.io.client.release.bits.addr_block <= UInt<1>("h00") T_11464.io.client.release.bits.addr_beat <= UInt<1>("h00") T_11464.io.client.release.valid <= UInt<1>("h00") T_11464.io.client.probe.ready <= UInt<1>("h00") T_11464.io.client.grant.ready <= UInt<1>("h00") T_11464.io.client.acquire.bits.data <= UInt<1>("h00") T_11464.io.client.acquire.bits.union <= UInt<1>("h00") T_11464.io.client.acquire.bits.a_type <= UInt<1>("h00") T_11464.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") T_11464.io.client.acquire.bits.addr_beat <= UInt<1>("h00") T_11464.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") T_11464.io.client.acquire.bits.addr_block <= UInt<1>("h00") T_11464.io.client.acquire.valid <= UInt<1>("h00") T_11464.clk <= clk T_11464.reset <= reset inst T_11499 of TileLinkEnqueuer T_11499.io.manager.release.ready <= UInt<1>("h00") T_11499.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") T_11499.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") T_11499.io.manager.probe.bits.header.dst <= UInt<1>("h00") T_11499.io.manager.probe.bits.header.src <= UInt<1>("h00") T_11499.io.manager.probe.valid <= UInt<1>("h00") T_11499.io.manager.finish.ready <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.data <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11499.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11499.io.manager.grant.bits.header.dst <= UInt<1>("h00") T_11499.io.manager.grant.bits.header.src <= UInt<1>("h00") T_11499.io.manager.grant.valid <= UInt<1>("h00") T_11499.io.manager.acquire.ready <= UInt<1>("h00") T_11499.io.client.release.bits.payload.data <= UInt<1>("h00") T_11499.io.client.release.bits.payload.r_type <= UInt<1>("h00") T_11499.io.client.release.bits.payload.voluntary <= UInt<1>("h00") T_11499.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") T_11499.io.client.release.bits.payload.addr_block <= UInt<1>("h00") T_11499.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") T_11499.io.client.release.bits.header.dst <= UInt<1>("h00") T_11499.io.client.release.bits.header.src <= UInt<1>("h00") T_11499.io.client.release.valid <= UInt<1>("h00") T_11499.io.client.probe.ready <= UInt<1>("h00") T_11499.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") T_11499.io.client.finish.bits.header.dst <= UInt<1>("h00") T_11499.io.client.finish.bits.header.src <= UInt<1>("h00") T_11499.io.client.finish.valid <= UInt<1>("h00") T_11499.io.client.grant.ready <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.data <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.union <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") T_11499.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") T_11499.io.client.acquire.bits.header.dst <= UInt<1>("h00") T_11499.io.client.acquire.bits.header.src <= UInt<1>("h00") T_11499.io.client.acquire.valid <= UInt<1>("h00") T_11499.clk <= clk T_11499.reset <= reset T_11464.io.client <- io.clients[1] T_11499.io.client <- T_11464.io.network inst T_11542 of ClientTileLinkNetworkPort_15 T_11542.io.network.release.ready <= UInt<1>("h00") T_11542.io.network.probe.bits.payload.p_type <= UInt<1>("h00") T_11542.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") T_11542.io.network.probe.bits.header.dst <= UInt<1>("h00") T_11542.io.network.probe.bits.header.src <= UInt<1>("h00") T_11542.io.network.probe.valid <= UInt<1>("h00") T_11542.io.network.finish.ready <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.data <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.g_type <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11542.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11542.io.network.grant.bits.header.dst <= UInt<1>("h00") T_11542.io.network.grant.bits.header.src <= UInt<1>("h00") T_11542.io.network.grant.valid <= UInt<1>("h00") T_11542.io.network.acquire.ready <= UInt<1>("h00") T_11542.io.client.release.bits.data <= UInt<1>("h00") T_11542.io.client.release.bits.r_type <= UInt<1>("h00") T_11542.io.client.release.bits.voluntary <= UInt<1>("h00") T_11542.io.client.release.bits.client_xact_id <= UInt<1>("h00") T_11542.io.client.release.bits.addr_block <= UInt<1>("h00") T_11542.io.client.release.bits.addr_beat <= UInt<1>("h00") T_11542.io.client.release.valid <= UInt<1>("h00") T_11542.io.client.probe.ready <= UInt<1>("h00") T_11542.io.client.grant.ready <= UInt<1>("h00") T_11542.io.client.acquire.bits.data <= UInt<1>("h00") T_11542.io.client.acquire.bits.union <= UInt<1>("h00") T_11542.io.client.acquire.bits.a_type <= UInt<1>("h00") T_11542.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") T_11542.io.client.acquire.bits.addr_beat <= UInt<1>("h00") T_11542.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") T_11542.io.client.acquire.bits.addr_block <= UInt<1>("h00") T_11542.io.client.acquire.valid <= UInt<1>("h00") T_11542.clk <= clk T_11542.reset <= reset inst T_11577 of TileLinkEnqueuer T_11577.io.manager.release.ready <= UInt<1>("h00") T_11577.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") T_11577.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") T_11577.io.manager.probe.bits.header.dst <= UInt<1>("h00") T_11577.io.manager.probe.bits.header.src <= UInt<1>("h00") T_11577.io.manager.probe.valid <= UInt<1>("h00") T_11577.io.manager.finish.ready <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.data <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11577.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11577.io.manager.grant.bits.header.dst <= UInt<1>("h00") T_11577.io.manager.grant.bits.header.src <= UInt<1>("h00") T_11577.io.manager.grant.valid <= UInt<1>("h00") T_11577.io.manager.acquire.ready <= UInt<1>("h00") T_11577.io.client.release.bits.payload.data <= UInt<1>("h00") T_11577.io.client.release.bits.payload.r_type <= UInt<1>("h00") T_11577.io.client.release.bits.payload.voluntary <= UInt<1>("h00") T_11577.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") T_11577.io.client.release.bits.payload.addr_block <= UInt<1>("h00") T_11577.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") T_11577.io.client.release.bits.header.dst <= UInt<1>("h00") T_11577.io.client.release.bits.header.src <= UInt<1>("h00") T_11577.io.client.release.valid <= UInt<1>("h00") T_11577.io.client.probe.ready <= UInt<1>("h00") T_11577.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") T_11577.io.client.finish.bits.header.dst <= UInt<1>("h00") T_11577.io.client.finish.bits.header.src <= UInt<1>("h00") T_11577.io.client.finish.valid <= UInt<1>("h00") T_11577.io.client.grant.ready <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.data <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.union <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") T_11577.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") T_11577.io.client.acquire.bits.header.dst <= UInt<1>("h00") T_11577.io.client.acquire.bits.header.src <= UInt<1>("h00") T_11577.io.client.acquire.valid <= UInt<1>("h00") T_11577.clk <= clk T_11577.reset <= reset T_11542.io.client <- io.clients[2] T_11577.io.client <- T_11542.io.network inst T_11620 of ManagerTileLinkNetworkPort T_11620.io.network.release.bits.payload.data <= UInt<1>("h00") T_11620.io.network.release.bits.payload.r_type <= UInt<1>("h00") T_11620.io.network.release.bits.payload.voluntary <= UInt<1>("h00") T_11620.io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") T_11620.io.network.release.bits.payload.addr_block <= UInt<1>("h00") T_11620.io.network.release.bits.payload.addr_beat <= UInt<1>("h00") T_11620.io.network.release.bits.header.dst <= UInt<1>("h00") T_11620.io.network.release.bits.header.src <= UInt<1>("h00") T_11620.io.network.release.valid <= UInt<1>("h00") T_11620.io.network.probe.ready <= UInt<1>("h00") T_11620.io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") T_11620.io.network.finish.bits.header.dst <= UInt<1>("h00") T_11620.io.network.finish.bits.header.src <= UInt<1>("h00") T_11620.io.network.finish.valid <= UInt<1>("h00") T_11620.io.network.grant.ready <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.data <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.union <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.a_type <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") T_11620.io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") T_11620.io.network.acquire.bits.header.dst <= UInt<1>("h00") T_11620.io.network.acquire.bits.header.src <= UInt<1>("h00") T_11620.io.network.acquire.valid <= UInt<1>("h00") T_11620.io.manager.release.ready <= UInt<1>("h00") T_11620.io.manager.probe.bits.client_id <= UInt<1>("h00") T_11620.io.manager.probe.bits.p_type <= UInt<1>("h00") T_11620.io.manager.probe.bits.addr_block <= UInt<1>("h00") T_11620.io.manager.probe.valid <= UInt<1>("h00") T_11620.io.manager.finish.ready <= UInt<1>("h00") T_11620.io.manager.grant.bits.client_id <= UInt<1>("h00") T_11620.io.manager.grant.bits.data <= UInt<1>("h00") T_11620.io.manager.grant.bits.g_type <= UInt<1>("h00") T_11620.io.manager.grant.bits.is_builtin_type <= UInt<1>("h00") T_11620.io.manager.grant.bits.manager_xact_id <= UInt<1>("h00") T_11620.io.manager.grant.bits.client_xact_id <= UInt<1>("h00") T_11620.io.manager.grant.bits.addr_beat <= UInt<1>("h00") T_11620.io.manager.grant.valid <= UInt<1>("h00") T_11620.io.manager.acquire.ready <= UInt<1>("h00") T_11620.clk <= clk T_11620.reset <= reset inst T_11661 of TileLinkEnqueuer_24 T_11661.io.manager.release.ready <= UInt<1>("h00") T_11661.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") T_11661.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") T_11661.io.manager.probe.bits.header.dst <= UInt<1>("h00") T_11661.io.manager.probe.bits.header.src <= UInt<1>("h00") T_11661.io.manager.probe.valid <= UInt<1>("h00") T_11661.io.manager.finish.ready <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.data <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") T_11661.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") T_11661.io.manager.grant.bits.header.dst <= UInt<1>("h00") T_11661.io.manager.grant.bits.header.src <= UInt<1>("h00") T_11661.io.manager.grant.valid <= UInt<1>("h00") T_11661.io.manager.acquire.ready <= UInt<1>("h00") T_11661.io.client.release.bits.payload.data <= UInt<1>("h00") T_11661.io.client.release.bits.payload.r_type <= UInt<1>("h00") T_11661.io.client.release.bits.payload.voluntary <= UInt<1>("h00") T_11661.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") T_11661.io.client.release.bits.payload.addr_block <= UInt<1>("h00") T_11661.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") T_11661.io.client.release.bits.header.dst <= UInt<1>("h00") T_11661.io.client.release.bits.header.src <= UInt<1>("h00") T_11661.io.client.release.valid <= UInt<1>("h00") T_11661.io.client.probe.ready <= UInt<1>("h00") T_11661.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") T_11661.io.client.finish.bits.header.dst <= UInt<1>("h00") T_11661.io.client.finish.bits.header.src <= UInt<1>("h00") T_11661.io.client.finish.valid <= UInt<1>("h00") T_11661.io.client.grant.ready <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.data <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.union <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") T_11661.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") T_11661.io.client.acquire.bits.header.dst <= UInt<1>("h00") T_11661.io.client.acquire.bits.header.src <= UInt<1>("h00") T_11661.io.client.acquire.valid <= UInt<1>("h00") T_11661.clk <= clk T_11661.reset <= reset T_11620.io.manager <- io.managers[0] T_11620.io.network <- T_11661.io.manager inst T_11704 of LockingRRArbiter T_11704.io.out.ready <= UInt<1>("h00") T_11704.io.in[0].bits.payload.data <= UInt<1>("h00") T_11704.io.in[0].bits.payload.union <= UInt<1>("h00") T_11704.io.in[0].bits.payload.a_type <= UInt<1>("h00") T_11704.io.in[0].bits.payload.is_builtin_type <= UInt<1>("h00") T_11704.io.in[0].bits.payload.addr_beat <= UInt<1>("h00") T_11704.io.in[0].bits.payload.client_xact_id <= UInt<1>("h00") T_11704.io.in[0].bits.payload.addr_block <= UInt<1>("h00") T_11704.io.in[0].bits.header.dst <= UInt<1>("h00") T_11704.io.in[0].bits.header.src <= UInt<1>("h00") T_11704.io.in[0].valid <= UInt<1>("h00") T_11704.io.in[1].bits.payload.data <= UInt<1>("h00") T_11704.io.in[1].bits.payload.union <= UInt<1>("h00") T_11704.io.in[1].bits.payload.a_type <= UInt<1>("h00") T_11704.io.in[1].bits.payload.is_builtin_type <= UInt<1>("h00") T_11704.io.in[1].bits.payload.addr_beat <= UInt<1>("h00") T_11704.io.in[1].bits.payload.client_xact_id <= UInt<1>("h00") T_11704.io.in[1].bits.payload.addr_block <= UInt<1>("h00") T_11704.io.in[1].bits.header.dst <= UInt<1>("h00") T_11704.io.in[1].bits.header.src <= UInt<1>("h00") T_11704.io.in[1].valid <= UInt<1>("h00") T_11704.io.in[2].bits.payload.data <= UInt<1>("h00") T_11704.io.in[2].bits.payload.union <= UInt<1>("h00") T_11704.io.in[2].bits.payload.a_type <= UInt<1>("h00") T_11704.io.in[2].bits.payload.is_builtin_type <= UInt<1>("h00") T_11704.io.in[2].bits.payload.addr_beat <= UInt<1>("h00") T_11704.io.in[2].bits.payload.client_xact_id <= UInt<1>("h00") T_11704.io.in[2].bits.payload.addr_block <= UInt<1>("h00") T_11704.io.in[2].bits.header.dst <= UInt<1>("h00") T_11704.io.in[2].bits.header.src <= UInt<1>("h00") T_11704.io.in[2].valid <= UInt<1>("h00") T_11704.clk <= clk T_11704.reset <= reset T_11704.io.in[0].valid <= T_11421.io.manager.acquire.valid T_11704.io.in[0].bits <- T_11421.io.manager.acquire.bits T_11704.io.in[0].bits.payload.client_xact_id <= T_11421.io.manager.acquire.bits.payload.client_xact_id T_11421.io.manager.acquire.ready <= T_11704.io.in[0].ready T_11704.io.in[1].valid <= T_11499.io.manager.acquire.valid T_11704.io.in[1].bits <- T_11499.io.manager.acquire.bits T_11704.io.in[1].bits.payload.client_xact_id <= T_11499.io.manager.acquire.bits.payload.client_xact_id T_11499.io.manager.acquire.ready <= T_11704.io.in[1].ready T_11704.io.in[2].valid <= T_11577.io.manager.acquire.valid T_11704.io.in[2].bits <- T_11577.io.manager.acquire.bits T_11704.io.in[2].bits.payload.client_xact_id <= T_11577.io.manager.acquire.bits.payload.client_xact_id T_11577.io.manager.acquire.ready <= T_11704.io.in[2].ready T_11661.io.client.acquire <- T_11704.io.out inst T_11736 of LockingRRArbiter_26 T_11736.io.out.ready <= UInt<1>("h00") T_11736.io.in[0].bits.payload.data <= UInt<1>("h00") T_11736.io.in[0].bits.payload.r_type <= UInt<1>("h00") T_11736.io.in[0].bits.payload.voluntary <= UInt<1>("h00") T_11736.io.in[0].bits.payload.client_xact_id <= UInt<1>("h00") T_11736.io.in[0].bits.payload.addr_block <= UInt<1>("h00") T_11736.io.in[0].bits.payload.addr_beat <= UInt<1>("h00") T_11736.io.in[0].bits.header.dst <= UInt<1>("h00") T_11736.io.in[0].bits.header.src <= UInt<1>("h00") T_11736.io.in[0].valid <= UInt<1>("h00") T_11736.io.in[1].bits.payload.data <= UInt<1>("h00") T_11736.io.in[1].bits.payload.r_type <= UInt<1>("h00") T_11736.io.in[1].bits.payload.voluntary <= UInt<1>("h00") T_11736.io.in[1].bits.payload.client_xact_id <= UInt<1>("h00") T_11736.io.in[1].bits.payload.addr_block <= UInt<1>("h00") T_11736.io.in[1].bits.payload.addr_beat <= UInt<1>("h00") T_11736.io.in[1].bits.header.dst <= UInt<1>("h00") T_11736.io.in[1].bits.header.src <= UInt<1>("h00") T_11736.io.in[1].valid <= UInt<1>("h00") T_11736.io.in[2].bits.payload.data <= UInt<1>("h00") T_11736.io.in[2].bits.payload.r_type <= UInt<1>("h00") T_11736.io.in[2].bits.payload.voluntary <= UInt<1>("h00") T_11736.io.in[2].bits.payload.client_xact_id <= UInt<1>("h00") T_11736.io.in[2].bits.payload.addr_block <= UInt<1>("h00") T_11736.io.in[2].bits.payload.addr_beat <= UInt<1>("h00") T_11736.io.in[2].bits.header.dst <= UInt<1>("h00") T_11736.io.in[2].bits.header.src <= UInt<1>("h00") T_11736.io.in[2].valid <= UInt<1>("h00") T_11736.clk <= clk T_11736.reset <= reset T_11736.io.in[0].valid <= T_11421.io.manager.release.valid T_11736.io.in[0].bits <- T_11421.io.manager.release.bits T_11736.io.in[0].bits.payload.client_xact_id <= T_11421.io.manager.release.bits.payload.client_xact_id T_11421.io.manager.release.ready <= T_11736.io.in[0].ready T_11736.io.in[1].valid <= T_11499.io.manager.release.valid T_11736.io.in[1].bits <- T_11499.io.manager.release.bits T_11736.io.in[1].bits.payload.client_xact_id <= T_11499.io.manager.release.bits.payload.client_xact_id T_11499.io.manager.release.ready <= T_11736.io.in[1].ready T_11736.io.in[2].valid <= T_11577.io.manager.release.valid T_11736.io.in[2].bits <- T_11577.io.manager.release.bits T_11736.io.in[2].bits.payload.client_xact_id <= T_11577.io.manager.release.bits.payload.client_xact_id T_11577.io.manager.release.ready <= T_11736.io.in[2].ready T_11661.io.client.release <- T_11736.io.out inst T_11765 of RRArbiter T_11765.io.out.ready <= UInt<1>("h00") T_11765.io.in[0].bits.payload.manager_xact_id <= UInt<1>("h00") T_11765.io.in[0].bits.header.dst <= UInt<1>("h00") T_11765.io.in[0].bits.header.src <= UInt<1>("h00") T_11765.io.in[0].valid <= UInt<1>("h00") T_11765.io.in[1].bits.payload.manager_xact_id <= UInt<1>("h00") T_11765.io.in[1].bits.header.dst <= UInt<1>("h00") T_11765.io.in[1].bits.header.src <= UInt<1>("h00") T_11765.io.in[1].valid <= UInt<1>("h00") T_11765.io.in[2].bits.payload.manager_xact_id <= UInt<1>("h00") T_11765.io.in[2].bits.header.dst <= UInt<1>("h00") T_11765.io.in[2].bits.header.src <= UInt<1>("h00") T_11765.io.in[2].valid <= UInt<1>("h00") T_11765.clk <= clk T_11765.reset <= reset T_11765.io.in[0] <- T_11421.io.manager.finish T_11765.io.in[1] <- T_11499.io.manager.finish T_11765.io.in[2] <- T_11577.io.manager.finish T_11661.io.client.finish <- T_11765.io.out T_11661.io.client.probe.ready <= UInt<1>("h00") T_11421.io.manager.probe.valid <= UInt<1>("h00") node T_11782 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h00")) when T_11782 : T_11421.io.manager.probe.valid <= T_11661.io.client.probe.valid T_11661.io.client.probe.ready <= T_11421.io.manager.probe.ready skip T_11421.io.manager.probe.bits <- T_11661.io.client.probe.bits T_11499.io.manager.probe.valid <= UInt<1>("h00") node T_11785 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h01")) when T_11785 : T_11499.io.manager.probe.valid <= T_11661.io.client.probe.valid T_11661.io.client.probe.ready <= T_11499.io.manager.probe.ready skip T_11499.io.manager.probe.bits <- T_11661.io.client.probe.bits T_11577.io.manager.probe.valid <= UInt<1>("h00") node T_11788 = eq(T_11661.io.client.probe.bits.header.dst, UInt<2>("h02")) when T_11788 : T_11577.io.manager.probe.valid <= T_11661.io.client.probe.valid T_11661.io.client.probe.ready <= T_11577.io.manager.probe.ready skip T_11577.io.manager.probe.bits <- T_11661.io.client.probe.bits T_11661.io.client.grant.ready <= UInt<1>("h00") T_11421.io.manager.grant.valid <= UInt<1>("h00") node T_11792 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h00")) when T_11792 : T_11421.io.manager.grant.valid <= T_11661.io.client.grant.valid T_11661.io.client.grant.ready <= T_11421.io.manager.grant.ready skip T_11421.io.manager.grant.bits <- T_11661.io.client.grant.bits T_11499.io.manager.grant.valid <= UInt<1>("h00") node T_11795 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h01")) when T_11795 : T_11499.io.manager.grant.valid <= T_11661.io.client.grant.valid T_11661.io.client.grant.ready <= T_11499.io.manager.grant.ready skip T_11499.io.manager.grant.bits <- T_11661.io.client.grant.bits T_11577.io.manager.grant.valid <= UInt<1>("h00") node T_11798 = eq(T_11661.io.client.grant.bits.header.dst, UInt<2>("h02")) when T_11798 : T_11577.io.manager.grant.valid <= T_11661.io.client.grant.valid T_11661.io.client.grant.ready <= T_11577.io.manager.grant.ready skip T_11577.io.manager.grant.bits <- T_11661.io.client.grant.bits module BroadcastVoluntaryReleaseTracker : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") reg collect_irel_data : UInt<1>, clk, reset, UInt<1>("h00") reg irel_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_303 = and(io.inner.release.ready, io.inner.release.valid) wire T_307 : UInt<2>[3] T_307[0] <= UInt<1>("h00") T_307[1] <= UInt<1>("h01") T_307[2] <= UInt<2>("h02") node T_312 = eq(T_307[0], io.inner.release.bits.r_type) node T_313 = eq(T_307[1], io.inner.release.bits.r_type) node T_314 = eq(T_307[2], io.inner.release.bits.r_type) node T_316 = or(UInt<1>("h00"), T_312) node T_317 = or(T_316, T_313) node T_318 = or(T_317, T_314) node T_319 = and(UInt<1>("h01"), T_318) node T_320 = and(T_303, T_319) reg T_322 : UInt<2>, clk, reset, UInt<2>("h00") when T_320 : node T_324 = eq(T_322, UInt<2>("h03")) node T_326 = and(UInt<1>("h00"), T_324) node T_329 = addw(T_322, UInt<1>("h01")) node T_330 = mux(T_326, UInt<1>("h00"), T_329) T_322 <= T_330 skip node T_331 = and(T_320, T_324) node T_332 = mux(T_319, T_322, UInt<1>("h00")) node irel_data_done = mux(T_319, T_331, T_303) node T_335 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_337 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_340 : UInt<3>[1] T_340[0] <= UInt<3>("h03") node T_343 = eq(T_340[0], io.outer.acquire.bits.a_type) node T_345 = or(UInt<1>("h00"), T_343) node T_346 = and(T_337, T_345) node T_347 = and(T_335, T_346) reg T_349 : UInt<2>, clk, reset, UInt<2>("h00") when T_347 : node T_351 = eq(T_349, UInt<2>("h03")) node T_353 = and(UInt<1>("h00"), T_351) node T_356 = addw(T_349, UInt<1>("h01")) node T_357 = mux(T_353, UInt<1>("h00"), T_356) T_349 <= T_357 skip node T_358 = and(T_347, T_351) node oacq_data_cnt = mux(T_346, T_349, UInt<1>("h00")) node oacq_data_done = mux(T_346, T_358, T_335) io.has_acquire_conflict <= UInt<1>("h00") io.has_release_match <= io.inner.release.bits.voluntary io.has_acquire_match <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") wire T_383 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_383.client_id <= UInt<1>("h00") T_383.data <= UInt<1>("h00") T_383.g_type <= UInt<1>("h00") T_383.is_builtin_type <= UInt<1>("h00") T_383.manager_xact_id <= UInt<1>("h00") T_383.client_xact_id <= UInt<1>("h00") T_383.addr_beat <= UInt<1>("h00") T_383.client_id <= xact.client_id T_383.is_builtin_type <= UInt<1>("h01") T_383.g_type <= UInt<3>("h00") T_383.client_xact_id <= xact.client_xact_id T_383.manager_xact_id <= UInt<1>("h00") T_383.addr_beat <= UInt<1>("h00") T_383.data <= UInt<1>("h00") io.inner.grant.bits <- T_383 node T_403 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_409 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_410 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_411 = cat(T_409, T_410) node T_413 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_414 = cat(UInt<3>("h07"), T_413) node T_416 = cat(T_403, UInt<1>("h01")) node T_418 = cat(T_403, UInt<1>("h01")) node T_420 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_421 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_422 = cat(T_420, T_421) node T_424 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_426 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_427 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_428 = mux(T_427, T_426, UInt<1>("h00")) node T_429 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_430 = mux(T_429, T_424, T_428) node T_431 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_432 = mux(T_431, T_422, T_430) node T_433 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_434 = mux(T_433, T_418, T_432) node T_435 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_436 = mux(T_435, T_416, T_434) node T_437 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_438 = mux(T_437, T_414, T_436) node T_439 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_440 = mux(T_439, T_411, T_438) wire T_449 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_449.data <= UInt<1>("h00") T_449.union <= UInt<1>("h00") T_449.a_type <= UInt<1>("h00") T_449.is_builtin_type <= UInt<1>("h00") T_449.addr_beat <= UInt<1>("h00") T_449.client_xact_id <= UInt<1>("h00") T_449.addr_block <= UInt<1>("h00") T_449.is_builtin_type <= UInt<1>("h01") T_449.a_type <= UInt<3>("h03") T_449.client_xact_id <= UInt<1>("h00") T_449.addr_block <= xact.addr_block T_449.addr_beat <= oacq_data_cnt T_449.data <= xact.data_buffer[oacq_data_cnt] T_449.union <= T_440 io.outer.acquire.bits <- T_449 when collect_irel_data : io.inner.release.ready <= UInt<1>("h01") when io.inner.release.valid : xact.data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data node T_468 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) node T_469 = or(irel_data_valid, T_468) node T_470 = not(irel_data_valid) node T_471 = or(T_470, T_468) node T_472 = not(T_471) node T_473 = mux(UInt<1>("h01"), T_469, T_472) irel_data_valid <= T_473 skip when irel_data_done : collect_irel_data <= UInt<1>("h00") skip skip node T_475 = eq(UInt<1>("h00"), state) when T_475 : io.inner.release.ready <= UInt<1>("h01") when io.inner.release.valid : xact <- io.inner.release.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.release.bits.data wire T_481 : UInt<2>[3] T_481[0] <= UInt<1>("h00") T_481[1] <= UInt<1>("h01") T_481[2] <= UInt<2>("h02") node T_486 = eq(T_481[0], io.inner.release.bits.r_type) node T_487 = eq(T_481[1], io.inner.release.bits.r_type) node T_488 = eq(T_481[2], io.inner.release.bits.r_type) node T_490 = or(UInt<1>("h00"), T_486) node T_491 = or(T_490, T_487) node T_492 = or(T_491, T_488) node T_493 = and(UInt<1>("h01"), T_492) collect_irel_data <= T_493 wire T_495 : UInt<2>[3] T_495[0] <= UInt<1>("h00") T_495[1] <= UInt<1>("h01") T_495[2] <= UInt<2>("h02") node T_500 = eq(T_495[0], io.inner.release.bits.r_type) node T_501 = eq(T_495[1], io.inner.release.bits.r_type) node T_502 = eq(T_495[2], io.inner.release.bits.r_type) node T_504 = or(UInt<1>("h00"), T_500) node T_505 = or(T_504, T_501) node T_506 = or(T_505, T_502) node T_507 = dshl(T_506, io.inner.release.bits.addr_beat) irel_data_valid <= T_507 wire T_509 : UInt<2>[3] T_509[0] <= UInt<1>("h00") T_509[1] <= UInt<1>("h01") T_509[2] <= UInt<2>("h02") node T_514 = eq(T_509[0], io.inner.release.bits.r_type) node T_515 = eq(T_509[1], io.inner.release.bits.r_type) node T_516 = eq(T_509[2], io.inner.release.bits.r_type) node T_518 = or(UInt<1>("h00"), T_514) node T_519 = or(T_518, T_515) node T_520 = or(T_519, T_516) node T_523 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_524 = mux(T_523, UInt<2>("h03"), UInt<1>("h00")) node T_525 = mux(T_520, UInt<1>("h01"), T_524) state <= T_525 skip skip node T_526 = eq(UInt<1>("h01"), state) when T_526 : node T_528 = eq(collect_irel_data, UInt<1>("h00")) node T_529 = dshr(irel_data_valid, oacq_data_cnt) node T_530 = bit(T_529, 0) node T_531 = or(T_528, T_530) io.outer.acquire.valid <= T_531 when oacq_data_done : state <= UInt<2>("h02") skip skip node T_532 = eq(UInt<2>("h02"), state) when T_532 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid node T_533 = and(io.inner.grant.ready, io.inner.grant.valid) when T_533 : node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_538 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_539 = and(io.inner.grant.bits.is_builtin_type, T_538) node T_541 = eq(T_539, UInt<1>("h00")) node T_542 = and(T_536, T_541) node T_543 = mux(T_542, UInt<2>("h03"), UInt<1>("h00")) state <= T_543 skip skip node T_544 = eq(UInt<2>("h03"), state) when T_544 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<1>("h01") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<1>("h01") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<1>("h01") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<1>("h01") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h01") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<1>("h01") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<1>("h01") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_27 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<2>("h02") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<2>("h02") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<2>("h02") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<2>("h02") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<2>("h02") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<2>("h02") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<2>("h02") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_28 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<2>("h03") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<2>("h03") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<2>("h03") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<2>("h03") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<2>("h03") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<2>("h03") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<2>("h03") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_29 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<3>("h04") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h04") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h04") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h04") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h04") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h04") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<3>("h04") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_30 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<3>("h05") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h05") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h05") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h05") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h05") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h05") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<3>("h05") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_31 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<3>("h06") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h06") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h06") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h06") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h06") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h06") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<3>("h06") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module BroadcastAcquireTracker_32 : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} io.has_release_match <= UInt<1>("h00") io.has_acquire_match <= UInt<1>("h00") io.has_acquire_conflict <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact wire coh : {sharers : UInt<1>} coh.sharers <= UInt<1>("h00") coh.sharers <= UInt<1>("h00") node T_304 = neq(state, UInt<1>("h00")) node T_305 = and(T_304, xact.is_builtin_type) wire T_310 : UInt<3>[3] T_310[0] <= UInt<3>("h04") T_310[1] <= UInt<3>("h05") T_310[2] <= UInt<3>("h06") node T_315 = eq(T_310[0], xact.a_type) node T_316 = eq(T_310[1], xact.a_type) node T_317 = eq(T_310[2], xact.a_type) node T_319 = or(UInt<1>("h00"), T_315) node T_320 = or(T_319, T_316) node T_321 = or(T_320, T_317) node T_322 = and(T_305, T_321) node T_324 = eq(T_322, UInt<1>("h00")) node T_326 = eq(reset, UInt<1>("h00")) when T_326 : node T_328 = eq(T_324, UInt<1>("h00")) when T_328 : node T_330 = eq(reset, UInt<1>("h00")) when T_330 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip reg release_count : UInt<1>, clk, reset, UInt<1>("h00") reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") node T_335 = bit(pending_probes, 0) wire T_337 : UInt<1>[1] T_337[0] <= T_335 node T_342 = asUInt(asSInt(UInt<1>("h01"))) node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) node T_346 = or(T_342, T_345) node T_347 = not(T_342) node T_348 = or(T_347, T_345) node T_349 = not(T_348) node mask_self = mux(UInt<1>("h00"), T_346, T_349) node T_351 = not(io.incoherent[0]) node mask_incoherent = and(mask_self, T_351) reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_363 : UInt<3>[1] T_363[0] <= UInt<3>("h03") node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) node T_368 = or(UInt<1>("h00"), T_366) node T_369 = and(T_360, T_368) node T_370 = and(T_357, T_369) reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") when T_370 : node T_374 = eq(T_372, UInt<2>("h03")) node T_376 = and(UInt<1>("h00"), T_374) node T_379 = addw(T_372, UInt<1>("h01")) node T_380 = mux(T_376, UInt<1>("h00"), T_379) T_372 <= T_380 skip node T_381 = and(T_370, T_374) node T_382 = mux(T_369, T_372, UInt<1>("h00")) node iacq_data_done = mux(T_369, T_381, T_357) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") T_388[1] <= UInt<1>("h01") T_388[2] <= UInt<2>("h02") node T_393 = eq(T_388[0], io.inner.release.bits.r_type) node T_394 = eq(T_388[1], io.inner.release.bits.r_type) node T_395 = eq(T_388[2], io.inner.release.bits.r_type) node T_397 = or(UInt<1>("h00"), T_393) node T_398 = or(T_397, T_394) node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) node T_410 = addw(T_403, UInt<1>("h01")) node T_411 = mux(T_407, UInt<1>("h00"), T_410) T_403 <= T_411 skip node T_412 = and(T_401, T_405) node T_413 = mux(T_400, T_403, UInt<1>("h00")) node irel_data_done = mux(T_400, T_412, T_384) node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) wire T_420 : UInt<3>[1] T_420[0] <= UInt<3>("h05") node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) node T_425 = or(UInt<1>("h00"), T_423) wire T_427 : UInt<1>[2] T_427[0] <= UInt<1>("h00") T_427[1] <= UInt<1>("h01") node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) node T_434 = or(UInt<1>("h00"), T_431) node T_435 = or(T_434, T_432) node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) node T_437 = and(UInt<1>("h01"), T_436) node T_438 = and(T_416, T_437) reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") when T_438 : node T_442 = eq(T_440, UInt<2>("h03")) node T_444 = and(UInt<1>("h00"), T_442) node T_447 = addw(T_440, UInt<1>("h01")) node T_448 = mux(T_444, UInt<1>("h00"), T_447) T_440 <= T_448 skip node T_449 = and(T_438, T_442) node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) node ignt_data_done = mux(T_437, T_449, T_416) node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_458 : UInt<3>[1] T_458[0] <= UInt<3>("h03") node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) node T_463 = or(UInt<1>("h00"), T_461) node T_464 = and(T_455, T_463) node T_465 = and(T_453, T_464) reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") when T_465 : node T_469 = eq(T_467, UInt<2>("h03")) node T_471 = and(UInt<1>("h00"), T_469) node T_474 = addw(T_467, UInt<1>("h01")) node T_475 = mux(T_471, UInt<1>("h00"), T_474) T_467 <= T_475 skip node T_476 = and(T_465, T_469) node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) node oacq_data_done = mux(T_464, T_476, T_453) node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) wire T_484 : UInt<3>[1] T_484[0] <= UInt<3>("h05") node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) node T_489 = or(UInt<1>("h00"), T_487) wire T_491 : UInt<1>[1] T_491[0] <= UInt<1>("h00") node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) node T_496 = or(UInt<1>("h00"), T_494) node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) node T_498 = and(UInt<1>("h01"), T_497) node T_499 = and(T_479, T_498) reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") when T_499 : node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = and(UInt<1>("h00"), T_503) node T_508 = addw(T_501, UInt<1>("h01")) node T_509 = mux(T_505, UInt<1>("h00"), T_508) T_501 <= T_509 skip node T_510 = and(T_499, T_503) node T_511 = mux(T_498, T_501, UInt<1>("h00")) node ognt_data_done = mux(T_498, T_510, T_479) reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") wire T_519 : UInt<3>[3] T_519[0] <= UInt<3>("h02") T_519[1] <= UInt<3>("h03") T_519[2] <= UInt<3>("h04") node T_524 = eq(T_519[0], xact.a_type) node T_525 = eq(T_519[1], xact.a_type) node T_526 = eq(T_519[2], xact.a_type) node T_528 = or(UInt<1>("h00"), T_524) node T_529 = or(T_528, T_525) node T_530 = or(T_529, T_526) node pending_outer_write = and(xact.is_builtin_type, T_530) wire T_536 : UInt<3>[3] T_536[0] <= UInt<3>("h02") T_536[1] <= UInt<3>("h03") T_536[2] <= UInt<3>("h04") node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) node T_545 = or(UInt<1>("h00"), T_541) node T_546 = or(T_545, T_542) node T_547 = or(T_546, T_543) node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) wire T_552 : UInt<3>[2] T_552[0] <= UInt<3>("h05") T_552[1] <= UInt<3>("h04") node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) node T_559 = or(UInt<1>("h00"), T_556) node T_560 = or(T_559, T_557) wire T_562 : UInt<1>[2] T_562[0] <= UInt<1>("h00") T_562[1] <= UInt<1>("h01") node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) node T_569 = or(UInt<1>("h00"), T_566) node T_570 = or(T_569, T_567) node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) node T_593 = mux(T_592, UInt<3>("h01"), T_591) node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) node T_595 = mux(T_594, UInt<3>("h04"), T_593) node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) node T_597 = mux(T_596, UInt<3>("h03"), T_595) node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) node T_599 = mux(T_598, UInt<3>("h03"), T_597) node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) node T_601 = mux(T_600, UInt<3>("h05"), T_599) node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) node T_603 = mux(T_602, UInt<3>("h04"), T_601) node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) node T_609 = mux(T_604, T_608, UInt<1>("h01")) node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_619.client_id <= UInt<1>("h00") T_619.data <= UInt<1>("h00") T_619.g_type <= UInt<1>("h00") T_619.is_builtin_type <= UInt<1>("h00") T_619.manager_xact_id <= UInt<1>("h00") T_619.client_xact_id <= UInt<1>("h00") T_619.addr_beat <= UInt<1>("h00") T_619.client_id <= io.inner.acquire.bits.client_id T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type T_619.g_type <= T_610 T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id T_619.manager_xact_id <= UInt<3>("h07") T_619.addr_beat <= UInt<1>("h00") T_619.data <= UInt<1>("h00") wire T_637 : UInt<3>[2] T_637[0] <= UInt<3>("h05") T_637[1] <= UInt<3>("h04") node T_641 = eq(T_637[0], T_619.g_type) node T_642 = eq(T_637[1], T_619.g_type) node T_644 = or(UInt<1>("h00"), T_641) node T_645 = or(T_644, T_642) wire T_647 : UInt<1>[2] T_647[0] <= UInt<1>("h00") T_647[1] <= UInt<1>("h01") node T_651 = eq(T_647[0], T_619.g_type) node T_652 = eq(T_647[1], T_619.g_type) node T_654 = or(UInt<1>("h00"), T_651) node T_655 = or(T_654, T_652) node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) wire T_661 : UInt<3>[3] T_661[0] <= UInt<3>("h02") T_661[1] <= UInt<3>("h00") T_661[2] <= UInt<3>("h04") node T_666 = eq(T_661[0], xact.a_type) node T_667 = eq(T_661[1], xact.a_type) node T_668 = eq(T_661[2], xact.a_type) node T_670 = or(UInt<1>("h00"), T_666) node T_671 = or(T_670, T_667) node T_672 = or(T_671, T_668) node subblock_type = and(xact.is_builtin_type, T_672) node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_675 = neq(state, UInt<1>("h00")) node T_676 = and(T_674, T_675) node T_678 = eq(collect_iacq_data, UInt<1>("h00")) node T_679 = and(T_676, T_678) io.has_acquire_conflict <= T_679 node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) node T_681 = and(T_680, collect_iacq_data) io.has_acquire_match <= T_681 node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) node T_685 = and(T_682, T_684) node T_686 = eq(state, UInt<1>("h01")) node T_687 = and(T_685, T_686) io.has_release_match <= T_687 node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_700 = cat(T_698, T_699) node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_703 = cat(UInt<3>("h07"), T_702) node T_705 = cat(T_692, UInt<1>("h01")) node T_707 = cat(T_692, UInt<1>("h01")) node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_711 = cat(T_709, T_710) node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_717 = mux(T_716, T_715, UInt<1>("h00")) node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_719 = mux(T_718, T_713, T_717) node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_721 = mux(T_720, T_711, T_719) node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_723 = mux(T_722, T_707, T_721) node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_725 = mux(T_724, T_705, T_723) node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_727 = mux(T_726, T_703, T_725) node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_729 = mux(T_728, T_700, T_727) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_probe.data <= UInt<1>("h00") oacq_probe.union <= UInt<1>("h00") oacq_probe.a_type <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h00") oacq_probe.addr_beat <= UInt<1>("h00") oacq_probe.client_xact_id <= UInt<1>("h00") oacq_probe.addr_block <= UInt<1>("h00") oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h07") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data oacq_probe.union <= T_729 node T_754 = bits(xact.union, 12, 9) node T_755 = bits(T_754, 3, 3) node T_757 = dshl(UInt<1>("h01"), T_755) node T_759 = eq(xact.a_type, UInt<3>("h04")) node T_760 = and(xact.is_builtin_type, T_759) node T_761 = bit(T_757, 0) node T_762 = bit(T_757, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 node T_769 = subw(UInt<8>("h00"), T_764[0]) node T_771 = subw(UInt<8>("h00"), T_764[1]) wire T_773 : UInt<8>[2] T_773[0] <= T_769 T_773[1] <= T_771 node T_777 = cat(T_773[1], T_773[0]) node T_779 = eq(xact.a_type, UInt<3>("h03")) node T_780 = and(xact.is_builtin_type, T_779) node T_782 = eq(xact.a_type, UInt<3>("h02")) node T_783 = and(xact.is_builtin_type, T_782) node T_784 = or(T_780, T_783) node T_785 = bits(xact.union, 16, 1) node T_787 = mux(T_784, T_785, UInt<16>("h00")) node T_788 = mux(T_760, T_777, T_787) node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_798 = cat(T_796, T_797) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_801 = cat(UInt<3>("h07"), T_800) node T_803 = cat(T_788, UInt<1>("h01")) node T_805 = cat(T_788, UInt<1>("h01")) node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_809 = cat(T_807, T_808) node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_815 = mux(T_814, T_813, UInt<1>("h00")) node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_817 = mux(T_816, T_811, T_815) node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_819 = mux(T_818, T_809, T_817) node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_821 = mux(T_820, T_805, T_819) node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_823 = mux(T_822, T_803, T_821) node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_825 = mux(T_824, T_801, T_823) node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_827 = mux(T_826, T_798, T_825) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_beat.data <= UInt<1>("h00") oacq_write_beat.union <= UInt<1>("h00") oacq_write_beat.a_type <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h00") oacq_write_beat.addr_beat <= UInt<1>("h00") oacq_write_beat.client_xact_id <= UInt<1>("h00") oacq_write_beat.addr_block <= UInt<1>("h00") oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h07") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] oacq_write_beat.union <= T_827 node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_863 = cat(T_861, T_862) node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_866 = cat(UInt<3>("h07"), T_865) node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_874 = cat(T_872, T_873) node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_880 = mux(T_879, T_878, UInt<1>("h00")) node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_882 = mux(T_881, T_876, T_880) node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_884 = mux(T_883, T_874, T_882) node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_886 = mux(T_885, T_870, T_884) node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_888 = mux(T_887, T_868, T_886) node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_890 = mux(T_889, T_866, T_888) node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_892 = mux(T_891, T_863, T_890) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_write_block.data <= UInt<1>("h00") oacq_write_block.union <= UInt<1>("h00") oacq_write_block.a_type <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h00") oacq_write_block.addr_beat <= UInt<1>("h00") oacq_write_block.client_xact_id <= UInt<1>("h00") oacq_write_block.addr_block <= UInt<1>("h00") oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h07") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] oacq_write_block.union <= T_892 node T_917 = bits(xact.union, 12, 9) node T_918 = bits(xact.union, 8, 6) node T_926 = cat(T_917, T_918) node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_928 = cat(T_926, T_927) node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_931 = cat(T_918, T_930) node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_937 = cat(T_917, T_918) node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_939 = cat(T_937, T_938) node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_945 = mux(T_944, T_943, UInt<1>("h00")) node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_947 = mux(T_946, T_941, T_945) node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_949 = mux(T_948, T_939, T_947) node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_951 = mux(T_950, T_935, T_949) node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_953 = mux(T_952, T_933, T_951) node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_955 = mux(T_954, T_931, T_953) node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_957 = mux(T_956, T_928, T_955) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= UInt<1>("h00") oacq_read_beat.a_type <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h00") oacq_read_beat.addr_beat <= UInt<1>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h00") oacq_read_beat.addr_block <= UInt<1>("h00") oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h07") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") oacq_read_beat.union <= T_957 node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_993 = cat(T_991, T_992) node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_996 = cat(UInt<3>("h07"), T_995) node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1004 = cat(T_1002, T_1003) node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1012 = mux(T_1011, T_1006, T_1010) node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1014 = mux(T_1013, T_1004, T_1012) node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1016 = mux(T_1015, T_1000, T_1014) node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1018 = mux(T_1017, T_998, T_1016) node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1020 = mux(T_1019, T_996, T_1018) node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1022 = mux(T_1021, T_993, T_1020) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= UInt<1>("h00") oacq_read_block.a_type <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h00") oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.client_xact_id <= UInt<1>("h00") oacq_read_block.addr_block <= UInt<1>("h00") oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h07") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") oacq_read_block.union <= T_1022 io.outer.acquire.valid <= UInt<1>("h00") node T_1047 = eq(state, UInt<1>("h01")) node T_1048 = eq(state, UInt<2>("h03")) wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1057 <- oacq_write_block when subblock_type : T_1057 <- oacq_write_beat skip wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1073 <- oacq_read_block when subblock_type : T_1073 <- oacq_read_beat skip wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1089 <- T_1073 when T_1048 : T_1089 <- T_1057 skip wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} T_1105 <- T_1089 when T_1047 : T_1105 <- oacq_probe skip io.outer.acquire.bits <- T_1105 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") node T_1122 = eq(UInt<3>("h04"), xact.a_type) node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) node T_1124 = eq(UInt<3>("h06"), xact.a_type) node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) node T_1126 = eq(UInt<3>("h05"), xact.a_type) node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) node T_1128 = eq(UInt<3>("h02"), xact.a_type) node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) node T_1130 = eq(UInt<3>("h00"), xact.a_type) node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) node T_1132 = eq(UInt<3>("h03"), xact.a_type) node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) node T_1134 = eq(UInt<3>("h01"), xact.a_type) node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) node T_1136 = eq(UInt<1>("h01"), xact.a_type) node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) node T_1138 = eq(UInt<1>("h00"), xact.a_type) node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= UInt<1>("h00") T_1145.addr_block <= UInt<1>("h00") T_1145.client_id <= UInt<1>("h00") T_1145.p_type <= T_1140 T_1145.addr_block <= xact.addr_block io.inner.probe.bits <- T_1145 io.inner.grant.valid <= UInt<1>("h00") node T_1171 = eq(UInt<3>("h06"), xact.a_type) node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) node T_1173 = eq(UInt<3>("h05"), xact.a_type) node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) node T_1175 = eq(UInt<3>("h04"), xact.a_type) node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) node T_1177 = eq(UInt<3>("h03"), xact.a_type) node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) node T_1179 = eq(UInt<3>("h02"), xact.a_type) node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) node T_1181 = eq(UInt<3>("h01"), xact.a_type) node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) node T_1183 = eq(UInt<3>("h00"), xact.a_type) node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) node T_1185 = eq(xact.a_type, UInt<1>("h00")) node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} T_1200.client_id <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") T_1200.g_type <= UInt<1>("h00") T_1200.is_builtin_type <= UInt<1>("h00") T_1200.manager_xact_id <= UInt<1>("h00") T_1200.client_xact_id <= UInt<1>("h00") T_1200.addr_beat <= UInt<1>("h00") T_1200.client_id <= xact.client_id T_1200.is_builtin_type <= xact.is_builtin_type T_1200.g_type <= T_1191 T_1200.client_xact_id <= xact.client_xact_id T_1200.manager_xact_id <= UInt<3>("h07") T_1200.addr_beat <= UInt<1>("h00") T_1200.data <= UInt<1>("h00") io.inner.grant.bits <- T_1200 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") node T_1218 = neq(state, UInt<1>("h00")) node T_1219 = and(T_1218, collect_iacq_data) node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1221 = and(T_1219, T_1220) node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) node T_1223 = and(T_1221, T_1222) node T_1225 = eq(T_1223, UInt<1>("h00")) node T_1227 = eq(reset, UInt<1>("h00")) when T_1227 : node T_1229 = eq(T_1225, UInt<1>("h00")) when T_1229 : node T_1231 = eq(reset, UInt<1>("h00")) when T_1231 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1232 = neq(state, UInt<1>("h00")) node T_1233 = and(T_1232, collect_iacq_data) node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1235 = and(T_1233, T_1234) node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) node T_1237 = and(T_1235, T_1236) node T_1239 = eq(T_1237, UInt<1>("h00")) node T_1241 = eq(reset, UInt<1>("h00")) when T_1241 : node T_1243 = eq(T_1239, UInt<1>("h00")) when T_1243 : node T_1245 = eq(reset, UInt<1>("h00")) when T_1245 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip node T_1246 = eq(state, UInt<1>("h00")) node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) node T_1248 = and(T_1246, T_1247) node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1253 : UInt<3>[1] T_1253[0] <= UInt<3>("h03") node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) node T_1258 = or(UInt<1>("h00"), T_1256) node T_1259 = and(T_1250, T_1258) node T_1260 = and(T_1248, T_1259) node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) node T_1263 = and(T_1260, T_1262) node T_1265 = eq(T_1263, UInt<1>("h00")) node T_1267 = eq(reset, UInt<1>("h00")) when T_1267 : node T_1269 = eq(T_1265, UInt<1>("h00")) when T_1269 : node T_1271 = eq(reset, UInt<1>("h00")) when T_1271 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) skip skip when collect_iacq_data : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) node T_1276 = bits(T_1275, 3, 3) node T_1278 = dshl(UInt<1>("h01"), T_1276) node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) node T_1282 = bit(T_1278, 0) node T_1283 = bit(T_1278, 1) wire T_1285 : UInt<1>[2] T_1285[0] <= T_1282 T_1285[1] <= T_1283 node T_1290 = subw(UInt<8>("h00"), T_1285[0]) node T_1292 = subw(UInt<8>("h00"), T_1285[1]) wire T_1294 : UInt<8>[2] T_1294[0] <= T_1290 T_1294[1] <= T_1292 node T_1298 = cat(T_1294[1], T_1294[0]) node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) node T_1305 = or(T_1301, T_1304) node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) node T_1309 = mux(T_1281, T_1298, T_1308) xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) node T_1313 = or(iacq_data_valid, T_1312) node T_1314 = not(iacq_data_valid) node T_1315 = or(T_1314, T_1312) node T_1316 = not(T_1315) node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) iacq_data_valid <= T_1317 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") skip skip when pending_ognt_ack : io.outer.grant.ready <= UInt<1>("h01") when io.outer.grant.valid : pending_ognt_ack <= UInt<1>("h00") skip skip node T_1321 = eq(UInt<1>("h00"), state) when T_1321 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) node T_1328 = bits(T_1327, 3, 3) node T_1330 = dshl(UInt<1>("h01"), T_1328) node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) node T_1334 = bit(T_1330, 0) node T_1335 = bit(T_1330, 1) wire T_1337 : UInt<1>[2] T_1337[0] <= T_1334 T_1337[1] <= T_1335 node T_1342 = subw(UInt<8>("h00"), T_1337[0]) node T_1344 = subw(UInt<8>("h00"), T_1337[1]) wire T_1346 : UInt<8>[2] T_1346[0] <= T_1342 T_1346[1] <= T_1344 node T_1350 = cat(T_1346[1], T_1346[0]) node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) node T_1357 = or(T_1353, T_1356) node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) node T_1361 = mux(T_1333, T_1350, T_1360) xact.wmask_buffer[UInt<1>("h00")] <= T_1361 node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) wire T_1366 : UInt<3>[1] T_1366[0] <= UInt<3>("h03") node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) node T_1371 = or(UInt<1>("h00"), T_1369) node T_1372 = and(T_1363, T_1371) collect_iacq_data <= T_1372 wire T_1377 : UInt<3>[3] T_1377[0] <= UInt<3>("h02") T_1377[1] <= UInt<3>("h03") T_1377[2] <= UInt<3>("h04") node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) node T_1386 = or(UInt<1>("h00"), T_1382) node T_1387 = or(T_1386, T_1383) node T_1388 = or(T_1387, T_1384) node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) iacq_data_valid <= T_1390 node T_1392 = neq(mask_incoherent, UInt<1>("h00")) when T_1392 : pending_probes <= mask_incoherent node T_1393 = bit(mask_incoherent, 0) node T_1394 = bit(mask_incoherent, 1) node T_1395 = bit(mask_incoherent, 2) node T_1396 = bit(mask_incoherent, 3) node T_1398 = cat(UInt<1>("h00"), T_1394) node T_1399 = addw(T_1393, T_1398) node T_1402 = cat(UInt<1>("h00"), T_1396) node T_1403 = addw(T_1395, T_1402) node T_1404 = cat(UInt<1>("h00"), T_1403) node T_1405 = addw(T_1399, T_1404) release_count <= T_1405 skip node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) state <= T_1408 skip skip node T_1409 = eq(UInt<1>("h01"), state) when T_1409 : node T_1411 = neq(pending_probes, UInt<1>("h00")) io.inner.probe.valid <= T_1411 when io.inner.probe.ready : node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) node T_1414 = not(T_1413) node T_1415 = and(pending_probes, T_1414) pending_probes <= T_1415 skip wire T_1417 : UInt<2>[3] T_1417[0] <= UInt<1>("h00") T_1417[1] <= UInt<1>("h01") T_1417[2] <= UInt<2>("h02") node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) node T_1426 = or(UInt<1>("h00"), T_1422) node T_1427 = or(T_1426, T_1423) node T_1428 = or(T_1427, T_1424) node T_1430 = eq(T_1428, UInt<1>("h00")) node T_1431 = or(T_1430, io.outer.acquire.ready) io.inner.release.ready <= T_1431 when io.inner.release.valid : wire T_1433 : UInt<2>[3] T_1433[0] <= UInt<1>("h00") T_1433[1] <= UInt<1>("h01") T_1433[2] <= UInt<2>("h02") node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) node T_1442 = or(UInt<1>("h00"), T_1438) node T_1443 = or(T_1442, T_1439) node T_1444 = or(T_1443, T_1440) when T_1444 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1448 = subw(release_count, UInt<1>("h01")) release_count <= T_1448 node T_1450 = eq(release_count, UInt<1>("h01")) when T_1450 : node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) state <= T_1452 skip skip skip skip node T_1454 = eq(T_1444, UInt<1>("h00")) when T_1454 : node T_1456 = subw(release_count, UInt<1>("h01")) release_count <= T_1456 node T_1458 = eq(release_count, UInt<1>("h01")) when T_1458 : node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) state <= T_1460 skip skip skip skip node T_1461 = eq(UInt<2>("h03"), state) when T_1461 : node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) node T_1467 = bit(T_1466, 0) node T_1468 = or(T_1465, T_1467) node T_1469 = and(T_1463, T_1468) io.outer.acquire.valid <= T_1469 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) state <= T_1471 skip skip node T_1472 = eq(UInt<2>("h02"), state) when T_1472 : node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) io.outer.acquire.valid <= T_1474 node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) when T_1475 : state <= UInt<3>("h05") skip skip node T_1476 = eq(UInt<3>("h05"), state) when T_1476 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) node T_1484 = eq(T_1482, UInt<1>("h00")) node T_1485 = and(T_1479, T_1484) node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) state <= T_1486 skip skip node T_1487 = eq(UInt<3>("h04"), state) when T_1487 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) node T_1496 = eq(T_1494, UInt<1>("h00")) node T_1497 = and(T_1491, T_1496) node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) state <= T_1498 skip skip node T_1499 = eq(UInt<3>("h06"), state) when T_1499 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") skip skip module LockingRRArbiter_33 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, chosen : UInt<3>} io.chosen <= UInt<1>("h00") io.out.bits.client_id <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.g_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.manager_xact_id <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") io.in[5].ready <= UInt<1>("h00") io.in[6].ready <= UInt<1>("h00") io.in[7].ready <= UInt<1>("h00") reg T_1502 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1504 : UInt, clk, reset, UInt<3>("h07") wire T_1506 : UInt<3> T_1506 <= UInt<1>("h00") io.out.valid <= io.in[T_1506].valid io.out.bits <- io.in[T_1506].bits io.chosen <= T_1506 io.in[T_1506].ready <= UInt<1>("h00") reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") node T_1707 = gt(UInt<1>("h00"), last_grant) node T_1708 = and(io.in[0].valid, T_1707) node T_1710 = gt(UInt<1>("h01"), last_grant) node T_1711 = and(io.in[1].valid, T_1710) node T_1713 = gt(UInt<2>("h02"), last_grant) node T_1714 = and(io.in[2].valid, T_1713) node T_1716 = gt(UInt<2>("h03"), last_grant) node T_1717 = and(io.in[3].valid, T_1716) node T_1719 = gt(UInt<3>("h04"), last_grant) node T_1720 = and(io.in[4].valid, T_1719) node T_1722 = gt(UInt<3>("h05"), last_grant) node T_1723 = and(io.in[5].valid, T_1722) node T_1725 = gt(UInt<3>("h06"), last_grant) node T_1726 = and(io.in[6].valid, T_1725) node T_1728 = gt(UInt<3>("h07"), last_grant) node T_1729 = and(io.in[7].valid, T_1728) node T_1732 = or(UInt<1>("h00"), T_1708) node T_1734 = eq(T_1732, UInt<1>("h00")) node T_1736 = or(UInt<1>("h00"), T_1708) node T_1737 = or(T_1736, T_1711) node T_1739 = eq(T_1737, UInt<1>("h00")) node T_1741 = or(UInt<1>("h00"), T_1708) node T_1742 = or(T_1741, T_1711) node T_1743 = or(T_1742, T_1714) node T_1745 = eq(T_1743, UInt<1>("h00")) node T_1747 = or(UInt<1>("h00"), T_1708) node T_1748 = or(T_1747, T_1711) node T_1749 = or(T_1748, T_1714) node T_1750 = or(T_1749, T_1717) node T_1752 = eq(T_1750, UInt<1>("h00")) node T_1754 = or(UInt<1>("h00"), T_1708) node T_1755 = or(T_1754, T_1711) node T_1756 = or(T_1755, T_1714) node T_1757 = or(T_1756, T_1717) node T_1758 = or(T_1757, T_1720) node T_1760 = eq(T_1758, UInt<1>("h00")) node T_1762 = or(UInt<1>("h00"), T_1708) node T_1763 = or(T_1762, T_1711) node T_1764 = or(T_1763, T_1714) node T_1765 = or(T_1764, T_1717) node T_1766 = or(T_1765, T_1720) node T_1767 = or(T_1766, T_1723) node T_1769 = eq(T_1767, UInt<1>("h00")) node T_1771 = or(UInt<1>("h00"), T_1708) node T_1772 = or(T_1771, T_1711) node T_1773 = or(T_1772, T_1714) node T_1774 = or(T_1773, T_1717) node T_1775 = or(T_1774, T_1720) node T_1776 = or(T_1775, T_1723) node T_1777 = or(T_1776, T_1726) node T_1779 = eq(T_1777, UInt<1>("h00")) node T_1781 = or(UInt<1>("h00"), T_1708) node T_1782 = or(T_1781, T_1711) node T_1783 = or(T_1782, T_1714) node T_1784 = or(T_1783, T_1717) node T_1785 = or(T_1784, T_1720) node T_1786 = or(T_1785, T_1723) node T_1787 = or(T_1786, T_1726) node T_1788 = or(T_1787, T_1729) node T_1790 = eq(T_1788, UInt<1>("h00")) node T_1792 = or(UInt<1>("h00"), T_1708) node T_1793 = or(T_1792, T_1711) node T_1794 = or(T_1793, T_1714) node T_1795 = or(T_1794, T_1717) node T_1796 = or(T_1795, T_1720) node T_1797 = or(T_1796, T_1723) node T_1798 = or(T_1797, T_1726) node T_1799 = or(T_1798, T_1729) node T_1800 = or(T_1799, io.in[0].valid) node T_1802 = eq(T_1800, UInt<1>("h00")) node T_1804 = or(UInt<1>("h00"), T_1708) node T_1805 = or(T_1804, T_1711) node T_1806 = or(T_1805, T_1714) node T_1807 = or(T_1806, T_1717) node T_1808 = or(T_1807, T_1720) node T_1809 = or(T_1808, T_1723) node T_1810 = or(T_1809, T_1726) node T_1811 = or(T_1810, T_1729) node T_1812 = or(T_1811, io.in[0].valid) node T_1813 = or(T_1812, io.in[1].valid) node T_1815 = eq(T_1813, UInt<1>("h00")) node T_1817 = or(UInt<1>("h00"), T_1708) node T_1818 = or(T_1817, T_1711) node T_1819 = or(T_1818, T_1714) node T_1820 = or(T_1819, T_1717) node T_1821 = or(T_1820, T_1720) node T_1822 = or(T_1821, T_1723) node T_1823 = or(T_1822, T_1726) node T_1824 = or(T_1823, T_1729) node T_1825 = or(T_1824, io.in[0].valid) node T_1826 = or(T_1825, io.in[1].valid) node T_1827 = or(T_1826, io.in[2].valid) node T_1829 = eq(T_1827, UInt<1>("h00")) node T_1831 = or(UInt<1>("h00"), T_1708) node T_1832 = or(T_1831, T_1711) node T_1833 = or(T_1832, T_1714) node T_1834 = or(T_1833, T_1717) node T_1835 = or(T_1834, T_1720) node T_1836 = or(T_1835, T_1723) node T_1837 = or(T_1836, T_1726) node T_1838 = or(T_1837, T_1729) node T_1839 = or(T_1838, io.in[0].valid) node T_1840 = or(T_1839, io.in[1].valid) node T_1841 = or(T_1840, io.in[2].valid) node T_1842 = or(T_1841, io.in[3].valid) node T_1844 = eq(T_1842, UInt<1>("h00")) node T_1846 = or(UInt<1>("h00"), T_1708) node T_1847 = or(T_1846, T_1711) node T_1848 = or(T_1847, T_1714) node T_1849 = or(T_1848, T_1717) node T_1850 = or(T_1849, T_1720) node T_1851 = or(T_1850, T_1723) node T_1852 = or(T_1851, T_1726) node T_1853 = or(T_1852, T_1729) node T_1854 = or(T_1853, io.in[0].valid) node T_1855 = or(T_1854, io.in[1].valid) node T_1856 = or(T_1855, io.in[2].valid) node T_1857 = or(T_1856, io.in[3].valid) node T_1858 = or(T_1857, io.in[4].valid) node T_1860 = eq(T_1858, UInt<1>("h00")) node T_1862 = or(UInt<1>("h00"), T_1708) node T_1863 = or(T_1862, T_1711) node T_1864 = or(T_1863, T_1714) node T_1865 = or(T_1864, T_1717) node T_1866 = or(T_1865, T_1720) node T_1867 = or(T_1866, T_1723) node T_1868 = or(T_1867, T_1726) node T_1869 = or(T_1868, T_1729) node T_1870 = or(T_1869, io.in[0].valid) node T_1871 = or(T_1870, io.in[1].valid) node T_1872 = or(T_1871, io.in[2].valid) node T_1873 = or(T_1872, io.in[3].valid) node T_1874 = or(T_1873, io.in[4].valid) node T_1875 = or(T_1874, io.in[5].valid) node T_1877 = eq(T_1875, UInt<1>("h00")) node T_1879 = or(UInt<1>("h00"), T_1708) node T_1880 = or(T_1879, T_1711) node T_1881 = or(T_1880, T_1714) node T_1882 = or(T_1881, T_1717) node T_1883 = or(T_1882, T_1720) node T_1884 = or(T_1883, T_1723) node T_1885 = or(T_1884, T_1726) node T_1886 = or(T_1885, T_1729) node T_1887 = or(T_1886, io.in[0].valid) node T_1888 = or(T_1887, io.in[1].valid) node T_1889 = or(T_1888, io.in[2].valid) node T_1890 = or(T_1889, io.in[3].valid) node T_1891 = or(T_1890, io.in[4].valid) node T_1892 = or(T_1891, io.in[5].valid) node T_1893 = or(T_1892, io.in[6].valid) node T_1895 = eq(T_1893, UInt<1>("h00")) node T_1897 = gt(UInt<1>("h00"), last_grant) node T_1898 = and(UInt<1>("h01"), T_1897) node T_1899 = or(T_1898, T_1790) node T_1901 = gt(UInt<1>("h01"), last_grant) node T_1902 = and(T_1734, T_1901) node T_1903 = or(T_1902, T_1802) node T_1905 = gt(UInt<2>("h02"), last_grant) node T_1906 = and(T_1739, T_1905) node T_1907 = or(T_1906, T_1815) node T_1909 = gt(UInt<2>("h03"), last_grant) node T_1910 = and(T_1745, T_1909) node T_1911 = or(T_1910, T_1829) node T_1913 = gt(UInt<3>("h04"), last_grant) node T_1914 = and(T_1752, T_1913) node T_1915 = or(T_1914, T_1844) node T_1917 = gt(UInt<3>("h05"), last_grant) node T_1918 = and(T_1760, T_1917) node T_1919 = or(T_1918, T_1860) node T_1921 = gt(UInt<3>("h06"), last_grant) node T_1922 = and(T_1769, T_1921) node T_1923 = or(T_1922, T_1877) node T_1925 = gt(UInt<3>("h07"), last_grant) node T_1926 = and(T_1779, T_1925) node T_1927 = or(T_1926, T_1895) node T_1929 = eq(T_1504, UInt<1>("h00")) node T_1930 = mux(T_1502, T_1929, T_1899) node T_1931 = and(T_1930, io.out.ready) io.in[0].ready <= T_1931 node T_1933 = eq(T_1504, UInt<1>("h01")) node T_1934 = mux(T_1502, T_1933, T_1903) node T_1935 = and(T_1934, io.out.ready) io.in[1].ready <= T_1935 node T_1937 = eq(T_1504, UInt<2>("h02")) node T_1938 = mux(T_1502, T_1937, T_1907) node T_1939 = and(T_1938, io.out.ready) io.in[2].ready <= T_1939 node T_1941 = eq(T_1504, UInt<2>("h03")) node T_1942 = mux(T_1502, T_1941, T_1911) node T_1943 = and(T_1942, io.out.ready) io.in[3].ready <= T_1943 node T_1945 = eq(T_1504, UInt<3>("h04")) node T_1946 = mux(T_1502, T_1945, T_1915) node T_1947 = and(T_1946, io.out.ready) io.in[4].ready <= T_1947 node T_1949 = eq(T_1504, UInt<3>("h05")) node T_1950 = mux(T_1502, T_1949, T_1919) node T_1951 = and(T_1950, io.out.ready) io.in[5].ready <= T_1951 node T_1953 = eq(T_1504, UInt<3>("h06")) node T_1954 = mux(T_1502, T_1953, T_1923) node T_1955 = and(T_1954, io.out.ready) io.in[6].ready <= T_1955 node T_1957 = eq(T_1504, UInt<3>("h07")) node T_1958 = mux(T_1502, T_1957, T_1927) node T_1959 = and(T_1958, io.out.ready) io.in[7].ready <= T_1959 reg T_1961 : UInt<2>, clk, reset, UInt<2>("h00") node T_1963 = addw(T_1961, UInt<1>("h01")) node T_1964 = and(io.out.ready, io.out.valid) when T_1964 : wire T_1968 : UInt<3>[1] T_1968[0] <= UInt<3>("h05") node T_1971 = eq(T_1968[0], io.out.bits.g_type) node T_1973 = or(UInt<1>("h00"), T_1971) wire T_1975 : UInt<1>[2] T_1975[0] <= UInt<1>("h00") T_1975[1] <= UInt<1>("h01") node T_1979 = eq(T_1975[0], io.out.bits.g_type) node T_1980 = eq(T_1975[1], io.out.bits.g_type) node T_1982 = or(UInt<1>("h00"), T_1979) node T_1983 = or(T_1982, T_1980) node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983) node T_1985 = and(UInt<1>("h01"), T_1984) when T_1985 : T_1961 <= T_1963 node T_1987 = eq(T_1502, UInt<1>("h00")) when T_1987 : T_1502 <= UInt<1>("h01") node T_1989 = and(io.in[0].ready, io.in[0].valid) node T_1990 = and(io.in[1].ready, io.in[1].valid) node T_1991 = and(io.in[2].ready, io.in[2].valid) node T_1992 = and(io.in[3].ready, io.in[3].valid) node T_1993 = and(io.in[4].ready, io.in[4].valid) node T_1994 = and(io.in[5].ready, io.in[5].valid) node T_1995 = and(io.in[6].ready, io.in[6].valid) node T_1996 = and(io.in[7].ready, io.in[7].valid) wire T_1998 : UInt<1>[8] T_1998[0] <= T_1989 T_1998[1] <= T_1990 T_1998[2] <= T_1991 T_1998[3] <= T_1992 T_1998[4] <= T_1993 T_1998[5] <= T_1994 T_1998[6] <= T_1995 T_1998[7] <= T_1996 node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07")) node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016) node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017) node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018) node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019) node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020) node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021) T_1504 <= T_2022 skip skip node T_2024 = eq(T_1963, UInt<1>("h00")) when T_2024 : T_1502 <= UInt<1>("h00") skip skip node T_2028 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_2030 = mux(io.in[5].valid, UInt<3>("h05"), T_2028) node T_2032 = mux(io.in[4].valid, UInt<3>("h04"), T_2030) node T_2034 = mux(io.in[3].valid, UInt<2>("h03"), T_2032) node T_2036 = mux(io.in[2].valid, UInt<2>("h02"), T_2034) node T_2038 = mux(io.in[1].valid, UInt<1>("h01"), T_2036) node T_2040 = mux(io.in[0].valid, UInt<1>("h00"), T_2038) node T_2042 = gt(UInt<3>("h07"), last_grant) node T_2043 = and(io.in[7].valid, T_2042) node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040) node T_2047 = gt(UInt<3>("h06"), last_grant) node T_2048 = and(io.in[6].valid, T_2047) node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045) node T_2052 = gt(UInt<3>("h05"), last_grant) node T_2053 = and(io.in[5].valid, T_2052) node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050) node T_2057 = gt(UInt<3>("h04"), last_grant) node T_2058 = and(io.in[4].valid, T_2057) node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055) node T_2062 = gt(UInt<2>("h03"), last_grant) node T_2063 = and(io.in[3].valid, T_2062) node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060) node T_2067 = gt(UInt<2>("h02"), last_grant) node T_2068 = and(io.in[2].valid, T_2067) node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065) node T_2072 = gt(UInt<1>("h01"), last_grant) node T_2073 = and(io.in[1].valid, T_2072) node choose = mux(T_2073, UInt<1>("h01"), T_2070) node T_2076 = mux(T_1502, T_1504, choose) T_1506 <= T_2076 node T_2077 = and(io.out.ready, io.out.valid) when T_2077 : last_grant <= T_1506 skip module LockingRRArbiter_34 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>} io.chosen <= UInt<1>("h00") io.out.bits.client_id <= UInt<1>("h00") io.out.bits.p_type <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") io.in[5].ready <= UInt<1>("h00") io.in[6].ready <= UInt<1>("h00") io.in[7].ready <= UInt<1>("h00") reg T_1318 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1320 : UInt, clk, reset, UInt<3>("h07") wire T_1322 : UInt<3> T_1322 <= UInt<1>("h00") io.out.valid <= io.in[T_1322].valid io.out.bits <- io.in[T_1322].bits io.chosen <= T_1322 io.in[T_1322].ready <= UInt<1>("h00") reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") node T_1499 = gt(UInt<1>("h00"), last_grant) node T_1500 = and(io.in[0].valid, T_1499) node T_1502 = gt(UInt<1>("h01"), last_grant) node T_1503 = and(io.in[1].valid, T_1502) node T_1505 = gt(UInt<2>("h02"), last_grant) node T_1506 = and(io.in[2].valid, T_1505) node T_1508 = gt(UInt<2>("h03"), last_grant) node T_1509 = and(io.in[3].valid, T_1508) node T_1511 = gt(UInt<3>("h04"), last_grant) node T_1512 = and(io.in[4].valid, T_1511) node T_1514 = gt(UInt<3>("h05"), last_grant) node T_1515 = and(io.in[5].valid, T_1514) node T_1517 = gt(UInt<3>("h06"), last_grant) node T_1518 = and(io.in[6].valid, T_1517) node T_1520 = gt(UInt<3>("h07"), last_grant) node T_1521 = and(io.in[7].valid, T_1520) node T_1524 = or(UInt<1>("h00"), T_1500) node T_1526 = eq(T_1524, UInt<1>("h00")) node T_1528 = or(UInt<1>("h00"), T_1500) node T_1529 = or(T_1528, T_1503) node T_1531 = eq(T_1529, UInt<1>("h00")) node T_1533 = or(UInt<1>("h00"), T_1500) node T_1534 = or(T_1533, T_1503) node T_1535 = or(T_1534, T_1506) node T_1537 = eq(T_1535, UInt<1>("h00")) node T_1539 = or(UInt<1>("h00"), T_1500) node T_1540 = or(T_1539, T_1503) node T_1541 = or(T_1540, T_1506) node T_1542 = or(T_1541, T_1509) node T_1544 = eq(T_1542, UInt<1>("h00")) node T_1546 = or(UInt<1>("h00"), T_1500) node T_1547 = or(T_1546, T_1503) node T_1548 = or(T_1547, T_1506) node T_1549 = or(T_1548, T_1509) node T_1550 = or(T_1549, T_1512) node T_1552 = eq(T_1550, UInt<1>("h00")) node T_1554 = or(UInt<1>("h00"), T_1500) node T_1555 = or(T_1554, T_1503) node T_1556 = or(T_1555, T_1506) node T_1557 = or(T_1556, T_1509) node T_1558 = or(T_1557, T_1512) node T_1559 = or(T_1558, T_1515) node T_1561 = eq(T_1559, UInt<1>("h00")) node T_1563 = or(UInt<1>("h00"), T_1500) node T_1564 = or(T_1563, T_1503) node T_1565 = or(T_1564, T_1506) node T_1566 = or(T_1565, T_1509) node T_1567 = or(T_1566, T_1512) node T_1568 = or(T_1567, T_1515) node T_1569 = or(T_1568, T_1518) node T_1571 = eq(T_1569, UInt<1>("h00")) node T_1573 = or(UInt<1>("h00"), T_1500) node T_1574 = or(T_1573, T_1503) node T_1575 = or(T_1574, T_1506) node T_1576 = or(T_1575, T_1509) node T_1577 = or(T_1576, T_1512) node T_1578 = or(T_1577, T_1515) node T_1579 = or(T_1578, T_1518) node T_1580 = or(T_1579, T_1521) node T_1582 = eq(T_1580, UInt<1>("h00")) node T_1584 = or(UInt<1>("h00"), T_1500) node T_1585 = or(T_1584, T_1503) node T_1586 = or(T_1585, T_1506) node T_1587 = or(T_1586, T_1509) node T_1588 = or(T_1587, T_1512) node T_1589 = or(T_1588, T_1515) node T_1590 = or(T_1589, T_1518) node T_1591 = or(T_1590, T_1521) node T_1592 = or(T_1591, io.in[0].valid) node T_1594 = eq(T_1592, UInt<1>("h00")) node T_1596 = or(UInt<1>("h00"), T_1500) node T_1597 = or(T_1596, T_1503) node T_1598 = or(T_1597, T_1506) node T_1599 = or(T_1598, T_1509) node T_1600 = or(T_1599, T_1512) node T_1601 = or(T_1600, T_1515) node T_1602 = or(T_1601, T_1518) node T_1603 = or(T_1602, T_1521) node T_1604 = or(T_1603, io.in[0].valid) node T_1605 = or(T_1604, io.in[1].valid) node T_1607 = eq(T_1605, UInt<1>("h00")) node T_1609 = or(UInt<1>("h00"), T_1500) node T_1610 = or(T_1609, T_1503) node T_1611 = or(T_1610, T_1506) node T_1612 = or(T_1611, T_1509) node T_1613 = or(T_1612, T_1512) node T_1614 = or(T_1613, T_1515) node T_1615 = or(T_1614, T_1518) node T_1616 = or(T_1615, T_1521) node T_1617 = or(T_1616, io.in[0].valid) node T_1618 = or(T_1617, io.in[1].valid) node T_1619 = or(T_1618, io.in[2].valid) node T_1621 = eq(T_1619, UInt<1>("h00")) node T_1623 = or(UInt<1>("h00"), T_1500) node T_1624 = or(T_1623, T_1503) node T_1625 = or(T_1624, T_1506) node T_1626 = or(T_1625, T_1509) node T_1627 = or(T_1626, T_1512) node T_1628 = or(T_1627, T_1515) node T_1629 = or(T_1628, T_1518) node T_1630 = or(T_1629, T_1521) node T_1631 = or(T_1630, io.in[0].valid) node T_1632 = or(T_1631, io.in[1].valid) node T_1633 = or(T_1632, io.in[2].valid) node T_1634 = or(T_1633, io.in[3].valid) node T_1636 = eq(T_1634, UInt<1>("h00")) node T_1638 = or(UInt<1>("h00"), T_1500) node T_1639 = or(T_1638, T_1503) node T_1640 = or(T_1639, T_1506) node T_1641 = or(T_1640, T_1509) node T_1642 = or(T_1641, T_1512) node T_1643 = or(T_1642, T_1515) node T_1644 = or(T_1643, T_1518) node T_1645 = or(T_1644, T_1521) node T_1646 = or(T_1645, io.in[0].valid) node T_1647 = or(T_1646, io.in[1].valid) node T_1648 = or(T_1647, io.in[2].valid) node T_1649 = or(T_1648, io.in[3].valid) node T_1650 = or(T_1649, io.in[4].valid) node T_1652 = eq(T_1650, UInt<1>("h00")) node T_1654 = or(UInt<1>("h00"), T_1500) node T_1655 = or(T_1654, T_1503) node T_1656 = or(T_1655, T_1506) node T_1657 = or(T_1656, T_1509) node T_1658 = or(T_1657, T_1512) node T_1659 = or(T_1658, T_1515) node T_1660 = or(T_1659, T_1518) node T_1661 = or(T_1660, T_1521) node T_1662 = or(T_1661, io.in[0].valid) node T_1663 = or(T_1662, io.in[1].valid) node T_1664 = or(T_1663, io.in[2].valid) node T_1665 = or(T_1664, io.in[3].valid) node T_1666 = or(T_1665, io.in[4].valid) node T_1667 = or(T_1666, io.in[5].valid) node T_1669 = eq(T_1667, UInt<1>("h00")) node T_1671 = or(UInt<1>("h00"), T_1500) node T_1672 = or(T_1671, T_1503) node T_1673 = or(T_1672, T_1506) node T_1674 = or(T_1673, T_1509) node T_1675 = or(T_1674, T_1512) node T_1676 = or(T_1675, T_1515) node T_1677 = or(T_1676, T_1518) node T_1678 = or(T_1677, T_1521) node T_1679 = or(T_1678, io.in[0].valid) node T_1680 = or(T_1679, io.in[1].valid) node T_1681 = or(T_1680, io.in[2].valid) node T_1682 = or(T_1681, io.in[3].valid) node T_1683 = or(T_1682, io.in[4].valid) node T_1684 = or(T_1683, io.in[5].valid) node T_1685 = or(T_1684, io.in[6].valid) node T_1687 = eq(T_1685, UInt<1>("h00")) node T_1689 = gt(UInt<1>("h00"), last_grant) node T_1690 = and(UInt<1>("h01"), T_1689) node T_1691 = or(T_1690, T_1582) node T_1693 = gt(UInt<1>("h01"), last_grant) node T_1694 = and(T_1526, T_1693) node T_1695 = or(T_1694, T_1594) node T_1697 = gt(UInt<2>("h02"), last_grant) node T_1698 = and(T_1531, T_1697) node T_1699 = or(T_1698, T_1607) node T_1701 = gt(UInt<2>("h03"), last_grant) node T_1702 = and(T_1537, T_1701) node T_1703 = or(T_1702, T_1621) node T_1705 = gt(UInt<3>("h04"), last_grant) node T_1706 = and(T_1544, T_1705) node T_1707 = or(T_1706, T_1636) node T_1709 = gt(UInt<3>("h05"), last_grant) node T_1710 = and(T_1552, T_1709) node T_1711 = or(T_1710, T_1652) node T_1713 = gt(UInt<3>("h06"), last_grant) node T_1714 = and(T_1561, T_1713) node T_1715 = or(T_1714, T_1669) node T_1717 = gt(UInt<3>("h07"), last_grant) node T_1718 = and(T_1571, T_1717) node T_1719 = or(T_1718, T_1687) node T_1721 = eq(T_1320, UInt<1>("h00")) node T_1722 = mux(T_1318, T_1721, T_1691) node T_1723 = and(T_1722, io.out.ready) io.in[0].ready <= T_1723 node T_1725 = eq(T_1320, UInt<1>("h01")) node T_1726 = mux(T_1318, T_1725, T_1695) node T_1727 = and(T_1726, io.out.ready) io.in[1].ready <= T_1727 node T_1729 = eq(T_1320, UInt<2>("h02")) node T_1730 = mux(T_1318, T_1729, T_1699) node T_1731 = and(T_1730, io.out.ready) io.in[2].ready <= T_1731 node T_1733 = eq(T_1320, UInt<2>("h03")) node T_1734 = mux(T_1318, T_1733, T_1703) node T_1735 = and(T_1734, io.out.ready) io.in[3].ready <= T_1735 node T_1737 = eq(T_1320, UInt<3>("h04")) node T_1738 = mux(T_1318, T_1737, T_1707) node T_1739 = and(T_1738, io.out.ready) io.in[4].ready <= T_1739 node T_1741 = eq(T_1320, UInt<3>("h05")) node T_1742 = mux(T_1318, T_1741, T_1711) node T_1743 = and(T_1742, io.out.ready) io.in[5].ready <= T_1743 node T_1745 = eq(T_1320, UInt<3>("h06")) node T_1746 = mux(T_1318, T_1745, T_1715) node T_1747 = and(T_1746, io.out.ready) io.in[6].ready <= T_1747 node T_1749 = eq(T_1320, UInt<3>("h07")) node T_1750 = mux(T_1318, T_1749, T_1719) node T_1751 = and(T_1750, io.out.ready) io.in[7].ready <= T_1751 reg T_1753 : UInt<2>, clk, reset, UInt<2>("h00") node T_1755 = addw(T_1753, UInt<1>("h01")) node T_1756 = and(io.out.ready, io.out.valid) when T_1756 : when UInt<1>("h00") : T_1753 <= T_1755 node T_1759 = eq(T_1318, UInt<1>("h00")) when T_1759 : T_1318 <= UInt<1>("h01") node T_1761 = and(io.in[0].ready, io.in[0].valid) node T_1762 = and(io.in[1].ready, io.in[1].valid) node T_1763 = and(io.in[2].ready, io.in[2].valid) node T_1764 = and(io.in[3].ready, io.in[3].valid) node T_1765 = and(io.in[4].ready, io.in[4].valid) node T_1766 = and(io.in[5].ready, io.in[5].valid) node T_1767 = and(io.in[6].ready, io.in[6].valid) node T_1768 = and(io.in[7].ready, io.in[7].valid) wire T_1770 : UInt<1>[8] T_1770[0] <= T_1761 T_1770[1] <= T_1762 T_1770[2] <= T_1763 T_1770[3] <= T_1764 T_1770[4] <= T_1765 T_1770[5] <= T_1766 T_1770[6] <= T_1767 T_1770[7] <= T_1768 node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07")) node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788) node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789) node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790) node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791) node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792) node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793) T_1320 <= T_1794 skip skip node T_1796 = eq(T_1755, UInt<1>("h00")) when T_1796 : T_1318 <= UInt<1>("h00") skip skip node T_1800 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_1802 = mux(io.in[5].valid, UInt<3>("h05"), T_1800) node T_1804 = mux(io.in[4].valid, UInt<3>("h04"), T_1802) node T_1806 = mux(io.in[3].valid, UInt<2>("h03"), T_1804) node T_1808 = mux(io.in[2].valid, UInt<2>("h02"), T_1806) node T_1810 = mux(io.in[1].valid, UInt<1>("h01"), T_1808) node T_1812 = mux(io.in[0].valid, UInt<1>("h00"), T_1810) node T_1814 = gt(UInt<3>("h07"), last_grant) node T_1815 = and(io.in[7].valid, T_1814) node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812) node T_1819 = gt(UInt<3>("h06"), last_grant) node T_1820 = and(io.in[6].valid, T_1819) node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817) node T_1824 = gt(UInt<3>("h05"), last_grant) node T_1825 = and(io.in[5].valid, T_1824) node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822) node T_1829 = gt(UInt<3>("h04"), last_grant) node T_1830 = and(io.in[4].valid, T_1829) node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827) node T_1834 = gt(UInt<2>("h03"), last_grant) node T_1835 = and(io.in[3].valid, T_1834) node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832) node T_1839 = gt(UInt<2>("h02"), last_grant) node T_1840 = and(io.in[2].valid, T_1839) node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837) node T_1844 = gt(UInt<1>("h01"), last_grant) node T_1845 = and(io.in[1].valid, T_1844) node choose = mux(T_1845, UInt<1>("h01"), T_1842) node T_1848 = mux(T_1318, T_1320, choose) T_1322 <= T_1848 node T_1849 = and(io.out.ready, io.out.valid) when T_1849 : last_grant <= T_1322 skip module LockingRRArbiter_35 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, chosen : UInt<3>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.union <= UInt<1>("h00") io.out.bits.a_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") io.in[5].ready <= UInt<1>("h00") io.in[6].ready <= UInt<1>("h00") io.in[7].ready <= UInt<1>("h00") reg T_444 : UInt<1>, clk, reset, UInt<1>("h00") reg T_446 : UInt, clk, reset, UInt<3>("h07") wire T_448 : UInt<3> T_448 <= UInt<1>("h00") io.out.valid <= io.in[T_448].valid io.out.bits <- io.in[T_448].bits io.chosen <= T_448 io.in[T_448].ready <= UInt<1>("h00") reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") node T_511 = gt(UInt<1>("h00"), last_grant) node T_512 = and(io.in[0].valid, T_511) node T_514 = gt(UInt<1>("h01"), last_grant) node T_515 = and(io.in[1].valid, T_514) node T_517 = gt(UInt<2>("h02"), last_grant) node T_518 = and(io.in[2].valid, T_517) node T_520 = gt(UInt<2>("h03"), last_grant) node T_521 = and(io.in[3].valid, T_520) node T_523 = gt(UInt<3>("h04"), last_grant) node T_524 = and(io.in[4].valid, T_523) node T_526 = gt(UInt<3>("h05"), last_grant) node T_527 = and(io.in[5].valid, T_526) node T_529 = gt(UInt<3>("h06"), last_grant) node T_530 = and(io.in[6].valid, T_529) node T_532 = gt(UInt<3>("h07"), last_grant) node T_533 = and(io.in[7].valid, T_532) node T_536 = or(UInt<1>("h00"), T_512) node T_538 = eq(T_536, UInt<1>("h00")) node T_540 = or(UInt<1>("h00"), T_512) node T_541 = or(T_540, T_515) node T_543 = eq(T_541, UInt<1>("h00")) node T_545 = or(UInt<1>("h00"), T_512) node T_546 = or(T_545, T_515) node T_547 = or(T_546, T_518) node T_549 = eq(T_547, UInt<1>("h00")) node T_551 = or(UInt<1>("h00"), T_512) node T_552 = or(T_551, T_515) node T_553 = or(T_552, T_518) node T_554 = or(T_553, T_521) node T_556 = eq(T_554, UInt<1>("h00")) node T_558 = or(UInt<1>("h00"), T_512) node T_559 = or(T_558, T_515) node T_560 = or(T_559, T_518) node T_561 = or(T_560, T_521) node T_562 = or(T_561, T_524) node T_564 = eq(T_562, UInt<1>("h00")) node T_566 = or(UInt<1>("h00"), T_512) node T_567 = or(T_566, T_515) node T_568 = or(T_567, T_518) node T_569 = or(T_568, T_521) node T_570 = or(T_569, T_524) node T_571 = or(T_570, T_527) node T_573 = eq(T_571, UInt<1>("h00")) node T_575 = or(UInt<1>("h00"), T_512) node T_576 = or(T_575, T_515) node T_577 = or(T_576, T_518) node T_578 = or(T_577, T_521) node T_579 = or(T_578, T_524) node T_580 = or(T_579, T_527) node T_581 = or(T_580, T_530) node T_583 = eq(T_581, UInt<1>("h00")) node T_585 = or(UInt<1>("h00"), T_512) node T_586 = or(T_585, T_515) node T_587 = or(T_586, T_518) node T_588 = or(T_587, T_521) node T_589 = or(T_588, T_524) node T_590 = or(T_589, T_527) node T_591 = or(T_590, T_530) node T_592 = or(T_591, T_533) node T_594 = eq(T_592, UInt<1>("h00")) node T_596 = or(UInt<1>("h00"), T_512) node T_597 = or(T_596, T_515) node T_598 = or(T_597, T_518) node T_599 = or(T_598, T_521) node T_600 = or(T_599, T_524) node T_601 = or(T_600, T_527) node T_602 = or(T_601, T_530) node T_603 = or(T_602, T_533) node T_604 = or(T_603, io.in[0].valid) node T_606 = eq(T_604, UInt<1>("h00")) node T_608 = or(UInt<1>("h00"), T_512) node T_609 = or(T_608, T_515) node T_610 = or(T_609, T_518) node T_611 = or(T_610, T_521) node T_612 = or(T_611, T_524) node T_613 = or(T_612, T_527) node T_614 = or(T_613, T_530) node T_615 = or(T_614, T_533) node T_616 = or(T_615, io.in[0].valid) node T_617 = or(T_616, io.in[1].valid) node T_619 = eq(T_617, UInt<1>("h00")) node T_621 = or(UInt<1>("h00"), T_512) node T_622 = or(T_621, T_515) node T_623 = or(T_622, T_518) node T_624 = or(T_623, T_521) node T_625 = or(T_624, T_524) node T_626 = or(T_625, T_527) node T_627 = or(T_626, T_530) node T_628 = or(T_627, T_533) node T_629 = or(T_628, io.in[0].valid) node T_630 = or(T_629, io.in[1].valid) node T_631 = or(T_630, io.in[2].valid) node T_633 = eq(T_631, UInt<1>("h00")) node T_635 = or(UInt<1>("h00"), T_512) node T_636 = or(T_635, T_515) node T_637 = or(T_636, T_518) node T_638 = or(T_637, T_521) node T_639 = or(T_638, T_524) node T_640 = or(T_639, T_527) node T_641 = or(T_640, T_530) node T_642 = or(T_641, T_533) node T_643 = or(T_642, io.in[0].valid) node T_644 = or(T_643, io.in[1].valid) node T_645 = or(T_644, io.in[2].valid) node T_646 = or(T_645, io.in[3].valid) node T_648 = eq(T_646, UInt<1>("h00")) node T_650 = or(UInt<1>("h00"), T_512) node T_651 = or(T_650, T_515) node T_652 = or(T_651, T_518) node T_653 = or(T_652, T_521) node T_654 = or(T_653, T_524) node T_655 = or(T_654, T_527) node T_656 = or(T_655, T_530) node T_657 = or(T_656, T_533) node T_658 = or(T_657, io.in[0].valid) node T_659 = or(T_658, io.in[1].valid) node T_660 = or(T_659, io.in[2].valid) node T_661 = or(T_660, io.in[3].valid) node T_662 = or(T_661, io.in[4].valid) node T_664 = eq(T_662, UInt<1>("h00")) node T_666 = or(UInt<1>("h00"), T_512) node T_667 = or(T_666, T_515) node T_668 = or(T_667, T_518) node T_669 = or(T_668, T_521) node T_670 = or(T_669, T_524) node T_671 = or(T_670, T_527) node T_672 = or(T_671, T_530) node T_673 = or(T_672, T_533) node T_674 = or(T_673, io.in[0].valid) node T_675 = or(T_674, io.in[1].valid) node T_676 = or(T_675, io.in[2].valid) node T_677 = or(T_676, io.in[3].valid) node T_678 = or(T_677, io.in[4].valid) node T_679 = or(T_678, io.in[5].valid) node T_681 = eq(T_679, UInt<1>("h00")) node T_683 = or(UInt<1>("h00"), T_512) node T_684 = or(T_683, T_515) node T_685 = or(T_684, T_518) node T_686 = or(T_685, T_521) node T_687 = or(T_686, T_524) node T_688 = or(T_687, T_527) node T_689 = or(T_688, T_530) node T_690 = or(T_689, T_533) node T_691 = or(T_690, io.in[0].valid) node T_692 = or(T_691, io.in[1].valid) node T_693 = or(T_692, io.in[2].valid) node T_694 = or(T_693, io.in[3].valid) node T_695 = or(T_694, io.in[4].valid) node T_696 = or(T_695, io.in[5].valid) node T_697 = or(T_696, io.in[6].valid) node T_699 = eq(T_697, UInt<1>("h00")) node T_701 = gt(UInt<1>("h00"), last_grant) node T_702 = and(UInt<1>("h01"), T_701) node T_703 = or(T_702, T_594) node T_705 = gt(UInt<1>("h01"), last_grant) node T_706 = and(T_538, T_705) node T_707 = or(T_706, T_606) node T_709 = gt(UInt<2>("h02"), last_grant) node T_710 = and(T_543, T_709) node T_711 = or(T_710, T_619) node T_713 = gt(UInt<2>("h03"), last_grant) node T_714 = and(T_549, T_713) node T_715 = or(T_714, T_633) node T_717 = gt(UInt<3>("h04"), last_grant) node T_718 = and(T_556, T_717) node T_719 = or(T_718, T_648) node T_721 = gt(UInt<3>("h05"), last_grant) node T_722 = and(T_564, T_721) node T_723 = or(T_722, T_664) node T_725 = gt(UInt<3>("h06"), last_grant) node T_726 = and(T_573, T_725) node T_727 = or(T_726, T_681) node T_729 = gt(UInt<3>("h07"), last_grant) node T_730 = and(T_583, T_729) node T_731 = or(T_730, T_699) node T_733 = eq(T_446, UInt<1>("h00")) node T_734 = mux(T_444, T_733, T_703) node T_735 = and(T_734, io.out.ready) io.in[0].ready <= T_735 node T_737 = eq(T_446, UInt<1>("h01")) node T_738 = mux(T_444, T_737, T_707) node T_739 = and(T_738, io.out.ready) io.in[1].ready <= T_739 node T_741 = eq(T_446, UInt<2>("h02")) node T_742 = mux(T_444, T_741, T_711) node T_743 = and(T_742, io.out.ready) io.in[2].ready <= T_743 node T_745 = eq(T_446, UInt<2>("h03")) node T_746 = mux(T_444, T_745, T_715) node T_747 = and(T_746, io.out.ready) io.in[3].ready <= T_747 node T_749 = eq(T_446, UInt<3>("h04")) node T_750 = mux(T_444, T_749, T_719) node T_751 = and(T_750, io.out.ready) io.in[4].ready <= T_751 node T_753 = eq(T_446, UInt<3>("h05")) node T_754 = mux(T_444, T_753, T_723) node T_755 = and(T_754, io.out.ready) io.in[5].ready <= T_755 node T_757 = eq(T_446, UInt<3>("h06")) node T_758 = mux(T_444, T_757, T_727) node T_759 = and(T_758, io.out.ready) io.in[6].ready <= T_759 node T_761 = eq(T_446, UInt<3>("h07")) node T_762 = mux(T_444, T_761, T_731) node T_763 = and(T_762, io.out.ready) io.in[7].ready <= T_763 reg T_765 : UInt<2>, clk, reset, UInt<2>("h00") node T_767 = addw(T_765, UInt<1>("h01")) node T_768 = and(io.out.ready, io.out.valid) when T_768 : node T_770 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_773 : UInt<3>[1] T_773[0] <= UInt<3>("h03") node T_776 = eq(T_773[0], io.out.bits.a_type) node T_778 = or(UInt<1>("h00"), T_776) node T_779 = and(T_770, T_778) when T_779 : T_765 <= T_767 node T_781 = eq(T_444, UInt<1>("h00")) when T_781 : T_444 <= UInt<1>("h01") node T_783 = and(io.in[0].ready, io.in[0].valid) node T_784 = and(io.in[1].ready, io.in[1].valid) node T_785 = and(io.in[2].ready, io.in[2].valid) node T_786 = and(io.in[3].ready, io.in[3].valid) node T_787 = and(io.in[4].ready, io.in[4].valid) node T_788 = and(io.in[5].ready, io.in[5].valid) node T_789 = and(io.in[6].ready, io.in[6].valid) node T_790 = and(io.in[7].ready, io.in[7].valid) wire T_792 : UInt<1>[8] T_792[0] <= T_783 T_792[1] <= T_784 T_792[2] <= T_785 T_792[3] <= T_786 T_792[4] <= T_787 T_792[5] <= T_788 T_792[6] <= T_789 T_792[7] <= T_790 node T_810 = mux(T_792[6], UInt<3>("h06"), UInt<3>("h07")) node T_811 = mux(T_792[5], UInt<3>("h05"), T_810) node T_812 = mux(T_792[4], UInt<3>("h04"), T_811) node T_813 = mux(T_792[3], UInt<2>("h03"), T_812) node T_814 = mux(T_792[2], UInt<2>("h02"), T_813) node T_815 = mux(T_792[1], UInt<1>("h01"), T_814) node T_816 = mux(T_792[0], UInt<1>("h00"), T_815) T_446 <= T_816 skip skip node T_818 = eq(T_767, UInt<1>("h00")) when T_818 : T_444 <= UInt<1>("h00") skip skip node T_822 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07")) node T_824 = mux(io.in[5].valid, UInt<3>("h05"), T_822) node T_826 = mux(io.in[4].valid, UInt<3>("h04"), T_824) node T_828 = mux(io.in[3].valid, UInt<2>("h03"), T_826) node T_830 = mux(io.in[2].valid, UInt<2>("h02"), T_828) node T_832 = mux(io.in[1].valid, UInt<1>("h01"), T_830) node T_834 = mux(io.in[0].valid, UInt<1>("h00"), T_832) node T_836 = gt(UInt<3>("h07"), last_grant) node T_837 = and(io.in[7].valid, T_836) node T_839 = mux(T_837, UInt<3>("h07"), T_834) node T_841 = gt(UInt<3>("h06"), last_grant) node T_842 = and(io.in[6].valid, T_841) node T_844 = mux(T_842, UInt<3>("h06"), T_839) node T_846 = gt(UInt<3>("h05"), last_grant) node T_847 = and(io.in[5].valid, T_846) node T_849 = mux(T_847, UInt<3>("h05"), T_844) node T_851 = gt(UInt<3>("h04"), last_grant) node T_852 = and(io.in[4].valid, T_851) node T_854 = mux(T_852, UInt<3>("h04"), T_849) node T_856 = gt(UInt<2>("h03"), last_grant) node T_857 = and(io.in[3].valid, T_856) node T_859 = mux(T_857, UInt<2>("h03"), T_854) node T_861 = gt(UInt<2>("h02"), last_grant) node T_862 = and(io.in[2].valid, T_861) node T_864 = mux(T_862, UInt<2>("h02"), T_859) node T_866 = gt(UInt<1>("h01"), last_grant) node T_867 = and(io.in[1].valid, T_866) node choose = mux(T_867, UInt<1>("h01"), T_864) node T_870 = mux(T_444, T_446, choose) T_448 <= T_870 node T_871 = and(io.out.ready, io.out.valid) when T_871 : last_grant <= T_448 skip module ClientUncachedTileLinkIOArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}} io.out.grant.ready <= UInt<1>("h00") io.out.acquire.bits.data <= UInt<1>("h00") io.out.acquire.bits.union <= UInt<1>("h00") io.out.acquire.bits.a_type <= UInt<1>("h00") io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") io.out.acquire.bits.addr_beat <= UInt<1>("h00") io.out.acquire.bits.client_xact_id <= UInt<1>("h00") io.out.acquire.bits.addr_block <= UInt<1>("h00") io.out.acquire.valid <= UInt<1>("h00") io.in[0].grant.bits.data <= UInt<1>("h00") io.in[0].grant.bits.g_type <= UInt<1>("h00") io.in[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[0].grant.bits.client_xact_id <= UInt<1>("h00") io.in[0].grant.bits.addr_beat <= UInt<1>("h00") io.in[0].grant.valid <= UInt<1>("h00") io.in[0].acquire.ready <= UInt<1>("h00") io.in[1].grant.bits.data <= UInt<1>("h00") io.in[1].grant.bits.g_type <= UInt<1>("h00") io.in[1].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[1].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[1].grant.bits.client_xact_id <= UInt<1>("h00") io.in[1].grant.bits.addr_beat <= UInt<1>("h00") io.in[1].grant.valid <= UInt<1>("h00") io.in[1].acquire.ready <= UInt<1>("h00") io.in[2].grant.bits.data <= UInt<1>("h00") io.in[2].grant.bits.g_type <= UInt<1>("h00") io.in[2].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[2].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[2].grant.bits.client_xact_id <= UInt<1>("h00") io.in[2].grant.bits.addr_beat <= UInt<1>("h00") io.in[2].grant.valid <= UInt<1>("h00") io.in[2].acquire.ready <= UInt<1>("h00") io.in[3].grant.bits.data <= UInt<1>("h00") io.in[3].grant.bits.g_type <= UInt<1>("h00") io.in[3].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[3].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[3].grant.bits.client_xact_id <= UInt<1>("h00") io.in[3].grant.bits.addr_beat <= UInt<1>("h00") io.in[3].grant.valid <= UInt<1>("h00") io.in[3].acquire.ready <= UInt<1>("h00") io.in[4].grant.bits.data <= UInt<1>("h00") io.in[4].grant.bits.g_type <= UInt<1>("h00") io.in[4].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[4].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[4].grant.bits.client_xact_id <= UInt<1>("h00") io.in[4].grant.bits.addr_beat <= UInt<1>("h00") io.in[4].grant.valid <= UInt<1>("h00") io.in[4].acquire.ready <= UInt<1>("h00") io.in[5].grant.bits.data <= UInt<1>("h00") io.in[5].grant.bits.g_type <= UInt<1>("h00") io.in[5].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[5].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[5].grant.bits.client_xact_id <= UInt<1>("h00") io.in[5].grant.bits.addr_beat <= UInt<1>("h00") io.in[5].grant.valid <= UInt<1>("h00") io.in[5].acquire.ready <= UInt<1>("h00") io.in[6].grant.bits.data <= UInt<1>("h00") io.in[6].grant.bits.g_type <= UInt<1>("h00") io.in[6].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[6].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[6].grant.bits.client_xact_id <= UInt<1>("h00") io.in[6].grant.bits.addr_beat <= UInt<1>("h00") io.in[6].grant.valid <= UInt<1>("h00") io.in[6].acquire.ready <= UInt<1>("h00") io.in[7].grant.bits.data <= UInt<1>("h00") io.in[7].grant.bits.g_type <= UInt<1>("h00") io.in[7].grant.bits.is_builtin_type <= UInt<1>("h00") io.in[7].grant.bits.manager_xact_id <= UInt<1>("h00") io.in[7].grant.bits.client_xact_id <= UInt<1>("h00") io.in[7].grant.bits.addr_beat <= UInt<1>("h00") io.in[7].grant.valid <= UInt<1>("h00") io.in[7].acquire.ready <= UInt<1>("h00") inst T_1593 of LockingRRArbiter_35 T_1593.io.out.ready <= UInt<1>("h00") T_1593.io.in[0].bits.data <= UInt<1>("h00") T_1593.io.in[0].bits.union <= UInt<1>("h00") T_1593.io.in[0].bits.a_type <= UInt<1>("h00") T_1593.io.in[0].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[0].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[0].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[0].bits.addr_block <= UInt<1>("h00") T_1593.io.in[0].valid <= UInt<1>("h00") T_1593.io.in[1].bits.data <= UInt<1>("h00") T_1593.io.in[1].bits.union <= UInt<1>("h00") T_1593.io.in[1].bits.a_type <= UInt<1>("h00") T_1593.io.in[1].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[1].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[1].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[1].bits.addr_block <= UInt<1>("h00") T_1593.io.in[1].valid <= UInt<1>("h00") T_1593.io.in[2].bits.data <= UInt<1>("h00") T_1593.io.in[2].bits.union <= UInt<1>("h00") T_1593.io.in[2].bits.a_type <= UInt<1>("h00") T_1593.io.in[2].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[2].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[2].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[2].bits.addr_block <= UInt<1>("h00") T_1593.io.in[2].valid <= UInt<1>("h00") T_1593.io.in[3].bits.data <= UInt<1>("h00") T_1593.io.in[3].bits.union <= UInt<1>("h00") T_1593.io.in[3].bits.a_type <= UInt<1>("h00") T_1593.io.in[3].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[3].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[3].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[3].bits.addr_block <= UInt<1>("h00") T_1593.io.in[3].valid <= UInt<1>("h00") T_1593.io.in[4].bits.data <= UInt<1>("h00") T_1593.io.in[4].bits.union <= UInt<1>("h00") T_1593.io.in[4].bits.a_type <= UInt<1>("h00") T_1593.io.in[4].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[4].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[4].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[4].bits.addr_block <= UInt<1>("h00") T_1593.io.in[4].valid <= UInt<1>("h00") T_1593.io.in[5].bits.data <= UInt<1>("h00") T_1593.io.in[5].bits.union <= UInt<1>("h00") T_1593.io.in[5].bits.a_type <= UInt<1>("h00") T_1593.io.in[5].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[5].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[5].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[5].bits.addr_block <= UInt<1>("h00") T_1593.io.in[5].valid <= UInt<1>("h00") T_1593.io.in[6].bits.data <= UInt<1>("h00") T_1593.io.in[6].bits.union <= UInt<1>("h00") T_1593.io.in[6].bits.a_type <= UInt<1>("h00") T_1593.io.in[6].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[6].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[6].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[6].bits.addr_block <= UInt<1>("h00") T_1593.io.in[6].valid <= UInt<1>("h00") T_1593.io.in[7].bits.data <= UInt<1>("h00") T_1593.io.in[7].bits.union <= UInt<1>("h00") T_1593.io.in[7].bits.a_type <= UInt<1>("h00") T_1593.io.in[7].bits.is_builtin_type <= UInt<1>("h00") T_1593.io.in[7].bits.addr_beat <= UInt<1>("h00") T_1593.io.in[7].bits.client_xact_id <= UInt<1>("h00") T_1593.io.in[7].bits.addr_block <= UInt<1>("h00") T_1593.io.in[7].valid <= UInt<1>("h00") T_1593.clk <= clk T_1593.reset <= reset T_1593.io.in[0].valid <= io.in[0].acquire.valid T_1593.io.in[0].bits <- io.in[0].acquire.bits node T_1660 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) T_1593.io.in[0].bits.client_xact_id <= T_1660 io.in[0].acquire.ready <= T_1593.io.in[0].ready T_1593.io.in[1].valid <= io.in[1].acquire.valid T_1593.io.in[1].bits <- io.in[1].acquire.bits node T_1662 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) T_1593.io.in[1].bits.client_xact_id <= T_1662 io.in[1].acquire.ready <= T_1593.io.in[1].ready T_1593.io.in[2].valid <= io.in[2].acquire.valid T_1593.io.in[2].bits <- io.in[2].acquire.bits node T_1664 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) T_1593.io.in[2].bits.client_xact_id <= T_1664 io.in[2].acquire.ready <= T_1593.io.in[2].ready T_1593.io.in[3].valid <= io.in[3].acquire.valid T_1593.io.in[3].bits <- io.in[3].acquire.bits node T_1666 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) T_1593.io.in[3].bits.client_xact_id <= T_1666 io.in[3].acquire.ready <= T_1593.io.in[3].ready T_1593.io.in[4].valid <= io.in[4].acquire.valid T_1593.io.in[4].bits <- io.in[4].acquire.bits node T_1668 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) T_1593.io.in[4].bits.client_xact_id <= T_1668 io.in[4].acquire.ready <= T_1593.io.in[4].ready T_1593.io.in[5].valid <= io.in[5].acquire.valid T_1593.io.in[5].bits <- io.in[5].acquire.bits node T_1670 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) T_1593.io.in[5].bits.client_xact_id <= T_1670 io.in[5].acquire.ready <= T_1593.io.in[5].ready T_1593.io.in[6].valid <= io.in[6].acquire.valid T_1593.io.in[6].bits <- io.in[6].acquire.bits node T_1672 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) T_1593.io.in[6].bits.client_xact_id <= T_1672 io.in[6].acquire.ready <= T_1593.io.in[6].ready T_1593.io.in[7].valid <= io.in[7].acquire.valid T_1593.io.in[7].bits <- io.in[7].acquire.bits node T_1674 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) T_1593.io.in[7].bits.client_xact_id <= T_1674 io.in[7].acquire.ready <= T_1593.io.in[7].ready io.out.acquire <- T_1593.io.out io.out.grant.ready <= UInt<1>("h00") io.in[0].grant.valid <= UInt<1>("h00") node T_1677 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1679 = eq(T_1677, UInt<1>("h00")) when T_1679 : io.in[0].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[0].grant.ready skip io.in[0].grant.bits <- io.out.grant.bits node T_1680 = shr(io.out.grant.bits.client_xact_id, 3) io.in[0].grant.bits.client_xact_id <= T_1680 io.in[1].grant.valid <= UInt<1>("h00") node T_1682 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1684 = eq(T_1682, UInt<1>("h01")) when T_1684 : io.in[1].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[1].grant.ready skip io.in[1].grant.bits <- io.out.grant.bits node T_1685 = shr(io.out.grant.bits.client_xact_id, 3) io.in[1].grant.bits.client_xact_id <= T_1685 io.in[2].grant.valid <= UInt<1>("h00") node T_1687 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1689 = eq(T_1687, UInt<2>("h02")) when T_1689 : io.in[2].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[2].grant.ready skip io.in[2].grant.bits <- io.out.grant.bits node T_1690 = shr(io.out.grant.bits.client_xact_id, 3) io.in[2].grant.bits.client_xact_id <= T_1690 io.in[3].grant.valid <= UInt<1>("h00") node T_1692 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1694 = eq(T_1692, UInt<2>("h03")) when T_1694 : io.in[3].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[3].grant.ready skip io.in[3].grant.bits <- io.out.grant.bits node T_1695 = shr(io.out.grant.bits.client_xact_id, 3) io.in[3].grant.bits.client_xact_id <= T_1695 io.in[4].grant.valid <= UInt<1>("h00") node T_1697 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1699 = eq(T_1697, UInt<3>("h04")) when T_1699 : io.in[4].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[4].grant.ready skip io.in[4].grant.bits <- io.out.grant.bits node T_1700 = shr(io.out.grant.bits.client_xact_id, 3) io.in[4].grant.bits.client_xact_id <= T_1700 io.in[5].grant.valid <= UInt<1>("h00") node T_1702 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1704 = eq(T_1702, UInt<3>("h05")) when T_1704 : io.in[5].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[5].grant.ready skip io.in[5].grant.bits <- io.out.grant.bits node T_1705 = shr(io.out.grant.bits.client_xact_id, 3) io.in[5].grant.bits.client_xact_id <= T_1705 io.in[6].grant.valid <= UInt<1>("h00") node T_1707 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1709 = eq(T_1707, UInt<3>("h06")) when T_1709 : io.in[6].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[6].grant.ready skip io.in[6].grant.bits <- io.out.grant.bits node T_1710 = shr(io.out.grant.bits.client_xact_id, 3) io.in[6].grant.bits.client_xact_id <= T_1710 io.in[7].grant.valid <= UInt<1>("h00") node T_1712 = bits(io.out.grant.bits.client_xact_id, 2, 0) node T_1714 = eq(T_1712, UInt<3>("h07")) when T_1714 : io.in[7].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[7].grant.ready skip io.in[7].grant.bits <- io.out.grant.bits node T_1715 = shr(io.out.grant.bits.client_xact_id, 3) io.in[7].grant.bits.client_xact_id <= T_1715 module L2BroadcastHub : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.client_id <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") io.inner.grant.bits.client_id <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") inst T_1060 of BroadcastVoluntaryReleaseTracker T_1060.io.outer.grant.bits.data <= UInt<1>("h00") T_1060.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1060.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1060.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1060.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1060.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1060.io.outer.grant.valid <= UInt<1>("h00") T_1060.io.outer.acquire.ready <= UInt<1>("h00") T_1060.io.incoherent[0] <= UInt<1>("h00") T_1060.io.inner.release.bits.client_id <= UInt<1>("h00") T_1060.io.inner.release.bits.data <= UInt<1>("h00") T_1060.io.inner.release.bits.r_type <= UInt<1>("h00") T_1060.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1060.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1060.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1060.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1060.io.inner.release.valid <= UInt<1>("h00") T_1060.io.inner.probe.ready <= UInt<1>("h00") T_1060.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1060.io.inner.finish.valid <= UInt<1>("h00") T_1060.io.inner.grant.ready <= UInt<1>("h00") T_1060.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1060.io.inner.acquire.bits.data <= UInt<1>("h00") T_1060.io.inner.acquire.bits.union <= UInt<1>("h00") T_1060.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1060.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1060.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1060.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1060.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1060.io.inner.acquire.valid <= UInt<1>("h00") T_1060.clk <= clk T_1060.reset <= reset inst T_1091 of BroadcastAcquireTracker T_1091.io.outer.grant.bits.data <= UInt<1>("h00") T_1091.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1091.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1091.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1091.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1091.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1091.io.outer.grant.valid <= UInt<1>("h00") T_1091.io.outer.acquire.ready <= UInt<1>("h00") T_1091.io.incoherent[0] <= UInt<1>("h00") T_1091.io.inner.release.bits.client_id <= UInt<1>("h00") T_1091.io.inner.release.bits.data <= UInt<1>("h00") T_1091.io.inner.release.bits.r_type <= UInt<1>("h00") T_1091.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1091.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1091.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1091.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1091.io.inner.release.valid <= UInt<1>("h00") T_1091.io.inner.probe.ready <= UInt<1>("h00") T_1091.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1091.io.inner.finish.valid <= UInt<1>("h00") T_1091.io.inner.grant.ready <= UInt<1>("h00") T_1091.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1091.io.inner.acquire.bits.data <= UInt<1>("h00") T_1091.io.inner.acquire.bits.union <= UInt<1>("h00") T_1091.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1091.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1091.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1091.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1091.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1091.io.inner.acquire.valid <= UInt<1>("h00") T_1091.clk <= clk T_1091.reset <= reset inst T_1122 of BroadcastAcquireTracker_27 T_1122.io.outer.grant.bits.data <= UInt<1>("h00") T_1122.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1122.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1122.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1122.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1122.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1122.io.outer.grant.valid <= UInt<1>("h00") T_1122.io.outer.acquire.ready <= UInt<1>("h00") T_1122.io.incoherent[0] <= UInt<1>("h00") T_1122.io.inner.release.bits.client_id <= UInt<1>("h00") T_1122.io.inner.release.bits.data <= UInt<1>("h00") T_1122.io.inner.release.bits.r_type <= UInt<1>("h00") T_1122.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1122.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1122.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1122.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1122.io.inner.release.valid <= UInt<1>("h00") T_1122.io.inner.probe.ready <= UInt<1>("h00") T_1122.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1122.io.inner.finish.valid <= UInt<1>("h00") T_1122.io.inner.grant.ready <= UInt<1>("h00") T_1122.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1122.io.inner.acquire.bits.data <= UInt<1>("h00") T_1122.io.inner.acquire.bits.union <= UInt<1>("h00") T_1122.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1122.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1122.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1122.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1122.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1122.io.inner.acquire.valid <= UInt<1>("h00") T_1122.clk <= clk T_1122.reset <= reset inst T_1153 of BroadcastAcquireTracker_28 T_1153.io.outer.grant.bits.data <= UInt<1>("h00") T_1153.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1153.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1153.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1153.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1153.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1153.io.outer.grant.valid <= UInt<1>("h00") T_1153.io.outer.acquire.ready <= UInt<1>("h00") T_1153.io.incoherent[0] <= UInt<1>("h00") T_1153.io.inner.release.bits.client_id <= UInt<1>("h00") T_1153.io.inner.release.bits.data <= UInt<1>("h00") T_1153.io.inner.release.bits.r_type <= UInt<1>("h00") T_1153.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1153.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1153.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1153.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1153.io.inner.release.valid <= UInt<1>("h00") T_1153.io.inner.probe.ready <= UInt<1>("h00") T_1153.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1153.io.inner.finish.valid <= UInt<1>("h00") T_1153.io.inner.grant.ready <= UInt<1>("h00") T_1153.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1153.io.inner.acquire.bits.data <= UInt<1>("h00") T_1153.io.inner.acquire.bits.union <= UInt<1>("h00") T_1153.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1153.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1153.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1153.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1153.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1153.io.inner.acquire.valid <= UInt<1>("h00") T_1153.clk <= clk T_1153.reset <= reset inst T_1184 of BroadcastAcquireTracker_29 T_1184.io.outer.grant.bits.data <= UInt<1>("h00") T_1184.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1184.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1184.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1184.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1184.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1184.io.outer.grant.valid <= UInt<1>("h00") T_1184.io.outer.acquire.ready <= UInt<1>("h00") T_1184.io.incoherent[0] <= UInt<1>("h00") T_1184.io.inner.release.bits.client_id <= UInt<1>("h00") T_1184.io.inner.release.bits.data <= UInt<1>("h00") T_1184.io.inner.release.bits.r_type <= UInt<1>("h00") T_1184.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1184.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1184.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1184.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1184.io.inner.release.valid <= UInt<1>("h00") T_1184.io.inner.probe.ready <= UInt<1>("h00") T_1184.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1184.io.inner.finish.valid <= UInt<1>("h00") T_1184.io.inner.grant.ready <= UInt<1>("h00") T_1184.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1184.io.inner.acquire.bits.data <= UInt<1>("h00") T_1184.io.inner.acquire.bits.union <= UInt<1>("h00") T_1184.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1184.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1184.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1184.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1184.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1184.io.inner.acquire.valid <= UInt<1>("h00") T_1184.clk <= clk T_1184.reset <= reset inst T_1215 of BroadcastAcquireTracker_30 T_1215.io.outer.grant.bits.data <= UInt<1>("h00") T_1215.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1215.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1215.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1215.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1215.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1215.io.outer.grant.valid <= UInt<1>("h00") T_1215.io.outer.acquire.ready <= UInt<1>("h00") T_1215.io.incoherent[0] <= UInt<1>("h00") T_1215.io.inner.release.bits.client_id <= UInt<1>("h00") T_1215.io.inner.release.bits.data <= UInt<1>("h00") T_1215.io.inner.release.bits.r_type <= UInt<1>("h00") T_1215.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1215.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1215.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1215.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1215.io.inner.release.valid <= UInt<1>("h00") T_1215.io.inner.probe.ready <= UInt<1>("h00") T_1215.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1215.io.inner.finish.valid <= UInt<1>("h00") T_1215.io.inner.grant.ready <= UInt<1>("h00") T_1215.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1215.io.inner.acquire.bits.data <= UInt<1>("h00") T_1215.io.inner.acquire.bits.union <= UInt<1>("h00") T_1215.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1215.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1215.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1215.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1215.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1215.io.inner.acquire.valid <= UInt<1>("h00") T_1215.clk <= clk T_1215.reset <= reset inst T_1246 of BroadcastAcquireTracker_31 T_1246.io.outer.grant.bits.data <= UInt<1>("h00") T_1246.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1246.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1246.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1246.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1246.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1246.io.outer.grant.valid <= UInt<1>("h00") T_1246.io.outer.acquire.ready <= UInt<1>("h00") T_1246.io.incoherent[0] <= UInt<1>("h00") T_1246.io.inner.release.bits.client_id <= UInt<1>("h00") T_1246.io.inner.release.bits.data <= UInt<1>("h00") T_1246.io.inner.release.bits.r_type <= UInt<1>("h00") T_1246.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1246.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1246.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1246.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1246.io.inner.release.valid <= UInt<1>("h00") T_1246.io.inner.probe.ready <= UInt<1>("h00") T_1246.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1246.io.inner.finish.valid <= UInt<1>("h00") T_1246.io.inner.grant.ready <= UInt<1>("h00") T_1246.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1246.io.inner.acquire.bits.data <= UInt<1>("h00") T_1246.io.inner.acquire.bits.union <= UInt<1>("h00") T_1246.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1246.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1246.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1246.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1246.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1246.io.inner.acquire.valid <= UInt<1>("h00") T_1246.clk <= clk T_1246.reset <= reset inst T_1277 of BroadcastAcquireTracker_32 T_1277.io.outer.grant.bits.data <= UInt<1>("h00") T_1277.io.outer.grant.bits.g_type <= UInt<1>("h00") T_1277.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_1277.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_1277.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_1277.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_1277.io.outer.grant.valid <= UInt<1>("h00") T_1277.io.outer.acquire.ready <= UInt<1>("h00") T_1277.io.incoherent[0] <= UInt<1>("h00") T_1277.io.inner.release.bits.client_id <= UInt<1>("h00") T_1277.io.inner.release.bits.data <= UInt<1>("h00") T_1277.io.inner.release.bits.r_type <= UInt<1>("h00") T_1277.io.inner.release.bits.voluntary <= UInt<1>("h00") T_1277.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_1277.io.inner.release.bits.addr_block <= UInt<1>("h00") T_1277.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_1277.io.inner.release.valid <= UInt<1>("h00") T_1277.io.inner.probe.ready <= UInt<1>("h00") T_1277.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_1277.io.inner.finish.valid <= UInt<1>("h00") T_1277.io.inner.grant.ready <= UInt<1>("h00") T_1277.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_1277.io.inner.acquire.bits.data <= UInt<1>("h00") T_1277.io.inner.acquire.bits.union <= UInt<1>("h00") T_1277.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_1277.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_1277.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_1277.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_1277.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_1277.io.inner.acquire.valid <= UInt<1>("h00") T_1277.clk <= clk T_1277.reset <= reset T_1060.io.incoherent <= io.incoherent T_1091.io.incoherent <= io.incoherent T_1122.io.incoherent <= io.incoherent T_1153.io.incoherent <= io.incoherent T_1184.io.incoherent <= io.incoherent T_1215.io.incoherent <= io.incoherent T_1246.io.incoherent <= io.incoherent T_1277.io.incoherent <= io.incoherent reg sdq : UInt<128>[4], clk, UInt<1>("h00"), sdq reg sdq_val : UInt<4>, clk, reset, UInt<4>("h00") node T_1325 = not(sdq_val) node T_1326 = bit(T_1325, 0) node T_1327 = bit(T_1325, 1) node T_1328 = bit(T_1325, 2) node T_1329 = bit(T_1325, 3) wire T_1331 : UInt<1>[4] T_1331[0] <= T_1326 T_1331[1] <= T_1327 T_1331[2] <= T_1328 T_1331[3] <= T_1329 node T_1341 = mux(T_1331[2], UInt<2>("h02"), UInt<2>("h03")) node T_1342 = mux(T_1331[1], UInt<1>("h01"), T_1341) node sdq_alloc_id = mux(T_1331[0], UInt<1>("h00"), T_1342) node T_1344 = not(sdq_val) node T_1346 = eq(T_1344, UInt<1>("h00")) node sdq_rdy = eq(T_1346, UInt<1>("h00")) node T_1349 = and(io.inner.acquire.ready, io.inner.acquire.valid) wire T_1354 : UInt<3>[3] T_1354[0] <= UInt<3>("h02") T_1354[1] <= UInt<3>("h03") T_1354[2] <= UInt<3>("h04") node T_1359 = eq(T_1354[0], io.inner.acquire.bits.a_type) node T_1360 = eq(T_1354[1], io.inner.acquire.bits.a_type) node T_1361 = eq(T_1354[2], io.inner.acquire.bits.a_type) node T_1363 = or(UInt<1>("h00"), T_1359) node T_1364 = or(T_1363, T_1360) node T_1365 = or(T_1364, T_1361) node T_1366 = and(io.inner.acquire.bits.is_builtin_type, T_1365) node sdq_enq = and(T_1349, T_1366) when sdq_enq : sdq[sdq_alloc_id] <= io.inner.acquire.bits.data skip wire T_1370 : UInt<1>[8] T_1370[0] <= T_1060.io.has_acquire_conflict T_1370[1] <= T_1091.io.has_acquire_conflict T_1370[2] <= T_1122.io.has_acquire_conflict T_1370[3] <= T_1153.io.has_acquire_conflict T_1370[4] <= T_1184.io.has_acquire_conflict T_1370[5] <= T_1215.io.has_acquire_conflict T_1370[6] <= T_1246.io.has_acquire_conflict T_1370[7] <= T_1277.io.has_acquire_conflict node T_1380 = cat(T_1370[7], T_1370[6]) node T_1381 = cat(T_1370[5], T_1370[4]) node T_1382 = cat(T_1380, T_1381) node T_1383 = cat(T_1370[3], T_1370[2]) node T_1384 = cat(T_1370[1], T_1370[0]) node T_1385 = cat(T_1383, T_1384) node acquireConflicts = cat(T_1382, T_1385) wire T_1388 : UInt<1>[8] T_1388[0] <= T_1060.io.has_acquire_match T_1388[1] <= T_1091.io.has_acquire_match T_1388[2] <= T_1122.io.has_acquire_match T_1388[3] <= T_1153.io.has_acquire_match T_1388[4] <= T_1184.io.has_acquire_match T_1388[5] <= T_1215.io.has_acquire_match T_1388[6] <= T_1246.io.has_acquire_match T_1388[7] <= T_1277.io.has_acquire_match node T_1398 = cat(T_1388[7], T_1388[6]) node T_1399 = cat(T_1388[5], T_1388[4]) node T_1400 = cat(T_1398, T_1399) node T_1401 = cat(T_1388[3], T_1388[2]) node T_1402 = cat(T_1388[1], T_1388[0]) node T_1403 = cat(T_1401, T_1402) node acquireMatches = cat(T_1400, T_1403) wire T_1406 : UInt<1>[8] T_1406[0] <= T_1060.io.inner.acquire.ready T_1406[1] <= T_1091.io.inner.acquire.ready T_1406[2] <= T_1122.io.inner.acquire.ready T_1406[3] <= T_1153.io.inner.acquire.ready T_1406[4] <= T_1184.io.inner.acquire.ready T_1406[5] <= T_1215.io.inner.acquire.ready T_1406[6] <= T_1246.io.inner.acquire.ready T_1406[7] <= T_1277.io.inner.acquire.ready node T_1416 = cat(T_1406[7], T_1406[6]) node T_1417 = cat(T_1406[5], T_1406[4]) node T_1418 = cat(T_1416, T_1417) node T_1419 = cat(T_1406[3], T_1406[2]) node T_1420 = cat(T_1406[1], T_1406[0]) node T_1421 = cat(T_1419, T_1420) node acquireReadys = cat(T_1418, T_1421) node T_1424 = neq(acquireMatches, UInt<1>("h00")) node T_1425 = bit(acquireMatches, 0) node T_1426 = bit(acquireMatches, 1) node T_1427 = bit(acquireMatches, 2) node T_1428 = bit(acquireMatches, 3) node T_1429 = bit(acquireMatches, 4) node T_1430 = bit(acquireMatches, 5) node T_1431 = bit(acquireMatches, 6) node T_1432 = bit(acquireMatches, 7) wire T_1434 : UInt<1>[8] T_1434[0] <= T_1425 T_1434[1] <= T_1426 T_1434[2] <= T_1427 T_1434[3] <= T_1428 T_1434[4] <= T_1429 T_1434[5] <= T_1430 T_1434[6] <= T_1431 T_1434[7] <= T_1432 node T_1452 = mux(T_1434[6], UInt<3>("h06"), UInt<3>("h07")) node T_1453 = mux(T_1434[5], UInt<3>("h05"), T_1452) node T_1454 = mux(T_1434[4], UInt<3>("h04"), T_1453) node T_1455 = mux(T_1434[3], UInt<2>("h03"), T_1454) node T_1456 = mux(T_1434[2], UInt<2>("h02"), T_1455) node T_1457 = mux(T_1434[1], UInt<1>("h01"), T_1456) node T_1458 = mux(T_1434[0], UInt<1>("h00"), T_1457) node T_1459 = bit(acquireReadys, 0) node T_1460 = bit(acquireReadys, 1) node T_1461 = bit(acquireReadys, 2) node T_1462 = bit(acquireReadys, 3) node T_1463 = bit(acquireReadys, 4) node T_1464 = bit(acquireReadys, 5) node T_1465 = bit(acquireReadys, 6) node T_1466 = bit(acquireReadys, 7) wire T_1468 : UInt<1>[8] T_1468[0] <= T_1459 T_1468[1] <= T_1460 T_1468[2] <= T_1461 T_1468[3] <= T_1462 T_1468[4] <= T_1463 T_1468[5] <= T_1464 T_1468[6] <= T_1465 T_1468[7] <= T_1466 node T_1486 = mux(T_1468[6], UInt<3>("h06"), UInt<3>("h07")) node T_1487 = mux(T_1468[5], UInt<3>("h05"), T_1486) node T_1488 = mux(T_1468[4], UInt<3>("h04"), T_1487) node T_1489 = mux(T_1468[3], UInt<2>("h03"), T_1488) node T_1490 = mux(T_1468[2], UInt<2>("h02"), T_1489) node T_1491 = mux(T_1468[1], UInt<1>("h01"), T_1490) node T_1492 = mux(T_1468[0], UInt<1>("h00"), T_1491) node acquire_idx = mux(T_1424, T_1458, T_1492) node T_1495 = neq(acquireConflicts, UInt<1>("h00")) node T_1497 = eq(sdq_rdy, UInt<1>("h00")) node block_acquires = or(T_1495, T_1497) node T_1500 = neq(acquireReadys, UInt<1>("h00")) node T_1502 = eq(block_acquires, UInt<1>("h00")) node T_1503 = and(T_1500, T_1502) io.inner.acquire.ready <= T_1503 T_1060.io.inner.acquire.bits <- io.inner.acquire.bits wire T_1550 : {idx : UInt<2>, loc : UInt<2>} T_1550.loc <= UInt<1>("h00") T_1550.idx <= UInt<1>("h00") T_1550.idx <= sdq_alloc_id T_1550.loc <= UInt<1>("h00") node T_1598 = cat(T_1550.idx, T_1550.loc) T_1060.io.inner.acquire.bits.data <= T_1598 node T_1600 = eq(block_acquires, UInt<1>("h00")) node T_1601 = and(io.inner.acquire.valid, T_1600) node T_1603 = eq(acquire_idx, UInt<1>("h00")) node T_1604 = and(T_1601, T_1603) T_1060.io.inner.acquire.valid <= T_1604 T_1091.io.inner.acquire.bits <- io.inner.acquire.bits wire T_1651 : {idx : UInt<2>, loc : UInt<2>} T_1651.loc <= UInt<1>("h00") T_1651.idx <= UInt<1>("h00") T_1651.idx <= sdq_alloc_id T_1651.loc <= UInt<1>("h00") node T_1699 = cat(T_1651.idx, T_1651.loc) T_1091.io.inner.acquire.bits.data <= T_1699 node T_1701 = eq(block_acquires, UInt<1>("h00")) node T_1702 = and(io.inner.acquire.valid, T_1701) node T_1704 = eq(acquire_idx, UInt<1>("h01")) node T_1705 = and(T_1702, T_1704) T_1091.io.inner.acquire.valid <= T_1705 T_1122.io.inner.acquire.bits <- io.inner.acquire.bits wire T_1752 : {idx : UInt<2>, loc : UInt<2>} T_1752.loc <= UInt<1>("h00") T_1752.idx <= UInt<1>("h00") T_1752.idx <= sdq_alloc_id T_1752.loc <= UInt<1>("h00") node T_1800 = cat(T_1752.idx, T_1752.loc) T_1122.io.inner.acquire.bits.data <= T_1800 node T_1802 = eq(block_acquires, UInt<1>("h00")) node T_1803 = and(io.inner.acquire.valid, T_1802) node T_1805 = eq(acquire_idx, UInt<2>("h02")) node T_1806 = and(T_1803, T_1805) T_1122.io.inner.acquire.valid <= T_1806 T_1153.io.inner.acquire.bits <- io.inner.acquire.bits wire T_1853 : {idx : UInt<2>, loc : UInt<2>} T_1853.loc <= UInt<1>("h00") T_1853.idx <= UInt<1>("h00") T_1853.idx <= sdq_alloc_id T_1853.loc <= UInt<1>("h00") node T_1901 = cat(T_1853.idx, T_1853.loc) T_1153.io.inner.acquire.bits.data <= T_1901 node T_1903 = eq(block_acquires, UInt<1>("h00")) node T_1904 = and(io.inner.acquire.valid, T_1903) node T_1906 = eq(acquire_idx, UInt<2>("h03")) node T_1907 = and(T_1904, T_1906) T_1153.io.inner.acquire.valid <= T_1907 T_1184.io.inner.acquire.bits <- io.inner.acquire.bits wire T_1954 : {idx : UInt<2>, loc : UInt<2>} T_1954.loc <= UInt<1>("h00") T_1954.idx <= UInt<1>("h00") T_1954.idx <= sdq_alloc_id T_1954.loc <= UInt<1>("h00") node T_2002 = cat(T_1954.idx, T_1954.loc) T_1184.io.inner.acquire.bits.data <= T_2002 node T_2004 = eq(block_acquires, UInt<1>("h00")) node T_2005 = and(io.inner.acquire.valid, T_2004) node T_2007 = eq(acquire_idx, UInt<3>("h04")) node T_2008 = and(T_2005, T_2007) T_1184.io.inner.acquire.valid <= T_2008 T_1215.io.inner.acquire.bits <- io.inner.acquire.bits wire T_2055 : {idx : UInt<2>, loc : UInt<2>} T_2055.loc <= UInt<1>("h00") T_2055.idx <= UInt<1>("h00") T_2055.idx <= sdq_alloc_id T_2055.loc <= UInt<1>("h00") node T_2103 = cat(T_2055.idx, T_2055.loc) T_1215.io.inner.acquire.bits.data <= T_2103 node T_2105 = eq(block_acquires, UInt<1>("h00")) node T_2106 = and(io.inner.acquire.valid, T_2105) node T_2108 = eq(acquire_idx, UInt<3>("h05")) node T_2109 = and(T_2106, T_2108) T_1215.io.inner.acquire.valid <= T_2109 T_1246.io.inner.acquire.bits <- io.inner.acquire.bits wire T_2156 : {idx : UInt<2>, loc : UInt<2>} T_2156.loc <= UInt<1>("h00") T_2156.idx <= UInt<1>("h00") T_2156.idx <= sdq_alloc_id T_2156.loc <= UInt<1>("h00") node T_2204 = cat(T_2156.idx, T_2156.loc) T_1246.io.inner.acquire.bits.data <= T_2204 node T_2206 = eq(block_acquires, UInt<1>("h00")) node T_2207 = and(io.inner.acquire.valid, T_2206) node T_2209 = eq(acquire_idx, UInt<3>("h06")) node T_2210 = and(T_2207, T_2209) T_1246.io.inner.acquire.valid <= T_2210 T_1277.io.inner.acquire.bits <- io.inner.acquire.bits wire T_2257 : {idx : UInt<2>, loc : UInt<2>} T_2257.loc <= UInt<1>("h00") T_2257.idx <= UInt<1>("h00") T_2257.idx <= sdq_alloc_id T_2257.loc <= UInt<1>("h00") node T_2305 = cat(T_2257.idx, T_2257.loc) T_1277.io.inner.acquire.bits.data <= T_2305 node T_2307 = eq(block_acquires, UInt<1>("h00")) node T_2308 = and(io.inner.acquire.valid, T_2307) node T_2310 = eq(acquire_idx, UInt<3>("h07")) node T_2311 = and(T_2308, T_2310) T_1277.io.inner.acquire.valid <= T_2311 node T_2312 = and(io.inner.release.ready, io.inner.release.valid) node T_2313 = and(T_2312, io.inner.release.bits.voluntary) wire T_2315 : UInt<2>[3] T_2315[0] <= UInt<1>("h00") T_2315[1] <= UInt<1>("h01") T_2315[2] <= UInt<2>("h02") node T_2320 = eq(T_2315[0], io.inner.release.bits.r_type) node T_2321 = eq(T_2315[1], io.inner.release.bits.r_type) node T_2322 = eq(T_2315[2], io.inner.release.bits.r_type) node T_2324 = or(UInt<1>("h00"), T_2320) node T_2325 = or(T_2324, T_2321) node T_2326 = or(T_2325, T_2322) node vwbdq_enq = and(T_2313, T_2326) reg rel_data_cnt : UInt<2>, clk, reset, UInt<2>("h00") when vwbdq_enq : node T_2331 = eq(rel_data_cnt, UInt<2>("h03")) node T_2333 = and(UInt<1>("h00"), T_2331) node T_2336 = addw(rel_data_cnt, UInt<1>("h01")) node T_2337 = mux(T_2333, UInt<1>("h00"), T_2336) rel_data_cnt <= T_2337 skip node rel_data_done = and(vwbdq_enq, T_2331) reg vwbdq : UInt<128>[4], clk, UInt<1>("h00"), vwbdq when vwbdq_enq : vwbdq[rel_data_cnt] <= io.inner.release.bits.data skip wire T_2356 : UInt<1>[8] T_2356[0] <= T_1060.io.inner.release.ready T_2356[1] <= T_1091.io.inner.release.ready T_2356[2] <= T_1122.io.inner.release.ready T_2356[3] <= T_1153.io.inner.release.ready T_2356[4] <= T_1184.io.inner.release.ready T_2356[5] <= T_1215.io.inner.release.ready T_2356[6] <= T_1246.io.inner.release.ready T_2356[7] <= T_1277.io.inner.release.ready node T_2366 = cat(T_2356[7], T_2356[6]) node T_2367 = cat(T_2356[5], T_2356[4]) node T_2368 = cat(T_2366, T_2367) node T_2369 = cat(T_2356[3], T_2356[2]) node T_2370 = cat(T_2356[1], T_2356[0]) node T_2371 = cat(T_2369, T_2370) node releaseReadys = cat(T_2368, T_2371) wire T_2374 : UInt<1>[8] T_2374[0] <= T_1060.io.has_release_match T_2374[1] <= T_1091.io.has_release_match T_2374[2] <= T_1122.io.has_release_match T_2374[3] <= T_1153.io.has_release_match T_2374[4] <= T_1184.io.has_release_match T_2374[5] <= T_1215.io.has_release_match T_2374[6] <= T_1246.io.has_release_match T_2374[7] <= T_1277.io.has_release_match node T_2384 = cat(T_2374[7], T_2374[6]) node T_2385 = cat(T_2374[5], T_2374[4]) node T_2386 = cat(T_2384, T_2385) node T_2387 = cat(T_2374[3], T_2374[2]) node T_2388 = cat(T_2374[1], T_2374[0]) node T_2389 = cat(T_2387, T_2388) node releaseMatches = cat(T_2386, T_2389) node T_2391 = bit(releaseMatches, 0) node T_2392 = bit(releaseMatches, 1) node T_2393 = bit(releaseMatches, 2) node T_2394 = bit(releaseMatches, 3) node T_2395 = bit(releaseMatches, 4) node T_2396 = bit(releaseMatches, 5) node T_2397 = bit(releaseMatches, 6) node T_2398 = bit(releaseMatches, 7) wire T_2400 : UInt<1>[8] T_2400[0] <= T_2391 T_2400[1] <= T_2392 T_2400[2] <= T_2393 T_2400[3] <= T_2394 T_2400[4] <= T_2395 T_2400[5] <= T_2396 T_2400[6] <= T_2397 T_2400[7] <= T_2398 node T_2418 = mux(T_2400[6], UInt<3>("h06"), UInt<3>("h07")) node T_2419 = mux(T_2400[5], UInt<3>("h05"), T_2418) node T_2420 = mux(T_2400[4], UInt<3>("h04"), T_2419) node T_2421 = mux(T_2400[3], UInt<2>("h03"), T_2420) node T_2422 = mux(T_2400[2], UInt<2>("h02"), T_2421) node T_2423 = mux(T_2400[1], UInt<1>("h01"), T_2422) node release_idx = mux(T_2400[0], UInt<1>("h00"), T_2423) node T_2425 = dshr(releaseReadys, release_idx) node T_2426 = bit(T_2425, 0) io.inner.release.ready <= T_2426 node T_2428 = eq(release_idx, UInt<1>("h00")) node T_2429 = and(io.inner.release.valid, T_2428) T_1060.io.inner.release.valid <= T_2429 T_1060.io.inner.release.bits <- io.inner.release.bits wire T_2476 : {idx : UInt<2>, loc : UInt<2>} T_2476.loc <= UInt<1>("h00") T_2476.idx <= UInt<1>("h00") T_2476.idx <= rel_data_cnt T_2476.loc <= UInt<1>("h01") node T_2524 = cat(T_2476.idx, T_2476.loc) T_1060.io.inner.release.bits.data <= T_2524 node T_2526 = eq(release_idx, UInt<1>("h01")) node T_2527 = and(io.inner.release.valid, T_2526) T_1091.io.inner.release.valid <= T_2527 T_1091.io.inner.release.bits <- io.inner.release.bits wire T_2574 : {idx : UInt<2>, loc : UInt<2>} T_2574.loc <= UInt<1>("h00") T_2574.idx <= UInt<1>("h00") T_2574.idx <= rel_data_cnt T_2574.loc <= UInt<2>("h02") node T_2622 = cat(T_2574.idx, T_2574.loc) T_1091.io.inner.release.bits.data <= T_2622 node T_2624 = eq(release_idx, UInt<2>("h02")) node T_2625 = and(io.inner.release.valid, T_2624) T_1122.io.inner.release.valid <= T_2625 T_1122.io.inner.release.bits <- io.inner.release.bits wire T_2672 : {idx : UInt<2>, loc : UInt<2>} T_2672.loc <= UInt<1>("h00") T_2672.idx <= UInt<1>("h00") T_2672.idx <= rel_data_cnt T_2672.loc <= UInt<2>("h02") node T_2720 = cat(T_2672.idx, T_2672.loc) T_1122.io.inner.release.bits.data <= T_2720 node T_2722 = eq(release_idx, UInt<2>("h03")) node T_2723 = and(io.inner.release.valid, T_2722) T_1153.io.inner.release.valid <= T_2723 T_1153.io.inner.release.bits <- io.inner.release.bits wire T_2770 : {idx : UInt<2>, loc : UInt<2>} T_2770.loc <= UInt<1>("h00") T_2770.idx <= UInt<1>("h00") T_2770.idx <= rel_data_cnt T_2770.loc <= UInt<2>("h02") node T_2818 = cat(T_2770.idx, T_2770.loc) T_1153.io.inner.release.bits.data <= T_2818 node T_2820 = eq(release_idx, UInt<3>("h04")) node T_2821 = and(io.inner.release.valid, T_2820) T_1184.io.inner.release.valid <= T_2821 T_1184.io.inner.release.bits <- io.inner.release.bits wire T_2868 : {idx : UInt<2>, loc : UInt<2>} T_2868.loc <= UInt<1>("h00") T_2868.idx <= UInt<1>("h00") T_2868.idx <= rel_data_cnt T_2868.loc <= UInt<2>("h02") node T_2916 = cat(T_2868.idx, T_2868.loc) T_1184.io.inner.release.bits.data <= T_2916 node T_2918 = eq(release_idx, UInt<3>("h05")) node T_2919 = and(io.inner.release.valid, T_2918) T_1215.io.inner.release.valid <= T_2919 T_1215.io.inner.release.bits <- io.inner.release.bits wire T_2966 : {idx : UInt<2>, loc : UInt<2>} T_2966.loc <= UInt<1>("h00") T_2966.idx <= UInt<1>("h00") T_2966.idx <= rel_data_cnt T_2966.loc <= UInt<2>("h02") node T_3014 = cat(T_2966.idx, T_2966.loc) T_1215.io.inner.release.bits.data <= T_3014 node T_3016 = eq(release_idx, UInt<3>("h06")) node T_3017 = and(io.inner.release.valid, T_3016) T_1246.io.inner.release.valid <= T_3017 T_1246.io.inner.release.bits <- io.inner.release.bits wire T_3064 : {idx : UInt<2>, loc : UInt<2>} T_3064.loc <= UInt<1>("h00") T_3064.idx <= UInt<1>("h00") T_3064.idx <= rel_data_cnt T_3064.loc <= UInt<2>("h02") node T_3112 = cat(T_3064.idx, T_3064.loc) T_1246.io.inner.release.bits.data <= T_3112 node T_3114 = eq(release_idx, UInt<3>("h07")) node T_3115 = and(io.inner.release.valid, T_3114) T_1277.io.inner.release.valid <= T_3115 T_1277.io.inner.release.bits <- io.inner.release.bits wire T_3162 : {idx : UInt<2>, loc : UInt<2>} T_3162.loc <= UInt<1>("h00") T_3162.idx <= UInt<1>("h00") T_3162.idx <= rel_data_cnt T_3162.loc <= UInt<2>("h02") node T_3210 = cat(T_3162.idx, T_3162.loc) T_1277.io.inner.release.bits.data <= T_3210 node T_3212 = neq(releaseMatches, UInt<1>("h00")) node T_3214 = eq(T_3212, UInt<1>("h00")) node T_3215 = and(io.inner.release.valid, T_3214) node T_3217 = eq(T_3215, UInt<1>("h00")) node T_3219 = eq(reset, UInt<1>("h00")) when T_3219 : node T_3221 = eq(T_3217, UInt<1>("h00")) when T_3221 : node T_3223 = eq(reset, UInt<1>("h00")) when T_3223 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.") skip stop(clk, UInt<1>(1), 1) skip skip inst T_3224 of LockingRRArbiter_33 T_3224.io.out.ready <= UInt<1>("h00") T_3224.io.in[0].bits.client_id <= UInt<1>("h00") T_3224.io.in[0].bits.data <= UInt<1>("h00") T_3224.io.in[0].bits.g_type <= UInt<1>("h00") T_3224.io.in[0].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[0].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[0].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[0].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[0].valid <= UInt<1>("h00") T_3224.io.in[1].bits.client_id <= UInt<1>("h00") T_3224.io.in[1].bits.data <= UInt<1>("h00") T_3224.io.in[1].bits.g_type <= UInt<1>("h00") T_3224.io.in[1].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[1].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[1].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[1].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[1].valid <= UInt<1>("h00") T_3224.io.in[2].bits.client_id <= UInt<1>("h00") T_3224.io.in[2].bits.data <= UInt<1>("h00") T_3224.io.in[2].bits.g_type <= UInt<1>("h00") T_3224.io.in[2].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[2].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[2].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[2].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[2].valid <= UInt<1>("h00") T_3224.io.in[3].bits.client_id <= UInt<1>("h00") T_3224.io.in[3].bits.data <= UInt<1>("h00") T_3224.io.in[3].bits.g_type <= UInt<1>("h00") T_3224.io.in[3].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[3].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[3].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[3].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[3].valid <= UInt<1>("h00") T_3224.io.in[4].bits.client_id <= UInt<1>("h00") T_3224.io.in[4].bits.data <= UInt<1>("h00") T_3224.io.in[4].bits.g_type <= UInt<1>("h00") T_3224.io.in[4].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[4].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[4].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[4].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[4].valid <= UInt<1>("h00") T_3224.io.in[5].bits.client_id <= UInt<1>("h00") T_3224.io.in[5].bits.data <= UInt<1>("h00") T_3224.io.in[5].bits.g_type <= UInt<1>("h00") T_3224.io.in[5].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[5].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[5].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[5].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[5].valid <= UInt<1>("h00") T_3224.io.in[6].bits.client_id <= UInt<1>("h00") T_3224.io.in[6].bits.data <= UInt<1>("h00") T_3224.io.in[6].bits.g_type <= UInt<1>("h00") T_3224.io.in[6].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[6].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[6].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[6].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[6].valid <= UInt<1>("h00") T_3224.io.in[7].bits.client_id <= UInt<1>("h00") T_3224.io.in[7].bits.data <= UInt<1>("h00") T_3224.io.in[7].bits.g_type <= UInt<1>("h00") T_3224.io.in[7].bits.is_builtin_type <= UInt<1>("h00") T_3224.io.in[7].bits.manager_xact_id <= UInt<1>("h00") T_3224.io.in[7].bits.client_xact_id <= UInt<1>("h00") T_3224.io.in[7].bits.addr_beat <= UInt<1>("h00") T_3224.io.in[7].valid <= UInt<1>("h00") T_3224.clk <= clk T_3224.reset <= reset io.inner.grant <- T_3224.io.out T_3224.io.in[0] <- T_1060.io.inner.grant T_3224.io.in[1] <- T_1091.io.inner.grant T_3224.io.in[2] <- T_1122.io.inner.grant T_3224.io.in[3] <- T_1153.io.inner.grant T_3224.io.in[4] <- T_1184.io.inner.grant T_3224.io.in[5] <- T_1215.io.inner.grant T_3224.io.in[6] <- T_1246.io.inner.grant T_3224.io.in[7] <- T_1277.io.inner.grant io.inner.grant.bits.data <= io.outer.grant.bits.data io.inner.grant.bits.addr_beat <= io.outer.grant.bits.addr_beat inst T_3290 of LockingRRArbiter_34 T_3290.io.out.ready <= UInt<1>("h00") T_3290.io.in[0].bits.client_id <= UInt<1>("h00") T_3290.io.in[0].bits.p_type <= UInt<1>("h00") T_3290.io.in[0].bits.addr_block <= UInt<1>("h00") T_3290.io.in[0].valid <= UInt<1>("h00") T_3290.io.in[1].bits.client_id <= UInt<1>("h00") T_3290.io.in[1].bits.p_type <= UInt<1>("h00") T_3290.io.in[1].bits.addr_block <= UInt<1>("h00") T_3290.io.in[1].valid <= UInt<1>("h00") T_3290.io.in[2].bits.client_id <= UInt<1>("h00") T_3290.io.in[2].bits.p_type <= UInt<1>("h00") T_3290.io.in[2].bits.addr_block <= UInt<1>("h00") T_3290.io.in[2].valid <= UInt<1>("h00") T_3290.io.in[3].bits.client_id <= UInt<1>("h00") T_3290.io.in[3].bits.p_type <= UInt<1>("h00") T_3290.io.in[3].bits.addr_block <= UInt<1>("h00") T_3290.io.in[3].valid <= UInt<1>("h00") T_3290.io.in[4].bits.client_id <= UInt<1>("h00") T_3290.io.in[4].bits.p_type <= UInt<1>("h00") T_3290.io.in[4].bits.addr_block <= UInt<1>("h00") T_3290.io.in[4].valid <= UInt<1>("h00") T_3290.io.in[5].bits.client_id <= UInt<1>("h00") T_3290.io.in[5].bits.p_type <= UInt<1>("h00") T_3290.io.in[5].bits.addr_block <= UInt<1>("h00") T_3290.io.in[5].valid <= UInt<1>("h00") T_3290.io.in[6].bits.client_id <= UInt<1>("h00") T_3290.io.in[6].bits.p_type <= UInt<1>("h00") T_3290.io.in[6].bits.addr_block <= UInt<1>("h00") T_3290.io.in[6].valid <= UInt<1>("h00") T_3290.io.in[7].bits.client_id <= UInt<1>("h00") T_3290.io.in[7].bits.p_type <= UInt<1>("h00") T_3290.io.in[7].bits.addr_block <= UInt<1>("h00") T_3290.io.in[7].valid <= UInt<1>("h00") T_3290.clk <= clk T_3290.reset <= reset io.inner.probe <- T_3290.io.out T_3290.io.in[0] <- T_1060.io.inner.probe T_3290.io.in[1] <- T_1091.io.inner.probe T_3290.io.in[2] <- T_1122.io.inner.probe T_3290.io.in[3] <- T_1153.io.inner.probe T_3290.io.in[4] <- T_1184.io.inner.probe T_3290.io.in[5] <- T_1215.io.inner.probe T_3290.io.in[6] <- T_1246.io.inner.probe T_3290.io.in[7] <- T_1277.io.inner.probe T_1060.io.inner.finish.bits <- io.inner.finish.bits T_1091.io.inner.finish.bits <- io.inner.finish.bits T_1122.io.inner.finish.bits <- io.inner.finish.bits T_1153.io.inner.finish.bits <- io.inner.finish.bits T_1184.io.inner.finish.bits <- io.inner.finish.bits T_1215.io.inner.finish.bits <- io.inner.finish.bits T_1246.io.inner.finish.bits <- io.inner.finish.bits T_1277.io.inner.finish.bits <- io.inner.finish.bits node T_3325 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) node T_3326 = and(io.inner.finish.valid, T_3325) T_1060.io.inner.finish.valid <= T_3326 node T_3328 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) node T_3329 = and(io.inner.finish.valid, T_3328) T_1091.io.inner.finish.valid <= T_3329 node T_3331 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) node T_3332 = and(io.inner.finish.valid, T_3331) T_1122.io.inner.finish.valid <= T_3332 node T_3334 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) node T_3335 = and(io.inner.finish.valid, T_3334) T_1153.io.inner.finish.valid <= T_3335 node T_3337 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) node T_3338 = and(io.inner.finish.valid, T_3337) T_1184.io.inner.finish.valid <= T_3338 node T_3340 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) node T_3341 = and(io.inner.finish.valid, T_3340) T_1215.io.inner.finish.valid <= T_3341 node T_3343 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) node T_3344 = and(io.inner.finish.valid, T_3343) T_1246.io.inner.finish.valid <= T_3344 node T_3346 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) node T_3347 = and(io.inner.finish.valid, T_3346) T_1277.io.inner.finish.valid <= T_3347 wire T_3349 : UInt<1>[8] T_3349[0] <= T_1060.io.inner.finish.ready T_3349[1] <= T_1091.io.inner.finish.ready T_3349[2] <= T_1122.io.inner.finish.ready T_3349[3] <= T_1153.io.inner.finish.ready T_3349[4] <= T_1184.io.inner.finish.ready T_3349[5] <= T_1215.io.inner.finish.ready T_3349[6] <= T_1246.io.inner.finish.ready T_3349[7] <= T_1277.io.inner.finish.ready io.inner.finish.ready <= T_3349[io.inner.finish.bits.manager_xact_id] inst outer_arb of ClientUncachedTileLinkIOArbiter outer_arb.io.out.grant.bits.data <= UInt<1>("h00") outer_arb.io.out.grant.bits.g_type <= UInt<1>("h00") outer_arb.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") outer_arb.io.out.grant.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.out.grant.bits.addr_beat <= UInt<1>("h00") outer_arb.io.out.grant.valid <= UInt<1>("h00") outer_arb.io.out.acquire.ready <= UInt<1>("h00") outer_arb.io.in[0].grant.ready <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[0].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[0].acquire.valid <= UInt<1>("h00") outer_arb.io.in[1].grant.ready <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[1].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[1].acquire.valid <= UInt<1>("h00") outer_arb.io.in[2].grant.ready <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[2].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[2].acquire.valid <= UInt<1>("h00") outer_arb.io.in[3].grant.ready <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[3].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[3].acquire.valid <= UInt<1>("h00") outer_arb.io.in[4].grant.ready <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[4].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[4].acquire.valid <= UInt<1>("h00") outer_arb.io.in[5].grant.ready <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[5].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[5].acquire.valid <= UInt<1>("h00") outer_arb.io.in[6].grant.ready <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[6].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[6].acquire.valid <= UInt<1>("h00") outer_arb.io.in[7].grant.ready <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.data <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.union <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.a_type <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.is_builtin_type <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.addr_beat <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.client_xact_id <= UInt<1>("h00") outer_arb.io.in[7].acquire.bits.addr_block <= UInt<1>("h00") outer_arb.io.in[7].acquire.valid <= UInt<1>("h00") outer_arb.clk <= clk outer_arb.reset <= reset outer_arb.io.in[0] <- T_1060.io.outer outer_arb.io.in[1] <- T_1091.io.outer outer_arb.io.in[2] <- T_1122.io.outer outer_arb.io.in[3] <- T_1153.io.outer outer_arb.io.in[4] <- T_1184.io.outer outer_arb.io.in[5] <- T_1215.io.outer outer_arb.io.in[6] <- T_1246.io.outer outer_arb.io.in[7] <- T_1277.io.outer wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} outer_data_ptr.loc <= UInt<1>("h00") outer_data_ptr.idx <= UInt<1>("h00") node T_3581 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) outer_data_ptr.loc <= T_3581 node T_3582 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) outer_data_ptr.idx <= T_3582 node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) node T_3584 = and(io.outer.acquire.ready, io.outer.acquire.valid) wire T_3589 : UInt<3>[3] T_3589[0] <= UInt<3>("h02") T_3589[1] <= UInt<3>("h03") T_3589[2] <= UInt<3>("h04") node T_3594 = eq(T_3589[0], io.outer.acquire.bits.a_type) node T_3595 = eq(T_3589[1], io.outer.acquire.bits.a_type) node T_3596 = eq(T_3589[2], io.outer.acquire.bits.a_type) node T_3598 = or(UInt<1>("h00"), T_3594) node T_3599 = or(T_3598, T_3595) node T_3600 = or(T_3599, T_3596) node T_3601 = and(io.outer.acquire.bits.is_builtin_type, T_3600) node T_3602 = and(T_3584, T_3601) node T_3603 = eq(outer_data_ptr.loc, UInt<1>("h00")) node free_sdq = and(T_3602, T_3603) io.outer <- outer_arb.io.out node T_3607 = eq(UInt<1>("h01"), outer_data_ptr.loc) node T_3608 = mux(T_3607, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data) node T_3609 = eq(UInt<1>("h00"), outer_data_ptr.loc) node T_3610 = mux(T_3609, sdq[outer_data_ptr.idx], T_3608) io.outer.acquire.bits.data <= T_3610 node T_3611 = or(io.outer.acquire.valid, sdq_enq) when T_3611 : node T_3613 = dshl(UInt<1>("h01"), outer_data_ptr.idx) node T_3615 = subw(UInt<4>("h00"), free_sdq) node T_3616 = and(T_3613, T_3615) node T_3617 = not(T_3616) node T_3618 = and(sdq_val, T_3617) node T_3619 = bits(sdq_val, 3, 0) node T_3620 = not(T_3619) node T_3621 = bit(T_3620, 0) node T_3622 = bit(T_3620, 1) node T_3623 = bit(T_3620, 2) node T_3624 = bit(T_3620, 3) wire T_3630 : UInt<4>[4] T_3630[0] <= UInt<4>("h01") T_3630[1] <= UInt<4>("h02") T_3630[2] <= UInt<4>("h04") T_3630[3] <= UInt<4>("h08") node T_3638 = mux(T_3624, T_3630[3], UInt<4>("h00")) node T_3639 = mux(T_3623, T_3630[2], T_3638) node T_3640 = mux(T_3622, T_3630[1], T_3639) node T_3641 = mux(T_3621, T_3630[0], T_3640) node T_3643 = subw(UInt<4>("h00"), sdq_enq) node T_3644 = and(T_3641, T_3643) node T_3645 = or(T_3618, T_3644) sdq_val <= T_3645 skip module Queue_36 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.user <= UInt<1>("h00") io.deq.bits.id <= UInt<1>("h00") io.deq.bits.region <= UInt<1>("h00") io.deq.bits.qos <= UInt<1>("h00") io.deq.bits.prot <= UInt<1>("h00") io.deq.bits.cache <= UInt<1>("h00") io.deq.bits.lock <= UInt<1>("h00") io.deq.bits.burst <= UInt<1>("h00") io.deq.bits.size <= UInt<1>("h00") io.deq.bits.len <= UInt<1>("h00") io.deq.bits.addr <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[2] reg T_125 : UInt<1>, clk, reset, UInt<1>("h00") reg T_127 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_125, T_127) node T_132 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_132) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_138 = and(io.enq.ready, io.enq.valid) node T_140 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_138, T_140) node T_142 = and(io.deq.ready, io.deq.valid) node T_144 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_142, T_144) when do_enq : infer mport T_146 = ram[T_125], clk T_146 <- io.enq.bits node T_159 = eq(T_125, UInt<1>("h01")) node T_161 = and(UInt<1>("h00"), T_159) node T_164 = addw(T_125, UInt<1>("h01")) node T_165 = mux(T_161, UInt<1>("h00"), T_164) T_125 <= T_165 skip when do_deq : node T_167 = eq(T_127, UInt<1>("h01")) node T_169 = and(UInt<1>("h00"), T_167) node T_172 = addw(T_127, UInt<1>("h01")) node T_173 = mux(T_169, UInt<1>("h00"), T_172) T_127 <= T_173 skip node T_174 = neq(do_enq, do_deq) when T_174 : maybe_full <= do_enq skip node T_176 = eq(empty, UInt<1>("h00")) node T_178 = and(UInt<1>("h00"), io.enq.valid) node T_179 = or(T_176, T_178) io.deq.valid <= T_179 node T_181 = eq(full, UInt<1>("h00")) node T_183 = and(UInt<1>("h00"), io.deq.ready) node T_184 = or(T_181, T_183) io.enq.ready <= T_184 infer mport T_185 = ram[T_127], clk wire T_209 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} T_209 <- T_185 when maybe_flow : T_209 <- io.enq.bits skip io.deq.bits <- T_209 node ptr_diff = subw(T_125, T_127) node T_222 = and(maybe_full, ptr_match) node T_223 = cat(T_222, ptr_diff) io.count <= T_223 module Queue_37 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : UInt<5>[2] reg T_26 : UInt<1>, clk, reset, UInt<1>("h00") reg T_28 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_39 = and(io.enq.ready, io.enq.valid) node T_41 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_39, T_41) node T_43 = and(io.deq.ready, io.deq.valid) node T_45 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_43, T_45) when do_enq : infer mport T_47 = ram[T_26], clk T_47 <= io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) node T_54 = addw(T_26, UInt<1>("h01")) node T_55 = mux(T_51, UInt<1>("h00"), T_54) T_26 <= T_55 skip when do_deq : node T_57 = eq(T_28, UInt<1>("h01")) node T_59 = and(UInt<1>("h00"), T_57) node T_62 = addw(T_28, UInt<1>("h01")) node T_63 = mux(T_59, UInt<1>("h00"), T_62) T_28 <= T_63 skip node T_64 = neq(do_enq, do_deq) when T_64 : maybe_full <= do_enq skip node T_66 = eq(empty, UInt<1>("h00")) node T_68 = and(UInt<1>("h00"), io.enq.valid) node T_69 = or(T_66, T_68) io.deq.valid <= T_69 node T_71 = eq(full, UInt<1>("h00")) node T_73 = and(UInt<1>("h00"), io.deq.ready) node T_74 = or(T_71, T_73) io.enq.ready <= T_74 infer mport T_75 = ram[T_28], clk node T_76 = mux(maybe_flow, io.enq.bits, T_75) io.deq.bits <= T_76 node ptr_diff = subw(T_26, T_28) node T_78 = and(maybe_full, ptr_match) node T_79 = cat(T_78, ptr_diff) io.count <= T_79 module NastiErrorSlave : input clk : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.r.bits.user <= UInt<1>("h00") io.r.bits.id <= UInt<1>("h00") io.r.bits.last <= UInt<1>("h00") io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<1>("h00") io.r.valid <= UInt<1>("h00") io.ar.ready <= UInt<1>("h00") io.b.bits.user <= UInt<1>("h00") io.b.bits.id <= UInt<1>("h00") io.b.bits.resp <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.aw.ready <= UInt<1>("h00") node T_322 = and(io.ar.ready, io.ar.valid) when T_322 : node T_324 = eq(reset, UInt<1>("h00")) when T_324 : printf(clk, UInt<1>(1), "Invalid read address %x ", io.ar.bits.addr) skip skip node T_325 = and(io.aw.ready, io.aw.valid) when T_325 : node T_327 = eq(reset, UInt<1>("h00")) when T_327 : printf(clk, UInt<1>(1), "Invalid write address %x ", io.aw.bits.addr) skip skip inst r_queue of Queue_36 r_queue.io.deq.ready <= UInt<1>("h00") r_queue.io.enq.bits.user <= UInt<1>("h00") r_queue.io.enq.bits.id <= UInt<1>("h00") r_queue.io.enq.bits.region <= UInt<1>("h00") r_queue.io.enq.bits.qos <= UInt<1>("h00") r_queue.io.enq.bits.prot <= UInt<1>("h00") r_queue.io.enq.bits.cache <= UInt<1>("h00") r_queue.io.enq.bits.lock <= UInt<1>("h00") r_queue.io.enq.bits.burst <= UInt<1>("h00") r_queue.io.enq.bits.size <= UInt<1>("h00") r_queue.io.enq.bits.len <= UInt<1>("h00") r_queue.io.enq.bits.addr <= UInt<1>("h00") r_queue.io.enq.valid <= UInt<1>("h00") r_queue.clk <= clk r_queue.reset <= reset r_queue.io.enq <- io.ar reg responding : UInt<1>, clk, reset, UInt<1>("h00") reg beats_left : UInt<8>, clk, reset, UInt<8>("h00") node T_359 = eq(responding, UInt<1>("h00")) node T_360 = and(T_359, r_queue.io.deq.valid) when T_360 : responding <= UInt<1>("h01") beats_left <= r_queue.io.deq.bits.len skip node T_362 = and(r_queue.io.deq.valid, responding) io.r.valid <= T_362 io.r.bits.id <= r_queue.io.deq.bits.id io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<2>("h03") node T_372 = eq(beats_left, UInt<1>("h00")) io.r.bits.last <= T_372 node T_373 = and(io.r.ready, io.r.valid) node T_374 = and(T_373, io.r.bits.last) r_queue.io.deq.ready <= T_374 node T_375 = and(io.r.ready, io.r.valid) when T_375 : node T_377 = eq(beats_left, UInt<1>("h00")) when T_377 : responding <= UInt<1>("h00") skip node T_380 = eq(T_377, UInt<1>("h00")) when T_380 : node T_382 = subw(beats_left, UInt<1>("h01")) beats_left <= T_382 skip skip reg draining : UInt<1>, clk, reset, UInt<1>("h00") io.w.ready <= draining node T_385 = and(io.aw.ready, io.aw.valid) when T_385 : draining <= UInt<1>("h01") skip node T_387 = and(io.w.ready, io.w.valid) node T_388 = and(T_387, io.w.bits.last) when T_388 : draining <= UInt<1>("h00") skip inst b_queue of Queue_37 b_queue.io.deq.ready <= UInt<1>("h00") b_queue.io.enq.bits <= UInt<1>("h00") b_queue.io.enq.valid <= UInt<1>("h00") b_queue.clk <= clk b_queue.reset <= reset node T_396 = eq(draining, UInt<1>("h00")) node T_397 = and(io.aw.valid, T_396) b_queue.io.enq.valid <= T_397 b_queue.io.enq.bits <= io.aw.bits.id node T_399 = eq(draining, UInt<1>("h00")) node T_400 = and(b_queue.io.enq.ready, T_399) io.aw.ready <= T_400 node T_402 = eq(draining, UInt<1>("h00")) node T_403 = and(b_queue.io.deq.valid, T_402) io.b.valid <= T_403 io.b.bits.id <= b_queue.io.deq.bits io.b.bits.resp <= UInt<2>("h03") node T_406 = eq(draining, UInt<1>("h00")) node T_407 = and(io.b.ready, T_406) b_queue.io.deq.ready <= T_407 module RRArbiter_38 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<3>} io.chosen <= UInt<1>("h00") io.out.bits.user <= UInt<1>("h00") io.out.bits.id <= UInt<1>("h00") io.out.bits.resp <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") wire T_196 : UInt<3> T_196 <= UInt<1>("h00") io.out.valid <= io.in[T_196].valid io.out.bits <- io.in[T_196].bits io.chosen <= T_196 io.in[T_196].ready <= UInt<1>("h00") reg T_234 : UInt<3>, clk, reset, UInt<3>("h00") node T_235 = gt(UInt<1>("h00"), T_234) node T_236 = and(io.in[0].valid, T_235) node T_238 = gt(UInt<1>("h01"), T_234) node T_239 = and(io.in[1].valid, T_238) node T_241 = gt(UInt<2>("h02"), T_234) node T_242 = and(io.in[2].valid, T_241) node T_244 = gt(UInt<2>("h03"), T_234) node T_245 = and(io.in[3].valid, T_244) node T_247 = gt(UInt<3>("h04"), T_234) node T_248 = and(io.in[4].valid, T_247) node T_251 = or(UInt<1>("h00"), T_236) node T_253 = eq(T_251, UInt<1>("h00")) node T_255 = or(UInt<1>("h00"), T_236) node T_256 = or(T_255, T_239) node T_258 = eq(T_256, UInt<1>("h00")) node T_260 = or(UInt<1>("h00"), T_236) node T_261 = or(T_260, T_239) node T_262 = or(T_261, T_242) node T_264 = eq(T_262, UInt<1>("h00")) node T_266 = or(UInt<1>("h00"), T_236) node T_267 = or(T_266, T_239) node T_268 = or(T_267, T_242) node T_269 = or(T_268, T_245) node T_271 = eq(T_269, UInt<1>("h00")) node T_273 = or(UInt<1>("h00"), T_236) node T_274 = or(T_273, T_239) node T_275 = or(T_274, T_242) node T_276 = or(T_275, T_245) node T_277 = or(T_276, T_248) node T_279 = eq(T_277, UInt<1>("h00")) node T_281 = or(UInt<1>("h00"), T_236) node T_282 = or(T_281, T_239) node T_283 = or(T_282, T_242) node T_284 = or(T_283, T_245) node T_285 = or(T_284, T_248) node T_286 = or(T_285, io.in[0].valid) node T_288 = eq(T_286, UInt<1>("h00")) node T_290 = or(UInt<1>("h00"), T_236) node T_291 = or(T_290, T_239) node T_292 = or(T_291, T_242) node T_293 = or(T_292, T_245) node T_294 = or(T_293, T_248) node T_295 = or(T_294, io.in[0].valid) node T_296 = or(T_295, io.in[1].valid) node T_298 = eq(T_296, UInt<1>("h00")) node T_300 = or(UInt<1>("h00"), T_236) node T_301 = or(T_300, T_239) node T_302 = or(T_301, T_242) node T_303 = or(T_302, T_245) node T_304 = or(T_303, T_248) node T_305 = or(T_304, io.in[0].valid) node T_306 = or(T_305, io.in[1].valid) node T_307 = or(T_306, io.in[2].valid) node T_309 = eq(T_307, UInt<1>("h00")) node T_311 = or(UInt<1>("h00"), T_236) node T_312 = or(T_311, T_239) node T_313 = or(T_312, T_242) node T_314 = or(T_313, T_245) node T_315 = or(T_314, T_248) node T_316 = or(T_315, io.in[0].valid) node T_317 = or(T_316, io.in[1].valid) node T_318 = or(T_317, io.in[2].valid) node T_319 = or(T_318, io.in[3].valid) node T_321 = eq(T_319, UInt<1>("h00")) node T_323 = gt(UInt<1>("h00"), T_234) node T_324 = and(UInt<1>("h01"), T_323) node T_325 = or(T_324, T_279) node T_327 = gt(UInt<1>("h01"), T_234) node T_328 = and(T_253, T_327) node T_329 = or(T_328, T_288) node T_331 = gt(UInt<2>("h02"), T_234) node T_332 = and(T_258, T_331) node T_333 = or(T_332, T_298) node T_335 = gt(UInt<2>("h03"), T_234) node T_336 = and(T_264, T_335) node T_337 = or(T_336, T_309) node T_339 = gt(UInt<3>("h04"), T_234) node T_340 = and(T_271, T_339) node T_341 = or(T_340, T_321) node T_343 = eq(UInt<3>("h04"), UInt<1>("h00")) node T_344 = mux(UInt<1>("h00"), T_343, T_325) node T_345 = and(T_344, io.out.ready) io.in[0].ready <= T_345 node T_347 = eq(UInt<3>("h04"), UInt<1>("h01")) node T_348 = mux(UInt<1>("h00"), T_347, T_329) node T_349 = and(T_348, io.out.ready) io.in[1].ready <= T_349 node T_351 = eq(UInt<3>("h04"), UInt<2>("h02")) node T_352 = mux(UInt<1>("h00"), T_351, T_333) node T_353 = and(T_352, io.out.ready) io.in[2].ready <= T_353 node T_355 = eq(UInt<3>("h04"), UInt<2>("h03")) node T_356 = mux(UInt<1>("h00"), T_355, T_337) node T_357 = and(T_356, io.out.ready) io.in[3].ready <= T_357 node T_359 = eq(UInt<3>("h04"), UInt<3>("h04")) node T_360 = mux(UInt<1>("h00"), T_359, T_341) node T_361 = and(T_360, io.out.ready) io.in[4].ready <= T_361 node T_364 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) node T_366 = mux(io.in[2].valid, UInt<2>("h02"), T_364) node T_368 = mux(io.in[1].valid, UInt<1>("h01"), T_366) node T_370 = mux(io.in[0].valid, UInt<1>("h00"), T_368) node T_372 = gt(UInt<3>("h04"), T_234) node T_373 = and(io.in[4].valid, T_372) node T_375 = mux(T_373, UInt<3>("h04"), T_370) node T_377 = gt(UInt<2>("h03"), T_234) node T_378 = and(io.in[3].valid, T_377) node T_380 = mux(T_378, UInt<2>("h03"), T_375) node T_382 = gt(UInt<2>("h02"), T_234) node T_383 = and(io.in[2].valid, T_382) node T_385 = mux(T_383, UInt<2>("h02"), T_380) node T_387 = gt(UInt<1>("h01"), T_234) node T_388 = and(io.in[1].valid, T_387) node T_390 = mux(T_388, UInt<1>("h01"), T_385) node T_391 = mux(UInt<1>("h00"), UInt<3>("h04"), T_390) T_196 <= T_391 node T_392 = and(io.out.ready, io.out.valid) when T_392 : T_234 <= T_196 skip module JunctionsPeekingArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.out.bits.user <= UInt<1>("h00") io.out.bits.id <= UInt<1>("h00") io.out.bits.last <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.resp <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") reg T_273 : UInt<3>, clk, reset, UInt<3>("h00") reg T_275 : UInt<1>, clk, reset, UInt<1>("h00") wire T_277 : UInt<1>[5] T_277[0] <= io.in[0].valid T_277[1] <= io.in[1].valid T_277[2] <= io.in[2].valid T_277[3] <= io.in[3].valid T_277[4] <= io.in[4].valid node T_285 = addw(T_273, UInt<1>("h01")) node T_287 = lt(T_285, UInt<3>("h05")) node T_289 = addw(UInt<1>("h00"), T_285) node T_292 = subw(T_285, UInt<3>("h05")) node T_294 = mux(T_287, T_277[T_289], T_277[T_292]) node T_296 = lt(T_285, UInt<3>("h04")) node T_298 = addw(UInt<1>("h01"), T_285) node T_301 = subw(T_285, UInt<3>("h04")) node T_303 = mux(T_296, T_277[T_298], T_277[T_301]) node T_305 = lt(T_285, UInt<2>("h03")) node T_307 = addw(UInt<2>("h02"), T_285) node T_310 = subw(T_285, UInt<2>("h03")) node T_312 = mux(T_305, T_277[T_307], T_277[T_310]) node T_314 = lt(T_285, UInt<2>("h02")) node T_316 = addw(UInt<2>("h03"), T_285) node T_319 = subw(T_285, UInt<2>("h02")) node T_321 = mux(T_314, T_277[T_316], T_277[T_319]) node T_323 = lt(T_285, UInt<1>("h01")) node T_325 = addw(UInt<3>("h04"), T_285) node T_328 = subw(T_285, UInt<1>("h01")) node T_330 = mux(T_323, T_277[T_325], T_277[T_328]) wire T_332 : UInt<1>[5] T_332[0] <= T_294 T_332[1] <= T_303 T_332[2] <= T_312 T_332[3] <= T_321 T_332[4] <= T_330 wire T_345 : UInt<3>[5] T_345[0] <= UInt<1>("h00") T_345[1] <= UInt<1>("h01") T_345[2] <= UInt<2>("h02") T_345[3] <= UInt<2>("h03") T_345[4] <= UInt<3>("h04") node T_353 = addw(T_273, UInt<1>("h01")) node T_355 = lt(T_353, UInt<3>("h05")) node T_357 = addw(UInt<1>("h00"), T_353) node T_360 = subw(T_353, UInt<3>("h05")) node T_362 = mux(T_355, T_345[T_357], T_345[T_360]) node T_364 = lt(T_353, UInt<3>("h04")) node T_366 = addw(UInt<1>("h01"), T_353) node T_369 = subw(T_353, UInt<3>("h04")) node T_371 = mux(T_364, T_345[T_366], T_345[T_369]) node T_373 = lt(T_353, UInt<2>("h03")) node T_375 = addw(UInt<2>("h02"), T_353) node T_378 = subw(T_353, UInt<2>("h03")) node T_380 = mux(T_373, T_345[T_375], T_345[T_378]) node T_382 = lt(T_353, UInt<2>("h02")) node T_384 = addw(UInt<2>("h03"), T_353) node T_387 = subw(T_353, UInt<2>("h02")) node T_389 = mux(T_382, T_345[T_384], T_345[T_387]) node T_391 = lt(T_353, UInt<1>("h01")) node T_393 = addw(UInt<3>("h04"), T_353) node T_396 = subw(T_353, UInt<1>("h01")) node T_398 = mux(T_391, T_345[T_393], T_345[T_396]) wire T_400 : UInt<3>[5] T_400[0] <= T_362 T_400[1] <= T_371 T_400[2] <= T_380 T_400[3] <= T_389 T_400[4] <= T_398 node T_407 = mux(T_332[3], T_400[3], T_400[4]) node T_408 = mux(T_332[2], T_400[2], T_407) node T_409 = mux(T_332[1], T_400[1], T_408) node T_410 = mux(T_332[0], T_400[0], T_409) node T_411 = mux(T_275, T_273, T_410) node T_413 = eq(T_411, UInt<1>("h00")) node T_414 = and(io.out.ready, T_413) io.in[0].ready <= T_414 node T_416 = eq(T_411, UInt<1>("h01")) node T_417 = and(io.out.ready, T_416) io.in[1].ready <= T_417 node T_419 = eq(T_411, UInt<2>("h02")) node T_420 = and(io.out.ready, T_419) io.in[2].ready <= T_420 node T_422 = eq(T_411, UInt<2>("h03")) node T_423 = and(io.out.ready, T_422) io.in[3].ready <= T_423 node T_425 = eq(T_411, UInt<3>("h04")) node T_426 = and(io.out.ready, T_425) io.in[4].ready <= T_426 io.out.valid <= io.in[T_411].valid io.out.bits <- io.in[T_411].bits node T_457 = and(io.out.ready, io.out.valid) when T_457 : node T_459 = eq(T_275, UInt<1>("h00")) node T_461 = and(T_459, UInt<1>("h01")) when T_461 : T_273 <= T_410 T_275 <= UInt<1>("h01") skip when io.out.bits.last : T_275 <= UInt<1>("h00") skip skip module NastiRouter : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} io.slave[0].r.ready <= UInt<1>("h00") io.slave[0].ar.bits.user <= UInt<1>("h00") io.slave[0].ar.bits.id <= UInt<1>("h00") io.slave[0].ar.bits.region <= UInt<1>("h00") io.slave[0].ar.bits.qos <= UInt<1>("h00") io.slave[0].ar.bits.prot <= UInt<1>("h00") io.slave[0].ar.bits.cache <= UInt<1>("h00") io.slave[0].ar.bits.lock <= UInt<1>("h00") io.slave[0].ar.bits.burst <= UInt<1>("h00") io.slave[0].ar.bits.size <= UInt<1>("h00") io.slave[0].ar.bits.len <= UInt<1>("h00") io.slave[0].ar.bits.addr <= UInt<1>("h00") io.slave[0].ar.valid <= UInt<1>("h00") io.slave[0].b.ready <= UInt<1>("h00") io.slave[0].w.bits.user <= UInt<1>("h00") io.slave[0].w.bits.strb <= UInt<1>("h00") io.slave[0].w.bits.last <= UInt<1>("h00") io.slave[0].w.bits.data <= UInt<1>("h00") io.slave[0].w.valid <= UInt<1>("h00") io.slave[0].aw.bits.user <= UInt<1>("h00") io.slave[0].aw.bits.id <= UInt<1>("h00") io.slave[0].aw.bits.region <= UInt<1>("h00") io.slave[0].aw.bits.qos <= UInt<1>("h00") io.slave[0].aw.bits.prot <= UInt<1>("h00") io.slave[0].aw.bits.cache <= UInt<1>("h00") io.slave[0].aw.bits.lock <= UInt<1>("h00") io.slave[0].aw.bits.burst <= UInt<1>("h00") io.slave[0].aw.bits.size <= UInt<1>("h00") io.slave[0].aw.bits.len <= UInt<1>("h00") io.slave[0].aw.bits.addr <= UInt<1>("h00") io.slave[0].aw.valid <= UInt<1>("h00") io.slave[1].r.ready <= UInt<1>("h00") io.slave[1].ar.bits.user <= UInt<1>("h00") io.slave[1].ar.bits.id <= UInt<1>("h00") io.slave[1].ar.bits.region <= UInt<1>("h00") io.slave[1].ar.bits.qos <= UInt<1>("h00") io.slave[1].ar.bits.prot <= UInt<1>("h00") io.slave[1].ar.bits.cache <= UInt<1>("h00") io.slave[1].ar.bits.lock <= UInt<1>("h00") io.slave[1].ar.bits.burst <= UInt<1>("h00") io.slave[1].ar.bits.size <= UInt<1>("h00") io.slave[1].ar.bits.len <= UInt<1>("h00") io.slave[1].ar.bits.addr <= UInt<1>("h00") io.slave[1].ar.valid <= UInt<1>("h00") io.slave[1].b.ready <= UInt<1>("h00") io.slave[1].w.bits.user <= UInt<1>("h00") io.slave[1].w.bits.strb <= UInt<1>("h00") io.slave[1].w.bits.last <= UInt<1>("h00") io.slave[1].w.bits.data <= UInt<1>("h00") io.slave[1].w.valid <= UInt<1>("h00") io.slave[1].aw.bits.user <= UInt<1>("h00") io.slave[1].aw.bits.id <= UInt<1>("h00") io.slave[1].aw.bits.region <= UInt<1>("h00") io.slave[1].aw.bits.qos <= UInt<1>("h00") io.slave[1].aw.bits.prot <= UInt<1>("h00") io.slave[1].aw.bits.cache <= UInt<1>("h00") io.slave[1].aw.bits.lock <= UInt<1>("h00") io.slave[1].aw.bits.burst <= UInt<1>("h00") io.slave[1].aw.bits.size <= UInt<1>("h00") io.slave[1].aw.bits.len <= UInt<1>("h00") io.slave[1].aw.bits.addr <= UInt<1>("h00") io.slave[1].aw.valid <= UInt<1>("h00") io.slave[2].r.ready <= UInt<1>("h00") io.slave[2].ar.bits.user <= UInt<1>("h00") io.slave[2].ar.bits.id <= UInt<1>("h00") io.slave[2].ar.bits.region <= UInt<1>("h00") io.slave[2].ar.bits.qos <= UInt<1>("h00") io.slave[2].ar.bits.prot <= UInt<1>("h00") io.slave[2].ar.bits.cache <= UInt<1>("h00") io.slave[2].ar.bits.lock <= UInt<1>("h00") io.slave[2].ar.bits.burst <= UInt<1>("h00") io.slave[2].ar.bits.size <= UInt<1>("h00") io.slave[2].ar.bits.len <= UInt<1>("h00") io.slave[2].ar.bits.addr <= UInt<1>("h00") io.slave[2].ar.valid <= UInt<1>("h00") io.slave[2].b.ready <= UInt<1>("h00") io.slave[2].w.bits.user <= UInt<1>("h00") io.slave[2].w.bits.strb <= UInt<1>("h00") io.slave[2].w.bits.last <= UInt<1>("h00") io.slave[2].w.bits.data <= UInt<1>("h00") io.slave[2].w.valid <= UInt<1>("h00") io.slave[2].aw.bits.user <= UInt<1>("h00") io.slave[2].aw.bits.id <= UInt<1>("h00") io.slave[2].aw.bits.region <= UInt<1>("h00") io.slave[2].aw.bits.qos <= UInt<1>("h00") io.slave[2].aw.bits.prot <= UInt<1>("h00") io.slave[2].aw.bits.cache <= UInt<1>("h00") io.slave[2].aw.bits.lock <= UInt<1>("h00") io.slave[2].aw.bits.burst <= UInt<1>("h00") io.slave[2].aw.bits.size <= UInt<1>("h00") io.slave[2].aw.bits.len <= UInt<1>("h00") io.slave[2].aw.bits.addr <= UInt<1>("h00") io.slave[2].aw.valid <= UInt<1>("h00") io.slave[3].r.ready <= UInt<1>("h00") io.slave[3].ar.bits.user <= UInt<1>("h00") io.slave[3].ar.bits.id <= UInt<1>("h00") io.slave[3].ar.bits.region <= UInt<1>("h00") io.slave[3].ar.bits.qos <= UInt<1>("h00") io.slave[3].ar.bits.prot <= UInt<1>("h00") io.slave[3].ar.bits.cache <= UInt<1>("h00") io.slave[3].ar.bits.lock <= UInt<1>("h00") io.slave[3].ar.bits.burst <= UInt<1>("h00") io.slave[3].ar.bits.size <= UInt<1>("h00") io.slave[3].ar.bits.len <= UInt<1>("h00") io.slave[3].ar.bits.addr <= UInt<1>("h00") io.slave[3].ar.valid <= UInt<1>("h00") io.slave[3].b.ready <= UInt<1>("h00") io.slave[3].w.bits.user <= UInt<1>("h00") io.slave[3].w.bits.strb <= UInt<1>("h00") io.slave[3].w.bits.last <= UInt<1>("h00") io.slave[3].w.bits.data <= UInt<1>("h00") io.slave[3].w.valid <= UInt<1>("h00") io.slave[3].aw.bits.user <= UInt<1>("h00") io.slave[3].aw.bits.id <= UInt<1>("h00") io.slave[3].aw.bits.region <= UInt<1>("h00") io.slave[3].aw.bits.qos <= UInt<1>("h00") io.slave[3].aw.bits.prot <= UInt<1>("h00") io.slave[3].aw.bits.cache <= UInt<1>("h00") io.slave[3].aw.bits.lock <= UInt<1>("h00") io.slave[3].aw.bits.burst <= UInt<1>("h00") io.slave[3].aw.bits.size <= UInt<1>("h00") io.slave[3].aw.bits.len <= UInt<1>("h00") io.slave[3].aw.bits.addr <= UInt<1>("h00") io.slave[3].aw.valid <= UInt<1>("h00") io.master.r.bits.user <= UInt<1>("h00") io.master.r.bits.id <= UInt<1>("h00") io.master.r.bits.last <= UInt<1>("h00") io.master.r.bits.data <= UInt<1>("h00") io.master.r.bits.resp <= UInt<1>("h00") io.master.r.valid <= UInt<1>("h00") io.master.ar.ready <= UInt<1>("h00") io.master.b.bits.user <= UInt<1>("h00") io.master.b.bits.id <= UInt<1>("h00") io.master.b.bits.resp <= UInt<1>("h00") io.master.b.valid <= UInt<1>("h00") io.master.w.ready <= UInt<1>("h00") io.master.aw.ready <= UInt<1>("h00") node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1440 = and(T_1437, T_1439) node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000")) node T_1445 = and(T_1442, T_1444) node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000")) node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1450 = and(T_1447, T_1449) node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000")) node T_1455 = and(T_1452, T_1454) wire T_1457 : UInt<1>[4] T_1457[0] <= T_1440 T_1457[1] <= T_1445 T_1457[2] <= T_1450 T_1457[3] <= T_1455 node T_1463 = cat(T_1457[3], T_1457[2]) node T_1464 = cat(T_1457[1], T_1457[0]) node ar_route = cat(T_1463, T_1464) node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00")) node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1470 = and(T_1467, T_1469) node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000")) node T_1475 = and(T_1472, T_1474) node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000")) node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1480 = and(T_1477, T_1479) node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000")) node T_1485 = and(T_1482, T_1484) wire T_1487 : UInt<1>[4] T_1487[0] <= T_1470 T_1487[1] <= T_1475 T_1487[2] <= T_1480 T_1487[3] <= T_1485 node T_1493 = cat(T_1487[3], T_1487[2]) node T_1494 = cat(T_1487[1], T_1487[0]) node aw_route = cat(T_1493, T_1494) node T_1499 = bit(ar_route, 0) node T_1500 = and(io.master.ar.valid, T_1499) io.slave[0].ar.valid <= T_1500 io.slave[0].ar.bits <- io.master.ar.bits node T_1501 = bit(ar_route, 0) node T_1502 = and(io.slave[0].ar.ready, T_1501) node T_1503 = or(UInt<1>("h00"), T_1502) node T_1504 = bit(aw_route, 0) node T_1505 = and(io.master.aw.valid, T_1504) io.slave[0].aw.valid <= T_1505 io.slave[0].aw.bits <- io.master.aw.bits node T_1506 = bit(aw_route, 0) node T_1507 = and(io.slave[0].aw.ready, T_1506) node T_1508 = or(UInt<1>("h00"), T_1507) reg T_1510 : UInt<1>, clk, reset, UInt<1>("h00") node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1511 : T_1510 <= UInt<1>("h01") skip node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) node T_1514 = and(T_1513, io.slave[0].w.bits.last) when T_1514 : T_1510 <= UInt<1>("h00") skip node T_1516 = and(io.master.w.valid, T_1510) io.slave[0].w.valid <= T_1516 io.slave[0].w.bits <- io.master.w.bits node T_1517 = and(io.slave[0].w.ready, T_1510) node T_1518 = or(UInt<1>("h00"), T_1517) node T_1519 = bit(ar_route, 1) node T_1520 = and(io.master.ar.valid, T_1519) io.slave[1].ar.valid <= T_1520 io.slave[1].ar.bits <- io.master.ar.bits node T_1521 = bit(ar_route, 1) node T_1522 = and(io.slave[1].ar.ready, T_1521) node T_1523 = or(T_1503, T_1522) node T_1524 = bit(aw_route, 1) node T_1525 = and(io.master.aw.valid, T_1524) io.slave[1].aw.valid <= T_1525 io.slave[1].aw.bits <- io.master.aw.bits node T_1526 = bit(aw_route, 1) node T_1527 = and(io.slave[1].aw.ready, T_1526) node T_1528 = or(T_1508, T_1527) reg T_1530 : UInt<1>, clk, reset, UInt<1>("h00") node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1531 : T_1530 <= UInt<1>("h01") skip node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) node T_1534 = and(T_1533, io.slave[1].w.bits.last) when T_1534 : T_1530 <= UInt<1>("h00") skip node T_1536 = and(io.master.w.valid, T_1530) io.slave[1].w.valid <= T_1536 io.slave[1].w.bits <- io.master.w.bits node T_1537 = and(io.slave[1].w.ready, T_1530) node T_1538 = or(T_1518, T_1537) node T_1539 = bit(ar_route, 2) node T_1540 = and(io.master.ar.valid, T_1539) io.slave[2].ar.valid <= T_1540 io.slave[2].ar.bits <- io.master.ar.bits node T_1541 = bit(ar_route, 2) node T_1542 = and(io.slave[2].ar.ready, T_1541) node T_1543 = or(T_1523, T_1542) node T_1544 = bit(aw_route, 2) node T_1545 = and(io.master.aw.valid, T_1544) io.slave[2].aw.valid <= T_1545 io.slave[2].aw.bits <- io.master.aw.bits node T_1546 = bit(aw_route, 2) node T_1547 = and(io.slave[2].aw.ready, T_1546) node T_1548 = or(T_1528, T_1547) reg T_1550 : UInt<1>, clk, reset, UInt<1>("h00") node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1551 : T_1550 <= UInt<1>("h01") skip node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) node T_1554 = and(T_1553, io.slave[2].w.bits.last) when T_1554 : T_1550 <= UInt<1>("h00") skip node T_1556 = and(io.master.w.valid, T_1550) io.slave[2].w.valid <= T_1556 io.slave[2].w.bits <- io.master.w.bits node T_1557 = and(io.slave[2].w.ready, T_1550) node T_1558 = or(T_1538, T_1557) node T_1559 = bit(ar_route, 3) node T_1560 = and(io.master.ar.valid, T_1559) io.slave[3].ar.valid <= T_1560 io.slave[3].ar.bits <- io.master.ar.bits node T_1561 = bit(ar_route, 3) node T_1562 = and(io.slave[3].ar.ready, T_1561) node ar_ready = or(T_1543, T_1562) node T_1564 = bit(aw_route, 3) node T_1565 = and(io.master.aw.valid, T_1564) io.slave[3].aw.valid <= T_1565 io.slave[3].aw.bits <- io.master.aw.bits node T_1566 = bit(aw_route, 3) node T_1567 = and(io.slave[3].aw.ready, T_1566) node aw_ready = or(T_1548, T_1567) reg T_1570 : UInt<1>, clk, reset, UInt<1>("h00") node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) when T_1571 : T_1570 <= UInt<1>("h01") skip node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) node T_1574 = and(T_1573, io.slave[3].w.bits.last) when T_1574 : T_1570 <= UInt<1>("h00") skip node T_1576 = and(io.master.w.valid, T_1570) io.slave[3].w.valid <= T_1576 io.slave[3].w.bits <- io.master.w.bits node T_1577 = and(io.slave[3].w.ready, T_1570) node w_ready = or(T_1558, T_1577) node T_1580 = neq(ar_route, UInt<1>("h00")) node r_invalid = eq(T_1580, UInt<1>("h00")) node T_1584 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1584, UInt<1>("h00")) inst err_slave of NastiErrorSlave err_slave.io.r.ready <= UInt<1>("h00") err_slave.io.ar.bits.user <= UInt<1>("h00") err_slave.io.ar.bits.id <= UInt<1>("h00") err_slave.io.ar.bits.region <= UInt<1>("h00") err_slave.io.ar.bits.qos <= UInt<1>("h00") err_slave.io.ar.bits.prot <= UInt<1>("h00") err_slave.io.ar.bits.cache <= UInt<1>("h00") err_slave.io.ar.bits.lock <= UInt<1>("h00") err_slave.io.ar.bits.burst <= UInt<1>("h00") err_slave.io.ar.bits.size <= UInt<1>("h00") err_slave.io.ar.bits.len <= UInt<1>("h00") err_slave.io.ar.bits.addr <= UInt<1>("h00") err_slave.io.ar.valid <= UInt<1>("h00") err_slave.io.b.ready <= UInt<1>("h00") err_slave.io.w.bits.user <= UInt<1>("h00") err_slave.io.w.bits.strb <= UInt<1>("h00") err_slave.io.w.bits.last <= UInt<1>("h00") err_slave.io.w.bits.data <= UInt<1>("h00") err_slave.io.w.valid <= UInt<1>("h00") err_slave.io.aw.bits.user <= UInt<1>("h00") err_slave.io.aw.bits.id <= UInt<1>("h00") err_slave.io.aw.bits.region <= UInt<1>("h00") err_slave.io.aw.bits.qos <= UInt<1>("h00") err_slave.io.aw.bits.prot <= UInt<1>("h00") err_slave.io.aw.bits.cache <= UInt<1>("h00") err_slave.io.aw.bits.lock <= UInt<1>("h00") err_slave.io.aw.bits.burst <= UInt<1>("h00") err_slave.io.aw.bits.size <= UInt<1>("h00") err_slave.io.aw.bits.len <= UInt<1>("h00") err_slave.io.aw.bits.addr <= UInt<1>("h00") err_slave.io.aw.valid <= UInt<1>("h00") err_slave.clk <= clk err_slave.reset <= reset node T_1619 = and(r_invalid, io.master.ar.valid) err_slave.io.ar.valid <= T_1619 err_slave.io.ar.bits <- io.master.ar.bits node T_1620 = and(w_invalid, io.master.aw.valid) err_slave.io.aw.valid <= T_1620 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits node T_1621 = and(r_invalid, err_slave.io.ar.ready) node T_1622 = or(ar_ready, T_1621) io.master.ar.ready <= T_1622 node T_1623 = and(w_invalid, err_slave.io.aw.ready) node T_1624 = or(aw_ready, T_1623) io.master.aw.ready <= T_1624 node T_1625 = or(w_ready, err_slave.io.w.ready) io.master.w.ready <= T_1625 inst b_arb of RRArbiter_38 b_arb.io.out.ready <= UInt<1>("h00") b_arb.io.in[0].bits.user <= UInt<1>("h00") b_arb.io.in[0].bits.id <= UInt<1>("h00") b_arb.io.in[0].bits.resp <= UInt<1>("h00") b_arb.io.in[0].valid <= UInt<1>("h00") b_arb.io.in[1].bits.user <= UInt<1>("h00") b_arb.io.in[1].bits.id <= UInt<1>("h00") b_arb.io.in[1].bits.resp <= UInt<1>("h00") b_arb.io.in[1].valid <= UInt<1>("h00") b_arb.io.in[2].bits.user <= UInt<1>("h00") b_arb.io.in[2].bits.id <= UInt<1>("h00") b_arb.io.in[2].bits.resp <= UInt<1>("h00") b_arb.io.in[2].valid <= UInt<1>("h00") b_arb.io.in[3].bits.user <= UInt<1>("h00") b_arb.io.in[3].bits.id <= UInt<1>("h00") b_arb.io.in[3].bits.resp <= UInt<1>("h00") b_arb.io.in[3].valid <= UInt<1>("h00") b_arb.io.in[4].bits.user <= UInt<1>("h00") b_arb.io.in[4].bits.id <= UInt<1>("h00") b_arb.io.in[4].bits.resp <= UInt<1>("h00") b_arb.io.in[4].valid <= UInt<1>("h00") b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter r_arb.io.out.ready <= UInt<1>("h00") r_arb.io.in[0].bits.user <= UInt<1>("h00") r_arb.io.in[0].bits.id <= UInt<1>("h00") r_arb.io.in[0].bits.last <= UInt<1>("h00") r_arb.io.in[0].bits.data <= UInt<1>("h00") r_arb.io.in[0].bits.resp <= UInt<1>("h00") r_arb.io.in[0].valid <= UInt<1>("h00") r_arb.io.in[1].bits.user <= UInt<1>("h00") r_arb.io.in[1].bits.id <= UInt<1>("h00") r_arb.io.in[1].bits.last <= UInt<1>("h00") r_arb.io.in[1].bits.data <= UInt<1>("h00") r_arb.io.in[1].bits.resp <= UInt<1>("h00") r_arb.io.in[1].valid <= UInt<1>("h00") r_arb.io.in[2].bits.user <= UInt<1>("h00") r_arb.io.in[2].bits.id <= UInt<1>("h00") r_arb.io.in[2].bits.last <= UInt<1>("h00") r_arb.io.in[2].bits.data <= UInt<1>("h00") r_arb.io.in[2].bits.resp <= UInt<1>("h00") r_arb.io.in[2].valid <= UInt<1>("h00") r_arb.io.in[3].bits.user <= UInt<1>("h00") r_arb.io.in[3].bits.id <= UInt<1>("h00") r_arb.io.in[3].bits.last <= UInt<1>("h00") r_arb.io.in[3].bits.data <= UInt<1>("h00") r_arb.io.in[3].bits.resp <= UInt<1>("h00") r_arb.io.in[3].valid <= UInt<1>("h00") r_arb.io.in[4].bits.user <= UInt<1>("h00") r_arb.io.in[4].bits.id <= UInt<1>("h00") r_arb.io.in[4].bits.last <= UInt<1>("h00") r_arb.io.in[4].bits.data <= UInt<1>("h00") r_arb.io.in[4].bits.resp <= UInt<1>("h00") r_arb.io.in[4].valid <= UInt<1>("h00") r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b r_arb.io.in[0] <- io.slave[0].r b_arb.io.in[1] <- io.slave[1].b r_arb.io.in[1] <- io.slave[1].r b_arb.io.in[2] <- io.slave[2].b r_arb.io.in[2] <- io.slave[2].r b_arb.io.in[3] <- io.slave[3].b r_arb.io.in[3] <- io.slave[3].r b_arb.io.in[4] <- err_slave.io.b r_arb.io.in[4] <- err_slave.io.r io.master.b <- b_arb.io.out io.master.r <- r_arb.io.out module NastiErrorSlave_40 : input clk : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.r.bits.user <= UInt<1>("h00") io.r.bits.id <= UInt<1>("h00") io.r.bits.last <= UInt<1>("h00") io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<1>("h00") io.r.valid <= UInt<1>("h00") io.ar.ready <= UInt<1>("h00") io.b.bits.user <= UInt<1>("h00") io.b.bits.id <= UInt<1>("h00") io.b.bits.resp <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.aw.ready <= UInt<1>("h00") node T_322 = and(io.ar.ready, io.ar.valid) when T_322 : node T_324 = eq(reset, UInt<1>("h00")) when T_324 : printf(clk, UInt<1>(1), "Invalid read address %x ", io.ar.bits.addr) skip skip node T_325 = and(io.aw.ready, io.aw.valid) when T_325 : node T_327 = eq(reset, UInt<1>("h00")) when T_327 : printf(clk, UInt<1>(1), "Invalid write address %x ", io.aw.bits.addr) skip skip inst r_queue of Queue_36 r_queue.io.deq.ready <= UInt<1>("h00") r_queue.io.enq.bits.user <= UInt<1>("h00") r_queue.io.enq.bits.id <= UInt<1>("h00") r_queue.io.enq.bits.region <= UInt<1>("h00") r_queue.io.enq.bits.qos <= UInt<1>("h00") r_queue.io.enq.bits.prot <= UInt<1>("h00") r_queue.io.enq.bits.cache <= UInt<1>("h00") r_queue.io.enq.bits.lock <= UInt<1>("h00") r_queue.io.enq.bits.burst <= UInt<1>("h00") r_queue.io.enq.bits.size <= UInt<1>("h00") r_queue.io.enq.bits.len <= UInt<1>("h00") r_queue.io.enq.bits.addr <= UInt<1>("h00") r_queue.io.enq.valid <= UInt<1>("h00") r_queue.clk <= clk r_queue.reset <= reset r_queue.io.enq <- io.ar reg responding : UInt<1>, clk, reset, UInt<1>("h00") reg beats_left : UInt<8>, clk, reset, UInt<8>("h00") node T_359 = eq(responding, UInt<1>("h00")) node T_360 = and(T_359, r_queue.io.deq.valid) when T_360 : responding <= UInt<1>("h01") beats_left <= r_queue.io.deq.bits.len skip node T_362 = and(r_queue.io.deq.valid, responding) io.r.valid <= T_362 io.r.bits.id <= r_queue.io.deq.bits.id io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<2>("h03") node T_365 = eq(beats_left, UInt<1>("h00")) io.r.bits.last <= T_365 node T_366 = and(io.r.ready, io.r.valid) node T_367 = and(T_366, io.r.bits.last) r_queue.io.deq.ready <= T_367 node T_368 = and(io.r.ready, io.r.valid) when T_368 : node T_370 = eq(beats_left, UInt<1>("h00")) when T_370 : responding <= UInt<1>("h00") skip node T_373 = eq(T_370, UInt<1>("h00")) when T_373 : node T_375 = subw(beats_left, UInt<1>("h01")) beats_left <= T_375 skip skip reg draining : UInt<1>, clk, reset, UInt<1>("h00") io.w.ready <= draining node T_378 = and(io.aw.ready, io.aw.valid) when T_378 : draining <= UInt<1>("h01") skip node T_380 = and(io.w.ready, io.w.valid) node T_381 = and(T_380, io.w.bits.last) when T_381 : draining <= UInt<1>("h00") skip inst b_queue of Queue_37 b_queue.io.deq.ready <= UInt<1>("h00") b_queue.io.enq.bits <= UInt<1>("h00") b_queue.io.enq.valid <= UInt<1>("h00") b_queue.clk <= clk b_queue.reset <= reset node T_389 = eq(draining, UInt<1>("h00")) node T_390 = and(io.aw.valid, T_389) b_queue.io.enq.valid <= T_390 b_queue.io.enq.bits <= io.aw.bits.id node T_392 = eq(draining, UInt<1>("h00")) node T_393 = and(b_queue.io.enq.ready, T_392) io.aw.ready <= T_393 node T_395 = eq(draining, UInt<1>("h00")) node T_396 = and(b_queue.io.deq.valid, T_395) io.b.valid <= T_396 io.b.bits.id <= b_queue.io.deq.bits io.b.bits.resp <= UInt<2>("h03") node T_399 = eq(draining, UInt<1>("h00")) node T_400 = and(io.b.ready, T_399) b_queue.io.deq.ready <= T_400 module NastiRouter_39 : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} io.slave[0].r.ready <= UInt<1>("h00") io.slave[0].ar.bits.user <= UInt<1>("h00") io.slave[0].ar.bits.id <= UInt<1>("h00") io.slave[0].ar.bits.region <= UInt<1>("h00") io.slave[0].ar.bits.qos <= UInt<1>("h00") io.slave[0].ar.bits.prot <= UInt<1>("h00") io.slave[0].ar.bits.cache <= UInt<1>("h00") io.slave[0].ar.bits.lock <= UInt<1>("h00") io.slave[0].ar.bits.burst <= UInt<1>("h00") io.slave[0].ar.bits.size <= UInt<1>("h00") io.slave[0].ar.bits.len <= UInt<1>("h00") io.slave[0].ar.bits.addr <= UInt<1>("h00") io.slave[0].ar.valid <= UInt<1>("h00") io.slave[0].b.ready <= UInt<1>("h00") io.slave[0].w.bits.user <= UInt<1>("h00") io.slave[0].w.bits.strb <= UInt<1>("h00") io.slave[0].w.bits.last <= UInt<1>("h00") io.slave[0].w.bits.data <= UInt<1>("h00") io.slave[0].w.valid <= UInt<1>("h00") io.slave[0].aw.bits.user <= UInt<1>("h00") io.slave[0].aw.bits.id <= UInt<1>("h00") io.slave[0].aw.bits.region <= UInt<1>("h00") io.slave[0].aw.bits.qos <= UInt<1>("h00") io.slave[0].aw.bits.prot <= UInt<1>("h00") io.slave[0].aw.bits.cache <= UInt<1>("h00") io.slave[0].aw.bits.lock <= UInt<1>("h00") io.slave[0].aw.bits.burst <= UInt<1>("h00") io.slave[0].aw.bits.size <= UInt<1>("h00") io.slave[0].aw.bits.len <= UInt<1>("h00") io.slave[0].aw.bits.addr <= UInt<1>("h00") io.slave[0].aw.valid <= UInt<1>("h00") io.slave[1].r.ready <= UInt<1>("h00") io.slave[1].ar.bits.user <= UInt<1>("h00") io.slave[1].ar.bits.id <= UInt<1>("h00") io.slave[1].ar.bits.region <= UInt<1>("h00") io.slave[1].ar.bits.qos <= UInt<1>("h00") io.slave[1].ar.bits.prot <= UInt<1>("h00") io.slave[1].ar.bits.cache <= UInt<1>("h00") io.slave[1].ar.bits.lock <= UInt<1>("h00") io.slave[1].ar.bits.burst <= UInt<1>("h00") io.slave[1].ar.bits.size <= UInt<1>("h00") io.slave[1].ar.bits.len <= UInt<1>("h00") io.slave[1].ar.bits.addr <= UInt<1>("h00") io.slave[1].ar.valid <= UInt<1>("h00") io.slave[1].b.ready <= UInt<1>("h00") io.slave[1].w.bits.user <= UInt<1>("h00") io.slave[1].w.bits.strb <= UInt<1>("h00") io.slave[1].w.bits.last <= UInt<1>("h00") io.slave[1].w.bits.data <= UInt<1>("h00") io.slave[1].w.valid <= UInt<1>("h00") io.slave[1].aw.bits.user <= UInt<1>("h00") io.slave[1].aw.bits.id <= UInt<1>("h00") io.slave[1].aw.bits.region <= UInt<1>("h00") io.slave[1].aw.bits.qos <= UInt<1>("h00") io.slave[1].aw.bits.prot <= UInt<1>("h00") io.slave[1].aw.bits.cache <= UInt<1>("h00") io.slave[1].aw.bits.lock <= UInt<1>("h00") io.slave[1].aw.bits.burst <= UInt<1>("h00") io.slave[1].aw.bits.size <= UInt<1>("h00") io.slave[1].aw.bits.len <= UInt<1>("h00") io.slave[1].aw.bits.addr <= UInt<1>("h00") io.slave[1].aw.valid <= UInt<1>("h00") io.slave[2].r.ready <= UInt<1>("h00") io.slave[2].ar.bits.user <= UInt<1>("h00") io.slave[2].ar.bits.id <= UInt<1>("h00") io.slave[2].ar.bits.region <= UInt<1>("h00") io.slave[2].ar.bits.qos <= UInt<1>("h00") io.slave[2].ar.bits.prot <= UInt<1>("h00") io.slave[2].ar.bits.cache <= UInt<1>("h00") io.slave[2].ar.bits.lock <= UInt<1>("h00") io.slave[2].ar.bits.burst <= UInt<1>("h00") io.slave[2].ar.bits.size <= UInt<1>("h00") io.slave[2].ar.bits.len <= UInt<1>("h00") io.slave[2].ar.bits.addr <= UInt<1>("h00") io.slave[2].ar.valid <= UInt<1>("h00") io.slave[2].b.ready <= UInt<1>("h00") io.slave[2].w.bits.user <= UInt<1>("h00") io.slave[2].w.bits.strb <= UInt<1>("h00") io.slave[2].w.bits.last <= UInt<1>("h00") io.slave[2].w.bits.data <= UInt<1>("h00") io.slave[2].w.valid <= UInt<1>("h00") io.slave[2].aw.bits.user <= UInt<1>("h00") io.slave[2].aw.bits.id <= UInt<1>("h00") io.slave[2].aw.bits.region <= UInt<1>("h00") io.slave[2].aw.bits.qos <= UInt<1>("h00") io.slave[2].aw.bits.prot <= UInt<1>("h00") io.slave[2].aw.bits.cache <= UInt<1>("h00") io.slave[2].aw.bits.lock <= UInt<1>("h00") io.slave[2].aw.bits.burst <= UInt<1>("h00") io.slave[2].aw.bits.size <= UInt<1>("h00") io.slave[2].aw.bits.len <= UInt<1>("h00") io.slave[2].aw.bits.addr <= UInt<1>("h00") io.slave[2].aw.valid <= UInt<1>("h00") io.slave[3].r.ready <= UInt<1>("h00") io.slave[3].ar.bits.user <= UInt<1>("h00") io.slave[3].ar.bits.id <= UInt<1>("h00") io.slave[3].ar.bits.region <= UInt<1>("h00") io.slave[3].ar.bits.qos <= UInt<1>("h00") io.slave[3].ar.bits.prot <= UInt<1>("h00") io.slave[3].ar.bits.cache <= UInt<1>("h00") io.slave[3].ar.bits.lock <= UInt<1>("h00") io.slave[3].ar.bits.burst <= UInt<1>("h00") io.slave[3].ar.bits.size <= UInt<1>("h00") io.slave[3].ar.bits.len <= UInt<1>("h00") io.slave[3].ar.bits.addr <= UInt<1>("h00") io.slave[3].ar.valid <= UInt<1>("h00") io.slave[3].b.ready <= UInt<1>("h00") io.slave[3].w.bits.user <= UInt<1>("h00") io.slave[3].w.bits.strb <= UInt<1>("h00") io.slave[3].w.bits.last <= UInt<1>("h00") io.slave[3].w.bits.data <= UInt<1>("h00") io.slave[3].w.valid <= UInt<1>("h00") io.slave[3].aw.bits.user <= UInt<1>("h00") io.slave[3].aw.bits.id <= UInt<1>("h00") io.slave[3].aw.bits.region <= UInt<1>("h00") io.slave[3].aw.bits.qos <= UInt<1>("h00") io.slave[3].aw.bits.prot <= UInt<1>("h00") io.slave[3].aw.bits.cache <= UInt<1>("h00") io.slave[3].aw.bits.lock <= UInt<1>("h00") io.slave[3].aw.bits.burst <= UInt<1>("h00") io.slave[3].aw.bits.size <= UInt<1>("h00") io.slave[3].aw.bits.len <= UInt<1>("h00") io.slave[3].aw.bits.addr <= UInt<1>("h00") io.slave[3].aw.valid <= UInt<1>("h00") io.master.r.bits.user <= UInt<1>("h00") io.master.r.bits.id <= UInt<1>("h00") io.master.r.bits.last <= UInt<1>("h00") io.master.r.bits.data <= UInt<1>("h00") io.master.r.bits.resp <= UInt<1>("h00") io.master.r.valid <= UInt<1>("h00") io.master.ar.ready <= UInt<1>("h00") io.master.b.bits.user <= UInt<1>("h00") io.master.b.bits.id <= UInt<1>("h00") io.master.b.bits.resp <= UInt<1>("h00") io.master.b.valid <= UInt<1>("h00") io.master.w.ready <= UInt<1>("h00") io.master.aw.ready <= UInt<1>("h00") node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1440 = and(T_1437, T_1439) node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000")) node T_1445 = and(T_1442, T_1444) node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000")) node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1450 = and(T_1447, T_1449) node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000")) node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000")) node T_1455 = and(T_1452, T_1454) wire T_1457 : UInt<1>[4] T_1457[0] <= T_1440 T_1457[1] <= T_1445 T_1457[2] <= T_1450 T_1457[3] <= T_1455 node T_1463 = cat(T_1457[3], T_1457[2]) node T_1464 = cat(T_1457[1], T_1457[0]) node ar_route = cat(T_1463, T_1464) node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00")) node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1470 = and(T_1467, T_1469) node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000")) node T_1475 = and(T_1472, T_1474) node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000")) node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1480 = and(T_1477, T_1479) node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000")) node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000")) node T_1485 = and(T_1482, T_1484) wire T_1487 : UInt<1>[4] T_1487[0] <= T_1470 T_1487[1] <= T_1475 T_1487[2] <= T_1480 T_1487[3] <= T_1485 node T_1493 = cat(T_1487[3], T_1487[2]) node T_1494 = cat(T_1487[1], T_1487[0]) node aw_route = cat(T_1493, T_1494) node T_1499 = bit(ar_route, 0) node T_1500 = and(io.master.ar.valid, T_1499) io.slave[0].ar.valid <= T_1500 io.slave[0].ar.bits <- io.master.ar.bits node T_1501 = bit(ar_route, 0) node T_1502 = and(io.slave[0].ar.ready, T_1501) node T_1503 = or(UInt<1>("h00"), T_1502) node T_1504 = bit(aw_route, 0) node T_1505 = and(io.master.aw.valid, T_1504) io.slave[0].aw.valid <= T_1505 io.slave[0].aw.bits <- io.master.aw.bits node T_1506 = bit(aw_route, 0) node T_1507 = and(io.slave[0].aw.ready, T_1506) node T_1508 = or(UInt<1>("h00"), T_1507) reg T_1510 : UInt<1>, clk, reset, UInt<1>("h00") node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1511 : T_1510 <= UInt<1>("h01") skip node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid) node T_1514 = and(T_1513, io.slave[0].w.bits.last) when T_1514 : T_1510 <= UInt<1>("h00") skip node T_1516 = and(io.master.w.valid, T_1510) io.slave[0].w.valid <= T_1516 io.slave[0].w.bits <- io.master.w.bits node T_1517 = and(io.slave[0].w.ready, T_1510) node T_1518 = or(UInt<1>("h00"), T_1517) node T_1519 = bit(ar_route, 1) node T_1520 = and(io.master.ar.valid, T_1519) io.slave[1].ar.valid <= T_1520 io.slave[1].ar.bits <- io.master.ar.bits node T_1521 = bit(ar_route, 1) node T_1522 = and(io.slave[1].ar.ready, T_1521) node T_1523 = or(T_1503, T_1522) node T_1524 = bit(aw_route, 1) node T_1525 = and(io.master.aw.valid, T_1524) io.slave[1].aw.valid <= T_1525 io.slave[1].aw.bits <- io.master.aw.bits node T_1526 = bit(aw_route, 1) node T_1527 = and(io.slave[1].aw.ready, T_1526) node T_1528 = or(T_1508, T_1527) reg T_1530 : UInt<1>, clk, reset, UInt<1>("h00") node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1531 : T_1530 <= UInt<1>("h01") skip node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid) node T_1534 = and(T_1533, io.slave[1].w.bits.last) when T_1534 : T_1530 <= UInt<1>("h00") skip node T_1536 = and(io.master.w.valid, T_1530) io.slave[1].w.valid <= T_1536 io.slave[1].w.bits <- io.master.w.bits node T_1537 = and(io.slave[1].w.ready, T_1530) node T_1538 = or(T_1518, T_1537) node T_1539 = bit(ar_route, 2) node T_1540 = and(io.master.ar.valid, T_1539) io.slave[2].ar.valid <= T_1540 io.slave[2].ar.bits <- io.master.ar.bits node T_1541 = bit(ar_route, 2) node T_1542 = and(io.slave[2].ar.ready, T_1541) node T_1543 = or(T_1523, T_1542) node T_1544 = bit(aw_route, 2) node T_1545 = and(io.master.aw.valid, T_1544) io.slave[2].aw.valid <= T_1545 io.slave[2].aw.bits <- io.master.aw.bits node T_1546 = bit(aw_route, 2) node T_1547 = and(io.slave[2].aw.ready, T_1546) node T_1548 = or(T_1528, T_1547) reg T_1550 : UInt<1>, clk, reset, UInt<1>("h00") node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1551 : T_1550 <= UInt<1>("h01") skip node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid) node T_1554 = and(T_1553, io.slave[2].w.bits.last) when T_1554 : T_1550 <= UInt<1>("h00") skip node T_1556 = and(io.master.w.valid, T_1550) io.slave[2].w.valid <= T_1556 io.slave[2].w.bits <- io.master.w.bits node T_1557 = and(io.slave[2].w.ready, T_1550) node T_1558 = or(T_1538, T_1557) node T_1559 = bit(ar_route, 3) node T_1560 = and(io.master.ar.valid, T_1559) io.slave[3].ar.valid <= T_1560 io.slave[3].ar.bits <- io.master.ar.bits node T_1561 = bit(ar_route, 3) node T_1562 = and(io.slave[3].ar.ready, T_1561) node ar_ready = or(T_1543, T_1562) node T_1564 = bit(aw_route, 3) node T_1565 = and(io.master.aw.valid, T_1564) io.slave[3].aw.valid <= T_1565 io.slave[3].aw.bits <- io.master.aw.bits node T_1566 = bit(aw_route, 3) node T_1567 = and(io.slave[3].aw.ready, T_1566) node aw_ready = or(T_1548, T_1567) reg T_1570 : UInt<1>, clk, reset, UInt<1>("h00") node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) when T_1571 : T_1570 <= UInt<1>("h01") skip node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid) node T_1574 = and(T_1573, io.slave[3].w.bits.last) when T_1574 : T_1570 <= UInt<1>("h00") skip node T_1576 = and(io.master.w.valid, T_1570) io.slave[3].w.valid <= T_1576 io.slave[3].w.bits <- io.master.w.bits node T_1577 = and(io.slave[3].w.ready, T_1570) node w_ready = or(T_1558, T_1577) node T_1580 = neq(ar_route, UInt<1>("h00")) node r_invalid = eq(T_1580, UInt<1>("h00")) node T_1584 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1584, UInt<1>("h00")) inst err_slave of NastiErrorSlave_40 err_slave.io.r.ready <= UInt<1>("h00") err_slave.io.ar.bits.user <= UInt<1>("h00") err_slave.io.ar.bits.id <= UInt<1>("h00") err_slave.io.ar.bits.region <= UInt<1>("h00") err_slave.io.ar.bits.qos <= UInt<1>("h00") err_slave.io.ar.bits.prot <= UInt<1>("h00") err_slave.io.ar.bits.cache <= UInt<1>("h00") err_slave.io.ar.bits.lock <= UInt<1>("h00") err_slave.io.ar.bits.burst <= UInt<1>("h00") err_slave.io.ar.bits.size <= UInt<1>("h00") err_slave.io.ar.bits.len <= UInt<1>("h00") err_slave.io.ar.bits.addr <= UInt<1>("h00") err_slave.io.ar.valid <= UInt<1>("h00") err_slave.io.b.ready <= UInt<1>("h00") err_slave.io.w.bits.user <= UInt<1>("h00") err_slave.io.w.bits.strb <= UInt<1>("h00") err_slave.io.w.bits.last <= UInt<1>("h00") err_slave.io.w.bits.data <= UInt<1>("h00") err_slave.io.w.valid <= UInt<1>("h00") err_slave.io.aw.bits.user <= UInt<1>("h00") err_slave.io.aw.bits.id <= UInt<1>("h00") err_slave.io.aw.bits.region <= UInt<1>("h00") err_slave.io.aw.bits.qos <= UInt<1>("h00") err_slave.io.aw.bits.prot <= UInt<1>("h00") err_slave.io.aw.bits.cache <= UInt<1>("h00") err_slave.io.aw.bits.lock <= UInt<1>("h00") err_slave.io.aw.bits.burst <= UInt<1>("h00") err_slave.io.aw.bits.size <= UInt<1>("h00") err_slave.io.aw.bits.len <= UInt<1>("h00") err_slave.io.aw.bits.addr <= UInt<1>("h00") err_slave.io.aw.valid <= UInt<1>("h00") err_slave.clk <= clk err_slave.reset <= reset node T_1619 = and(r_invalid, io.master.ar.valid) err_slave.io.ar.valid <= T_1619 err_slave.io.ar.bits <- io.master.ar.bits node T_1620 = and(w_invalid, io.master.aw.valid) err_slave.io.aw.valid <= T_1620 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits node T_1621 = and(r_invalid, err_slave.io.ar.ready) node T_1622 = or(ar_ready, T_1621) io.master.ar.ready <= T_1622 node T_1623 = and(w_invalid, err_slave.io.aw.ready) node T_1624 = or(aw_ready, T_1623) io.master.aw.ready <= T_1624 node T_1625 = or(w_ready, err_slave.io.w.ready) io.master.w.ready <= T_1625 inst b_arb of RRArbiter_38 b_arb.io.out.ready <= UInt<1>("h00") b_arb.io.in[0].bits.user <= UInt<1>("h00") b_arb.io.in[0].bits.id <= UInt<1>("h00") b_arb.io.in[0].bits.resp <= UInt<1>("h00") b_arb.io.in[0].valid <= UInt<1>("h00") b_arb.io.in[1].bits.user <= UInt<1>("h00") b_arb.io.in[1].bits.id <= UInt<1>("h00") b_arb.io.in[1].bits.resp <= UInt<1>("h00") b_arb.io.in[1].valid <= UInt<1>("h00") b_arb.io.in[2].bits.user <= UInt<1>("h00") b_arb.io.in[2].bits.id <= UInt<1>("h00") b_arb.io.in[2].bits.resp <= UInt<1>("h00") b_arb.io.in[2].valid <= UInt<1>("h00") b_arb.io.in[3].bits.user <= UInt<1>("h00") b_arb.io.in[3].bits.id <= UInt<1>("h00") b_arb.io.in[3].bits.resp <= UInt<1>("h00") b_arb.io.in[3].valid <= UInt<1>("h00") b_arb.io.in[4].bits.user <= UInt<1>("h00") b_arb.io.in[4].bits.id <= UInt<1>("h00") b_arb.io.in[4].bits.resp <= UInt<1>("h00") b_arb.io.in[4].valid <= UInt<1>("h00") b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter r_arb.io.out.ready <= UInt<1>("h00") r_arb.io.in[0].bits.user <= UInt<1>("h00") r_arb.io.in[0].bits.id <= UInt<1>("h00") r_arb.io.in[0].bits.last <= UInt<1>("h00") r_arb.io.in[0].bits.data <= UInt<1>("h00") r_arb.io.in[0].bits.resp <= UInt<1>("h00") r_arb.io.in[0].valid <= UInt<1>("h00") r_arb.io.in[1].bits.user <= UInt<1>("h00") r_arb.io.in[1].bits.id <= UInt<1>("h00") r_arb.io.in[1].bits.last <= UInt<1>("h00") r_arb.io.in[1].bits.data <= UInt<1>("h00") r_arb.io.in[1].bits.resp <= UInt<1>("h00") r_arb.io.in[1].valid <= UInt<1>("h00") r_arb.io.in[2].bits.user <= UInt<1>("h00") r_arb.io.in[2].bits.id <= UInt<1>("h00") r_arb.io.in[2].bits.last <= UInt<1>("h00") r_arb.io.in[2].bits.data <= UInt<1>("h00") r_arb.io.in[2].bits.resp <= UInt<1>("h00") r_arb.io.in[2].valid <= UInt<1>("h00") r_arb.io.in[3].bits.user <= UInt<1>("h00") r_arb.io.in[3].bits.id <= UInt<1>("h00") r_arb.io.in[3].bits.last <= UInt<1>("h00") r_arb.io.in[3].bits.data <= UInt<1>("h00") r_arb.io.in[3].bits.resp <= UInt<1>("h00") r_arb.io.in[3].valid <= UInt<1>("h00") r_arb.io.in[4].bits.user <= UInt<1>("h00") r_arb.io.in[4].bits.id <= UInt<1>("h00") r_arb.io.in[4].bits.last <= UInt<1>("h00") r_arb.io.in[4].bits.data <= UInt<1>("h00") r_arb.io.in[4].bits.resp <= UInt<1>("h00") r_arb.io.in[4].valid <= UInt<1>("h00") r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b r_arb.io.in[0] <- io.slave[0].r b_arb.io.in[1] <- io.slave[1].b r_arb.io.in[1] <- io.slave[1].r b_arb.io.in[2] <- io.slave[2].b r_arb.io.in[2] <- io.slave[2].r b_arb.io.in[3] <- io.slave[3].b r_arb.io.in[3] <- io.slave[3].r b_arb.io.in[4] <- err_slave.io.b r_arb.io.in[4] <- err_slave.io.r io.master.b <- b_arb.io.out io.master.r <- r_arb.io.out module RRArbiter_45 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.user <= UInt<1>("h00") io.out.bits.id <= UInt<1>("h00") io.out.bits.region <= UInt<1>("h00") io.out.bits.qos <= UInt<1>("h00") io.out.bits.prot <= UInt<1>("h00") io.out.bits.cache <= UInt<1>("h00") io.out.bits.lock <= UInt<1>("h00") io.out.bits.burst <= UInt<1>("h00") io.out.bits.size <= UInt<1>("h00") io.out.bits.len <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_306 : UInt<1> T_306 <= UInt<1>("h00") io.out.valid <= io.in[T_306].valid io.out.bits <- io.in[T_306].bits io.chosen <= T_306 io.in[T_306].ready <= UInt<1>("h00") reg T_392 : UInt<1>, clk, reset, UInt<1>("h00") node T_393 = gt(UInt<1>("h00"), T_392) node T_394 = and(io.in[0].valid, T_393) node T_396 = gt(UInt<1>("h01"), T_392) node T_397 = and(io.in[1].valid, T_396) node T_400 = or(UInt<1>("h00"), T_394) node T_402 = eq(T_400, UInt<1>("h00")) node T_404 = or(UInt<1>("h00"), T_394) node T_405 = or(T_404, T_397) node T_407 = eq(T_405, UInt<1>("h00")) node T_409 = or(UInt<1>("h00"), T_394) node T_410 = or(T_409, T_397) node T_411 = or(T_410, io.in[0].valid) node T_413 = eq(T_411, UInt<1>("h00")) node T_415 = gt(UInt<1>("h00"), T_392) node T_416 = and(UInt<1>("h01"), T_415) node T_417 = or(T_416, T_407) node T_419 = gt(UInt<1>("h01"), T_392) node T_420 = and(T_402, T_419) node T_421 = or(T_420, T_413) node T_423 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_424 = mux(UInt<1>("h00"), T_423, T_417) node T_425 = and(T_424, io.out.ready) io.in[0].ready <= T_425 node T_427 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_428 = mux(UInt<1>("h00"), T_427, T_421) node T_429 = and(T_428, io.out.ready) io.in[1].ready <= T_429 node T_432 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_434 = gt(UInt<1>("h01"), T_392) node T_435 = and(io.in[1].valid, T_434) node T_437 = mux(T_435, UInt<1>("h01"), T_432) node T_438 = mux(UInt<1>("h00"), UInt<1>("h01"), T_437) T_306 <= T_438 node T_439 = and(io.out.ready, io.out.valid) when T_439 : T_392 <= T_306 skip module NastiArbiter : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} io.slave.r.ready <= UInt<1>("h00") io.slave.ar.bits.user <= UInt<1>("h00") io.slave.ar.bits.id <= UInt<1>("h00") io.slave.ar.bits.region <= UInt<1>("h00") io.slave.ar.bits.qos <= UInt<1>("h00") io.slave.ar.bits.prot <= UInt<1>("h00") io.slave.ar.bits.cache <= UInt<1>("h00") io.slave.ar.bits.lock <= UInt<1>("h00") io.slave.ar.bits.burst <= UInt<1>("h00") io.slave.ar.bits.size <= UInt<1>("h00") io.slave.ar.bits.len <= UInt<1>("h00") io.slave.ar.bits.addr <= UInt<1>("h00") io.slave.ar.valid <= UInt<1>("h00") io.slave.b.ready <= UInt<1>("h00") io.slave.w.bits.user <= UInt<1>("h00") io.slave.w.bits.strb <= UInt<1>("h00") io.slave.w.bits.last <= UInt<1>("h00") io.slave.w.bits.data <= UInt<1>("h00") io.slave.w.valid <= UInt<1>("h00") io.slave.aw.bits.user <= UInt<1>("h00") io.slave.aw.bits.id <= UInt<1>("h00") io.slave.aw.bits.region <= UInt<1>("h00") io.slave.aw.bits.qos <= UInt<1>("h00") io.slave.aw.bits.prot <= UInt<1>("h00") io.slave.aw.bits.cache <= UInt<1>("h00") io.slave.aw.bits.lock <= UInt<1>("h00") io.slave.aw.bits.burst <= UInt<1>("h00") io.slave.aw.bits.size <= UInt<1>("h00") io.slave.aw.bits.len <= UInt<1>("h00") io.slave.aw.bits.addr <= UInt<1>("h00") io.slave.aw.valid <= UInt<1>("h00") io.master[0].r.bits.user <= UInt<1>("h00") io.master[0].r.bits.id <= UInt<1>("h00") io.master[0].r.bits.last <= UInt<1>("h00") io.master[0].r.bits.data <= UInt<1>("h00") io.master[0].r.bits.resp <= UInt<1>("h00") io.master[0].r.valid <= UInt<1>("h00") io.master[0].ar.ready <= UInt<1>("h00") io.master[0].b.bits.user <= UInt<1>("h00") io.master[0].b.bits.id <= UInt<1>("h00") io.master[0].b.bits.resp <= UInt<1>("h00") io.master[0].b.valid <= UInt<1>("h00") io.master[0].w.ready <= UInt<1>("h00") io.master[0].aw.ready <= UInt<1>("h00") io.master[1].r.bits.user <= UInt<1>("h00") io.master[1].r.bits.id <= UInt<1>("h00") io.master[1].r.bits.last <= UInt<1>("h00") io.master[1].r.bits.data <= UInt<1>("h00") io.master[1].r.bits.resp <= UInt<1>("h00") io.master[1].r.valid <= UInt<1>("h00") io.master[1].ar.ready <= UInt<1>("h00") io.master[1].b.bits.user <= UInt<1>("h00") io.master[1].b.bits.id <= UInt<1>("h00") io.master[1].b.bits.resp <= UInt<1>("h00") io.master[1].b.valid <= UInt<1>("h00") io.master[1].w.ready <= UInt<1>("h00") io.master[1].aw.ready <= UInt<1>("h00") inst T_1767 of RRArbiter_45 T_1767.io.out.ready <= UInt<1>("h00") T_1767.io.in[0].bits.user <= UInt<1>("h00") T_1767.io.in[0].bits.id <= UInt<1>("h00") T_1767.io.in[0].bits.region <= UInt<1>("h00") T_1767.io.in[0].bits.qos <= UInt<1>("h00") T_1767.io.in[0].bits.prot <= UInt<1>("h00") T_1767.io.in[0].bits.cache <= UInt<1>("h00") T_1767.io.in[0].bits.lock <= UInt<1>("h00") T_1767.io.in[0].bits.burst <= UInt<1>("h00") T_1767.io.in[0].bits.size <= UInt<1>("h00") T_1767.io.in[0].bits.len <= UInt<1>("h00") T_1767.io.in[0].bits.addr <= UInt<1>("h00") T_1767.io.in[0].valid <= UInt<1>("h00") T_1767.io.in[1].bits.user <= UInt<1>("h00") T_1767.io.in[1].bits.id <= UInt<1>("h00") T_1767.io.in[1].bits.region <= UInt<1>("h00") T_1767.io.in[1].bits.qos <= UInt<1>("h00") T_1767.io.in[1].bits.prot <= UInt<1>("h00") T_1767.io.in[1].bits.cache <= UInt<1>("h00") T_1767.io.in[1].bits.lock <= UInt<1>("h00") T_1767.io.in[1].bits.burst <= UInt<1>("h00") T_1767.io.in[1].bits.size <= UInt<1>("h00") T_1767.io.in[1].bits.len <= UInt<1>("h00") T_1767.io.in[1].bits.addr <= UInt<1>("h00") T_1767.io.in[1].valid <= UInt<1>("h00") T_1767.clk <= clk T_1767.reset <= reset inst T_1805 of RRArbiter_45 T_1805.io.out.ready <= UInt<1>("h00") T_1805.io.in[0].bits.user <= UInt<1>("h00") T_1805.io.in[0].bits.id <= UInt<1>("h00") T_1805.io.in[0].bits.region <= UInt<1>("h00") T_1805.io.in[0].bits.qos <= UInt<1>("h00") T_1805.io.in[0].bits.prot <= UInt<1>("h00") T_1805.io.in[0].bits.cache <= UInt<1>("h00") T_1805.io.in[0].bits.lock <= UInt<1>("h00") T_1805.io.in[0].bits.burst <= UInt<1>("h00") T_1805.io.in[0].bits.size <= UInt<1>("h00") T_1805.io.in[0].bits.len <= UInt<1>("h00") T_1805.io.in[0].bits.addr <= UInt<1>("h00") T_1805.io.in[0].valid <= UInt<1>("h00") T_1805.io.in[1].bits.user <= UInt<1>("h00") T_1805.io.in[1].bits.id <= UInt<1>("h00") T_1805.io.in[1].bits.region <= UInt<1>("h00") T_1805.io.in[1].bits.qos <= UInt<1>("h00") T_1805.io.in[1].bits.prot <= UInt<1>("h00") T_1805.io.in[1].bits.cache <= UInt<1>("h00") T_1805.io.in[1].bits.lock <= UInt<1>("h00") T_1805.io.in[1].bits.burst <= UInt<1>("h00") T_1805.io.in[1].bits.size <= UInt<1>("h00") T_1805.io.in[1].bits.len <= UInt<1>("h00") T_1805.io.in[1].bits.addr <= UInt<1>("h00") T_1805.io.in[1].valid <= UInt<1>("h00") T_1805.clk <= clk T_1805.reset <= reset node T_1831 = bits(io.slave.r.bits.id, 0, 0) node T_1832 = bits(io.slave.b.bits.id, 0, 0) reg T_1834 : UInt<1>, clk, UInt<1>("h00"), T_1834 reg T_1836 : UInt<1>, clk, reset, UInt<1>("h01") node T_1837 = and(T_1805.io.out.ready, T_1805.io.out.valid) when T_1837 : T_1834 <= T_1805.io.chosen T_1836 <= UInt<1>("h00") skip node T_1839 = and(io.slave.w.ready, io.slave.w.valid) node T_1840 = and(T_1839, io.slave.w.bits.last) when T_1840 : T_1836 <= UInt<1>("h01") skip T_1767.io.in[0] <- io.master[0].ar node T_1843 = cat(io.master[0].ar.bits.id, UInt<1>("h00")) T_1767.io.in[0].bits.id <= T_1843 T_1805.io.in[0] <- io.master[0].aw node T_1845 = cat(io.master[0].aw.bits.id, UInt<1>("h00")) T_1805.io.in[0].bits.id <= T_1845 node T_1847 = eq(T_1831, UInt<1>("h00")) node T_1848 = and(io.slave.r.valid, T_1847) io.master[0].r.valid <= T_1848 io.master[0].r.bits <- io.slave.r.bits node T_1850 = dshr(io.slave.r.bits.id, UInt<1>("h01")) io.master[0].r.bits.id <= T_1850 node T_1852 = eq(T_1832, UInt<1>("h00")) node T_1853 = and(io.slave.b.valid, T_1852) io.master[0].b.valid <= T_1853 io.master[0].b.bits <- io.slave.b.bits node T_1855 = dshr(io.slave.b.bits.id, UInt<1>("h01")) io.master[0].b.bits.id <= T_1855 node T_1857 = eq(T_1834, UInt<1>("h00")) node T_1858 = and(io.slave.w.ready, T_1857) node T_1860 = eq(T_1836, UInt<1>("h00")) node T_1861 = and(T_1858, T_1860) io.master[0].w.ready <= T_1861 T_1767.io.in[1] <- io.master[1].ar node T_1863 = cat(io.master[1].ar.bits.id, UInt<1>("h01")) T_1767.io.in[1].bits.id <= T_1863 T_1805.io.in[1] <- io.master[1].aw node T_1865 = cat(io.master[1].aw.bits.id, UInt<1>("h01")) T_1805.io.in[1].bits.id <= T_1865 node T_1867 = eq(T_1831, UInt<1>("h01")) node T_1868 = and(io.slave.r.valid, T_1867) io.master[1].r.valid <= T_1868 io.master[1].r.bits <- io.slave.r.bits node T_1870 = dshr(io.slave.r.bits.id, UInt<1>("h01")) io.master[1].r.bits.id <= T_1870 node T_1872 = eq(T_1832, UInt<1>("h01")) node T_1873 = and(io.slave.b.valid, T_1872) io.master[1].b.valid <= T_1873 io.master[1].b.bits <- io.slave.b.bits node T_1875 = dshr(io.slave.b.bits.id, UInt<1>("h01")) io.master[1].b.bits.id <= T_1875 node T_1877 = eq(T_1834, UInt<1>("h01")) node T_1878 = and(io.slave.w.ready, T_1877) node T_1880 = eq(T_1836, UInt<1>("h00")) node T_1881 = and(T_1878, T_1880) io.master[1].w.ready <= T_1881 io.slave.r.ready <= io.master[T_1831].r.ready io.slave.b.ready <= io.master[T_1832].b.ready io.slave.w.bits <- io.master[T_1834].w.bits node T_2519 = eq(T_1836, UInt<1>("h00")) node T_2520 = and(io.master[T_1834].w.valid, T_2519) io.slave.w.valid <= T_2520 io.slave.ar <- T_1767.io.out io.slave.aw.bits <- T_1805.io.out.bits node T_2521 = and(T_1805.io.out.valid, T_1836) io.slave.aw.valid <= T_2521 node T_2522 = and(io.slave.aw.ready, T_1836) T_1805.io.out.ready <= T_2522 module NastiCrossbar : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} io.slaves[0].r.ready <= UInt<1>("h00") io.slaves[0].ar.bits.user <= UInt<1>("h00") io.slaves[0].ar.bits.id <= UInt<1>("h00") io.slaves[0].ar.bits.region <= UInt<1>("h00") io.slaves[0].ar.bits.qos <= UInt<1>("h00") io.slaves[0].ar.bits.prot <= UInt<1>("h00") io.slaves[0].ar.bits.cache <= UInt<1>("h00") io.slaves[0].ar.bits.lock <= UInt<1>("h00") io.slaves[0].ar.bits.burst <= UInt<1>("h00") io.slaves[0].ar.bits.size <= UInt<1>("h00") io.slaves[0].ar.bits.len <= UInt<1>("h00") io.slaves[0].ar.bits.addr <= UInt<1>("h00") io.slaves[0].ar.valid <= UInt<1>("h00") io.slaves[0].b.ready <= UInt<1>("h00") io.slaves[0].w.bits.user <= UInt<1>("h00") io.slaves[0].w.bits.strb <= UInt<1>("h00") io.slaves[0].w.bits.last <= UInt<1>("h00") io.slaves[0].w.bits.data <= UInt<1>("h00") io.slaves[0].w.valid <= UInt<1>("h00") io.slaves[0].aw.bits.user <= UInt<1>("h00") io.slaves[0].aw.bits.id <= UInt<1>("h00") io.slaves[0].aw.bits.region <= UInt<1>("h00") io.slaves[0].aw.bits.qos <= UInt<1>("h00") io.slaves[0].aw.bits.prot <= UInt<1>("h00") io.slaves[0].aw.bits.cache <= UInt<1>("h00") io.slaves[0].aw.bits.lock <= UInt<1>("h00") io.slaves[0].aw.bits.burst <= UInt<1>("h00") io.slaves[0].aw.bits.size <= UInt<1>("h00") io.slaves[0].aw.bits.len <= UInt<1>("h00") io.slaves[0].aw.bits.addr <= UInt<1>("h00") io.slaves[0].aw.valid <= UInt<1>("h00") io.slaves[1].r.ready <= UInt<1>("h00") io.slaves[1].ar.bits.user <= UInt<1>("h00") io.slaves[1].ar.bits.id <= UInt<1>("h00") io.slaves[1].ar.bits.region <= UInt<1>("h00") io.slaves[1].ar.bits.qos <= UInt<1>("h00") io.slaves[1].ar.bits.prot <= UInt<1>("h00") io.slaves[1].ar.bits.cache <= UInt<1>("h00") io.slaves[1].ar.bits.lock <= UInt<1>("h00") io.slaves[1].ar.bits.burst <= UInt<1>("h00") io.slaves[1].ar.bits.size <= UInt<1>("h00") io.slaves[1].ar.bits.len <= UInt<1>("h00") io.slaves[1].ar.bits.addr <= UInt<1>("h00") io.slaves[1].ar.valid <= UInt<1>("h00") io.slaves[1].b.ready <= UInt<1>("h00") io.slaves[1].w.bits.user <= UInt<1>("h00") io.slaves[1].w.bits.strb <= UInt<1>("h00") io.slaves[1].w.bits.last <= UInt<1>("h00") io.slaves[1].w.bits.data <= UInt<1>("h00") io.slaves[1].w.valid <= UInt<1>("h00") io.slaves[1].aw.bits.user <= UInt<1>("h00") io.slaves[1].aw.bits.id <= UInt<1>("h00") io.slaves[1].aw.bits.region <= UInt<1>("h00") io.slaves[1].aw.bits.qos <= UInt<1>("h00") io.slaves[1].aw.bits.prot <= UInt<1>("h00") io.slaves[1].aw.bits.cache <= UInt<1>("h00") io.slaves[1].aw.bits.lock <= UInt<1>("h00") io.slaves[1].aw.bits.burst <= UInt<1>("h00") io.slaves[1].aw.bits.size <= UInt<1>("h00") io.slaves[1].aw.bits.len <= UInt<1>("h00") io.slaves[1].aw.bits.addr <= UInt<1>("h00") io.slaves[1].aw.valid <= UInt<1>("h00") io.slaves[2].r.ready <= UInt<1>("h00") io.slaves[2].ar.bits.user <= UInt<1>("h00") io.slaves[2].ar.bits.id <= UInt<1>("h00") io.slaves[2].ar.bits.region <= UInt<1>("h00") io.slaves[2].ar.bits.qos <= UInt<1>("h00") io.slaves[2].ar.bits.prot <= UInt<1>("h00") io.slaves[2].ar.bits.cache <= UInt<1>("h00") io.slaves[2].ar.bits.lock <= UInt<1>("h00") io.slaves[2].ar.bits.burst <= UInt<1>("h00") io.slaves[2].ar.bits.size <= UInt<1>("h00") io.slaves[2].ar.bits.len <= UInt<1>("h00") io.slaves[2].ar.bits.addr <= UInt<1>("h00") io.slaves[2].ar.valid <= UInt<1>("h00") io.slaves[2].b.ready <= UInt<1>("h00") io.slaves[2].w.bits.user <= UInt<1>("h00") io.slaves[2].w.bits.strb <= UInt<1>("h00") io.slaves[2].w.bits.last <= UInt<1>("h00") io.slaves[2].w.bits.data <= UInt<1>("h00") io.slaves[2].w.valid <= UInt<1>("h00") io.slaves[2].aw.bits.user <= UInt<1>("h00") io.slaves[2].aw.bits.id <= UInt<1>("h00") io.slaves[2].aw.bits.region <= UInt<1>("h00") io.slaves[2].aw.bits.qos <= UInt<1>("h00") io.slaves[2].aw.bits.prot <= UInt<1>("h00") io.slaves[2].aw.bits.cache <= UInt<1>("h00") io.slaves[2].aw.bits.lock <= UInt<1>("h00") io.slaves[2].aw.bits.burst <= UInt<1>("h00") io.slaves[2].aw.bits.size <= UInt<1>("h00") io.slaves[2].aw.bits.len <= UInt<1>("h00") io.slaves[2].aw.bits.addr <= UInt<1>("h00") io.slaves[2].aw.valid <= UInt<1>("h00") io.slaves[3].r.ready <= UInt<1>("h00") io.slaves[3].ar.bits.user <= UInt<1>("h00") io.slaves[3].ar.bits.id <= UInt<1>("h00") io.slaves[3].ar.bits.region <= UInt<1>("h00") io.slaves[3].ar.bits.qos <= UInt<1>("h00") io.slaves[3].ar.bits.prot <= UInt<1>("h00") io.slaves[3].ar.bits.cache <= UInt<1>("h00") io.slaves[3].ar.bits.lock <= UInt<1>("h00") io.slaves[3].ar.bits.burst <= UInt<1>("h00") io.slaves[3].ar.bits.size <= UInt<1>("h00") io.slaves[3].ar.bits.len <= UInt<1>("h00") io.slaves[3].ar.bits.addr <= UInt<1>("h00") io.slaves[3].ar.valid <= UInt<1>("h00") io.slaves[3].b.ready <= UInt<1>("h00") io.slaves[3].w.bits.user <= UInt<1>("h00") io.slaves[3].w.bits.strb <= UInt<1>("h00") io.slaves[3].w.bits.last <= UInt<1>("h00") io.slaves[3].w.bits.data <= UInt<1>("h00") io.slaves[3].w.valid <= UInt<1>("h00") io.slaves[3].aw.bits.user <= UInt<1>("h00") io.slaves[3].aw.bits.id <= UInt<1>("h00") io.slaves[3].aw.bits.region <= UInt<1>("h00") io.slaves[3].aw.bits.qos <= UInt<1>("h00") io.slaves[3].aw.bits.prot <= UInt<1>("h00") io.slaves[3].aw.bits.cache <= UInt<1>("h00") io.slaves[3].aw.bits.lock <= UInt<1>("h00") io.slaves[3].aw.bits.burst <= UInt<1>("h00") io.slaves[3].aw.bits.size <= UInt<1>("h00") io.slaves[3].aw.bits.len <= UInt<1>("h00") io.slaves[3].aw.bits.addr <= UInt<1>("h00") io.slaves[3].aw.valid <= UInt<1>("h00") io.masters[0].r.bits.user <= UInt<1>("h00") io.masters[0].r.bits.id <= UInt<1>("h00") io.masters[0].r.bits.last <= UInt<1>("h00") io.masters[0].r.bits.data <= UInt<1>("h00") io.masters[0].r.bits.resp <= UInt<1>("h00") io.masters[0].r.valid <= UInt<1>("h00") io.masters[0].ar.ready <= UInt<1>("h00") io.masters[0].b.bits.user <= UInt<1>("h00") io.masters[0].b.bits.id <= UInt<1>("h00") io.masters[0].b.bits.resp <= UInt<1>("h00") io.masters[0].b.valid <= UInt<1>("h00") io.masters[0].w.ready <= UInt<1>("h00") io.masters[0].aw.ready <= UInt<1>("h00") io.masters[1].r.bits.user <= UInt<1>("h00") io.masters[1].r.bits.id <= UInt<1>("h00") io.masters[1].r.bits.last <= UInt<1>("h00") io.masters[1].r.bits.data <= UInt<1>("h00") io.masters[1].r.bits.resp <= UInt<1>("h00") io.masters[1].r.valid <= UInt<1>("h00") io.masters[1].ar.ready <= UInt<1>("h00") io.masters[1].b.bits.user <= UInt<1>("h00") io.masters[1].b.bits.id <= UInt<1>("h00") io.masters[1].b.bits.resp <= UInt<1>("h00") io.masters[1].b.valid <= UInt<1>("h00") io.masters[1].w.ready <= UInt<1>("h00") io.masters[1].aw.ready <= UInt<1>("h00") inst T_2710 of NastiRouter T_2710.io.slave[0].r.bits.user <= UInt<1>("h00") T_2710.io.slave[0].r.bits.id <= UInt<1>("h00") T_2710.io.slave[0].r.bits.last <= UInt<1>("h00") T_2710.io.slave[0].r.bits.data <= UInt<1>("h00") T_2710.io.slave[0].r.bits.resp <= UInt<1>("h00") T_2710.io.slave[0].r.valid <= UInt<1>("h00") T_2710.io.slave[0].ar.ready <= UInt<1>("h00") T_2710.io.slave[0].b.bits.user <= UInt<1>("h00") T_2710.io.slave[0].b.bits.id <= UInt<1>("h00") T_2710.io.slave[0].b.bits.resp <= UInt<1>("h00") T_2710.io.slave[0].b.valid <= UInt<1>("h00") T_2710.io.slave[0].w.ready <= UInt<1>("h00") T_2710.io.slave[0].aw.ready <= UInt<1>("h00") T_2710.io.slave[1].r.bits.user <= UInt<1>("h00") T_2710.io.slave[1].r.bits.id <= UInt<1>("h00") T_2710.io.slave[1].r.bits.last <= UInt<1>("h00") T_2710.io.slave[1].r.bits.data <= UInt<1>("h00") T_2710.io.slave[1].r.bits.resp <= UInt<1>("h00") T_2710.io.slave[1].r.valid <= UInt<1>("h00") T_2710.io.slave[1].ar.ready <= UInt<1>("h00") T_2710.io.slave[1].b.bits.user <= UInt<1>("h00") T_2710.io.slave[1].b.bits.id <= UInt<1>("h00") T_2710.io.slave[1].b.bits.resp <= UInt<1>("h00") T_2710.io.slave[1].b.valid <= UInt<1>("h00") T_2710.io.slave[1].w.ready <= UInt<1>("h00") T_2710.io.slave[1].aw.ready <= UInt<1>("h00") T_2710.io.slave[2].r.bits.user <= UInt<1>("h00") T_2710.io.slave[2].r.bits.id <= UInt<1>("h00") T_2710.io.slave[2].r.bits.last <= UInt<1>("h00") T_2710.io.slave[2].r.bits.data <= UInt<1>("h00") T_2710.io.slave[2].r.bits.resp <= UInt<1>("h00") T_2710.io.slave[2].r.valid <= UInt<1>("h00") T_2710.io.slave[2].ar.ready <= UInt<1>("h00") T_2710.io.slave[2].b.bits.user <= UInt<1>("h00") T_2710.io.slave[2].b.bits.id <= UInt<1>("h00") T_2710.io.slave[2].b.bits.resp <= UInt<1>("h00") T_2710.io.slave[2].b.valid <= UInt<1>("h00") T_2710.io.slave[2].w.ready <= UInt<1>("h00") T_2710.io.slave[2].aw.ready <= UInt<1>("h00") T_2710.io.slave[3].r.bits.user <= UInt<1>("h00") T_2710.io.slave[3].r.bits.id <= UInt<1>("h00") T_2710.io.slave[3].r.bits.last <= UInt<1>("h00") T_2710.io.slave[3].r.bits.data <= UInt<1>("h00") T_2710.io.slave[3].r.bits.resp <= UInt<1>("h00") T_2710.io.slave[3].r.valid <= UInt<1>("h00") T_2710.io.slave[3].ar.ready <= UInt<1>("h00") T_2710.io.slave[3].b.bits.user <= UInt<1>("h00") T_2710.io.slave[3].b.bits.id <= UInt<1>("h00") T_2710.io.slave[3].b.bits.resp <= UInt<1>("h00") T_2710.io.slave[3].b.valid <= UInt<1>("h00") T_2710.io.slave[3].w.ready <= UInt<1>("h00") T_2710.io.slave[3].aw.ready <= UInt<1>("h00") T_2710.io.master.r.ready <= UInt<1>("h00") T_2710.io.master.ar.bits.user <= UInt<1>("h00") T_2710.io.master.ar.bits.id <= UInt<1>("h00") T_2710.io.master.ar.bits.region <= UInt<1>("h00") T_2710.io.master.ar.bits.qos <= UInt<1>("h00") T_2710.io.master.ar.bits.prot <= UInt<1>("h00") T_2710.io.master.ar.bits.cache <= UInt<1>("h00") T_2710.io.master.ar.bits.lock <= UInt<1>("h00") T_2710.io.master.ar.bits.burst <= UInt<1>("h00") T_2710.io.master.ar.bits.size <= UInt<1>("h00") T_2710.io.master.ar.bits.len <= UInt<1>("h00") T_2710.io.master.ar.bits.addr <= UInt<1>("h00") T_2710.io.master.ar.valid <= UInt<1>("h00") T_2710.io.master.b.ready <= UInt<1>("h00") T_2710.io.master.w.bits.user <= UInt<1>("h00") T_2710.io.master.w.bits.strb <= UInt<1>("h00") T_2710.io.master.w.bits.last <= UInt<1>("h00") T_2710.io.master.w.bits.data <= UInt<1>("h00") T_2710.io.master.w.valid <= UInt<1>("h00") T_2710.io.master.aw.bits.user <= UInt<1>("h00") T_2710.io.master.aw.bits.id <= UInt<1>("h00") T_2710.io.master.aw.bits.region <= UInt<1>("h00") T_2710.io.master.aw.bits.qos <= UInt<1>("h00") T_2710.io.master.aw.bits.prot <= UInt<1>("h00") T_2710.io.master.aw.bits.cache <= UInt<1>("h00") T_2710.io.master.aw.bits.lock <= UInt<1>("h00") T_2710.io.master.aw.bits.burst <= UInt<1>("h00") T_2710.io.master.aw.bits.size <= UInt<1>("h00") T_2710.io.master.aw.bits.len <= UInt<1>("h00") T_2710.io.master.aw.bits.addr <= UInt<1>("h00") T_2710.io.master.aw.valid <= UInt<1>("h00") T_2710.clk <= clk T_2710.reset <= reset inst T_2794 of NastiRouter_39 T_2794.io.slave[0].r.bits.user <= UInt<1>("h00") T_2794.io.slave[0].r.bits.id <= UInt<1>("h00") T_2794.io.slave[0].r.bits.last <= UInt<1>("h00") T_2794.io.slave[0].r.bits.data <= UInt<1>("h00") T_2794.io.slave[0].r.bits.resp <= UInt<1>("h00") T_2794.io.slave[0].r.valid <= UInt<1>("h00") T_2794.io.slave[0].ar.ready <= UInt<1>("h00") T_2794.io.slave[0].b.bits.user <= UInt<1>("h00") T_2794.io.slave[0].b.bits.id <= UInt<1>("h00") T_2794.io.slave[0].b.bits.resp <= UInt<1>("h00") T_2794.io.slave[0].b.valid <= UInt<1>("h00") T_2794.io.slave[0].w.ready <= UInt<1>("h00") T_2794.io.slave[0].aw.ready <= UInt<1>("h00") T_2794.io.slave[1].r.bits.user <= UInt<1>("h00") T_2794.io.slave[1].r.bits.id <= UInt<1>("h00") T_2794.io.slave[1].r.bits.last <= UInt<1>("h00") T_2794.io.slave[1].r.bits.data <= UInt<1>("h00") T_2794.io.slave[1].r.bits.resp <= UInt<1>("h00") T_2794.io.slave[1].r.valid <= UInt<1>("h00") T_2794.io.slave[1].ar.ready <= UInt<1>("h00") T_2794.io.slave[1].b.bits.user <= UInt<1>("h00") T_2794.io.slave[1].b.bits.id <= UInt<1>("h00") T_2794.io.slave[1].b.bits.resp <= UInt<1>("h00") T_2794.io.slave[1].b.valid <= UInt<1>("h00") T_2794.io.slave[1].w.ready <= UInt<1>("h00") T_2794.io.slave[1].aw.ready <= UInt<1>("h00") T_2794.io.slave[2].r.bits.user <= UInt<1>("h00") T_2794.io.slave[2].r.bits.id <= UInt<1>("h00") T_2794.io.slave[2].r.bits.last <= UInt<1>("h00") T_2794.io.slave[2].r.bits.data <= UInt<1>("h00") T_2794.io.slave[2].r.bits.resp <= UInt<1>("h00") T_2794.io.slave[2].r.valid <= UInt<1>("h00") T_2794.io.slave[2].ar.ready <= UInt<1>("h00") T_2794.io.slave[2].b.bits.user <= UInt<1>("h00") T_2794.io.slave[2].b.bits.id <= UInt<1>("h00") T_2794.io.slave[2].b.bits.resp <= UInt<1>("h00") T_2794.io.slave[2].b.valid <= UInt<1>("h00") T_2794.io.slave[2].w.ready <= UInt<1>("h00") T_2794.io.slave[2].aw.ready <= UInt<1>("h00") T_2794.io.slave[3].r.bits.user <= UInt<1>("h00") T_2794.io.slave[3].r.bits.id <= UInt<1>("h00") T_2794.io.slave[3].r.bits.last <= UInt<1>("h00") T_2794.io.slave[3].r.bits.data <= UInt<1>("h00") T_2794.io.slave[3].r.bits.resp <= UInt<1>("h00") T_2794.io.slave[3].r.valid <= UInt<1>("h00") T_2794.io.slave[3].ar.ready <= UInt<1>("h00") T_2794.io.slave[3].b.bits.user <= UInt<1>("h00") T_2794.io.slave[3].b.bits.id <= UInt<1>("h00") T_2794.io.slave[3].b.bits.resp <= UInt<1>("h00") T_2794.io.slave[3].b.valid <= UInt<1>("h00") T_2794.io.slave[3].w.ready <= UInt<1>("h00") T_2794.io.slave[3].aw.ready <= UInt<1>("h00") T_2794.io.master.r.ready <= UInt<1>("h00") T_2794.io.master.ar.bits.user <= UInt<1>("h00") T_2794.io.master.ar.bits.id <= UInt<1>("h00") T_2794.io.master.ar.bits.region <= UInt<1>("h00") T_2794.io.master.ar.bits.qos <= UInt<1>("h00") T_2794.io.master.ar.bits.prot <= UInt<1>("h00") T_2794.io.master.ar.bits.cache <= UInt<1>("h00") T_2794.io.master.ar.bits.lock <= UInt<1>("h00") T_2794.io.master.ar.bits.burst <= UInt<1>("h00") T_2794.io.master.ar.bits.size <= UInt<1>("h00") T_2794.io.master.ar.bits.len <= UInt<1>("h00") T_2794.io.master.ar.bits.addr <= UInt<1>("h00") T_2794.io.master.ar.valid <= UInt<1>("h00") T_2794.io.master.b.ready <= UInt<1>("h00") T_2794.io.master.w.bits.user <= UInt<1>("h00") T_2794.io.master.w.bits.strb <= UInt<1>("h00") T_2794.io.master.w.bits.last <= UInt<1>("h00") T_2794.io.master.w.bits.data <= UInt<1>("h00") T_2794.io.master.w.valid <= UInt<1>("h00") T_2794.io.master.aw.bits.user <= UInt<1>("h00") T_2794.io.master.aw.bits.id <= UInt<1>("h00") T_2794.io.master.aw.bits.region <= UInt<1>("h00") T_2794.io.master.aw.bits.qos <= UInt<1>("h00") T_2794.io.master.aw.bits.prot <= UInt<1>("h00") T_2794.io.master.aw.bits.cache <= UInt<1>("h00") T_2794.io.master.aw.bits.lock <= UInt<1>("h00") T_2794.io.master.aw.bits.burst <= UInt<1>("h00") T_2794.io.master.aw.bits.size <= UInt<1>("h00") T_2794.io.master.aw.bits.len <= UInt<1>("h00") T_2794.io.master.aw.bits.addr <= UInt<1>("h00") T_2794.io.master.aw.valid <= UInt<1>("h00") T_2794.clk <= clk T_2794.reset <= reset wire T_4312 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2] T_4312[0] <- T_2710.io T_4312[1] <- T_2794.io inst T_8615 of NastiArbiter T_8615.io.slave.r.bits.user <= UInt<1>("h00") T_8615.io.slave.r.bits.id <= UInt<1>("h00") T_8615.io.slave.r.bits.last <= UInt<1>("h00") T_8615.io.slave.r.bits.data <= UInt<1>("h00") T_8615.io.slave.r.bits.resp <= UInt<1>("h00") T_8615.io.slave.r.valid <= UInt<1>("h00") T_8615.io.slave.ar.ready <= UInt<1>("h00") T_8615.io.slave.b.bits.user <= UInt<1>("h00") T_8615.io.slave.b.bits.id <= UInt<1>("h00") T_8615.io.slave.b.bits.resp <= UInt<1>("h00") T_8615.io.slave.b.valid <= UInt<1>("h00") T_8615.io.slave.w.ready <= UInt<1>("h00") T_8615.io.slave.aw.ready <= UInt<1>("h00") T_8615.io.master[0].r.ready <= UInt<1>("h00") T_8615.io.master[0].ar.bits.user <= UInt<1>("h00") T_8615.io.master[0].ar.bits.id <= UInt<1>("h00") T_8615.io.master[0].ar.bits.region <= UInt<1>("h00") T_8615.io.master[0].ar.bits.qos <= UInt<1>("h00") T_8615.io.master[0].ar.bits.prot <= UInt<1>("h00") T_8615.io.master[0].ar.bits.cache <= UInt<1>("h00") T_8615.io.master[0].ar.bits.lock <= UInt<1>("h00") T_8615.io.master[0].ar.bits.burst <= UInt<1>("h00") T_8615.io.master[0].ar.bits.size <= UInt<1>("h00") T_8615.io.master[0].ar.bits.len <= UInt<1>("h00") T_8615.io.master[0].ar.bits.addr <= UInt<1>("h00") T_8615.io.master[0].ar.valid <= UInt<1>("h00") T_8615.io.master[0].b.ready <= UInt<1>("h00") T_8615.io.master[0].w.bits.user <= UInt<1>("h00") T_8615.io.master[0].w.bits.strb <= UInt<1>("h00") T_8615.io.master[0].w.bits.last <= UInt<1>("h00") T_8615.io.master[0].w.bits.data <= UInt<1>("h00") T_8615.io.master[0].w.valid <= UInt<1>("h00") T_8615.io.master[0].aw.bits.user <= UInt<1>("h00") T_8615.io.master[0].aw.bits.id <= UInt<1>("h00") T_8615.io.master[0].aw.bits.region <= UInt<1>("h00") T_8615.io.master[0].aw.bits.qos <= UInt<1>("h00") T_8615.io.master[0].aw.bits.prot <= UInt<1>("h00") T_8615.io.master[0].aw.bits.cache <= UInt<1>("h00") T_8615.io.master[0].aw.bits.lock <= UInt<1>("h00") T_8615.io.master[0].aw.bits.burst <= UInt<1>("h00") T_8615.io.master[0].aw.bits.size <= UInt<1>("h00") T_8615.io.master[0].aw.bits.len <= UInt<1>("h00") T_8615.io.master[0].aw.bits.addr <= UInt<1>("h00") T_8615.io.master[0].aw.valid <= UInt<1>("h00") T_8615.io.master[1].r.ready <= UInt<1>("h00") T_8615.io.master[1].ar.bits.user <= UInt<1>("h00") T_8615.io.master[1].ar.bits.id <= UInt<1>("h00") T_8615.io.master[1].ar.bits.region <= UInt<1>("h00") T_8615.io.master[1].ar.bits.qos <= UInt<1>("h00") T_8615.io.master[1].ar.bits.prot <= UInt<1>("h00") T_8615.io.master[1].ar.bits.cache <= UInt<1>("h00") T_8615.io.master[1].ar.bits.lock <= UInt<1>("h00") T_8615.io.master[1].ar.bits.burst <= UInt<1>("h00") T_8615.io.master[1].ar.bits.size <= UInt<1>("h00") T_8615.io.master[1].ar.bits.len <= UInt<1>("h00") T_8615.io.master[1].ar.bits.addr <= UInt<1>("h00") T_8615.io.master[1].ar.valid <= UInt<1>("h00") T_8615.io.master[1].b.ready <= UInt<1>("h00") T_8615.io.master[1].w.bits.user <= UInt<1>("h00") T_8615.io.master[1].w.bits.strb <= UInt<1>("h00") T_8615.io.master[1].w.bits.last <= UInt<1>("h00") T_8615.io.master[1].w.bits.data <= UInt<1>("h00") T_8615.io.master[1].w.valid <= UInt<1>("h00") T_8615.io.master[1].aw.bits.user <= UInt<1>("h00") T_8615.io.master[1].aw.bits.id <= UInt<1>("h00") T_8615.io.master[1].aw.bits.region <= UInt<1>("h00") T_8615.io.master[1].aw.bits.qos <= UInt<1>("h00") T_8615.io.master[1].aw.bits.prot <= UInt<1>("h00") T_8615.io.master[1].aw.bits.cache <= UInt<1>("h00") T_8615.io.master[1].aw.bits.lock <= UInt<1>("h00") T_8615.io.master[1].aw.bits.burst <= UInt<1>("h00") T_8615.io.master[1].aw.bits.size <= UInt<1>("h00") T_8615.io.master[1].aw.bits.len <= UInt<1>("h00") T_8615.io.master[1].aw.bits.addr <= UInt<1>("h00") T_8615.io.master[1].aw.valid <= UInt<1>("h00") T_8615.clk <= clk T_8615.reset <= reset inst T_8691 of NastiArbiter T_8691.io.slave.r.bits.user <= UInt<1>("h00") T_8691.io.slave.r.bits.id <= UInt<1>("h00") T_8691.io.slave.r.bits.last <= UInt<1>("h00") T_8691.io.slave.r.bits.data <= UInt<1>("h00") T_8691.io.slave.r.bits.resp <= UInt<1>("h00") T_8691.io.slave.r.valid <= UInt<1>("h00") T_8691.io.slave.ar.ready <= UInt<1>("h00") T_8691.io.slave.b.bits.user <= UInt<1>("h00") T_8691.io.slave.b.bits.id <= UInt<1>("h00") T_8691.io.slave.b.bits.resp <= UInt<1>("h00") T_8691.io.slave.b.valid <= UInt<1>("h00") T_8691.io.slave.w.ready <= UInt<1>("h00") T_8691.io.slave.aw.ready <= UInt<1>("h00") T_8691.io.master[0].r.ready <= UInt<1>("h00") T_8691.io.master[0].ar.bits.user <= UInt<1>("h00") T_8691.io.master[0].ar.bits.id <= UInt<1>("h00") T_8691.io.master[0].ar.bits.region <= UInt<1>("h00") T_8691.io.master[0].ar.bits.qos <= UInt<1>("h00") T_8691.io.master[0].ar.bits.prot <= UInt<1>("h00") T_8691.io.master[0].ar.bits.cache <= UInt<1>("h00") T_8691.io.master[0].ar.bits.lock <= UInt<1>("h00") T_8691.io.master[0].ar.bits.burst <= UInt<1>("h00") T_8691.io.master[0].ar.bits.size <= UInt<1>("h00") T_8691.io.master[0].ar.bits.len <= UInt<1>("h00") T_8691.io.master[0].ar.bits.addr <= UInt<1>("h00") T_8691.io.master[0].ar.valid <= UInt<1>("h00") T_8691.io.master[0].b.ready <= UInt<1>("h00") T_8691.io.master[0].w.bits.user <= UInt<1>("h00") T_8691.io.master[0].w.bits.strb <= UInt<1>("h00") T_8691.io.master[0].w.bits.last <= UInt<1>("h00") T_8691.io.master[0].w.bits.data <= UInt<1>("h00") T_8691.io.master[0].w.valid <= UInt<1>("h00") T_8691.io.master[0].aw.bits.user <= UInt<1>("h00") T_8691.io.master[0].aw.bits.id <= UInt<1>("h00") T_8691.io.master[0].aw.bits.region <= UInt<1>("h00") T_8691.io.master[0].aw.bits.qos <= UInt<1>("h00") T_8691.io.master[0].aw.bits.prot <= UInt<1>("h00") T_8691.io.master[0].aw.bits.cache <= UInt<1>("h00") T_8691.io.master[0].aw.bits.lock <= UInt<1>("h00") T_8691.io.master[0].aw.bits.burst <= UInt<1>("h00") T_8691.io.master[0].aw.bits.size <= UInt<1>("h00") T_8691.io.master[0].aw.bits.len <= UInt<1>("h00") T_8691.io.master[0].aw.bits.addr <= UInt<1>("h00") T_8691.io.master[0].aw.valid <= UInt<1>("h00") T_8691.io.master[1].r.ready <= UInt<1>("h00") T_8691.io.master[1].ar.bits.user <= UInt<1>("h00") T_8691.io.master[1].ar.bits.id <= UInt<1>("h00") T_8691.io.master[1].ar.bits.region <= UInt<1>("h00") T_8691.io.master[1].ar.bits.qos <= UInt<1>("h00") T_8691.io.master[1].ar.bits.prot <= UInt<1>("h00") T_8691.io.master[1].ar.bits.cache <= UInt<1>("h00") T_8691.io.master[1].ar.bits.lock <= UInt<1>("h00") T_8691.io.master[1].ar.bits.burst <= UInt<1>("h00") T_8691.io.master[1].ar.bits.size <= UInt<1>("h00") T_8691.io.master[1].ar.bits.len <= UInt<1>("h00") T_8691.io.master[1].ar.bits.addr <= UInt<1>("h00") T_8691.io.master[1].ar.valid <= UInt<1>("h00") T_8691.io.master[1].b.ready <= UInt<1>("h00") T_8691.io.master[1].w.bits.user <= UInt<1>("h00") T_8691.io.master[1].w.bits.strb <= UInt<1>("h00") T_8691.io.master[1].w.bits.last <= UInt<1>("h00") T_8691.io.master[1].w.bits.data <= UInt<1>("h00") T_8691.io.master[1].w.valid <= UInt<1>("h00") T_8691.io.master[1].aw.bits.user <= UInt<1>("h00") T_8691.io.master[1].aw.bits.id <= UInt<1>("h00") T_8691.io.master[1].aw.bits.region <= UInt<1>("h00") T_8691.io.master[1].aw.bits.qos <= UInt<1>("h00") T_8691.io.master[1].aw.bits.prot <= UInt<1>("h00") T_8691.io.master[1].aw.bits.cache <= UInt<1>("h00") T_8691.io.master[1].aw.bits.lock <= UInt<1>("h00") T_8691.io.master[1].aw.bits.burst <= UInt<1>("h00") T_8691.io.master[1].aw.bits.size <= UInt<1>("h00") T_8691.io.master[1].aw.bits.len <= UInt<1>("h00") T_8691.io.master[1].aw.bits.addr <= UInt<1>("h00") T_8691.io.master[1].aw.valid <= UInt<1>("h00") T_8691.clk <= clk T_8691.reset <= reset inst T_8767 of NastiArbiter T_8767.io.slave.r.bits.user <= UInt<1>("h00") T_8767.io.slave.r.bits.id <= UInt<1>("h00") T_8767.io.slave.r.bits.last <= UInt<1>("h00") T_8767.io.slave.r.bits.data <= UInt<1>("h00") T_8767.io.slave.r.bits.resp <= UInt<1>("h00") T_8767.io.slave.r.valid <= UInt<1>("h00") T_8767.io.slave.ar.ready <= UInt<1>("h00") T_8767.io.slave.b.bits.user <= UInt<1>("h00") T_8767.io.slave.b.bits.id <= UInt<1>("h00") T_8767.io.slave.b.bits.resp <= UInt<1>("h00") T_8767.io.slave.b.valid <= UInt<1>("h00") T_8767.io.slave.w.ready <= UInt<1>("h00") T_8767.io.slave.aw.ready <= UInt<1>("h00") T_8767.io.master[0].r.ready <= UInt<1>("h00") T_8767.io.master[0].ar.bits.user <= UInt<1>("h00") T_8767.io.master[0].ar.bits.id <= UInt<1>("h00") T_8767.io.master[0].ar.bits.region <= UInt<1>("h00") T_8767.io.master[0].ar.bits.qos <= UInt<1>("h00") T_8767.io.master[0].ar.bits.prot <= UInt<1>("h00") T_8767.io.master[0].ar.bits.cache <= UInt<1>("h00") T_8767.io.master[0].ar.bits.lock <= UInt<1>("h00") T_8767.io.master[0].ar.bits.burst <= UInt<1>("h00") T_8767.io.master[0].ar.bits.size <= UInt<1>("h00") T_8767.io.master[0].ar.bits.len <= UInt<1>("h00") T_8767.io.master[0].ar.bits.addr <= UInt<1>("h00") T_8767.io.master[0].ar.valid <= UInt<1>("h00") T_8767.io.master[0].b.ready <= UInt<1>("h00") T_8767.io.master[0].w.bits.user <= UInt<1>("h00") T_8767.io.master[0].w.bits.strb <= UInt<1>("h00") T_8767.io.master[0].w.bits.last <= UInt<1>("h00") T_8767.io.master[0].w.bits.data <= UInt<1>("h00") T_8767.io.master[0].w.valid <= UInt<1>("h00") T_8767.io.master[0].aw.bits.user <= UInt<1>("h00") T_8767.io.master[0].aw.bits.id <= UInt<1>("h00") T_8767.io.master[0].aw.bits.region <= UInt<1>("h00") T_8767.io.master[0].aw.bits.qos <= UInt<1>("h00") T_8767.io.master[0].aw.bits.prot <= UInt<1>("h00") T_8767.io.master[0].aw.bits.cache <= UInt<1>("h00") T_8767.io.master[0].aw.bits.lock <= UInt<1>("h00") T_8767.io.master[0].aw.bits.burst <= UInt<1>("h00") T_8767.io.master[0].aw.bits.size <= UInt<1>("h00") T_8767.io.master[0].aw.bits.len <= UInt<1>("h00") T_8767.io.master[0].aw.bits.addr <= UInt<1>("h00") T_8767.io.master[0].aw.valid <= UInt<1>("h00") T_8767.io.master[1].r.ready <= UInt<1>("h00") T_8767.io.master[1].ar.bits.user <= UInt<1>("h00") T_8767.io.master[1].ar.bits.id <= UInt<1>("h00") T_8767.io.master[1].ar.bits.region <= UInt<1>("h00") T_8767.io.master[1].ar.bits.qos <= UInt<1>("h00") T_8767.io.master[1].ar.bits.prot <= UInt<1>("h00") T_8767.io.master[1].ar.bits.cache <= UInt<1>("h00") T_8767.io.master[1].ar.bits.lock <= UInt<1>("h00") T_8767.io.master[1].ar.bits.burst <= UInt<1>("h00") T_8767.io.master[1].ar.bits.size <= UInt<1>("h00") T_8767.io.master[1].ar.bits.len <= UInt<1>("h00") T_8767.io.master[1].ar.bits.addr <= UInt<1>("h00") T_8767.io.master[1].ar.valid <= UInt<1>("h00") T_8767.io.master[1].b.ready <= UInt<1>("h00") T_8767.io.master[1].w.bits.user <= UInt<1>("h00") T_8767.io.master[1].w.bits.strb <= UInt<1>("h00") T_8767.io.master[1].w.bits.last <= UInt<1>("h00") T_8767.io.master[1].w.bits.data <= UInt<1>("h00") T_8767.io.master[1].w.valid <= UInt<1>("h00") T_8767.io.master[1].aw.bits.user <= UInt<1>("h00") T_8767.io.master[1].aw.bits.id <= UInt<1>("h00") T_8767.io.master[1].aw.bits.region <= UInt<1>("h00") T_8767.io.master[1].aw.bits.qos <= UInt<1>("h00") T_8767.io.master[1].aw.bits.prot <= UInt<1>("h00") T_8767.io.master[1].aw.bits.cache <= UInt<1>("h00") T_8767.io.master[1].aw.bits.lock <= UInt<1>("h00") T_8767.io.master[1].aw.bits.burst <= UInt<1>("h00") T_8767.io.master[1].aw.bits.size <= UInt<1>("h00") T_8767.io.master[1].aw.bits.len <= UInt<1>("h00") T_8767.io.master[1].aw.bits.addr <= UInt<1>("h00") T_8767.io.master[1].aw.valid <= UInt<1>("h00") T_8767.clk <= clk T_8767.reset <= reset inst T_8843 of NastiArbiter T_8843.io.slave.r.bits.user <= UInt<1>("h00") T_8843.io.slave.r.bits.id <= UInt<1>("h00") T_8843.io.slave.r.bits.last <= UInt<1>("h00") T_8843.io.slave.r.bits.data <= UInt<1>("h00") T_8843.io.slave.r.bits.resp <= UInt<1>("h00") T_8843.io.slave.r.valid <= UInt<1>("h00") T_8843.io.slave.ar.ready <= UInt<1>("h00") T_8843.io.slave.b.bits.user <= UInt<1>("h00") T_8843.io.slave.b.bits.id <= UInt<1>("h00") T_8843.io.slave.b.bits.resp <= UInt<1>("h00") T_8843.io.slave.b.valid <= UInt<1>("h00") T_8843.io.slave.w.ready <= UInt<1>("h00") T_8843.io.slave.aw.ready <= UInt<1>("h00") T_8843.io.master[0].r.ready <= UInt<1>("h00") T_8843.io.master[0].ar.bits.user <= UInt<1>("h00") T_8843.io.master[0].ar.bits.id <= UInt<1>("h00") T_8843.io.master[0].ar.bits.region <= UInt<1>("h00") T_8843.io.master[0].ar.bits.qos <= UInt<1>("h00") T_8843.io.master[0].ar.bits.prot <= UInt<1>("h00") T_8843.io.master[0].ar.bits.cache <= UInt<1>("h00") T_8843.io.master[0].ar.bits.lock <= UInt<1>("h00") T_8843.io.master[0].ar.bits.burst <= UInt<1>("h00") T_8843.io.master[0].ar.bits.size <= UInt<1>("h00") T_8843.io.master[0].ar.bits.len <= UInt<1>("h00") T_8843.io.master[0].ar.bits.addr <= UInt<1>("h00") T_8843.io.master[0].ar.valid <= UInt<1>("h00") T_8843.io.master[0].b.ready <= UInt<1>("h00") T_8843.io.master[0].w.bits.user <= UInt<1>("h00") T_8843.io.master[0].w.bits.strb <= UInt<1>("h00") T_8843.io.master[0].w.bits.last <= UInt<1>("h00") T_8843.io.master[0].w.bits.data <= UInt<1>("h00") T_8843.io.master[0].w.valid <= UInt<1>("h00") T_8843.io.master[0].aw.bits.user <= UInt<1>("h00") T_8843.io.master[0].aw.bits.id <= UInt<1>("h00") T_8843.io.master[0].aw.bits.region <= UInt<1>("h00") T_8843.io.master[0].aw.bits.qos <= UInt<1>("h00") T_8843.io.master[0].aw.bits.prot <= UInt<1>("h00") T_8843.io.master[0].aw.bits.cache <= UInt<1>("h00") T_8843.io.master[0].aw.bits.lock <= UInt<1>("h00") T_8843.io.master[0].aw.bits.burst <= UInt<1>("h00") T_8843.io.master[0].aw.bits.size <= UInt<1>("h00") T_8843.io.master[0].aw.bits.len <= UInt<1>("h00") T_8843.io.master[0].aw.bits.addr <= UInt<1>("h00") T_8843.io.master[0].aw.valid <= UInt<1>("h00") T_8843.io.master[1].r.ready <= UInt<1>("h00") T_8843.io.master[1].ar.bits.user <= UInt<1>("h00") T_8843.io.master[1].ar.bits.id <= UInt<1>("h00") T_8843.io.master[1].ar.bits.region <= UInt<1>("h00") T_8843.io.master[1].ar.bits.qos <= UInt<1>("h00") T_8843.io.master[1].ar.bits.prot <= UInt<1>("h00") T_8843.io.master[1].ar.bits.cache <= UInt<1>("h00") T_8843.io.master[1].ar.bits.lock <= UInt<1>("h00") T_8843.io.master[1].ar.bits.burst <= UInt<1>("h00") T_8843.io.master[1].ar.bits.size <= UInt<1>("h00") T_8843.io.master[1].ar.bits.len <= UInt<1>("h00") T_8843.io.master[1].ar.bits.addr <= UInt<1>("h00") T_8843.io.master[1].ar.valid <= UInt<1>("h00") T_8843.io.master[1].b.ready <= UInt<1>("h00") T_8843.io.master[1].w.bits.user <= UInt<1>("h00") T_8843.io.master[1].w.bits.strb <= UInt<1>("h00") T_8843.io.master[1].w.bits.last <= UInt<1>("h00") T_8843.io.master[1].w.bits.data <= UInt<1>("h00") T_8843.io.master[1].w.valid <= UInt<1>("h00") T_8843.io.master[1].aw.bits.user <= UInt<1>("h00") T_8843.io.master[1].aw.bits.id <= UInt<1>("h00") T_8843.io.master[1].aw.bits.region <= UInt<1>("h00") T_8843.io.master[1].aw.bits.qos <= UInt<1>("h00") T_8843.io.master[1].aw.bits.prot <= UInt<1>("h00") T_8843.io.master[1].aw.bits.cache <= UInt<1>("h00") T_8843.io.master[1].aw.bits.lock <= UInt<1>("h00") T_8843.io.master[1].aw.bits.burst <= UInt<1>("h00") T_8843.io.master[1].aw.bits.size <= UInt<1>("h00") T_8843.io.master[1].aw.bits.len <= UInt<1>("h00") T_8843.io.master[1].aw.bits.addr <= UInt<1>("h00") T_8843.io.master[1].aw.valid <= UInt<1>("h00") T_8843.clk <= clk T_8843.reset <= reset wire T_10672 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4] T_10672[0] <- T_8615.io T_10672[1] <- T_8691.io T_10672[2] <- T_8767.io T_10672[3] <- T_8843.io T_4312[0].master <- io.masters[0] T_4312[1].master <- io.masters[1] wire T_19597 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] T_19597[0] <- T_4312[0].slave[0] T_19597[1] <- T_4312[1].slave[0] T_10672[0].master <- T_19597 io.slaves[0] <- T_10672[0].slave wire T_20234 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] T_20234[0] <- T_4312[0].slave[1] T_20234[1] <- T_4312[1].slave[1] T_10672[1].master <- T_20234 io.slaves[1] <- T_10672[1].slave wire T_20871 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] T_20871[0] <- T_4312[0].slave[2] T_20871[1] <- T_4312[1].slave[2] T_10672[2].master <- T_20871 io.slaves[2] <- T_10672[2].slave wire T_21508 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] T_21508[0] <- T_4312[0].slave[3] T_21508[1] <- T_4312[1].slave[3] T_10672[3].master <- T_21508 io.slaves[3] <- T_10672[3].slave module RRArbiter_62 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.user <= UInt<1>("h00") io.out.bits.id <= UInt<1>("h00") io.out.bits.resp <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") wire T_174 : UInt<2> T_174 <= UInt<1>("h00") io.out.valid <= io.in[T_174].valid io.out.bits <- io.in[T_174].bits io.chosen <= T_174 io.in[T_174].ready <= UInt<1>("h00") reg T_212 : UInt<2>, clk, reset, UInt<2>("h00") node T_213 = gt(UInt<1>("h00"), T_212) node T_214 = and(io.in[0].valid, T_213) node T_216 = gt(UInt<1>("h01"), T_212) node T_217 = and(io.in[1].valid, T_216) node T_219 = gt(UInt<2>("h02"), T_212) node T_220 = and(io.in[2].valid, T_219) node T_222 = gt(UInt<2>("h03"), T_212) node T_223 = and(io.in[3].valid, T_222) node T_226 = or(UInt<1>("h00"), T_214) node T_228 = eq(T_226, UInt<1>("h00")) node T_230 = or(UInt<1>("h00"), T_214) node T_231 = or(T_230, T_217) node T_233 = eq(T_231, UInt<1>("h00")) node T_235 = or(UInt<1>("h00"), T_214) node T_236 = or(T_235, T_217) node T_237 = or(T_236, T_220) node T_239 = eq(T_237, UInt<1>("h00")) node T_241 = or(UInt<1>("h00"), T_214) node T_242 = or(T_241, T_217) node T_243 = or(T_242, T_220) node T_244 = or(T_243, T_223) node T_246 = eq(T_244, UInt<1>("h00")) node T_248 = or(UInt<1>("h00"), T_214) node T_249 = or(T_248, T_217) node T_250 = or(T_249, T_220) node T_251 = or(T_250, T_223) node T_252 = or(T_251, io.in[0].valid) node T_254 = eq(T_252, UInt<1>("h00")) node T_256 = or(UInt<1>("h00"), T_214) node T_257 = or(T_256, T_217) node T_258 = or(T_257, T_220) node T_259 = or(T_258, T_223) node T_260 = or(T_259, io.in[0].valid) node T_261 = or(T_260, io.in[1].valid) node T_263 = eq(T_261, UInt<1>("h00")) node T_265 = or(UInt<1>("h00"), T_214) node T_266 = or(T_265, T_217) node T_267 = or(T_266, T_220) node T_268 = or(T_267, T_223) node T_269 = or(T_268, io.in[0].valid) node T_270 = or(T_269, io.in[1].valid) node T_271 = or(T_270, io.in[2].valid) node T_273 = eq(T_271, UInt<1>("h00")) node T_275 = gt(UInt<1>("h00"), T_212) node T_276 = and(UInt<1>("h01"), T_275) node T_277 = or(T_276, T_246) node T_279 = gt(UInt<1>("h01"), T_212) node T_280 = and(T_228, T_279) node T_281 = or(T_280, T_254) node T_283 = gt(UInt<2>("h02"), T_212) node T_284 = and(T_233, T_283) node T_285 = or(T_284, T_263) node T_287 = gt(UInt<2>("h03"), T_212) node T_288 = and(T_239, T_287) node T_289 = or(T_288, T_273) node T_291 = eq(UInt<2>("h03"), UInt<1>("h00")) node T_292 = mux(UInt<1>("h00"), T_291, T_277) node T_293 = and(T_292, io.out.ready) io.in[0].ready <= T_293 node T_295 = eq(UInt<2>("h03"), UInt<1>("h01")) node T_296 = mux(UInt<1>("h00"), T_295, T_281) node T_297 = and(T_296, io.out.ready) io.in[1].ready <= T_297 node T_299 = eq(UInt<2>("h03"), UInt<2>("h02")) node T_300 = mux(UInt<1>("h00"), T_299, T_285) node T_301 = and(T_300, io.out.ready) io.in[2].ready <= T_301 node T_303 = eq(UInt<2>("h03"), UInt<2>("h03")) node T_304 = mux(UInt<1>("h00"), T_303, T_289) node T_305 = and(T_304, io.out.ready) io.in[3].ready <= T_305 node T_308 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) node T_310 = mux(io.in[1].valid, UInt<1>("h01"), T_308) node T_312 = mux(io.in[0].valid, UInt<1>("h00"), T_310) node T_314 = gt(UInt<2>("h03"), T_212) node T_315 = and(io.in[3].valid, T_314) node T_317 = mux(T_315, UInt<2>("h03"), T_312) node T_319 = gt(UInt<2>("h02"), T_212) node T_320 = and(io.in[2].valid, T_319) node T_322 = mux(T_320, UInt<2>("h02"), T_317) node T_324 = gt(UInt<1>("h01"), T_212) node T_325 = and(io.in[1].valid, T_324) node T_327 = mux(T_325, UInt<1>("h01"), T_322) node T_328 = mux(UInt<1>("h00"), UInt<2>("h03"), T_327) T_174 <= T_328 node T_329 = and(io.out.ready, io.out.valid) when T_329 : T_212 <= T_174 skip module JunctionsPeekingArbiter_63 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.out.bits.user <= UInt<1>("h00") io.out.bits.id <= UInt<1>("h00") io.out.bits.last <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.resp <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") reg T_243 : UInt<2>, clk, reset, UInt<2>("h00") reg T_245 : UInt<1>, clk, reset, UInt<1>("h00") wire T_247 : UInt<1>[4] T_247[0] <= io.in[0].valid T_247[1] <= io.in[1].valid T_247[2] <= io.in[2].valid T_247[3] <= io.in[3].valid node T_254 = addw(T_243, UInt<1>("h01")) node T_256 = lt(T_254, UInt<3>("h04")) node T_258 = addw(UInt<1>("h00"), T_254) node T_261 = subw(T_254, UInt<3>("h04")) node T_263 = mux(T_256, T_247[T_258], T_247[T_261]) node T_265 = lt(T_254, UInt<2>("h03")) node T_267 = addw(UInt<1>("h01"), T_254) node T_270 = subw(T_254, UInt<2>("h03")) node T_272 = mux(T_265, T_247[T_267], T_247[T_270]) node T_274 = lt(T_254, UInt<2>("h02")) node T_276 = addw(UInt<2>("h02"), T_254) node T_279 = subw(T_254, UInt<2>("h02")) node T_281 = mux(T_274, T_247[T_276], T_247[T_279]) node T_283 = lt(T_254, UInt<1>("h01")) node T_285 = addw(UInt<2>("h03"), T_254) node T_288 = subw(T_254, UInt<1>("h01")) node T_290 = mux(T_283, T_247[T_285], T_247[T_288]) wire T_292 : UInt<1>[4] T_292[0] <= T_263 T_292[1] <= T_272 T_292[2] <= T_281 T_292[3] <= T_290 wire T_303 : UInt<2>[4] T_303[0] <= UInt<1>("h00") T_303[1] <= UInt<1>("h01") T_303[2] <= UInt<2>("h02") T_303[3] <= UInt<2>("h03") node T_310 = addw(T_243, UInt<1>("h01")) node T_312 = lt(T_310, UInt<3>("h04")) node T_314 = addw(UInt<1>("h00"), T_310) node T_317 = subw(T_310, UInt<3>("h04")) node T_319 = mux(T_312, T_303[T_314], T_303[T_317]) node T_321 = lt(T_310, UInt<2>("h03")) node T_323 = addw(UInt<1>("h01"), T_310) node T_326 = subw(T_310, UInt<2>("h03")) node T_328 = mux(T_321, T_303[T_323], T_303[T_326]) node T_330 = lt(T_310, UInt<2>("h02")) node T_332 = addw(UInt<2>("h02"), T_310) node T_335 = subw(T_310, UInt<2>("h02")) node T_337 = mux(T_330, T_303[T_332], T_303[T_335]) node T_339 = lt(T_310, UInt<1>("h01")) node T_341 = addw(UInt<2>("h03"), T_310) node T_344 = subw(T_310, UInt<1>("h01")) node T_346 = mux(T_339, T_303[T_341], T_303[T_344]) wire T_348 : UInt<2>[4] T_348[0] <= T_319 T_348[1] <= T_328 T_348[2] <= T_337 T_348[3] <= T_346 node T_354 = mux(T_292[2], T_348[2], T_348[3]) node T_355 = mux(T_292[1], T_348[1], T_354) node T_356 = mux(T_292[0], T_348[0], T_355) node T_357 = mux(T_245, T_243, T_356) node T_359 = eq(T_357, UInt<1>("h00")) node T_360 = and(io.out.ready, T_359) io.in[0].ready <= T_360 node T_362 = eq(T_357, UInt<1>("h01")) node T_363 = and(io.out.ready, T_362) io.in[1].ready <= T_363 node T_365 = eq(T_357, UInt<2>("h02")) node T_366 = and(io.out.ready, T_365) io.in[2].ready <= T_366 node T_368 = eq(T_357, UInt<2>("h03")) node T_369 = and(io.out.ready, T_368) io.in[3].ready <= T_369 io.out.valid <= io.in[T_357].valid io.out.bits <- io.in[T_357].bits node T_400 = and(io.out.ready, io.out.valid) when T_400 : node T_402 = eq(T_245, UInt<1>("h00")) node T_404 = and(T_402, UInt<1>("h01")) when T_404 : T_243 <= T_356 T_245 <= UInt<1>("h01") skip when io.out.bits.last : T_245 <= UInt<1>("h00") skip skip module NastiRouter_58 : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} io.slave[0].r.ready <= UInt<1>("h00") io.slave[0].ar.bits.user <= UInt<1>("h00") io.slave[0].ar.bits.id <= UInt<1>("h00") io.slave[0].ar.bits.region <= UInt<1>("h00") io.slave[0].ar.bits.qos <= UInt<1>("h00") io.slave[0].ar.bits.prot <= UInt<1>("h00") io.slave[0].ar.bits.cache <= UInt<1>("h00") io.slave[0].ar.bits.lock <= UInt<1>("h00") io.slave[0].ar.bits.burst <= UInt<1>("h00") io.slave[0].ar.bits.size <= UInt<1>("h00") io.slave[0].ar.bits.len <= UInt<1>("h00") io.slave[0].ar.bits.addr <= UInt<1>("h00") io.slave[0].ar.valid <= UInt<1>("h00") io.slave[0].b.ready <= UInt<1>("h00") io.slave[0].w.bits.user <= UInt<1>("h00") io.slave[0].w.bits.strb <= UInt<1>("h00") io.slave[0].w.bits.last <= UInt<1>("h00") io.slave[0].w.bits.data <= UInt<1>("h00") io.slave[0].w.valid <= UInt<1>("h00") io.slave[0].aw.bits.user <= UInt<1>("h00") io.slave[0].aw.bits.id <= UInt<1>("h00") io.slave[0].aw.bits.region <= UInt<1>("h00") io.slave[0].aw.bits.qos <= UInt<1>("h00") io.slave[0].aw.bits.prot <= UInt<1>("h00") io.slave[0].aw.bits.cache <= UInt<1>("h00") io.slave[0].aw.bits.lock <= UInt<1>("h00") io.slave[0].aw.bits.burst <= UInt<1>("h00") io.slave[0].aw.bits.size <= UInt<1>("h00") io.slave[0].aw.bits.len <= UInt<1>("h00") io.slave[0].aw.bits.addr <= UInt<1>("h00") io.slave[0].aw.valid <= UInt<1>("h00") io.slave[1].r.ready <= UInt<1>("h00") io.slave[1].ar.bits.user <= UInt<1>("h00") io.slave[1].ar.bits.id <= UInt<1>("h00") io.slave[1].ar.bits.region <= UInt<1>("h00") io.slave[1].ar.bits.qos <= UInt<1>("h00") io.slave[1].ar.bits.prot <= UInt<1>("h00") io.slave[1].ar.bits.cache <= UInt<1>("h00") io.slave[1].ar.bits.lock <= UInt<1>("h00") io.slave[1].ar.bits.burst <= UInt<1>("h00") io.slave[1].ar.bits.size <= UInt<1>("h00") io.slave[1].ar.bits.len <= UInt<1>("h00") io.slave[1].ar.bits.addr <= UInt<1>("h00") io.slave[1].ar.valid <= UInt<1>("h00") io.slave[1].b.ready <= UInt<1>("h00") io.slave[1].w.bits.user <= UInt<1>("h00") io.slave[1].w.bits.strb <= UInt<1>("h00") io.slave[1].w.bits.last <= UInt<1>("h00") io.slave[1].w.bits.data <= UInt<1>("h00") io.slave[1].w.valid <= UInt<1>("h00") io.slave[1].aw.bits.user <= UInt<1>("h00") io.slave[1].aw.bits.id <= UInt<1>("h00") io.slave[1].aw.bits.region <= UInt<1>("h00") io.slave[1].aw.bits.qos <= UInt<1>("h00") io.slave[1].aw.bits.prot <= UInt<1>("h00") io.slave[1].aw.bits.cache <= UInt<1>("h00") io.slave[1].aw.bits.lock <= UInt<1>("h00") io.slave[1].aw.bits.burst <= UInt<1>("h00") io.slave[1].aw.bits.size <= UInt<1>("h00") io.slave[1].aw.bits.len <= UInt<1>("h00") io.slave[1].aw.bits.addr <= UInt<1>("h00") io.slave[1].aw.valid <= UInt<1>("h00") io.slave[2].r.ready <= UInt<1>("h00") io.slave[2].ar.bits.user <= UInt<1>("h00") io.slave[2].ar.bits.id <= UInt<1>("h00") io.slave[2].ar.bits.region <= UInt<1>("h00") io.slave[2].ar.bits.qos <= UInt<1>("h00") io.slave[2].ar.bits.prot <= UInt<1>("h00") io.slave[2].ar.bits.cache <= UInt<1>("h00") io.slave[2].ar.bits.lock <= UInt<1>("h00") io.slave[2].ar.bits.burst <= UInt<1>("h00") io.slave[2].ar.bits.size <= UInt<1>("h00") io.slave[2].ar.bits.len <= UInt<1>("h00") io.slave[2].ar.bits.addr <= UInt<1>("h00") io.slave[2].ar.valid <= UInt<1>("h00") io.slave[2].b.ready <= UInt<1>("h00") io.slave[2].w.bits.user <= UInt<1>("h00") io.slave[2].w.bits.strb <= UInt<1>("h00") io.slave[2].w.bits.last <= UInt<1>("h00") io.slave[2].w.bits.data <= UInt<1>("h00") io.slave[2].w.valid <= UInt<1>("h00") io.slave[2].aw.bits.user <= UInt<1>("h00") io.slave[2].aw.bits.id <= UInt<1>("h00") io.slave[2].aw.bits.region <= UInt<1>("h00") io.slave[2].aw.bits.qos <= UInt<1>("h00") io.slave[2].aw.bits.prot <= UInt<1>("h00") io.slave[2].aw.bits.cache <= UInt<1>("h00") io.slave[2].aw.bits.lock <= UInt<1>("h00") io.slave[2].aw.bits.burst <= UInt<1>("h00") io.slave[2].aw.bits.size <= UInt<1>("h00") io.slave[2].aw.bits.len <= UInt<1>("h00") io.slave[2].aw.bits.addr <= UInt<1>("h00") io.slave[2].aw.valid <= UInt<1>("h00") io.master.r.bits.user <= UInt<1>("h00") io.master.r.bits.id <= UInt<1>("h00") io.master.r.bits.last <= UInt<1>("h00") io.master.r.bits.data <= UInt<1>("h00") io.master.r.bits.resp <= UInt<1>("h00") io.master.r.valid <= UInt<1>("h00") io.master.ar.ready <= UInt<1>("h00") io.master.b.bits.user <= UInt<1>("h00") io.master.b.bits.id <= UInt<1>("h00") io.master.b.bits.resp <= UInt<1>("h00") io.master.b.valid <= UInt<1>("h00") io.master.w.ready <= UInt<1>("h00") io.master.aw.ready <= UInt<1>("h00") node T_1278 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1280 = lt(io.master.ar.bits.addr, UInt<31>("h040008000")) node T_1281 = and(T_1278, T_1280) node T_1283 = geq(io.master.ar.bits.addr, UInt<31>("h040008000")) node T_1285 = lt(io.master.ar.bits.addr, UInt<31>("h040010000")) node T_1286 = and(T_1283, T_1285) node T_1288 = geq(io.master.ar.bits.addr, UInt<31>("h040010000")) node T_1290 = lt(io.master.ar.bits.addr, UInt<31>("h040010200")) node T_1291 = and(T_1288, T_1290) wire T_1293 : UInt<1>[3] T_1293[0] <= T_1281 T_1293[1] <= T_1286 T_1293[2] <= T_1291 node T_1298 = cat(T_1293[1], T_1293[0]) node ar_route = cat(T_1293[2], T_1298) node T_1301 = geq(io.master.aw.bits.addr, UInt<31>("h040000000")) node T_1303 = lt(io.master.aw.bits.addr, UInt<31>("h040008000")) node T_1304 = and(T_1301, T_1303) node T_1306 = geq(io.master.aw.bits.addr, UInt<31>("h040008000")) node T_1308 = lt(io.master.aw.bits.addr, UInt<31>("h040010000")) node T_1309 = and(T_1306, T_1308) node T_1311 = geq(io.master.aw.bits.addr, UInt<31>("h040010000")) node T_1313 = lt(io.master.aw.bits.addr, UInt<31>("h040010200")) node T_1314 = and(T_1311, T_1313) wire T_1316 : UInt<1>[3] T_1316[0] <= T_1304 T_1316[1] <= T_1309 T_1316[2] <= T_1314 node T_1321 = cat(T_1316[1], T_1316[0]) node aw_route = cat(T_1316[2], T_1321) node T_1326 = bit(ar_route, 0) node T_1327 = and(io.master.ar.valid, T_1326) io.slave[0].ar.valid <= T_1327 io.slave[0].ar.bits <- io.master.ar.bits node T_1328 = bit(ar_route, 0) node T_1329 = and(io.slave[0].ar.ready, T_1328) node T_1330 = or(UInt<1>("h00"), T_1329) node T_1331 = bit(aw_route, 0) node T_1332 = and(io.master.aw.valid, T_1331) io.slave[0].aw.valid <= T_1332 io.slave[0].aw.bits <- io.master.aw.bits node T_1333 = bit(aw_route, 0) node T_1334 = and(io.slave[0].aw.ready, T_1333) node T_1335 = or(UInt<1>("h00"), T_1334) reg T_1337 : UInt<1>, clk, reset, UInt<1>("h00") node T_1338 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1338 : T_1337 <= UInt<1>("h01") skip node T_1340 = and(io.slave[0].w.ready, io.slave[0].w.valid) node T_1341 = and(T_1340, io.slave[0].w.bits.last) when T_1341 : T_1337 <= UInt<1>("h00") skip node T_1343 = and(io.master.w.valid, T_1337) io.slave[0].w.valid <= T_1343 io.slave[0].w.bits <- io.master.w.bits node T_1344 = and(io.slave[0].w.ready, T_1337) node T_1345 = or(UInt<1>("h00"), T_1344) node T_1346 = bit(ar_route, 1) node T_1347 = and(io.master.ar.valid, T_1346) io.slave[1].ar.valid <= T_1347 io.slave[1].ar.bits <- io.master.ar.bits node T_1348 = bit(ar_route, 1) node T_1349 = and(io.slave[1].ar.ready, T_1348) node T_1350 = or(T_1330, T_1349) node T_1351 = bit(aw_route, 1) node T_1352 = and(io.master.aw.valid, T_1351) io.slave[1].aw.valid <= T_1352 io.slave[1].aw.bits <- io.master.aw.bits node T_1353 = bit(aw_route, 1) node T_1354 = and(io.slave[1].aw.ready, T_1353) node T_1355 = or(T_1335, T_1354) reg T_1357 : UInt<1>, clk, reset, UInt<1>("h00") node T_1358 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1358 : T_1357 <= UInt<1>("h01") skip node T_1360 = and(io.slave[1].w.ready, io.slave[1].w.valid) node T_1361 = and(T_1360, io.slave[1].w.bits.last) when T_1361 : T_1357 <= UInt<1>("h00") skip node T_1363 = and(io.master.w.valid, T_1357) io.slave[1].w.valid <= T_1363 io.slave[1].w.bits <- io.master.w.bits node T_1364 = and(io.slave[1].w.ready, T_1357) node T_1365 = or(T_1345, T_1364) node T_1366 = bit(ar_route, 2) node T_1367 = and(io.master.ar.valid, T_1366) io.slave[2].ar.valid <= T_1367 io.slave[2].ar.bits <- io.master.ar.bits node T_1368 = bit(ar_route, 2) node T_1369 = and(io.slave[2].ar.ready, T_1368) node ar_ready = or(T_1350, T_1369) node T_1371 = bit(aw_route, 2) node T_1372 = and(io.master.aw.valid, T_1371) io.slave[2].aw.valid <= T_1372 io.slave[2].aw.bits <- io.master.aw.bits node T_1373 = bit(aw_route, 2) node T_1374 = and(io.slave[2].aw.ready, T_1373) node aw_ready = or(T_1355, T_1374) reg T_1377 : UInt<1>, clk, reset, UInt<1>("h00") node T_1378 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1378 : T_1377 <= UInt<1>("h01") skip node T_1380 = and(io.slave[2].w.ready, io.slave[2].w.valid) node T_1381 = and(T_1380, io.slave[2].w.bits.last) when T_1381 : T_1377 <= UInt<1>("h00") skip node T_1383 = and(io.master.w.valid, T_1377) io.slave[2].w.valid <= T_1383 io.slave[2].w.bits <- io.master.w.bits node T_1384 = and(io.slave[2].w.ready, T_1377) node w_ready = or(T_1365, T_1384) node T_1387 = neq(ar_route, UInt<1>("h00")) node r_invalid = eq(T_1387, UInt<1>("h00")) node T_1391 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1391, UInt<1>("h00")) inst err_slave of NastiErrorSlave_40 err_slave.io.r.ready <= UInt<1>("h00") err_slave.io.ar.bits.user <= UInt<1>("h00") err_slave.io.ar.bits.id <= UInt<1>("h00") err_slave.io.ar.bits.region <= UInt<1>("h00") err_slave.io.ar.bits.qos <= UInt<1>("h00") err_slave.io.ar.bits.prot <= UInt<1>("h00") err_slave.io.ar.bits.cache <= UInt<1>("h00") err_slave.io.ar.bits.lock <= UInt<1>("h00") err_slave.io.ar.bits.burst <= UInt<1>("h00") err_slave.io.ar.bits.size <= UInt<1>("h00") err_slave.io.ar.bits.len <= UInt<1>("h00") err_slave.io.ar.bits.addr <= UInt<1>("h00") err_slave.io.ar.valid <= UInt<1>("h00") err_slave.io.b.ready <= UInt<1>("h00") err_slave.io.w.bits.user <= UInt<1>("h00") err_slave.io.w.bits.strb <= UInt<1>("h00") err_slave.io.w.bits.last <= UInt<1>("h00") err_slave.io.w.bits.data <= UInt<1>("h00") err_slave.io.w.valid <= UInt<1>("h00") err_slave.io.aw.bits.user <= UInt<1>("h00") err_slave.io.aw.bits.id <= UInt<1>("h00") err_slave.io.aw.bits.region <= UInt<1>("h00") err_slave.io.aw.bits.qos <= UInt<1>("h00") err_slave.io.aw.bits.prot <= UInt<1>("h00") err_slave.io.aw.bits.cache <= UInt<1>("h00") err_slave.io.aw.bits.lock <= UInt<1>("h00") err_slave.io.aw.bits.burst <= UInt<1>("h00") err_slave.io.aw.bits.size <= UInt<1>("h00") err_slave.io.aw.bits.len <= UInt<1>("h00") err_slave.io.aw.bits.addr <= UInt<1>("h00") err_slave.io.aw.valid <= UInt<1>("h00") err_slave.clk <= clk err_slave.reset <= reset node T_1426 = and(r_invalid, io.master.ar.valid) err_slave.io.ar.valid <= T_1426 err_slave.io.ar.bits <- io.master.ar.bits node T_1427 = and(w_invalid, io.master.aw.valid) err_slave.io.aw.valid <= T_1427 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits node T_1428 = and(r_invalid, err_slave.io.ar.ready) node T_1429 = or(ar_ready, T_1428) io.master.ar.ready <= T_1429 node T_1430 = and(w_invalid, err_slave.io.aw.ready) node T_1431 = or(aw_ready, T_1430) io.master.aw.ready <= T_1431 node T_1432 = or(w_ready, err_slave.io.w.ready) io.master.w.ready <= T_1432 inst b_arb of RRArbiter_62 b_arb.io.out.ready <= UInt<1>("h00") b_arb.io.in[0].bits.user <= UInt<1>("h00") b_arb.io.in[0].bits.id <= UInt<1>("h00") b_arb.io.in[0].bits.resp <= UInt<1>("h00") b_arb.io.in[0].valid <= UInt<1>("h00") b_arb.io.in[1].bits.user <= UInt<1>("h00") b_arb.io.in[1].bits.id <= UInt<1>("h00") b_arb.io.in[1].bits.resp <= UInt<1>("h00") b_arb.io.in[1].valid <= UInt<1>("h00") b_arb.io.in[2].bits.user <= UInt<1>("h00") b_arb.io.in[2].bits.id <= UInt<1>("h00") b_arb.io.in[2].bits.resp <= UInt<1>("h00") b_arb.io.in[2].valid <= UInt<1>("h00") b_arb.io.in[3].bits.user <= UInt<1>("h00") b_arb.io.in[3].bits.id <= UInt<1>("h00") b_arb.io.in[3].bits.resp <= UInt<1>("h00") b_arb.io.in[3].valid <= UInt<1>("h00") b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter_63 r_arb.io.out.ready <= UInt<1>("h00") r_arb.io.in[0].bits.user <= UInt<1>("h00") r_arb.io.in[0].bits.id <= UInt<1>("h00") r_arb.io.in[0].bits.last <= UInt<1>("h00") r_arb.io.in[0].bits.data <= UInt<1>("h00") r_arb.io.in[0].bits.resp <= UInt<1>("h00") r_arb.io.in[0].valid <= UInt<1>("h00") r_arb.io.in[1].bits.user <= UInt<1>("h00") r_arb.io.in[1].bits.id <= UInt<1>("h00") r_arb.io.in[1].bits.last <= UInt<1>("h00") r_arb.io.in[1].bits.data <= UInt<1>("h00") r_arb.io.in[1].bits.resp <= UInt<1>("h00") r_arb.io.in[1].valid <= UInt<1>("h00") r_arb.io.in[2].bits.user <= UInt<1>("h00") r_arb.io.in[2].bits.id <= UInt<1>("h00") r_arb.io.in[2].bits.last <= UInt<1>("h00") r_arb.io.in[2].bits.data <= UInt<1>("h00") r_arb.io.in[2].bits.resp <= UInt<1>("h00") r_arb.io.in[2].valid <= UInt<1>("h00") r_arb.io.in[3].bits.user <= UInt<1>("h00") r_arb.io.in[3].bits.id <= UInt<1>("h00") r_arb.io.in[3].bits.last <= UInt<1>("h00") r_arb.io.in[3].bits.data <= UInt<1>("h00") r_arb.io.in[3].bits.resp <= UInt<1>("h00") r_arb.io.in[3].valid <= UInt<1>("h00") r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b r_arb.io.in[0] <- io.slave[0].r b_arb.io.in[1] <- io.slave[1].b r_arb.io.in[1] <- io.slave[1].r b_arb.io.in[2] <- io.slave[2].b r_arb.io.in[2] <- io.slave[2].r b_arb.io.in[3] <- err_slave.io.b r_arb.io.in[3] <- err_slave.io.r io.master.b <- b_arb.io.out io.master.r <- r_arb.io.out module NastiCrossbar_57 : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} io.slaves[0].r.ready <= UInt<1>("h00") io.slaves[0].ar.bits.user <= UInt<1>("h00") io.slaves[0].ar.bits.id <= UInt<1>("h00") io.slaves[0].ar.bits.region <= UInt<1>("h00") io.slaves[0].ar.bits.qos <= UInt<1>("h00") io.slaves[0].ar.bits.prot <= UInt<1>("h00") io.slaves[0].ar.bits.cache <= UInt<1>("h00") io.slaves[0].ar.bits.lock <= UInt<1>("h00") io.slaves[0].ar.bits.burst <= UInt<1>("h00") io.slaves[0].ar.bits.size <= UInt<1>("h00") io.slaves[0].ar.bits.len <= UInt<1>("h00") io.slaves[0].ar.bits.addr <= UInt<1>("h00") io.slaves[0].ar.valid <= UInt<1>("h00") io.slaves[0].b.ready <= UInt<1>("h00") io.slaves[0].w.bits.user <= UInt<1>("h00") io.slaves[0].w.bits.strb <= UInt<1>("h00") io.slaves[0].w.bits.last <= UInt<1>("h00") io.slaves[0].w.bits.data <= UInt<1>("h00") io.slaves[0].w.valid <= UInt<1>("h00") io.slaves[0].aw.bits.user <= UInt<1>("h00") io.slaves[0].aw.bits.id <= UInt<1>("h00") io.slaves[0].aw.bits.region <= UInt<1>("h00") io.slaves[0].aw.bits.qos <= UInt<1>("h00") io.slaves[0].aw.bits.prot <= UInt<1>("h00") io.slaves[0].aw.bits.cache <= UInt<1>("h00") io.slaves[0].aw.bits.lock <= UInt<1>("h00") io.slaves[0].aw.bits.burst <= UInt<1>("h00") io.slaves[0].aw.bits.size <= UInt<1>("h00") io.slaves[0].aw.bits.len <= UInt<1>("h00") io.slaves[0].aw.bits.addr <= UInt<1>("h00") io.slaves[0].aw.valid <= UInt<1>("h00") io.slaves[1].r.ready <= UInt<1>("h00") io.slaves[1].ar.bits.user <= UInt<1>("h00") io.slaves[1].ar.bits.id <= UInt<1>("h00") io.slaves[1].ar.bits.region <= UInt<1>("h00") io.slaves[1].ar.bits.qos <= UInt<1>("h00") io.slaves[1].ar.bits.prot <= UInt<1>("h00") io.slaves[1].ar.bits.cache <= UInt<1>("h00") io.slaves[1].ar.bits.lock <= UInt<1>("h00") io.slaves[1].ar.bits.burst <= UInt<1>("h00") io.slaves[1].ar.bits.size <= UInt<1>("h00") io.slaves[1].ar.bits.len <= UInt<1>("h00") io.slaves[1].ar.bits.addr <= UInt<1>("h00") io.slaves[1].ar.valid <= UInt<1>("h00") io.slaves[1].b.ready <= UInt<1>("h00") io.slaves[1].w.bits.user <= UInt<1>("h00") io.slaves[1].w.bits.strb <= UInt<1>("h00") io.slaves[1].w.bits.last <= UInt<1>("h00") io.slaves[1].w.bits.data <= UInt<1>("h00") io.slaves[1].w.valid <= UInt<1>("h00") io.slaves[1].aw.bits.user <= UInt<1>("h00") io.slaves[1].aw.bits.id <= UInt<1>("h00") io.slaves[1].aw.bits.region <= UInt<1>("h00") io.slaves[1].aw.bits.qos <= UInt<1>("h00") io.slaves[1].aw.bits.prot <= UInt<1>("h00") io.slaves[1].aw.bits.cache <= UInt<1>("h00") io.slaves[1].aw.bits.lock <= UInt<1>("h00") io.slaves[1].aw.bits.burst <= UInt<1>("h00") io.slaves[1].aw.bits.size <= UInt<1>("h00") io.slaves[1].aw.bits.len <= UInt<1>("h00") io.slaves[1].aw.bits.addr <= UInt<1>("h00") io.slaves[1].aw.valid <= UInt<1>("h00") io.slaves[2].r.ready <= UInt<1>("h00") io.slaves[2].ar.bits.user <= UInt<1>("h00") io.slaves[2].ar.bits.id <= UInt<1>("h00") io.slaves[2].ar.bits.region <= UInt<1>("h00") io.slaves[2].ar.bits.qos <= UInt<1>("h00") io.slaves[2].ar.bits.prot <= UInt<1>("h00") io.slaves[2].ar.bits.cache <= UInt<1>("h00") io.slaves[2].ar.bits.lock <= UInt<1>("h00") io.slaves[2].ar.bits.burst <= UInt<1>("h00") io.slaves[2].ar.bits.size <= UInt<1>("h00") io.slaves[2].ar.bits.len <= UInt<1>("h00") io.slaves[2].ar.bits.addr <= UInt<1>("h00") io.slaves[2].ar.valid <= UInt<1>("h00") io.slaves[2].b.ready <= UInt<1>("h00") io.slaves[2].w.bits.user <= UInt<1>("h00") io.slaves[2].w.bits.strb <= UInt<1>("h00") io.slaves[2].w.bits.last <= UInt<1>("h00") io.slaves[2].w.bits.data <= UInt<1>("h00") io.slaves[2].w.valid <= UInt<1>("h00") io.slaves[2].aw.bits.user <= UInt<1>("h00") io.slaves[2].aw.bits.id <= UInt<1>("h00") io.slaves[2].aw.bits.region <= UInt<1>("h00") io.slaves[2].aw.bits.qos <= UInt<1>("h00") io.slaves[2].aw.bits.prot <= UInt<1>("h00") io.slaves[2].aw.bits.cache <= UInt<1>("h00") io.slaves[2].aw.bits.lock <= UInt<1>("h00") io.slaves[2].aw.bits.burst <= UInt<1>("h00") io.slaves[2].aw.bits.size <= UInt<1>("h00") io.slaves[2].aw.bits.len <= UInt<1>("h00") io.slaves[2].aw.bits.addr <= UInt<1>("h00") io.slaves[2].aw.valid <= UInt<1>("h00") io.masters[0].r.bits.user <= UInt<1>("h00") io.masters[0].r.bits.id <= UInt<1>("h00") io.masters[0].r.bits.last <= UInt<1>("h00") io.masters[0].r.bits.data <= UInt<1>("h00") io.masters[0].r.bits.resp <= UInt<1>("h00") io.masters[0].r.valid <= UInt<1>("h00") io.masters[0].ar.ready <= UInt<1>("h00") io.masters[0].b.bits.user <= UInt<1>("h00") io.masters[0].b.bits.id <= UInt<1>("h00") io.masters[0].b.bits.resp <= UInt<1>("h00") io.masters[0].b.valid <= UInt<1>("h00") io.masters[0].w.ready <= UInt<1>("h00") io.masters[0].aw.ready <= UInt<1>("h00") inst T_2233 of NastiRouter_58 T_2233.io.slave[0].r.bits.user <= UInt<1>("h00") T_2233.io.slave[0].r.bits.id <= UInt<1>("h00") T_2233.io.slave[0].r.bits.last <= UInt<1>("h00") T_2233.io.slave[0].r.bits.data <= UInt<1>("h00") T_2233.io.slave[0].r.bits.resp <= UInt<1>("h00") T_2233.io.slave[0].r.valid <= UInt<1>("h00") T_2233.io.slave[0].ar.ready <= UInt<1>("h00") T_2233.io.slave[0].b.bits.user <= UInt<1>("h00") T_2233.io.slave[0].b.bits.id <= UInt<1>("h00") T_2233.io.slave[0].b.bits.resp <= UInt<1>("h00") T_2233.io.slave[0].b.valid <= UInt<1>("h00") T_2233.io.slave[0].w.ready <= UInt<1>("h00") T_2233.io.slave[0].aw.ready <= UInt<1>("h00") T_2233.io.slave[1].r.bits.user <= UInt<1>("h00") T_2233.io.slave[1].r.bits.id <= UInt<1>("h00") T_2233.io.slave[1].r.bits.last <= UInt<1>("h00") T_2233.io.slave[1].r.bits.data <= UInt<1>("h00") T_2233.io.slave[1].r.bits.resp <= UInt<1>("h00") T_2233.io.slave[1].r.valid <= UInt<1>("h00") T_2233.io.slave[1].ar.ready <= UInt<1>("h00") T_2233.io.slave[1].b.bits.user <= UInt<1>("h00") T_2233.io.slave[1].b.bits.id <= UInt<1>("h00") T_2233.io.slave[1].b.bits.resp <= UInt<1>("h00") T_2233.io.slave[1].b.valid <= UInt<1>("h00") T_2233.io.slave[1].w.ready <= UInt<1>("h00") T_2233.io.slave[1].aw.ready <= UInt<1>("h00") T_2233.io.slave[2].r.bits.user <= UInt<1>("h00") T_2233.io.slave[2].r.bits.id <= UInt<1>("h00") T_2233.io.slave[2].r.bits.last <= UInt<1>("h00") T_2233.io.slave[2].r.bits.data <= UInt<1>("h00") T_2233.io.slave[2].r.bits.resp <= UInt<1>("h00") T_2233.io.slave[2].r.valid <= UInt<1>("h00") T_2233.io.slave[2].ar.ready <= UInt<1>("h00") T_2233.io.slave[2].b.bits.user <= UInt<1>("h00") T_2233.io.slave[2].b.bits.id <= UInt<1>("h00") T_2233.io.slave[2].b.bits.resp <= UInt<1>("h00") T_2233.io.slave[2].b.valid <= UInt<1>("h00") T_2233.io.slave[2].w.ready <= UInt<1>("h00") T_2233.io.slave[2].aw.ready <= UInt<1>("h00") T_2233.io.master.r.ready <= UInt<1>("h00") T_2233.io.master.ar.bits.user <= UInt<1>("h00") T_2233.io.master.ar.bits.id <= UInt<1>("h00") T_2233.io.master.ar.bits.region <= UInt<1>("h00") T_2233.io.master.ar.bits.qos <= UInt<1>("h00") T_2233.io.master.ar.bits.prot <= UInt<1>("h00") T_2233.io.master.ar.bits.cache <= UInt<1>("h00") T_2233.io.master.ar.bits.lock <= UInt<1>("h00") T_2233.io.master.ar.bits.burst <= UInt<1>("h00") T_2233.io.master.ar.bits.size <= UInt<1>("h00") T_2233.io.master.ar.bits.len <= UInt<1>("h00") T_2233.io.master.ar.bits.addr <= UInt<1>("h00") T_2233.io.master.ar.valid <= UInt<1>("h00") T_2233.io.master.b.ready <= UInt<1>("h00") T_2233.io.master.w.bits.user <= UInt<1>("h00") T_2233.io.master.w.bits.strb <= UInt<1>("h00") T_2233.io.master.w.bits.last <= UInt<1>("h00") T_2233.io.master.w.bits.data <= UInt<1>("h00") T_2233.io.master.w.valid <= UInt<1>("h00") T_2233.io.master.aw.bits.user <= UInt<1>("h00") T_2233.io.master.aw.bits.id <= UInt<1>("h00") T_2233.io.master.aw.bits.region <= UInt<1>("h00") T_2233.io.master.aw.bits.qos <= UInt<1>("h00") T_2233.io.master.aw.bits.prot <= UInt<1>("h00") T_2233.io.master.aw.bits.cache <= UInt<1>("h00") T_2233.io.master.aw.bits.lock <= UInt<1>("h00") T_2233.io.master.aw.bits.burst <= UInt<1>("h00") T_2233.io.master.aw.bits.size <= UInt<1>("h00") T_2233.io.master.aw.bits.len <= UInt<1>("h00") T_2233.io.master.aw.bits.addr <= UInt<1>("h00") T_2233.io.master.aw.valid <= UInt<1>("h00") T_2233.clk <= clk T_2233.reset <= reset T_2233.io.master <- io.masters[0] io.slaves <- T_2233.io.slave module NastiRecursiveInterconnect_56 : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} io.slaves[0].r.ready <= UInt<1>("h00") io.slaves[0].ar.bits.user <= UInt<1>("h00") io.slaves[0].ar.bits.id <= UInt<1>("h00") io.slaves[0].ar.bits.region <= UInt<1>("h00") io.slaves[0].ar.bits.qos <= UInt<1>("h00") io.slaves[0].ar.bits.prot <= UInt<1>("h00") io.slaves[0].ar.bits.cache <= UInt<1>("h00") io.slaves[0].ar.bits.lock <= UInt<1>("h00") io.slaves[0].ar.bits.burst <= UInt<1>("h00") io.slaves[0].ar.bits.size <= UInt<1>("h00") io.slaves[0].ar.bits.len <= UInt<1>("h00") io.slaves[0].ar.bits.addr <= UInt<1>("h00") io.slaves[0].ar.valid <= UInt<1>("h00") io.slaves[0].b.ready <= UInt<1>("h00") io.slaves[0].w.bits.user <= UInt<1>("h00") io.slaves[0].w.bits.strb <= UInt<1>("h00") io.slaves[0].w.bits.last <= UInt<1>("h00") io.slaves[0].w.bits.data <= UInt<1>("h00") io.slaves[0].w.valid <= UInt<1>("h00") io.slaves[0].aw.bits.user <= UInt<1>("h00") io.slaves[0].aw.bits.id <= UInt<1>("h00") io.slaves[0].aw.bits.region <= UInt<1>("h00") io.slaves[0].aw.bits.qos <= UInt<1>("h00") io.slaves[0].aw.bits.prot <= UInt<1>("h00") io.slaves[0].aw.bits.cache <= UInt<1>("h00") io.slaves[0].aw.bits.lock <= UInt<1>("h00") io.slaves[0].aw.bits.burst <= UInt<1>("h00") io.slaves[0].aw.bits.size <= UInt<1>("h00") io.slaves[0].aw.bits.len <= UInt<1>("h00") io.slaves[0].aw.bits.addr <= UInt<1>("h00") io.slaves[0].aw.valid <= UInt<1>("h00") io.slaves[1].r.ready <= UInt<1>("h00") io.slaves[1].ar.bits.user <= UInt<1>("h00") io.slaves[1].ar.bits.id <= UInt<1>("h00") io.slaves[1].ar.bits.region <= UInt<1>("h00") io.slaves[1].ar.bits.qos <= UInt<1>("h00") io.slaves[1].ar.bits.prot <= UInt<1>("h00") io.slaves[1].ar.bits.cache <= UInt<1>("h00") io.slaves[1].ar.bits.lock <= UInt<1>("h00") io.slaves[1].ar.bits.burst <= UInt<1>("h00") io.slaves[1].ar.bits.size <= UInt<1>("h00") io.slaves[1].ar.bits.len <= UInt<1>("h00") io.slaves[1].ar.bits.addr <= UInt<1>("h00") io.slaves[1].ar.valid <= UInt<1>("h00") io.slaves[1].b.ready <= UInt<1>("h00") io.slaves[1].w.bits.user <= UInt<1>("h00") io.slaves[1].w.bits.strb <= UInt<1>("h00") io.slaves[1].w.bits.last <= UInt<1>("h00") io.slaves[1].w.bits.data <= UInt<1>("h00") io.slaves[1].w.valid <= UInt<1>("h00") io.slaves[1].aw.bits.user <= UInt<1>("h00") io.slaves[1].aw.bits.id <= UInt<1>("h00") io.slaves[1].aw.bits.region <= UInt<1>("h00") io.slaves[1].aw.bits.qos <= UInt<1>("h00") io.slaves[1].aw.bits.prot <= UInt<1>("h00") io.slaves[1].aw.bits.cache <= UInt<1>("h00") io.slaves[1].aw.bits.lock <= UInt<1>("h00") io.slaves[1].aw.bits.burst <= UInt<1>("h00") io.slaves[1].aw.bits.size <= UInt<1>("h00") io.slaves[1].aw.bits.len <= UInt<1>("h00") io.slaves[1].aw.bits.addr <= UInt<1>("h00") io.slaves[1].aw.valid <= UInt<1>("h00") io.slaves[2].r.ready <= UInt<1>("h00") io.slaves[2].ar.bits.user <= UInt<1>("h00") io.slaves[2].ar.bits.id <= UInt<1>("h00") io.slaves[2].ar.bits.region <= UInt<1>("h00") io.slaves[2].ar.bits.qos <= UInt<1>("h00") io.slaves[2].ar.bits.prot <= UInt<1>("h00") io.slaves[2].ar.bits.cache <= UInt<1>("h00") io.slaves[2].ar.bits.lock <= UInt<1>("h00") io.slaves[2].ar.bits.burst <= UInt<1>("h00") io.slaves[2].ar.bits.size <= UInt<1>("h00") io.slaves[2].ar.bits.len <= UInt<1>("h00") io.slaves[2].ar.bits.addr <= UInt<1>("h00") io.slaves[2].ar.valid <= UInt<1>("h00") io.slaves[2].b.ready <= UInt<1>("h00") io.slaves[2].w.bits.user <= UInt<1>("h00") io.slaves[2].w.bits.strb <= UInt<1>("h00") io.slaves[2].w.bits.last <= UInt<1>("h00") io.slaves[2].w.bits.data <= UInt<1>("h00") io.slaves[2].w.valid <= UInt<1>("h00") io.slaves[2].aw.bits.user <= UInt<1>("h00") io.slaves[2].aw.bits.id <= UInt<1>("h00") io.slaves[2].aw.bits.region <= UInt<1>("h00") io.slaves[2].aw.bits.qos <= UInt<1>("h00") io.slaves[2].aw.bits.prot <= UInt<1>("h00") io.slaves[2].aw.bits.cache <= UInt<1>("h00") io.slaves[2].aw.bits.lock <= UInt<1>("h00") io.slaves[2].aw.bits.burst <= UInt<1>("h00") io.slaves[2].aw.bits.size <= UInt<1>("h00") io.slaves[2].aw.bits.len <= UInt<1>("h00") io.slaves[2].aw.bits.addr <= UInt<1>("h00") io.slaves[2].aw.valid <= UInt<1>("h00") io.masters[0].r.bits.user <= UInt<1>("h00") io.masters[0].r.bits.id <= UInt<1>("h00") io.masters[0].r.bits.last <= UInt<1>("h00") io.masters[0].r.bits.data <= UInt<1>("h00") io.masters[0].r.bits.resp <= UInt<1>("h00") io.masters[0].r.valid <= UInt<1>("h00") io.masters[0].ar.ready <= UInt<1>("h00") io.masters[0].b.bits.user <= UInt<1>("h00") io.masters[0].b.bits.id <= UInt<1>("h00") io.masters[0].b.bits.resp <= UInt<1>("h00") io.masters[0].b.valid <= UInt<1>("h00") io.masters[0].w.ready <= UInt<1>("h00") io.masters[0].aw.ready <= UInt<1>("h00") inst xbar of NastiCrossbar_57 xbar.io.slaves[0].r.bits.user <= UInt<1>("h00") xbar.io.slaves[0].r.bits.id <= UInt<1>("h00") xbar.io.slaves[0].r.bits.last <= UInt<1>("h00") xbar.io.slaves[0].r.bits.data <= UInt<1>("h00") xbar.io.slaves[0].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[0].r.valid <= UInt<1>("h00") xbar.io.slaves[0].ar.ready <= UInt<1>("h00") xbar.io.slaves[0].b.bits.user <= UInt<1>("h00") xbar.io.slaves[0].b.bits.id <= UInt<1>("h00") xbar.io.slaves[0].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[0].b.valid <= UInt<1>("h00") xbar.io.slaves[0].w.ready <= UInt<1>("h00") xbar.io.slaves[0].aw.ready <= UInt<1>("h00") xbar.io.slaves[1].r.bits.user <= UInt<1>("h00") xbar.io.slaves[1].r.bits.id <= UInt<1>("h00") xbar.io.slaves[1].r.bits.last <= UInt<1>("h00") xbar.io.slaves[1].r.bits.data <= UInt<1>("h00") xbar.io.slaves[1].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[1].r.valid <= UInt<1>("h00") xbar.io.slaves[1].ar.ready <= UInt<1>("h00") xbar.io.slaves[1].b.bits.user <= UInt<1>("h00") xbar.io.slaves[1].b.bits.id <= UInt<1>("h00") xbar.io.slaves[1].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[1].b.valid <= UInt<1>("h00") xbar.io.slaves[1].w.ready <= UInt<1>("h00") xbar.io.slaves[1].aw.ready <= UInt<1>("h00") xbar.io.slaves[2].r.bits.user <= UInt<1>("h00") xbar.io.slaves[2].r.bits.id <= UInt<1>("h00") xbar.io.slaves[2].r.bits.last <= UInt<1>("h00") xbar.io.slaves[2].r.bits.data <= UInt<1>("h00") xbar.io.slaves[2].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[2].r.valid <= UInt<1>("h00") xbar.io.slaves[2].ar.ready <= UInt<1>("h00") xbar.io.slaves[2].b.bits.user <= UInt<1>("h00") xbar.io.slaves[2].b.bits.id <= UInt<1>("h00") xbar.io.slaves[2].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[2].b.valid <= UInt<1>("h00") xbar.io.slaves[2].w.ready <= UInt<1>("h00") xbar.io.slaves[2].aw.ready <= UInt<1>("h00") xbar.io.masters[0].r.ready <= UInt<1>("h00") xbar.io.masters[0].ar.bits.user <= UInt<1>("h00") xbar.io.masters[0].ar.bits.id <= UInt<1>("h00") xbar.io.masters[0].ar.bits.region <= UInt<1>("h00") xbar.io.masters[0].ar.bits.qos <= UInt<1>("h00") xbar.io.masters[0].ar.bits.prot <= UInt<1>("h00") xbar.io.masters[0].ar.bits.cache <= UInt<1>("h00") xbar.io.masters[0].ar.bits.lock <= UInt<1>("h00") xbar.io.masters[0].ar.bits.burst <= UInt<1>("h00") xbar.io.masters[0].ar.bits.size <= UInt<1>("h00") xbar.io.masters[0].ar.bits.len <= UInt<1>("h00") xbar.io.masters[0].ar.bits.addr <= UInt<1>("h00") xbar.io.masters[0].ar.valid <= UInt<1>("h00") xbar.io.masters[0].b.ready <= UInt<1>("h00") xbar.io.masters[0].w.bits.user <= UInt<1>("h00") xbar.io.masters[0].w.bits.strb <= UInt<1>("h00") xbar.io.masters[0].w.bits.last <= UInt<1>("h00") xbar.io.masters[0].w.bits.data <= UInt<1>("h00") xbar.io.masters[0].w.valid <= UInt<1>("h00") xbar.io.masters[0].aw.bits.user <= UInt<1>("h00") xbar.io.masters[0].aw.bits.id <= UInt<1>("h00") xbar.io.masters[0].aw.bits.region <= UInt<1>("h00") xbar.io.masters[0].aw.bits.qos <= UInt<1>("h00") xbar.io.masters[0].aw.bits.prot <= UInt<1>("h00") xbar.io.masters[0].aw.bits.cache <= UInt<1>("h00") xbar.io.masters[0].aw.bits.lock <= UInt<1>("h00") xbar.io.masters[0].aw.bits.burst <= UInt<1>("h00") xbar.io.masters[0].aw.bits.size <= UInt<1>("h00") xbar.io.masters[0].aw.bits.len <= UInt<1>("h00") xbar.io.masters[0].aw.bits.addr <= UInt<1>("h00") xbar.io.masters[0].aw.valid <= UInt<1>("h00") xbar.clk <= clk xbar.reset <= reset xbar.io.masters <- io.masters io.slaves[0] <- xbar.io.slaves[0] io.slaves[1] <- xbar.io.slaves[1] io.slaves[2] <- xbar.io.slaves[2] module NastiRecursiveInterconnect : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[5]} io.slaves[0].r.ready <= UInt<1>("h00") io.slaves[0].ar.bits.user <= UInt<1>("h00") io.slaves[0].ar.bits.id <= UInt<1>("h00") io.slaves[0].ar.bits.region <= UInt<1>("h00") io.slaves[0].ar.bits.qos <= UInt<1>("h00") io.slaves[0].ar.bits.prot <= UInt<1>("h00") io.slaves[0].ar.bits.cache <= UInt<1>("h00") io.slaves[0].ar.bits.lock <= UInt<1>("h00") io.slaves[0].ar.bits.burst <= UInt<1>("h00") io.slaves[0].ar.bits.size <= UInt<1>("h00") io.slaves[0].ar.bits.len <= UInt<1>("h00") io.slaves[0].ar.bits.addr <= UInt<1>("h00") io.slaves[0].ar.valid <= UInt<1>("h00") io.slaves[0].b.ready <= UInt<1>("h00") io.slaves[0].w.bits.user <= UInt<1>("h00") io.slaves[0].w.bits.strb <= UInt<1>("h00") io.slaves[0].w.bits.last <= UInt<1>("h00") io.slaves[0].w.bits.data <= UInt<1>("h00") io.slaves[0].w.valid <= UInt<1>("h00") io.slaves[0].aw.bits.user <= UInt<1>("h00") io.slaves[0].aw.bits.id <= UInt<1>("h00") io.slaves[0].aw.bits.region <= UInt<1>("h00") io.slaves[0].aw.bits.qos <= UInt<1>("h00") io.slaves[0].aw.bits.prot <= UInt<1>("h00") io.slaves[0].aw.bits.cache <= UInt<1>("h00") io.slaves[0].aw.bits.lock <= UInt<1>("h00") io.slaves[0].aw.bits.burst <= UInt<1>("h00") io.slaves[0].aw.bits.size <= UInt<1>("h00") io.slaves[0].aw.bits.len <= UInt<1>("h00") io.slaves[0].aw.bits.addr <= UInt<1>("h00") io.slaves[0].aw.valid <= UInt<1>("h00") io.slaves[1].r.ready <= UInt<1>("h00") io.slaves[1].ar.bits.user <= UInt<1>("h00") io.slaves[1].ar.bits.id <= UInt<1>("h00") io.slaves[1].ar.bits.region <= UInt<1>("h00") io.slaves[1].ar.bits.qos <= UInt<1>("h00") io.slaves[1].ar.bits.prot <= UInt<1>("h00") io.slaves[1].ar.bits.cache <= UInt<1>("h00") io.slaves[1].ar.bits.lock <= UInt<1>("h00") io.slaves[1].ar.bits.burst <= UInt<1>("h00") io.slaves[1].ar.bits.size <= UInt<1>("h00") io.slaves[1].ar.bits.len <= UInt<1>("h00") io.slaves[1].ar.bits.addr <= UInt<1>("h00") io.slaves[1].ar.valid <= UInt<1>("h00") io.slaves[1].b.ready <= UInt<1>("h00") io.slaves[1].w.bits.user <= UInt<1>("h00") io.slaves[1].w.bits.strb <= UInt<1>("h00") io.slaves[1].w.bits.last <= UInt<1>("h00") io.slaves[1].w.bits.data <= UInt<1>("h00") io.slaves[1].w.valid <= UInt<1>("h00") io.slaves[1].aw.bits.user <= UInt<1>("h00") io.slaves[1].aw.bits.id <= UInt<1>("h00") io.slaves[1].aw.bits.region <= UInt<1>("h00") io.slaves[1].aw.bits.qos <= UInt<1>("h00") io.slaves[1].aw.bits.prot <= UInt<1>("h00") io.slaves[1].aw.bits.cache <= UInt<1>("h00") io.slaves[1].aw.bits.lock <= UInt<1>("h00") io.slaves[1].aw.bits.burst <= UInt<1>("h00") io.slaves[1].aw.bits.size <= UInt<1>("h00") io.slaves[1].aw.bits.len <= UInt<1>("h00") io.slaves[1].aw.bits.addr <= UInt<1>("h00") io.slaves[1].aw.valid <= UInt<1>("h00") io.slaves[2].r.ready <= UInt<1>("h00") io.slaves[2].ar.bits.user <= UInt<1>("h00") io.slaves[2].ar.bits.id <= UInt<1>("h00") io.slaves[2].ar.bits.region <= UInt<1>("h00") io.slaves[2].ar.bits.qos <= UInt<1>("h00") io.slaves[2].ar.bits.prot <= UInt<1>("h00") io.slaves[2].ar.bits.cache <= UInt<1>("h00") io.slaves[2].ar.bits.lock <= UInt<1>("h00") io.slaves[2].ar.bits.burst <= UInt<1>("h00") io.slaves[2].ar.bits.size <= UInt<1>("h00") io.slaves[2].ar.bits.len <= UInt<1>("h00") io.slaves[2].ar.bits.addr <= UInt<1>("h00") io.slaves[2].ar.valid <= UInt<1>("h00") io.slaves[2].b.ready <= UInt<1>("h00") io.slaves[2].w.bits.user <= UInt<1>("h00") io.slaves[2].w.bits.strb <= UInt<1>("h00") io.slaves[2].w.bits.last <= UInt<1>("h00") io.slaves[2].w.bits.data <= UInt<1>("h00") io.slaves[2].w.valid <= UInt<1>("h00") io.slaves[2].aw.bits.user <= UInt<1>("h00") io.slaves[2].aw.bits.id <= UInt<1>("h00") io.slaves[2].aw.bits.region <= UInt<1>("h00") io.slaves[2].aw.bits.qos <= UInt<1>("h00") io.slaves[2].aw.bits.prot <= UInt<1>("h00") io.slaves[2].aw.bits.cache <= UInt<1>("h00") io.slaves[2].aw.bits.lock <= UInt<1>("h00") io.slaves[2].aw.bits.burst <= UInt<1>("h00") io.slaves[2].aw.bits.size <= UInt<1>("h00") io.slaves[2].aw.bits.len <= UInt<1>("h00") io.slaves[2].aw.bits.addr <= UInt<1>("h00") io.slaves[2].aw.valid <= UInt<1>("h00") io.slaves[3].r.ready <= UInt<1>("h00") io.slaves[3].ar.bits.user <= UInt<1>("h00") io.slaves[3].ar.bits.id <= UInt<1>("h00") io.slaves[3].ar.bits.region <= UInt<1>("h00") io.slaves[3].ar.bits.qos <= UInt<1>("h00") io.slaves[3].ar.bits.prot <= UInt<1>("h00") io.slaves[3].ar.bits.cache <= UInt<1>("h00") io.slaves[3].ar.bits.lock <= UInt<1>("h00") io.slaves[3].ar.bits.burst <= UInt<1>("h00") io.slaves[3].ar.bits.size <= UInt<1>("h00") io.slaves[3].ar.bits.len <= UInt<1>("h00") io.slaves[3].ar.bits.addr <= UInt<1>("h00") io.slaves[3].ar.valid <= UInt<1>("h00") io.slaves[3].b.ready <= UInt<1>("h00") io.slaves[3].w.bits.user <= UInt<1>("h00") io.slaves[3].w.bits.strb <= UInt<1>("h00") io.slaves[3].w.bits.last <= UInt<1>("h00") io.slaves[3].w.bits.data <= UInt<1>("h00") io.slaves[3].w.valid <= UInt<1>("h00") io.slaves[3].aw.bits.user <= UInt<1>("h00") io.slaves[3].aw.bits.id <= UInt<1>("h00") io.slaves[3].aw.bits.region <= UInt<1>("h00") io.slaves[3].aw.bits.qos <= UInt<1>("h00") io.slaves[3].aw.bits.prot <= UInt<1>("h00") io.slaves[3].aw.bits.cache <= UInt<1>("h00") io.slaves[3].aw.bits.lock <= UInt<1>("h00") io.slaves[3].aw.bits.burst <= UInt<1>("h00") io.slaves[3].aw.bits.size <= UInt<1>("h00") io.slaves[3].aw.bits.len <= UInt<1>("h00") io.slaves[3].aw.bits.addr <= UInt<1>("h00") io.slaves[3].aw.valid <= UInt<1>("h00") io.slaves[4].r.ready <= UInt<1>("h00") io.slaves[4].ar.bits.user <= UInt<1>("h00") io.slaves[4].ar.bits.id <= UInt<1>("h00") io.slaves[4].ar.bits.region <= UInt<1>("h00") io.slaves[4].ar.bits.qos <= UInt<1>("h00") io.slaves[4].ar.bits.prot <= UInt<1>("h00") io.slaves[4].ar.bits.cache <= UInt<1>("h00") io.slaves[4].ar.bits.lock <= UInt<1>("h00") io.slaves[4].ar.bits.burst <= UInt<1>("h00") io.slaves[4].ar.bits.size <= UInt<1>("h00") io.slaves[4].ar.bits.len <= UInt<1>("h00") io.slaves[4].ar.bits.addr <= UInt<1>("h00") io.slaves[4].ar.valid <= UInt<1>("h00") io.slaves[4].b.ready <= UInt<1>("h00") io.slaves[4].w.bits.user <= UInt<1>("h00") io.slaves[4].w.bits.strb <= UInt<1>("h00") io.slaves[4].w.bits.last <= UInt<1>("h00") io.slaves[4].w.bits.data <= UInt<1>("h00") io.slaves[4].w.valid <= UInt<1>("h00") io.slaves[4].aw.bits.user <= UInt<1>("h00") io.slaves[4].aw.bits.id <= UInt<1>("h00") io.slaves[4].aw.bits.region <= UInt<1>("h00") io.slaves[4].aw.bits.qos <= UInt<1>("h00") io.slaves[4].aw.bits.prot <= UInt<1>("h00") io.slaves[4].aw.bits.cache <= UInt<1>("h00") io.slaves[4].aw.bits.lock <= UInt<1>("h00") io.slaves[4].aw.bits.burst <= UInt<1>("h00") io.slaves[4].aw.bits.size <= UInt<1>("h00") io.slaves[4].aw.bits.len <= UInt<1>("h00") io.slaves[4].aw.bits.addr <= UInt<1>("h00") io.slaves[4].aw.valid <= UInt<1>("h00") io.masters[0].r.bits.user <= UInt<1>("h00") io.masters[0].r.bits.id <= UInt<1>("h00") io.masters[0].r.bits.last <= UInt<1>("h00") io.masters[0].r.bits.data <= UInt<1>("h00") io.masters[0].r.bits.resp <= UInt<1>("h00") io.masters[0].r.valid <= UInt<1>("h00") io.masters[0].ar.ready <= UInt<1>("h00") io.masters[0].b.bits.user <= UInt<1>("h00") io.masters[0].b.bits.id <= UInt<1>("h00") io.masters[0].b.bits.resp <= UInt<1>("h00") io.masters[0].b.valid <= UInt<1>("h00") io.masters[0].w.ready <= UInt<1>("h00") io.masters[0].aw.ready <= UInt<1>("h00") io.masters[1].r.bits.user <= UInt<1>("h00") io.masters[1].r.bits.id <= UInt<1>("h00") io.masters[1].r.bits.last <= UInt<1>("h00") io.masters[1].r.bits.data <= UInt<1>("h00") io.masters[1].r.bits.resp <= UInt<1>("h00") io.masters[1].r.valid <= UInt<1>("h00") io.masters[1].ar.ready <= UInt<1>("h00") io.masters[1].b.bits.user <= UInt<1>("h00") io.masters[1].b.bits.id <= UInt<1>("h00") io.masters[1].b.bits.resp <= UInt<1>("h00") io.masters[1].b.valid <= UInt<1>("h00") io.masters[1].w.ready <= UInt<1>("h00") io.masters[1].aw.ready <= UInt<1>("h00") inst xbar of NastiCrossbar xbar.io.slaves[0].r.bits.user <= UInt<1>("h00") xbar.io.slaves[0].r.bits.id <= UInt<1>("h00") xbar.io.slaves[0].r.bits.last <= UInt<1>("h00") xbar.io.slaves[0].r.bits.data <= UInt<1>("h00") xbar.io.slaves[0].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[0].r.valid <= UInt<1>("h00") xbar.io.slaves[0].ar.ready <= UInt<1>("h00") xbar.io.slaves[0].b.bits.user <= UInt<1>("h00") xbar.io.slaves[0].b.bits.id <= UInt<1>("h00") xbar.io.slaves[0].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[0].b.valid <= UInt<1>("h00") xbar.io.slaves[0].w.ready <= UInt<1>("h00") xbar.io.slaves[0].aw.ready <= UInt<1>("h00") xbar.io.slaves[1].r.bits.user <= UInt<1>("h00") xbar.io.slaves[1].r.bits.id <= UInt<1>("h00") xbar.io.slaves[1].r.bits.last <= UInt<1>("h00") xbar.io.slaves[1].r.bits.data <= UInt<1>("h00") xbar.io.slaves[1].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[1].r.valid <= UInt<1>("h00") xbar.io.slaves[1].ar.ready <= UInt<1>("h00") xbar.io.slaves[1].b.bits.user <= UInt<1>("h00") xbar.io.slaves[1].b.bits.id <= UInt<1>("h00") xbar.io.slaves[1].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[1].b.valid <= UInt<1>("h00") xbar.io.slaves[1].w.ready <= UInt<1>("h00") xbar.io.slaves[1].aw.ready <= UInt<1>("h00") xbar.io.slaves[2].r.bits.user <= UInt<1>("h00") xbar.io.slaves[2].r.bits.id <= UInt<1>("h00") xbar.io.slaves[2].r.bits.last <= UInt<1>("h00") xbar.io.slaves[2].r.bits.data <= UInt<1>("h00") xbar.io.slaves[2].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[2].r.valid <= UInt<1>("h00") xbar.io.slaves[2].ar.ready <= UInt<1>("h00") xbar.io.slaves[2].b.bits.user <= UInt<1>("h00") xbar.io.slaves[2].b.bits.id <= UInt<1>("h00") xbar.io.slaves[2].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[2].b.valid <= UInt<1>("h00") xbar.io.slaves[2].w.ready <= UInt<1>("h00") xbar.io.slaves[2].aw.ready <= UInt<1>("h00") xbar.io.slaves[3].r.bits.user <= UInt<1>("h00") xbar.io.slaves[3].r.bits.id <= UInt<1>("h00") xbar.io.slaves[3].r.bits.last <= UInt<1>("h00") xbar.io.slaves[3].r.bits.data <= UInt<1>("h00") xbar.io.slaves[3].r.bits.resp <= UInt<1>("h00") xbar.io.slaves[3].r.valid <= UInt<1>("h00") xbar.io.slaves[3].ar.ready <= UInt<1>("h00") xbar.io.slaves[3].b.bits.user <= UInt<1>("h00") xbar.io.slaves[3].b.bits.id <= UInt<1>("h00") xbar.io.slaves[3].b.bits.resp <= UInt<1>("h00") xbar.io.slaves[3].b.valid <= UInt<1>("h00") xbar.io.slaves[3].w.ready <= UInt<1>("h00") xbar.io.slaves[3].aw.ready <= UInt<1>("h00") xbar.io.masters[0].r.ready <= UInt<1>("h00") xbar.io.masters[0].ar.bits.user <= UInt<1>("h00") xbar.io.masters[0].ar.bits.id <= UInt<1>("h00") xbar.io.masters[0].ar.bits.region <= UInt<1>("h00") xbar.io.masters[0].ar.bits.qos <= UInt<1>("h00") xbar.io.masters[0].ar.bits.prot <= UInt<1>("h00") xbar.io.masters[0].ar.bits.cache <= UInt<1>("h00") xbar.io.masters[0].ar.bits.lock <= UInt<1>("h00") xbar.io.masters[0].ar.bits.burst <= UInt<1>("h00") xbar.io.masters[0].ar.bits.size <= UInt<1>("h00") xbar.io.masters[0].ar.bits.len <= UInt<1>("h00") xbar.io.masters[0].ar.bits.addr <= UInt<1>("h00") xbar.io.masters[0].ar.valid <= UInt<1>("h00") xbar.io.masters[0].b.ready <= UInt<1>("h00") xbar.io.masters[0].w.bits.user <= UInt<1>("h00") xbar.io.masters[0].w.bits.strb <= UInt<1>("h00") xbar.io.masters[0].w.bits.last <= UInt<1>("h00") xbar.io.masters[0].w.bits.data <= UInt<1>("h00") xbar.io.masters[0].w.valid <= UInt<1>("h00") xbar.io.masters[0].aw.bits.user <= UInt<1>("h00") xbar.io.masters[0].aw.bits.id <= UInt<1>("h00") xbar.io.masters[0].aw.bits.region <= UInt<1>("h00") xbar.io.masters[0].aw.bits.qos <= UInt<1>("h00") xbar.io.masters[0].aw.bits.prot <= UInt<1>("h00") xbar.io.masters[0].aw.bits.cache <= UInt<1>("h00") xbar.io.masters[0].aw.bits.lock <= UInt<1>("h00") xbar.io.masters[0].aw.bits.burst <= UInt<1>("h00") xbar.io.masters[0].aw.bits.size <= UInt<1>("h00") xbar.io.masters[0].aw.bits.len <= UInt<1>("h00") xbar.io.masters[0].aw.bits.addr <= UInt<1>("h00") xbar.io.masters[0].aw.valid <= UInt<1>("h00") xbar.io.masters[1].r.ready <= UInt<1>("h00") xbar.io.masters[1].ar.bits.user <= UInt<1>("h00") xbar.io.masters[1].ar.bits.id <= UInt<1>("h00") xbar.io.masters[1].ar.bits.region <= UInt<1>("h00") xbar.io.masters[1].ar.bits.qos <= UInt<1>("h00") xbar.io.masters[1].ar.bits.prot <= UInt<1>("h00") xbar.io.masters[1].ar.bits.cache <= UInt<1>("h00") xbar.io.masters[1].ar.bits.lock <= UInt<1>("h00") xbar.io.masters[1].ar.bits.burst <= UInt<1>("h00") xbar.io.masters[1].ar.bits.size <= UInt<1>("h00") xbar.io.masters[1].ar.bits.len <= UInt<1>("h00") xbar.io.masters[1].ar.bits.addr <= UInt<1>("h00") xbar.io.masters[1].ar.valid <= UInt<1>("h00") xbar.io.masters[1].b.ready <= UInt<1>("h00") xbar.io.masters[1].w.bits.user <= UInt<1>("h00") xbar.io.masters[1].w.bits.strb <= UInt<1>("h00") xbar.io.masters[1].w.bits.last <= UInt<1>("h00") xbar.io.masters[1].w.bits.data <= UInt<1>("h00") xbar.io.masters[1].w.valid <= UInt<1>("h00") xbar.io.masters[1].aw.bits.user <= UInt<1>("h00") xbar.io.masters[1].aw.bits.id <= UInt<1>("h00") xbar.io.masters[1].aw.bits.region <= UInt<1>("h00") xbar.io.masters[1].aw.bits.qos <= UInt<1>("h00") xbar.io.masters[1].aw.bits.prot <= UInt<1>("h00") xbar.io.masters[1].aw.bits.cache <= UInt<1>("h00") xbar.io.masters[1].aw.bits.lock <= UInt<1>("h00") xbar.io.masters[1].aw.bits.burst <= UInt<1>("h00") xbar.io.masters[1].aw.bits.size <= UInt<1>("h00") xbar.io.masters[1].aw.bits.len <= UInt<1>("h00") xbar.io.masters[1].aw.bits.addr <= UInt<1>("h00") xbar.io.masters[1].aw.valid <= UInt<1>("h00") xbar.clk <= clk xbar.reset <= reset xbar.io.masters <- io.masters io.slaves[0] <- xbar.io.slaves[0] inst T_2983 of NastiRecursiveInterconnect_56 T_2983.io.slaves[0].r.bits.user <= UInt<1>("h00") T_2983.io.slaves[0].r.bits.id <= UInt<1>("h00") T_2983.io.slaves[0].r.bits.last <= UInt<1>("h00") T_2983.io.slaves[0].r.bits.data <= UInt<1>("h00") T_2983.io.slaves[0].r.bits.resp <= UInt<1>("h00") T_2983.io.slaves[0].r.valid <= UInt<1>("h00") T_2983.io.slaves[0].ar.ready <= UInt<1>("h00") T_2983.io.slaves[0].b.bits.user <= UInt<1>("h00") T_2983.io.slaves[0].b.bits.id <= UInt<1>("h00") T_2983.io.slaves[0].b.bits.resp <= UInt<1>("h00") T_2983.io.slaves[0].b.valid <= UInt<1>("h00") T_2983.io.slaves[0].w.ready <= UInt<1>("h00") T_2983.io.slaves[0].aw.ready <= UInt<1>("h00") T_2983.io.slaves[1].r.bits.user <= UInt<1>("h00") T_2983.io.slaves[1].r.bits.id <= UInt<1>("h00") T_2983.io.slaves[1].r.bits.last <= UInt<1>("h00") T_2983.io.slaves[1].r.bits.data <= UInt<1>("h00") T_2983.io.slaves[1].r.bits.resp <= UInt<1>("h00") T_2983.io.slaves[1].r.valid <= UInt<1>("h00") T_2983.io.slaves[1].ar.ready <= UInt<1>("h00") T_2983.io.slaves[1].b.bits.user <= UInt<1>("h00") T_2983.io.slaves[1].b.bits.id <= UInt<1>("h00") T_2983.io.slaves[1].b.bits.resp <= UInt<1>("h00") T_2983.io.slaves[1].b.valid <= UInt<1>("h00") T_2983.io.slaves[1].w.ready <= UInt<1>("h00") T_2983.io.slaves[1].aw.ready <= UInt<1>("h00") T_2983.io.slaves[2].r.bits.user <= UInt<1>("h00") T_2983.io.slaves[2].r.bits.id <= UInt<1>("h00") T_2983.io.slaves[2].r.bits.last <= UInt<1>("h00") T_2983.io.slaves[2].r.bits.data <= UInt<1>("h00") T_2983.io.slaves[2].r.bits.resp <= UInt<1>("h00") T_2983.io.slaves[2].r.valid <= UInt<1>("h00") T_2983.io.slaves[2].ar.ready <= UInt<1>("h00") T_2983.io.slaves[2].b.bits.user <= UInt<1>("h00") T_2983.io.slaves[2].b.bits.id <= UInt<1>("h00") T_2983.io.slaves[2].b.bits.resp <= UInt<1>("h00") T_2983.io.slaves[2].b.valid <= UInt<1>("h00") T_2983.io.slaves[2].w.ready <= UInt<1>("h00") T_2983.io.slaves[2].aw.ready <= UInt<1>("h00") T_2983.io.masters[0].r.ready <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.user <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.id <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.region <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.qos <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.prot <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.cache <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.lock <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.burst <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.size <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.len <= UInt<1>("h00") T_2983.io.masters[0].ar.bits.addr <= UInt<1>("h00") T_2983.io.masters[0].ar.valid <= UInt<1>("h00") T_2983.io.masters[0].b.ready <= UInt<1>("h00") T_2983.io.masters[0].w.bits.user <= UInt<1>("h00") T_2983.io.masters[0].w.bits.strb <= UInt<1>("h00") T_2983.io.masters[0].w.bits.last <= UInt<1>("h00") T_2983.io.masters[0].w.bits.data <= UInt<1>("h00") T_2983.io.masters[0].w.valid <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.user <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.id <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.region <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.qos <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.prot <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.cache <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.lock <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.burst <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.size <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.len <= UInt<1>("h00") T_2983.io.masters[0].aw.bits.addr <= UInt<1>("h00") T_2983.io.masters[0].aw.valid <= UInt<1>("h00") T_2983.clk <= clk T_2983.reset <= reset T_2983.io.masters[0] <- xbar.io.slaves[1] io.slaves[1] <- T_2983.io.slaves[0] io.slaves[2] <- T_2983.io.slaves[1] io.slaves[3] <- T_2983.io.slaves[2] inst T_3054 of NastiErrorSlave_40 T_3054.io.r.ready <= UInt<1>("h00") T_3054.io.ar.bits.user <= UInt<1>("h00") T_3054.io.ar.bits.id <= UInt<1>("h00") T_3054.io.ar.bits.region <= UInt<1>("h00") T_3054.io.ar.bits.qos <= UInt<1>("h00") T_3054.io.ar.bits.prot <= UInt<1>("h00") T_3054.io.ar.bits.cache <= UInt<1>("h00") T_3054.io.ar.bits.lock <= UInt<1>("h00") T_3054.io.ar.bits.burst <= UInt<1>("h00") T_3054.io.ar.bits.size <= UInt<1>("h00") T_3054.io.ar.bits.len <= UInt<1>("h00") T_3054.io.ar.bits.addr <= UInt<1>("h00") T_3054.io.ar.valid <= UInt<1>("h00") T_3054.io.b.ready <= UInt<1>("h00") T_3054.io.w.bits.user <= UInt<1>("h00") T_3054.io.w.bits.strb <= UInt<1>("h00") T_3054.io.w.bits.last <= UInt<1>("h00") T_3054.io.w.bits.data <= UInt<1>("h00") T_3054.io.w.valid <= UInt<1>("h00") T_3054.io.aw.bits.user <= UInt<1>("h00") T_3054.io.aw.bits.id <= UInt<1>("h00") T_3054.io.aw.bits.region <= UInt<1>("h00") T_3054.io.aw.bits.qos <= UInt<1>("h00") T_3054.io.aw.bits.prot <= UInt<1>("h00") T_3054.io.aw.bits.cache <= UInt<1>("h00") T_3054.io.aw.bits.lock <= UInt<1>("h00") T_3054.io.aw.bits.burst <= UInt<1>("h00") T_3054.io.aw.bits.size <= UInt<1>("h00") T_3054.io.aw.bits.len <= UInt<1>("h00") T_3054.io.aw.bits.addr <= UInt<1>("h00") T_3054.io.aw.valid <= UInt<1>("h00") T_3054.clk <= clk T_3054.reset <= reset T_3054.io <- xbar.io.slaves[2] io.slaves[4] <- xbar.io.slaves[3] module LockingRRArbiter_67 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.union <= UInt<1>("h00") io.out.bits.a_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") reg T_656 : UInt<1>, clk, reset, UInt<1>("h00") reg T_658 : UInt, clk, reset, UInt<1>("h01") wire T_660 : UInt<1> T_660 <= UInt<1>("h00") io.out.valid <= io.in[T_660].valid io.out.bits <- io.in[T_660].bits io.chosen <= T_660 io.in[T_660].ready <= UInt<1>("h00") reg last_grant : UInt<1>, clk, reset, UInt<1>("h00") node T_843 = gt(UInt<1>("h00"), last_grant) node T_844 = and(io.in[0].valid, T_843) node T_846 = gt(UInt<1>("h01"), last_grant) node T_847 = and(io.in[1].valid, T_846) node T_850 = or(UInt<1>("h00"), T_844) node T_852 = eq(T_850, UInt<1>("h00")) node T_854 = or(UInt<1>("h00"), T_844) node T_855 = or(T_854, T_847) node T_857 = eq(T_855, UInt<1>("h00")) node T_859 = or(UInt<1>("h00"), T_844) node T_860 = or(T_859, T_847) node T_861 = or(T_860, io.in[0].valid) node T_863 = eq(T_861, UInt<1>("h00")) node T_865 = gt(UInt<1>("h00"), last_grant) node T_866 = and(UInt<1>("h01"), T_865) node T_867 = or(T_866, T_857) node T_869 = gt(UInt<1>("h01"), last_grant) node T_870 = and(T_852, T_869) node T_871 = or(T_870, T_863) node T_873 = eq(T_658, UInt<1>("h00")) node T_874 = mux(T_656, T_873, T_867) node T_875 = and(T_874, io.out.ready) io.in[0].ready <= T_875 node T_877 = eq(T_658, UInt<1>("h01")) node T_878 = mux(T_656, T_877, T_871) node T_879 = and(T_878, io.out.ready) io.in[1].ready <= T_879 reg T_881 : UInt<2>, clk, reset, UInt<2>("h00") node T_883 = addw(T_881, UInt<1>("h01")) node T_884 = and(io.out.ready, io.out.valid) when T_884 : node T_886 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_889 : UInt<3>[1] T_889[0] <= UInt<3>("h03") node T_892 = eq(T_889[0], io.out.bits.a_type) node T_894 = or(UInt<1>("h00"), T_892) node T_895 = and(T_886, T_894) when T_895 : T_881 <= T_883 node T_897 = eq(T_656, UInt<1>("h00")) when T_897 : T_656 <= UInt<1>("h01") node T_899 = and(io.in[0].ready, io.in[0].valid) node T_900 = and(io.in[1].ready, io.in[1].valid) wire T_902 : UInt<1>[2] T_902[0] <= T_899 T_902[1] <= T_900 node T_908 = mux(T_902[0], UInt<1>("h00"), UInt<1>("h01")) T_658 <= T_908 skip skip node T_910 = eq(T_883, UInt<1>("h00")) when T_910 : T_656 <= UInt<1>("h00") skip skip node T_914 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_916 = gt(UInt<1>("h01"), last_grant) node T_917 = and(io.in[1].valid, T_916) node choose = mux(T_917, UInt<1>("h01"), T_914) node T_920 = mux(T_656, T_658, choose) T_660 <= T_920 node T_921 = and(io.out.ready, io.out.valid) when T_921 : last_grant <= T_660 skip module ReorderQueue : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} io.deq.matches <= UInt<1>("h00") io.deq.data <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") reg roq_data : UInt<1>[9], clk, UInt<1>("h00"), roq_data reg roq_tags : UInt<4>[9], clk, UInt<1>("h00"), roq_tags wire T_93 : UInt<1>[9] T_93[0] <= UInt<1>("h01") T_93[1] <= UInt<1>("h01") T_93[2] <= UInt<1>("h01") T_93[3] <= UInt<1>("h01") T_93[4] <= UInt<1>("h01") T_93[5] <= UInt<1>("h01") T_93[6] <= UInt<1>("h01") T_93[7] <= UInt<1>("h01") T_93[8] <= UInt<1>("h01") reg roq_free : UInt<1>[9], clk, reset, T_93 node T_126 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) node T_127 = mux(roq_free[6], UInt<3>("h06"), T_126) node T_128 = mux(roq_free[5], UInt<3>("h05"), T_127) node T_129 = mux(roq_free[4], UInt<3>("h04"), T_128) node T_130 = mux(roq_free[3], UInt<2>("h03"), T_129) node T_131 = mux(roq_free[2], UInt<2>("h02"), T_130) node T_132 = mux(roq_free[1], UInt<1>("h01"), T_131) node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_132) node T_134 = eq(roq_tags[0], io.deq.tag) node T_136 = eq(roq_free[0], UInt<1>("h00")) node T_137 = and(T_134, T_136) node T_138 = eq(roq_tags[1], io.deq.tag) node T_140 = eq(roq_free[1], UInt<1>("h00")) node T_141 = and(T_138, T_140) node T_142 = eq(roq_tags[2], io.deq.tag) node T_144 = eq(roq_free[2], UInt<1>("h00")) node T_145 = and(T_142, T_144) node T_146 = eq(roq_tags[3], io.deq.tag) node T_148 = eq(roq_free[3], UInt<1>("h00")) node T_149 = and(T_146, T_148) node T_150 = eq(roq_tags[4], io.deq.tag) node T_152 = eq(roq_free[4], UInt<1>("h00")) node T_153 = and(T_150, T_152) node T_154 = eq(roq_tags[5], io.deq.tag) node T_156 = eq(roq_free[5], UInt<1>("h00")) node T_157 = and(T_154, T_156) node T_158 = eq(roq_tags[6], io.deq.tag) node T_160 = eq(roq_free[6], UInt<1>("h00")) node T_161 = and(T_158, T_160) node T_162 = eq(roq_tags[7], io.deq.tag) node T_164 = eq(roq_free[7], UInt<1>("h00")) node T_165 = and(T_162, T_164) node T_166 = eq(roq_tags[8], io.deq.tag) node T_168 = eq(roq_free[8], UInt<1>("h00")) node T_169 = and(T_166, T_168) node T_179 = mux(T_165, UInt<3>("h07"), UInt<4>("h08")) node T_180 = mux(T_161, UInt<3>("h06"), T_179) node T_181 = mux(T_157, UInt<3>("h05"), T_180) node T_182 = mux(T_153, UInt<3>("h04"), T_181) node T_183 = mux(T_149, UInt<2>("h03"), T_182) node T_184 = mux(T_145, UInt<2>("h02"), T_183) node T_185 = mux(T_141, UInt<1>("h01"), T_184) node roq_deq_addr = mux(T_137, UInt<1>("h00"), T_185) node T_187 = or(roq_free[0], roq_free[1]) node T_188 = or(T_187, roq_free[2]) node T_189 = or(T_188, roq_free[3]) node T_190 = or(T_189, roq_free[4]) node T_191 = or(T_190, roq_free[5]) node T_192 = or(T_191, roq_free[6]) node T_193 = or(T_192, roq_free[7]) node T_194 = or(T_193, roq_free[8]) io.enq.ready <= T_194 io.deq.data <= roq_data[roq_deq_addr] node T_196 = or(T_137, T_141) node T_197 = or(T_196, T_145) node T_198 = or(T_197, T_149) node T_199 = or(T_198, T_153) node T_200 = or(T_199, T_157) node T_201 = or(T_200, T_161) node T_202 = or(T_201, T_165) node T_203 = or(T_202, T_169) io.deq.matches <= T_203 node T_204 = and(io.enq.valid, io.enq.ready) when T_204 : roq_data[roq_enq_addr] <= io.enq.bits.data roq_tags[roq_enq_addr] <= io.enq.bits.tag roq_free[roq_enq_addr] <= UInt<1>("h00") skip when io.deq.valid : roq_free[roq_deq_addr] <= UInt<1>("h01") skip module ClientTileLinkIOUnwrapper : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} io.out.grant.ready <= UInt<1>("h00") io.out.acquire.bits.data <= UInt<1>("h00") io.out.acquire.bits.union <= UInt<1>("h00") io.out.acquire.bits.a_type <= UInt<1>("h00") io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") io.out.acquire.bits.addr_beat <= UInt<1>("h00") io.out.acquire.bits.client_xact_id <= UInt<1>("h00") io.out.acquire.bits.addr_block <= UInt<1>("h00") io.out.acquire.valid <= UInt<1>("h00") io.in.release.ready <= UInt<1>("h00") io.in.probe.bits.p_type <= UInt<1>("h00") io.in.probe.bits.addr_block <= UInt<1>("h00") io.in.probe.valid <= UInt<1>("h00") io.in.grant.bits.data <= UInt<1>("h00") io.in.grant.bits.g_type <= UInt<1>("h00") io.in.grant.bits.is_builtin_type <= UInt<1>("h00") io.in.grant.bits.manager_xact_id <= UInt<1>("h00") io.in.grant.bits.client_xact_id <= UInt<1>("h00") io.in.grant.bits.addr_beat <= UInt<1>("h00") io.in.grant.valid <= UInt<1>("h00") io.in.acquire.ready <= UInt<1>("h00") inst acqArb of LockingRRArbiter_67 acqArb.io.out.ready <= UInt<1>("h00") acqArb.io.in[0].bits.data <= UInt<1>("h00") acqArb.io.in[0].bits.union <= UInt<1>("h00") acqArb.io.in[0].bits.a_type <= UInt<1>("h00") acqArb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") acqArb.io.in[0].bits.addr_beat <= UInt<1>("h00") acqArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") acqArb.io.in[0].bits.addr_block <= UInt<1>("h00") acqArb.io.in[0].valid <= UInt<1>("h00") acqArb.io.in[1].bits.data <= UInt<1>("h00") acqArb.io.in[1].bits.union <= UInt<1>("h00") acqArb.io.in[1].bits.a_type <= UInt<1>("h00") acqArb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") acqArb.io.in[1].bits.addr_beat <= UInt<1>("h00") acqArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") acqArb.io.in[1].bits.addr_block <= UInt<1>("h00") acqArb.io.in[1].valid <= UInt<1>("h00") acqArb.clk <= clk acqArb.reset <= reset inst acqRoq of ReorderQueue acqRoq.io.deq.tag <= UInt<1>("h00") acqRoq.io.deq.valid <= UInt<1>("h00") acqRoq.io.enq.bits.tag <= UInt<1>("h00") acqRoq.io.enq.bits.data <= UInt<1>("h00") acqRoq.io.enq.valid <= UInt<1>("h00") acqRoq.clk <= clk acqRoq.reset <= reset inst relRoq of ReorderQueue relRoq.io.deq.tag <= UInt<1>("h00") relRoq.io.deq.valid <= UInt<1>("h00") relRoq.io.enq.bits.tag <= UInt<1>("h00") relRoq.io.enq.bits.data <= UInt<1>("h00") relRoq.io.enq.valid <= UInt<1>("h00") relRoq.clk <= clk relRoq.reset <= reset node T_1242 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) wire T_1245 : UInt<3>[1] T_1245[0] <= UInt<3>("h03") node T_1248 = eq(T_1245[0], io.in.acquire.bits.a_type) node T_1250 = or(UInt<1>("h00"), T_1248) node T_1251 = and(T_1242, T_1250) node T_1253 = eq(T_1251, UInt<1>("h00")) node T_1255 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) node acq_roq_enq = or(T_1253, T_1255) wire T_1259 : UInt<2>[3] T_1259[0] <= UInt<1>("h00") T_1259[1] <= UInt<1>("h01") T_1259[2] <= UInt<2>("h02") node T_1264 = eq(T_1259[0], io.in.release.bits.r_type) node T_1265 = eq(T_1259[1], io.in.release.bits.r_type) node T_1266 = eq(T_1259[2], io.in.release.bits.r_type) node T_1268 = or(UInt<1>("h00"), T_1264) node T_1269 = or(T_1268, T_1265) node T_1270 = or(T_1269, T_1266) node T_1271 = and(UInt<1>("h01"), T_1270) node T_1273 = eq(T_1271, UInt<1>("h00")) node T_1275 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) node rel_roq_enq = or(T_1273, T_1275) node T_1278 = eq(acq_roq_enq, UInt<1>("h00")) node acq_roq_ready = or(T_1278, acqRoq.io.enq.ready) node T_1281 = eq(rel_roq_enq, UInt<1>("h00")) node rel_roq_ready = or(T_1281, relRoq.io.enq.ready) node T_1283 = and(io.in.acquire.valid, acqArb.io.in[0].ready) node T_1284 = and(T_1283, acq_roq_enq) acqRoq.io.enq.valid <= T_1284 acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id node T_1285 = and(io.in.acquire.valid, acq_roq_ready) acqArb.io.in[0].valid <= T_1285 node T_1288 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) node T_1290 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1291 = cat(UInt<3>("h07"), T_1290) node T_1292 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1291) wire T_1321 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1321.data <= UInt<1>("h00") T_1321.union <= UInt<1>("h00") T_1321.a_type <= UInt<1>("h00") T_1321.is_builtin_type <= UInt<1>("h00") T_1321.addr_beat <= UInt<1>("h00") T_1321.client_xact_id <= UInt<1>("h00") T_1321.addr_block <= UInt<1>("h00") T_1321.is_builtin_type <= UInt<1>("h01") T_1321.a_type <= T_1288 T_1321.client_xact_id <= io.in.acquire.bits.client_xact_id T_1321.addr_block <= io.in.acquire.bits.addr_block T_1321.addr_beat <= io.in.acquire.bits.addr_beat T_1321.data <= io.in.acquire.bits.data T_1321.union <= T_1292 acqArb.io.in[0].bits <- T_1321 node T_1356 = and(acq_roq_ready, acqArb.io.in[0].ready) io.in.acquire.ready <= T_1356 node T_1357 = and(io.in.release.valid, acqArb.io.in[1].ready) node T_1358 = and(T_1357, rel_roq_enq) relRoq.io.enq.valid <= T_1358 relRoq.io.enq.bits.data <= io.in.release.bits.voluntary relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id node T_1359 = and(io.in.release.valid, rel_roq_ready) acqArb.io.in[1].valid <= T_1359 node T_1381 = asUInt(asSInt(UInt<16>("h0ffff"))) node T_1389 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1390 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1391 = cat(T_1389, T_1390) node T_1393 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1394 = cat(UInt<3>("h07"), T_1393) node T_1396 = cat(T_1381, UInt<1>("h01")) node T_1398 = cat(T_1381, UInt<1>("h01")) node T_1400 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1401 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1402 = cat(T_1400, T_1401) node T_1404 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1406 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1407 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_1408 = mux(T_1407, T_1406, UInt<1>("h00")) node T_1409 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_1410 = mux(T_1409, T_1404, T_1408) node T_1411 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_1412 = mux(T_1411, T_1402, T_1410) node T_1413 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_1414 = mux(T_1413, T_1398, T_1412) node T_1415 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_1416 = mux(T_1415, T_1396, T_1414) node T_1417 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_1418 = mux(T_1417, T_1394, T_1416) node T_1419 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_1420 = mux(T_1419, T_1391, T_1418) wire T_1449 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1449.data <= UInt<1>("h00") T_1449.union <= UInt<1>("h00") T_1449.a_type <= UInt<1>("h00") T_1449.is_builtin_type <= UInt<1>("h00") T_1449.addr_beat <= UInt<1>("h00") T_1449.client_xact_id <= UInt<1>("h00") T_1449.addr_block <= UInt<1>("h00") T_1449.is_builtin_type <= UInt<1>("h01") T_1449.a_type <= UInt<3>("h03") T_1449.client_xact_id <= io.in.release.bits.client_xact_id T_1449.addr_block <= io.in.release.bits.addr_block T_1449.addr_beat <= io.in.release.bits.addr_beat T_1449.data <= io.in.release.bits.data T_1449.union <= T_1420 acqArb.io.in[1].bits <- T_1449 node T_1484 = and(rel_roq_ready, acqArb.io.in[1].ready) io.in.release.ready <= T_1484 io.out.acquire <- acqArb.io.out node T_1485 = and(io.out.grant.ready, io.out.grant.valid) wire T_1489 : UInt<3>[1] T_1489[0] <= UInt<3>("h05") node T_1492 = eq(T_1489[0], io.out.grant.bits.g_type) node T_1494 = or(UInt<1>("h00"), T_1492) wire T_1496 : UInt<1>[1] T_1496[0] <= UInt<1>("h00") node T_1499 = eq(T_1496[0], io.out.grant.bits.g_type) node T_1501 = or(UInt<1>("h00"), T_1499) node T_1502 = mux(io.out.grant.bits.is_builtin_type, T_1494, T_1501) node T_1503 = and(UInt<1>("h01"), T_1502) node T_1505 = eq(T_1503, UInt<1>("h00")) node T_1507 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) node T_1508 = or(T_1505, T_1507) node T_1509 = and(T_1485, T_1508) acqRoq.io.deq.valid <= T_1509 acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id node T_1510 = and(io.out.grant.ready, io.out.grant.valid) wire T_1514 : UInt<3>[1] T_1514[0] <= UInt<3>("h05") node T_1517 = eq(T_1514[0], io.out.grant.bits.g_type) node T_1519 = or(UInt<1>("h00"), T_1517) wire T_1521 : UInt<1>[1] T_1521[0] <= UInt<1>("h00") node T_1524 = eq(T_1521[0], io.out.grant.bits.g_type) node T_1526 = or(UInt<1>("h00"), T_1524) node T_1527 = mux(io.out.grant.bits.is_builtin_type, T_1519, T_1526) node T_1528 = and(UInt<1>("h01"), T_1527) node T_1530 = eq(T_1528, UInt<1>("h00")) node T_1532 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) node T_1533 = or(T_1530, T_1532) node T_1534 = and(T_1510, T_1533) relRoq.io.deq.valid <= T_1534 relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id node T_1535 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00")) wire acq_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} acq_grant.data <= UInt<1>("h00") acq_grant.g_type <= UInt<1>("h00") acq_grant.is_builtin_type <= UInt<1>("h00") acq_grant.manager_xact_id <= UInt<1>("h00") acq_grant.client_xact_id <= UInt<1>("h00") acq_grant.addr_beat <= UInt<1>("h00") acq_grant.is_builtin_type <= acqRoq.io.deq.data acq_grant.g_type <= T_1535 acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id acq_grant.addr_beat <= io.out.grant.bits.addr_beat acq_grant.data <= io.out.grant.bits.data node T_1598 = mux(relRoq.io.deq.data, UInt<3>("h00"), io.out.grant.bits.g_type) wire rel_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} rel_grant.data <= UInt<1>("h00") rel_grant.g_type <= UInt<1>("h00") rel_grant.is_builtin_type <= UInt<1>("h00") rel_grant.manager_xact_id <= UInt<1>("h00") rel_grant.client_xact_id <= UInt<1>("h00") rel_grant.addr_beat <= UInt<1>("h00") rel_grant.is_builtin_type <= UInt<1>("h01") rel_grant.g_type <= T_1598 rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id rel_grant.addr_beat <= io.out.grant.bits.addr_beat rel_grant.data <= io.out.grant.bits.data io.in.grant.valid <= io.out.grant.valid wire T_1686 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_1686 <- rel_grant when acqRoq.io.deq.matches : T_1686 <- acq_grant skip io.in.grant.bits <- T_1686 io.out.grant.ready <= io.in.grant.ready io.in.probe.valid <= UInt<1>("h00") module TileLinkIONarrower : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} io.out.grant.ready <= UInt<1>("h00") io.out.acquire.bits.data <= UInt<1>("h00") io.out.acquire.bits.union <= UInt<1>("h00") io.out.acquire.bits.a_type <= UInt<1>("h00") io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") io.out.acquire.bits.addr_beat <= UInt<1>("h00") io.out.acquire.bits.client_xact_id <= UInt<1>("h00") io.out.acquire.bits.addr_block <= UInt<1>("h00") io.out.acquire.valid <= UInt<1>("h00") io.in.grant.bits.data <= UInt<1>("h00") io.in.grant.bits.g_type <= UInt<1>("h00") io.in.grant.bits.is_builtin_type <= UInt<1>("h00") io.in.grant.bits.manager_xact_id <= UInt<1>("h00") io.in.grant.bits.client_xact_id <= UInt<1>("h00") io.in.grant.bits.addr_beat <= UInt<1>("h00") io.in.grant.valid <= UInt<1>("h00") io.in.acquire.ready <= UInt<1>("h00") node T_815 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) node T_817 = eq(io.in.acquire.bits.a_type, UInt<3>("h01")) node T_819 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) node T_821 = eq(io.in.acquire.bits.a_type, UInt<3>("h00")) reg T_823 : UInt<128>, clk, UInt<1>("h00"), T_823 reg T_825 : UInt<16>, clk, UInt<1>("h00"), T_825 reg T_826 : UInt<4>, clk, UInt<1>("h00"), T_826 reg T_827 : UInt<26>, clk, UInt<1>("h00"), T_827 reg T_828 : UInt<2>, clk, UInt<1>("h00"), T_828 reg T_830 : UInt<1>, clk, reset, UInt<1>("h00") node T_831 = bits(io.in.acquire.bits.union, 12, 9) node T_832 = cat(io.in.acquire.bits.addr_beat, T_831) node T_833 = cat(io.in.acquire.bits.addr_block, T_832) node T_834 = bits(T_833, 3, 3) node T_835 = bits(io.in.acquire.bits.union, 12, 9) node T_836 = cat(io.in.acquire.bits.addr_beat, T_835) node T_837 = cat(io.in.acquire.bits.addr_block, T_836) node T_838 = bits(T_837, 5, 3) node T_839 = bits(io.in.acquire.bits.union, 12, 9) node T_840 = cat(io.in.acquire.bits.addr_beat, T_839) node T_841 = cat(io.in.acquire.bits.addr_block, T_840) node T_842 = bits(T_841, 2, 0) node T_843 = bits(io.in.acquire.bits.union, 12, 9) node T_844 = bits(T_843, 3, 3) node T_846 = dshl(UInt<1>("h01"), T_844) node T_848 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) node T_849 = and(io.in.acquire.bits.is_builtin_type, T_848) node T_850 = bit(T_846, 0) node T_851 = bit(T_846, 1) wire T_853 : UInt<1>[2] T_853[0] <= T_850 T_853[1] <= T_851 node T_858 = subw(UInt<8>("h00"), T_853[0]) node T_860 = subw(UInt<8>("h00"), T_853[1]) wire T_862 : UInt<8>[2] T_862[0] <= T_858 T_862[1] <= T_860 node T_866 = cat(T_862[1], T_862[0]) node T_868 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) node T_869 = and(io.in.acquire.bits.is_builtin_type, T_868) node T_871 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) node T_872 = and(io.in.acquire.bits.is_builtin_type, T_871) node T_873 = or(T_869, T_872) node T_874 = bits(io.in.acquire.bits.union, 16, 1) node T_876 = mux(T_873, T_874, UInt<16>("h00")) node T_877 = mux(T_849, T_866, T_876) node T_878 = bits(T_877, 7, 0) node T_879 = bits(io.in.acquire.bits.union, 12, 9) node T_880 = bits(T_879, 3, 3) node T_882 = dshl(UInt<1>("h01"), T_880) node T_884 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) node T_885 = and(io.in.acquire.bits.is_builtin_type, T_884) node T_886 = bit(T_882, 0) node T_887 = bit(T_882, 1) wire T_889 : UInt<1>[2] T_889[0] <= T_886 T_889[1] <= T_887 node T_894 = subw(UInt<8>("h00"), T_889[0]) node T_896 = subw(UInt<8>("h00"), T_889[1]) wire T_898 : UInt<8>[2] T_898[0] <= T_894 T_898[1] <= T_896 node T_902 = cat(T_898[1], T_898[0]) node T_904 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) node T_905 = and(io.in.acquire.bits.is_builtin_type, T_904) node T_907 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) node T_908 = and(io.in.acquire.bits.is_builtin_type, T_907) node T_909 = or(T_905, T_908) node T_910 = bits(io.in.acquire.bits.union, 16, 1) node T_912 = mux(T_909, T_910, UInt<16>("h00")) node T_913 = mux(T_885, T_902, T_912) node T_914 = bits(T_913, 15, 8) wire T_916 : UInt<8>[2] T_916[0] <= T_878 T_916[1] <= T_914 node T_920 = bits(io.in.acquire.bits.data, 63, 0) node T_921 = bits(io.in.acquire.bits.data, 127, 64) wire T_923 : UInt<64>[2] T_923[0] <= T_920 T_923[1] <= T_921 node T_928 = neq(T_916[0], UInt<1>("h00")) node T_930 = neq(T_916[1], UInt<1>("h00")) node T_931 = cat(T_930, T_928) node T_932 = bit(T_931, 0) node T_933 = bit(T_931, 1) node T_935 = mux(T_932, T_923[0], UInt<1>("h00")) node T_937 = mux(T_933, T_923[1], UInt<1>("h00")) node T_939 = or(T_935, T_937) wire T_940 : UInt<64> T_940 <= UInt<1>("h00") T_940 <= T_939 node T_942 = bit(T_931, 0) node T_943 = bit(T_931, 1) node T_945 = mux(T_942, T_916[0], UInt<1>("h00")) node T_947 = mux(T_943, T_916[1], UInt<1>("h00")) node T_949 = or(T_945, T_947) wire T_950 : UInt<8> T_950 <= UInt<1>("h00") T_950 <= T_949 node T_952 = bit(T_931, 0) node T_953 = bit(T_931, 1) wire T_955 : UInt<1>[2] T_955[0] <= T_952 T_955[1] <= T_953 node T_961 = mux(T_955[0], UInt<1>("h00"), UInt<1>("h01")) node T_962 = cat(io.in.acquire.bits.addr_beat, T_961) node T_964 = eq(io.in.acquire.valid, UInt<1>("h00")) node T_966 = eq(T_819, UInt<1>("h00")) node T_967 = or(T_964, T_966) node T_968 = bit(T_931, 0) node T_969 = bit(T_931, 1) node T_971 = cat(UInt<1>("h00"), T_969) node T_972 = addw(T_968, T_971) node T_974 = leq(T_972, UInt<1>("h01")) node T_975 = or(T_967, T_974) node T_977 = eq(reset, UInt<1>("h00")) when T_977 : node T_979 = eq(T_975, UInt<1>("h00")) when T_979 : node T_981 = eq(reset, UInt<1>("h00")) when T_981 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width") skip stop(clk, UInt<1>(1), 1) skip skip node T_982 = bits(io.in.acquire.bits.union, 8, 6) node T_991 = eq(UInt<3>("h07"), T_982) node T_992 = mux(T_991, UInt<1>("h00"), UInt<1>("h00")) node T_993 = eq(UInt<3>("h03"), T_982) node T_994 = mux(T_993, UInt<1>("h01"), T_992) node T_995 = eq(UInt<3>("h02"), T_982) node T_996 = mux(T_995, UInt<1>("h01"), T_994) node T_997 = eq(UInt<3>("h05"), T_982) node T_998 = mux(T_997, UInt<1>("h01"), T_996) node T_999 = eq(UInt<3>("h01"), T_982) node T_1000 = mux(T_999, UInt<1>("h01"), T_998) node T_1001 = eq(UInt<3>("h04"), T_982) node T_1002 = mux(T_1001, UInt<1>("h01"), T_1000) node T_1003 = eq(UInt<3>("h00"), T_982) node T_1004 = mux(T_1003, UInt<1>("h01"), T_1002) node T_1006 = eq(io.in.acquire.valid, UInt<1>("h00")) node T_1008 = eq(T_821, UInt<1>("h00")) node T_1009 = or(T_1006, T_1008) node T_1010 = or(T_1009, T_1004) node T_1012 = eq(reset, UInt<1>("h00")) when T_1012 : node T_1014 = eq(T_1010, UInt<1>("h00")) when T_1014 : node T_1016 = eq(reset, UInt<1>("h00")) when T_1016 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width") skip stop(clk, UInt<1>(1), 1) skip skip node T_1017 = bit(io.in.acquire.bits.union, 0) node T_1026 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1027 = cat(UInt<5>("h00"), T_1017) node T_1028 = cat(T_1026, T_1027) node T_1030 = cat(UInt<5>("h00"), T_1017) node T_1031 = cat(UInt<3>("h07"), T_1030) node T_1033 = cat(UInt<1>("h00"), T_1017) node T_1035 = cat(UInt<1>("h00"), T_1017) node T_1037 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1038 = cat(UInt<5>("h00"), T_1017) node T_1039 = cat(T_1037, T_1038) node T_1041 = cat(UInt<5>("h00"), T_1017) node T_1043 = cat(UInt<5>("h01"), T_1017) node T_1044 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1045 = mux(T_1044, T_1043, UInt<1>("h00")) node T_1046 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1047 = mux(T_1046, T_1041, T_1045) node T_1048 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1049 = mux(T_1048, T_1039, T_1047) node T_1050 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1051 = mux(T_1050, T_1035, T_1049) node T_1052 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1053 = mux(T_1052, T_1033, T_1051) node T_1054 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1055 = mux(T_1054, T_1031, T_1053) node T_1056 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1057 = mux(T_1056, T_1028, T_1055) wire T_1086 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1086.data <= UInt<1>("h00") T_1086.union <= UInt<1>("h00") T_1086.a_type <= UInt<1>("h00") T_1086.is_builtin_type <= UInt<1>("h00") T_1086.addr_beat <= UInt<1>("h00") T_1086.client_xact_id <= UInt<1>("h00") T_1086.addr_block <= UInt<1>("h00") T_1086.is_builtin_type <= UInt<1>("h01") T_1086.a_type <= UInt<3>("h01") T_1086.client_xact_id <= io.in.acquire.bits.client_xact_id T_1086.addr_block <= io.in.acquire.bits.addr_block T_1086.addr_beat <= UInt<1>("h00") T_1086.data <= UInt<1>("h00") T_1086.union <= T_1057 node T_1121 = cat(T_828, T_830) node T_1122 = bits(T_823, 63, 0) node T_1123 = bits(T_825, 7, 0) node T_1131 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1132 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1133 = cat(T_1131, T_1132) node T_1135 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1136 = cat(UInt<3>("h07"), T_1135) node T_1138 = cat(T_1123, UInt<1>("h01")) node T_1140 = cat(T_1123, UInt<1>("h01")) node T_1142 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1143 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1144 = cat(T_1142, T_1143) node T_1146 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1148 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1149 = eq(UInt<3>("h06"), UInt<3>("h03")) node T_1150 = mux(T_1149, T_1148, UInt<1>("h00")) node T_1151 = eq(UInt<3>("h05"), UInt<3>("h03")) node T_1152 = mux(T_1151, T_1146, T_1150) node T_1153 = eq(UInt<3>("h04"), UInt<3>("h03")) node T_1154 = mux(T_1153, T_1144, T_1152) node T_1155 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_1156 = mux(T_1155, T_1140, T_1154) node T_1157 = eq(UInt<3>("h02"), UInt<3>("h03")) node T_1158 = mux(T_1157, T_1138, T_1156) node T_1159 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_1160 = mux(T_1159, T_1136, T_1158) node T_1161 = eq(UInt<3>("h00"), UInt<3>("h03")) node T_1162 = mux(T_1161, T_1133, T_1160) wire T_1191 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1191.data <= UInt<1>("h00") T_1191.union <= UInt<1>("h00") T_1191.a_type <= UInt<1>("h00") T_1191.is_builtin_type <= UInt<1>("h00") T_1191.addr_beat <= UInt<1>("h00") T_1191.client_xact_id <= UInt<1>("h00") T_1191.addr_block <= UInt<1>("h00") T_1191.is_builtin_type <= UInt<1>("h01") T_1191.a_type <= UInt<3>("h03") T_1191.client_xact_id <= T_826 T_1191.addr_block <= T_827 T_1191.addr_beat <= T_1121 T_1191.data <= T_1122 T_1191.union <= T_1162 node T_1226 = bits(io.in.acquire.bits.union, 8, 6) node T_1227 = bit(io.in.acquire.bits.union, 0) node T_1234 = cat(T_842, T_1226) node T_1235 = cat(UInt<5>("h00"), T_1227) node T_1236 = cat(T_1234, T_1235) node T_1238 = cat(UInt<5>("h00"), T_1227) node T_1239 = cat(T_1226, T_1238) node T_1241 = cat(UInt<1>("h00"), T_1227) node T_1243 = cat(UInt<1>("h00"), T_1227) node T_1245 = cat(T_842, T_1226) node T_1246 = cat(UInt<5>("h00"), T_1227) node T_1247 = cat(T_1245, T_1246) node T_1249 = cat(UInt<5>("h00"), T_1227) node T_1251 = cat(UInt<5>("h01"), T_1227) node T_1252 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_1253 = mux(T_1252, T_1251, UInt<1>("h00")) node T_1254 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_1255 = mux(T_1254, T_1249, T_1253) node T_1256 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_1257 = mux(T_1256, T_1247, T_1255) node T_1258 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_1259 = mux(T_1258, T_1243, T_1257) node T_1260 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_1261 = mux(T_1260, T_1241, T_1259) node T_1262 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_1263 = mux(T_1262, T_1239, T_1261) node T_1264 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_1265 = mux(T_1264, T_1236, T_1263) wire T_1294 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1294.data <= UInt<1>("h00") T_1294.union <= UInt<1>("h00") T_1294.a_type <= UInt<1>("h00") T_1294.is_builtin_type <= UInt<1>("h00") T_1294.addr_beat <= UInt<1>("h00") T_1294.client_xact_id <= UInt<1>("h00") T_1294.addr_block <= UInt<1>("h00") T_1294.is_builtin_type <= UInt<1>("h01") T_1294.a_type <= UInt<3>("h00") T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id T_1294.addr_block <= io.in.acquire.bits.addr_block T_1294.addr_beat <= T_838 T_1294.data <= UInt<1>("h00") T_1294.union <= T_1265 node T_1336 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1337 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1338 = cat(T_1336, T_1337) node T_1340 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1341 = cat(UInt<3>("h07"), T_1340) node T_1343 = cat(T_950, UInt<1>("h01")) node T_1345 = cat(T_950, UInt<1>("h01")) node T_1347 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1348 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1349 = cat(T_1347, T_1348) node T_1351 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1353 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1354 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_1355 = mux(T_1354, T_1353, UInt<1>("h00")) node T_1356 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_1357 = mux(T_1356, T_1351, T_1355) node T_1358 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_1359 = mux(T_1358, T_1349, T_1357) node T_1360 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_1361 = mux(T_1360, T_1345, T_1359) node T_1362 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_1363 = mux(T_1362, T_1343, T_1361) node T_1364 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_1365 = mux(T_1364, T_1341, T_1363) node T_1366 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_1367 = mux(T_1366, T_1338, T_1365) wire T_1396 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1396.data <= UInt<1>("h00") T_1396.union <= UInt<1>("h00") T_1396.a_type <= UInt<1>("h00") T_1396.is_builtin_type <= UInt<1>("h00") T_1396.addr_beat <= UInt<1>("h00") T_1396.client_xact_id <= UInt<1>("h00") T_1396.addr_block <= UInt<1>("h00") T_1396.is_builtin_type <= UInt<1>("h01") T_1396.a_type <= UInt<3>("h02") T_1396.client_xact_id <= io.in.acquire.bits.client_xact_id T_1396.addr_block <= io.in.acquire.bits.addr_block T_1396.addr_beat <= T_962 T_1396.data <= T_940 T_1396.union <= T_1367 reg T_1432 : UInt<1>, clk, reset, UInt<1>("h00") node T_1434 = eq(T_815, UInt<1>("h00")) node T_1435 = and(io.in.acquire.valid, T_1434) node T_1437 = eq(T_821, UInt<1>("h00")) node T_1438 = and(T_1435, T_1437) node T_1439 = and(T_821, io.in.acquire.valid) inst T_1440 of ReorderQueue T_1440.io.deq.tag <= UInt<1>("h00") T_1440.io.deq.valid <= UInt<1>("h00") T_1440.io.enq.bits.tag <= UInt<1>("h00") T_1440.io.enq.bits.data <= UInt<1>("h00") T_1440.io.enq.valid <= UInt<1>("h00") T_1440.clk <= clk T_1440.reset <= reset node T_1447 = eq(T_1432, UInt<1>("h00")) node T_1448 = and(T_1439, io.out.acquire.ready) node T_1449 = and(T_1448, T_1447) T_1440.io.enq.valid <= T_1449 T_1440.io.enq.bits.data <= T_834 T_1440.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id wire T_1450 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1450 <- io.in.acquire.bits wire T_1506 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1506 <- T_1450 when T_821 : T_1506 <- T_1294 skip wire T_1562 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1562 <- T_1506 when T_819 : T_1562 <- T_1396 skip wire T_1618 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1618 <- T_1562 when T_817 : T_1618 <- T_1086 skip wire T_1674 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} T_1674 <- T_1618 when T_1432 : T_1674 <- T_1191 skip io.out.acquire.bits <- T_1674 node T_1702 = or(T_1432, T_1438) node T_1703 = and(T_1439, T_1440.io.enq.ready) node T_1704 = or(T_1702, T_1703) io.out.acquire.valid <= T_1704 node T_1706 = eq(T_1432, UInt<1>("h00")) node T_1708 = eq(T_821, UInt<1>("h00")) node T_1709 = and(T_1708, io.out.acquire.ready) node T_1710 = or(T_815, T_1709) node T_1711 = and(T_1440.io.enq.ready, io.out.acquire.ready) node T_1712 = or(T_1710, T_1711) node T_1713 = and(T_1706, T_1712) io.in.acquire.ready <= T_1713 node T_1714 = and(io.in.acquire.ready, io.in.acquire.valid) node T_1715 = and(T_1714, T_815) when T_1715 : T_823 <= io.in.acquire.bits.data node T_1716 = bits(io.in.acquire.bits.union, 12, 9) node T_1717 = bits(T_1716, 3, 3) node T_1719 = dshl(UInt<1>("h01"), T_1717) node T_1721 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) node T_1722 = and(io.in.acquire.bits.is_builtin_type, T_1721) node T_1723 = bit(T_1719, 0) node T_1724 = bit(T_1719, 1) wire T_1726 : UInt<1>[2] T_1726[0] <= T_1723 T_1726[1] <= T_1724 node T_1731 = subw(UInt<8>("h00"), T_1726[0]) node T_1733 = subw(UInt<8>("h00"), T_1726[1]) wire T_1735 : UInt<8>[2] T_1735[0] <= T_1731 T_1735[1] <= T_1733 node T_1739 = cat(T_1735[1], T_1735[0]) node T_1741 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) node T_1742 = and(io.in.acquire.bits.is_builtin_type, T_1741) node T_1744 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) node T_1745 = and(io.in.acquire.bits.is_builtin_type, T_1744) node T_1746 = or(T_1742, T_1745) node T_1747 = bits(io.in.acquire.bits.union, 16, 1) node T_1749 = mux(T_1746, T_1747, UInt<16>("h00")) node T_1750 = mux(T_1722, T_1739, T_1749) T_825 <= T_1750 T_826 <= io.in.acquire.bits.client_xact_id T_827 <= io.in.acquire.bits.addr_block T_828 <= io.in.acquire.bits.addr_beat T_1432 <= UInt<1>("h01") skip node T_1752 = and(T_1432, io.out.acquire.ready) when T_1752 : node T_1753 = shr(T_823, 64) T_823 <= T_1753 node T_1754 = shr(T_825, 8) T_825 <= T_1754 node T_1756 = eq(T_830, UInt<1>("h01")) node T_1758 = and(UInt<1>("h00"), T_1756) node T_1761 = addw(T_830, UInt<1>("h01")) node T_1762 = mux(T_1758, UInt<1>("h00"), T_1761) T_830 <= T_1762 when T_1756 : T_1432 <= UInt<1>("h00") skip skip wire T_1767 : UInt<3>[1] T_1767[0] <= UInt<3>("h05") node T_1770 = eq(T_1767[0], io.out.grant.bits.g_type) node T_1772 = or(UInt<1>("h00"), T_1770) wire T_1774 : UInt<1>[1] T_1774[0] <= UInt<1>("h00") node T_1777 = eq(T_1774[0], io.out.grant.bits.g_type) node T_1779 = or(UInt<1>("h00"), T_1777) node T_1780 = mux(io.out.grant.bits.is_builtin_type, T_1772, T_1779) node T_1781 = and(UInt<1>("h01"), T_1780) reg T_1790 : UInt<64>[2], clk, UInt<1>("h00"), T_1790 reg T_1794 : UInt<4>, clk, UInt<1>("h00"), T_1794 reg T_1795 : UInt<1>, clk, UInt<1>("h00"), T_1795 reg T_1797 : UInt<2>, clk, reset, UInt<2>("h00") reg T_1799 : UInt<1>, clk, reset, UInt<1>("h00") reg T_1801 : UInt<1>, clk, reset, UInt<1>("h00") node T_1804 = cat(T_1790[1], T_1790[0]) wire T_1832 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_1832.data <= UInt<1>("h00") T_1832.g_type <= UInt<1>("h00") T_1832.is_builtin_type <= UInt<1>("h00") T_1832.manager_xact_id <= UInt<1>("h00") T_1832.client_xact_id <= UInt<1>("h00") T_1832.addr_beat <= UInt<1>("h00") T_1832.is_builtin_type <= UInt<1>("h01") T_1832.g_type <= UInt<3>("h05") T_1832.client_xact_id <= T_1794 T_1832.manager_xact_id <= T_1795 T_1832.addr_beat <= T_1797 T_1832.data <= T_1804 node T_1866 = eq(io.out.grant.bits.g_type, UInt<3>("h04")) node T_1868 = cat(T_1440.io.deq.data, UInt<6>("h00")) node T_1869 = and(io.out.grant.ready, io.out.grant.valid) node T_1870 = and(T_1869, T_1866) T_1440.io.deq.valid <= T_1870 T_1440.io.deq.tag <= io.out.grant.bits.client_xact_id node T_1874 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h01")) node T_1875 = dshl(io.out.grant.bits.data, T_1868) wire T_1903 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_1903.data <= UInt<1>("h00") T_1903.g_type <= UInt<1>("h00") T_1903.is_builtin_type <= UInt<1>("h00") T_1903.manager_xact_id <= UInt<1>("h00") T_1903.client_xact_id <= UInt<1>("h00") T_1903.addr_beat <= UInt<1>("h00") T_1903.is_builtin_type <= UInt<1>("h01") T_1903.g_type <= UInt<3>("h04") T_1903.client_xact_id <= io.out.grant.bits.client_xact_id T_1903.manager_xact_id <= io.out.grant.bits.manager_xact_id T_1903.addr_beat <= T_1874 T_1903.data <= T_1875 node T_1937 = eq(T_1781, UInt<1>("h00")) node T_1938 = and(io.out.grant.valid, T_1937) node T_1939 = or(T_1801, T_1938) io.in.grant.valid <= T_1939 node T_1941 = eq(T_1801, UInt<1>("h00")) node T_1942 = or(T_1781, io.in.grant.ready) node T_1943 = and(T_1941, T_1942) io.out.grant.ready <= T_1943 wire T_1944 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_1944 <- io.out.grant.bits wire T_1998 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_1998 <- T_1944 when T_1866 : T_1998 <- T_1903 skip wire T_2052 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} T_2052 <- T_1998 when T_1801 : T_2052 <- T_1832 skip io.in.grant.bits <- T_2052 node T_2079 = and(io.out.grant.valid, T_1781) node T_2081 = eq(T_1801, UInt<1>("h00")) node T_2082 = and(T_2079, T_2081) when T_2082 : T_1790[T_1799] <= io.out.grant.bits.data node T_2085 = eq(T_1799, UInt<1>("h01")) node T_2087 = and(UInt<1>("h00"), T_2085) node T_2090 = addw(T_1799, UInt<1>("h01")) node T_2091 = mux(T_2087, UInt<1>("h00"), T_2090) T_1799 <= T_2091 when T_2085 : T_1794 <= io.out.grant.bits.client_xact_id T_1795 <= io.out.grant.bits.manager_xact_id T_1801 <= UInt<1>("h01") skip skip node T_2093 = and(io.in.grant.ready, T_1801) when T_2093 : node T_2095 = eq(T_1797, UInt<2>("h03")) node T_2097 = and(UInt<1>("h00"), T_2095) node T_2100 = addw(T_1797, UInt<1>("h01")) node T_2101 = mux(T_2097, UInt<1>("h00"), T_2100) T_1797 <= T_2101 T_1801 <= UInt<1>("h00") skip module ReorderQueue_70 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, tag : UInt<5>}}, deq : {flip valid : UInt<1>, flip tag : UInt<5>, data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} io.deq.matches <= UInt<1>("h00") io.deq.data.subblock <= UInt<1>("h00") io.deq.data.byteOff <= UInt<1>("h00") io.deq.data.addr_beat <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") reg roq_data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk, UInt<1>("h00"), roq_data reg roq_tags : UInt<5>[9], clk, UInt<1>("h00"), roq_tags wire T_806 : UInt<1>[9] T_806[0] <= UInt<1>("h01") T_806[1] <= UInt<1>("h01") T_806[2] <= UInt<1>("h01") T_806[3] <= UInt<1>("h01") T_806[4] <= UInt<1>("h01") T_806[5] <= UInt<1>("h01") T_806[6] <= UInt<1>("h01") T_806[7] <= UInt<1>("h01") T_806[8] <= UInt<1>("h01") reg roq_free : UInt<1>[9], clk, reset, T_806 node T_839 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) node T_840 = mux(roq_free[6], UInt<3>("h06"), T_839) node T_841 = mux(roq_free[5], UInt<3>("h05"), T_840) node T_842 = mux(roq_free[4], UInt<3>("h04"), T_841) node T_843 = mux(roq_free[3], UInt<2>("h03"), T_842) node T_844 = mux(roq_free[2], UInt<2>("h02"), T_843) node T_845 = mux(roq_free[1], UInt<1>("h01"), T_844) node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_845) node T_847 = eq(roq_tags[0], io.deq.tag) node T_849 = eq(roq_free[0], UInt<1>("h00")) node T_850 = and(T_847, T_849) node T_851 = eq(roq_tags[1], io.deq.tag) node T_853 = eq(roq_free[1], UInt<1>("h00")) node T_854 = and(T_851, T_853) node T_855 = eq(roq_tags[2], io.deq.tag) node T_857 = eq(roq_free[2], UInt<1>("h00")) node T_858 = and(T_855, T_857) node T_859 = eq(roq_tags[3], io.deq.tag) node T_861 = eq(roq_free[3], UInt<1>("h00")) node T_862 = and(T_859, T_861) node T_863 = eq(roq_tags[4], io.deq.tag) node T_865 = eq(roq_free[4], UInt<1>("h00")) node T_866 = and(T_863, T_865) node T_867 = eq(roq_tags[5], io.deq.tag) node T_869 = eq(roq_free[5], UInt<1>("h00")) node T_870 = and(T_867, T_869) node T_871 = eq(roq_tags[6], io.deq.tag) node T_873 = eq(roq_free[6], UInt<1>("h00")) node T_874 = and(T_871, T_873) node T_875 = eq(roq_tags[7], io.deq.tag) node T_877 = eq(roq_free[7], UInt<1>("h00")) node T_878 = and(T_875, T_877) node T_879 = eq(roq_tags[8], io.deq.tag) node T_881 = eq(roq_free[8], UInt<1>("h00")) node T_882 = and(T_879, T_881) node T_892 = mux(T_878, UInt<3>("h07"), UInt<4>("h08")) node T_893 = mux(T_874, UInt<3>("h06"), T_892) node T_894 = mux(T_870, UInt<3>("h05"), T_893) node T_895 = mux(T_866, UInt<3>("h04"), T_894) node T_896 = mux(T_862, UInt<2>("h03"), T_895) node T_897 = mux(T_858, UInt<2>("h02"), T_896) node T_898 = mux(T_854, UInt<1>("h01"), T_897) node roq_deq_addr = mux(T_850, UInt<1>("h00"), T_898) node T_900 = or(roq_free[0], roq_free[1]) node T_901 = or(T_900, roq_free[2]) node T_902 = or(T_901, roq_free[3]) node T_903 = or(T_902, roq_free[4]) node T_904 = or(T_903, roq_free[5]) node T_905 = or(T_904, roq_free[6]) node T_906 = or(T_905, roq_free[7]) node T_907 = or(T_906, roq_free[8]) io.enq.ready <= T_907 io.deq.data <- roq_data[roq_deq_addr] node T_932 = or(T_850, T_854) node T_933 = or(T_932, T_858) node T_934 = or(T_933, T_862) node T_935 = or(T_934, T_866) node T_936 = or(T_935, T_870) node T_937 = or(T_936, T_874) node T_938 = or(T_937, T_878) node T_939 = or(T_938, T_882) io.deq.matches <= T_939 node T_940 = and(io.enq.valid, io.enq.ready) when T_940 : roq_data[roq_enq_addr] <- io.enq.bits.data roq_tags[roq_enq_addr] <= io.enq.bits.tag roq_free[roq_enq_addr] <= UInt<1>("h00") skip when io.deq.valid : roq_free[roq_deq_addr] <= UInt<1>("h01") skip module Arbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.client_id <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.g_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.manager_xact_id <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_658 : UInt<1> T_658 <= UInt<1>("h00") io.out.valid <= io.in[T_658].valid io.out.bits <- io.in[T_658].bits io.chosen <= T_658 io.in[T_658].ready <= UInt<1>("h00") node T_840 = or(UInt<1>("h00"), io.in[0].valid) node T_842 = eq(T_840, UInt<1>("h00")) node T_844 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_845 = mux(UInt<1>("h00"), T_844, UInt<1>("h01")) node T_846 = and(T_845, io.out.ready) io.in[0].ready <= T_846 node T_848 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_849 = mux(UInt<1>("h00"), T_848, T_842) node T_850 = and(T_849, io.out.ready) io.in[1].ready <= T_850 node T_853 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_854 = mux(UInt<1>("h00"), UInt<1>("h01"), T_853) T_658 <= T_854 module NastiIOTileLinkIOConverter : input clk : Clock input reset : UInt<1> output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} io.nasti.r.ready <= UInt<1>("h00") io.nasti.ar.bits.user <= UInt<1>("h00") io.nasti.ar.bits.id <= UInt<1>("h00") io.nasti.ar.bits.region <= UInt<1>("h00") io.nasti.ar.bits.qos <= UInt<1>("h00") io.nasti.ar.bits.prot <= UInt<1>("h00") io.nasti.ar.bits.cache <= UInt<1>("h00") io.nasti.ar.bits.lock <= UInt<1>("h00") io.nasti.ar.bits.burst <= UInt<1>("h00") io.nasti.ar.bits.size <= UInt<1>("h00") io.nasti.ar.bits.len <= UInt<1>("h00") io.nasti.ar.bits.addr <= UInt<1>("h00") io.nasti.ar.valid <= UInt<1>("h00") io.nasti.b.ready <= UInt<1>("h00") io.nasti.w.bits.user <= UInt<1>("h00") io.nasti.w.bits.strb <= UInt<1>("h00") io.nasti.w.bits.last <= UInt<1>("h00") io.nasti.w.bits.data <= UInt<1>("h00") io.nasti.w.valid <= UInt<1>("h00") io.nasti.aw.bits.user <= UInt<1>("h00") io.nasti.aw.bits.id <= UInt<1>("h00") io.nasti.aw.bits.region <= UInt<1>("h00") io.nasti.aw.bits.qos <= UInt<1>("h00") io.nasti.aw.bits.prot <= UInt<1>("h00") io.nasti.aw.bits.cache <= UInt<1>("h00") io.nasti.aw.bits.lock <= UInt<1>("h00") io.nasti.aw.bits.burst <= UInt<1>("h00") io.nasti.aw.bits.size <= UInt<1>("h00") io.nasti.aw.bits.len <= UInt<1>("h00") io.nasti.aw.bits.addr <= UInt<1>("h00") io.nasti.aw.valid <= UInt<1>("h00") io.tl.grant.bits.data <= UInt<1>("h00") io.tl.grant.bits.g_type <= UInt<1>("h00") io.tl.grant.bits.is_builtin_type <= UInt<1>("h00") io.tl.grant.bits.manager_xact_id <= UInt<1>("h00") io.tl.grant.bits.client_xact_id <= UInt<1>("h00") io.tl.grant.bits.addr_beat <= UInt<1>("h00") io.tl.grant.valid <= UInt<1>("h00") io.tl.acquire.ready <= UInt<1>("h00") wire T_685 : UInt<3>[3] T_685[0] <= UInt<3>("h02") T_685[1] <= UInt<3>("h03") T_685[2] <= UInt<3>("h04") node T_690 = eq(T_685[0], io.tl.acquire.bits.a_type) node T_691 = eq(T_685[1], io.tl.acquire.bits.a_type) node T_692 = eq(T_685[2], io.tl.acquire.bits.a_type) node T_694 = or(UInt<1>("h00"), T_690) node T_695 = or(T_694, T_691) node T_696 = or(T_695, T_692) node has_data = and(io.tl.acquire.bits.is_builtin_type, T_696) wire T_702 : UInt<3>[3] T_702[0] <= UInt<3>("h02") T_702[1] <= UInt<3>("h00") T_702[2] <= UInt<3>("h04") node T_707 = eq(T_702[0], io.tl.acquire.bits.a_type) node T_708 = eq(T_702[1], io.tl.acquire.bits.a_type) node T_709 = eq(T_702[2], io.tl.acquire.bits.a_type) node T_711 = or(UInt<1>("h00"), T_707) node T_712 = or(T_711, T_708) node T_713 = or(T_712, T_709) node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_713) node T_716 = and(UInt<1>("h01"), io.tl.acquire.bits.is_builtin_type) wire T_719 : UInt<3>[1] T_719[0] <= UInt<3>("h03") node T_722 = eq(T_719[0], io.tl.acquire.bits.a_type) node T_724 = or(UInt<1>("h00"), T_722) node is_multibeat = and(T_716, T_724) node T_726 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_727 = and(T_726, is_multibeat) reg tl_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") when T_727 : node T_731 = eq(tl_cnt_out, UInt<3>("h07")) node T_733 = and(UInt<1>("h00"), T_731) node T_736 = addw(tl_cnt_out, UInt<1>("h01")) node T_737 = mux(T_733, UInt<1>("h00"), T_736) tl_cnt_out <= T_737 skip node tl_wrap_out = and(T_727, T_731) node T_740 = eq(has_data, UInt<1>("h00")) node get_valid = and(io.tl.acquire.valid, T_740) node put_valid = and(io.tl.acquire.valid, has_data) inst roq of ReorderQueue_70 roq.io.deq.tag <= UInt<1>("h00") roq.io.deq.valid <= UInt<1>("h00") roq.io.enq.bits.tag <= UInt<1>("h00") roq.io.enq.bits.data.subblock <= UInt<1>("h00") roq.io.enq.bits.data.byteOff <= UInt<1>("h00") roq.io.enq.bits.data.addr_beat <= UInt<1>("h00") roq.io.enq.valid <= UInt<1>("h00") roq.clk <= clk roq.reset <= reset reg w_inflight : UInt<1>, clk, reset, UInt<1>("h00") node aw_ready = or(w_inflight, io.nasti.aw.ready) node T_778 = and(io.nasti.r.ready, io.nasti.r.valid) node T_780 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) node T_781 = and(T_778, T_780) reg nasti_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") when T_781 : node T_785 = eq(nasti_cnt_out, UInt<3>("h07")) node T_787 = and(UInt<1>("h00"), T_785) node T_790 = addw(nasti_cnt_out, UInt<1>("h01")) node T_791 = mux(T_787, UInt<1>("h00"), T_790) nasti_cnt_out <= T_791 skip node nasti_wrap_out = and(T_781, T_785) node T_793 = and(get_valid, io.nasti.ar.ready) roq.io.enq.valid <= T_793 roq.io.enq.bits.tag <= io.nasti.ar.bits.id roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat node T_794 = bits(io.tl.acquire.bits.union, 11, 9) roq.io.enq.bits.data.byteOff <= T_794 roq.io.enq.bits.data.subblock <= is_subblock node T_795 = and(io.nasti.r.ready, io.nasti.r.valid) node T_796 = or(nasti_wrap_out, roq.io.deq.data.subblock) node T_797 = and(T_795, T_796) roq.io.deq.valid <= T_797 roq.io.deq.tag <= io.nasti.r.bits.id node T_798 = and(get_valid, roq.io.enq.ready) io.nasti.ar.valid <= T_798 node T_799 = bits(io.tl.acquire.bits.union, 11, 9) node T_800 = cat(io.tl.acquire.bits.addr_beat, T_799) node T_801 = cat(io.tl.acquire.bits.addr_block, T_800) node T_802 = bits(io.tl.acquire.bits.union, 8, 6) node T_811 = eq(UInt<3>("h07"), T_802) node T_812 = mux(T_811, UInt<2>("h03"), UInt<3>("h07")) node T_813 = eq(UInt<3>("h03"), T_802) node T_814 = mux(T_813, UInt<2>("h03"), T_812) node T_815 = eq(UInt<3>("h02"), T_802) node T_816 = mux(T_815, UInt<2>("h02"), T_814) node T_817 = eq(UInt<3>("h05"), T_802) node T_818 = mux(T_817, UInt<1>("h01"), T_816) node T_819 = eq(UInt<3>("h01"), T_802) node T_820 = mux(T_819, UInt<1>("h01"), T_818) node T_821 = eq(UInt<3>("h04"), T_802) node T_822 = mux(T_821, UInt<1>("h00"), T_820) node T_823 = eq(UInt<3>("h00"), T_802) node T_824 = mux(T_823, UInt<1>("h00"), T_822) node T_826 = mux(is_subblock, T_824, UInt<2>("h03")) node T_829 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07")) wire T_842 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} T_842.user <= UInt<1>("h00") T_842.id <= UInt<1>("h00") T_842.region <= UInt<1>("h00") T_842.qos <= UInt<1>("h00") T_842.prot <= UInt<1>("h00") T_842.cache <= UInt<1>("h00") T_842.lock <= UInt<1>("h00") T_842.burst <= UInt<1>("h00") T_842.size <= UInt<1>("h00") T_842.len <= UInt<1>("h00") T_842.addr <= UInt<1>("h00") T_842.id <= io.tl.acquire.bits.client_xact_id T_842.addr <= T_801 T_842.len <= T_829 T_842.size <= T_826 T_842.burst <= UInt<2>("h01") T_842.lock <= UInt<1>("h00") T_842.cache <= UInt<1>("h00") T_842.prot <= UInt<1>("h00") T_842.qos <= UInt<1>("h00") T_842.region <= UInt<1>("h00") T_842.user <= UInt<1>("h00") io.nasti.ar.bits <- T_842 node T_872 = eq(w_inflight, UInt<1>("h00")) node T_873 = and(put_valid, io.nasti.w.ready) node T_874 = and(T_873, T_872) io.nasti.aw.valid <= T_874 node T_875 = bits(io.tl.acquire.bits.union, 11, 9) node T_876 = cat(io.tl.acquire.bits.addr_beat, T_875) node T_877 = cat(io.tl.acquire.bits.addr_block, T_876) node T_881 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00")) wire T_894 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} T_894.user <= UInt<1>("h00") T_894.id <= UInt<1>("h00") T_894.region <= UInt<1>("h00") T_894.qos <= UInt<1>("h00") T_894.prot <= UInt<1>("h00") T_894.cache <= UInt<1>("h00") T_894.lock <= UInt<1>("h00") T_894.burst <= UInt<1>("h00") T_894.size <= UInt<1>("h00") T_894.len <= UInt<1>("h00") T_894.addr <= UInt<1>("h00") T_894.id <= io.tl.acquire.bits.client_xact_id T_894.addr <= T_877 T_894.len <= T_881 T_894.size <= UInt<2>("h03") T_894.burst <= UInt<2>("h01") T_894.lock <= UInt<1>("h00") T_894.cache <= UInt<4>("h00") T_894.prot <= UInt<3>("h00") T_894.qos <= UInt<4>("h00") T_894.region <= UInt<4>("h00") T_894.user <= UInt<1>("h00") io.nasti.aw.bits <- T_894 node T_923 = and(put_valid, aw_ready) io.nasti.w.valid <= T_923 node T_926 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) node T_927 = and(io.tl.acquire.bits.is_builtin_type, T_926) wire T_930 : UInt<1>[1] T_930[0] <= UInt<1>("h01") node T_934 = subw(UInt<8>("h00"), T_930[0]) wire T_936 : UInt<8>[1] T_936[0] <= T_934 node T_940 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) node T_941 = and(io.tl.acquire.bits.is_builtin_type, T_940) node T_943 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) node T_944 = and(io.tl.acquire.bits.is_builtin_type, T_943) node T_945 = or(T_941, T_944) node T_946 = bits(io.tl.acquire.bits.union, 8, 1) node T_948 = mux(T_945, T_946, UInt<8>("h00")) node T_949 = mux(T_927, T_936[0], T_948) node T_950 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_951 = and(T_950, is_subblock) node T_952 = or(tl_wrap_out, T_951) wire T_958 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} T_958.user <= UInt<1>("h00") T_958.strb <= UInt<1>("h00") T_958.last <= UInt<1>("h00") T_958.data <= UInt<1>("h00") node T_968 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_969 = cat(T_968, T_968) node T_970 = cat(T_969, T_969) T_958.strb <= T_970 T_958.data <= io.tl.acquire.bits.data T_958.last <= T_952 T_958.user <= UInt<1>("h00") T_958.strb <= T_949 io.nasti.w.bits <- T_958 node T_972 = and(aw_ready, io.nasti.w.ready) node T_973 = and(roq.io.enq.ready, io.nasti.ar.ready) node T_974 = mux(has_data, T_972, T_973) io.tl.acquire.ready <= T_974 node T_976 = eq(w_inflight, UInt<1>("h00")) node T_977 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_978 = and(T_976, T_977) node T_979 = and(T_978, is_multibeat) when T_979 : w_inflight <= UInt<1>("h01") skip when w_inflight : when tl_wrap_out : w_inflight <= UInt<1>("h00") skip skip node T_982 = and(io.tl.grant.ready, io.tl.grant.valid) wire T_986 : UInt<3>[1] T_986[0] <= UInt<3>("h05") node T_989 = eq(T_986[0], io.tl.grant.bits.g_type) node T_991 = or(UInt<1>("h00"), T_989) wire T_993 : UInt<1>[1] T_993[0] <= UInt<1>("h00") node T_996 = eq(T_993[0], io.tl.grant.bits.g_type) node T_998 = or(UInt<1>("h00"), T_996) node T_999 = mux(io.tl.grant.bits.is_builtin_type, T_991, T_998) node T_1000 = and(UInt<1>("h01"), T_999) node T_1001 = and(T_982, T_1000) reg tl_cnt_in : UInt<3>, clk, reset, UInt<3>("h00") when T_1001 : node T_1005 = eq(tl_cnt_in, UInt<3>("h07")) node T_1007 = and(UInt<1>("h00"), T_1005) node T_1010 = addw(tl_cnt_in, UInt<1>("h01")) node T_1011 = mux(T_1007, UInt<1>("h00"), T_1010) tl_cnt_in <= T_1011 skip node tl_wrap_in = and(T_1001, T_1005) inst gnt_arb of Arbiter gnt_arb.io.out.ready <= UInt<1>("h00") gnt_arb.io.in[0].bits.client_id <= UInt<1>("h00") gnt_arb.io.in[0].bits.data <= UInt<1>("h00") gnt_arb.io.in[0].bits.g_type <= UInt<1>("h00") gnt_arb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") gnt_arb.io.in[0].bits.manager_xact_id <= UInt<1>("h00") gnt_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") gnt_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") gnt_arb.io.in[0].valid <= UInt<1>("h00") gnt_arb.io.in[1].bits.client_id <= UInt<1>("h00") gnt_arb.io.in[1].bits.data <= UInt<1>("h00") gnt_arb.io.in[1].bits.g_type <= UInt<1>("h00") gnt_arb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") gnt_arb.io.in[1].bits.manager_xact_id <= UInt<1>("h00") gnt_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") gnt_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") gnt_arb.io.in[1].valid <= UInt<1>("h00") gnt_arb.clk <= clk gnt_arb.reset <= reset io.tl.grant <- gnt_arb.io.out node T_1060 = cat(roq.io.deq.data.byteOff, UInt<3>("h00")) node T_1061 = dshl(io.nasti.r.bits.data, T_1060) node r_aligned_data = mux(roq.io.deq.data.subblock, T_1061, io.nasti.r.bits.data) gnt_arb.io.in[0].valid <= io.nasti.r.valid io.nasti.r.ready <= gnt_arb.io.in[0].ready node T_1066 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) node T_1068 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) wire T_1096 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} T_1096.data <= UInt<1>("h00") T_1096.g_type <= UInt<1>("h00") T_1096.is_builtin_type <= UInt<1>("h00") T_1096.manager_xact_id <= UInt<1>("h00") T_1096.client_xact_id <= UInt<1>("h00") T_1096.addr_beat <= UInt<1>("h00") T_1096.is_builtin_type <= UInt<1>("h01") T_1096.g_type <= T_1066 T_1096.client_xact_id <= io.nasti.r.bits.id T_1096.manager_xact_id <= UInt<1>("h00") T_1096.addr_beat <= T_1068 T_1096.data <= r_aligned_data gnt_arb.io.in[0].bits <- T_1096 gnt_arb.io.in[1].valid <= io.nasti.b.valid io.nasti.b.ready <= gnt_arb.io.in[1].ready wire T_1161 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} T_1161.data <= UInt<1>("h00") T_1161.g_type <= UInt<1>("h00") T_1161.is_builtin_type <= UInt<1>("h00") T_1161.manager_xact_id <= UInt<1>("h00") T_1161.client_xact_id <= UInt<1>("h00") T_1161.addr_beat <= UInt<1>("h00") T_1161.is_builtin_type <= UInt<1>("h01") T_1161.g_type <= UInt<3>("h03") T_1161.client_xact_id <= io.nasti.b.bits.id T_1161.manager_xact_id <= UInt<1>("h00") T_1161.addr_beat <= UInt<1>("h00") T_1161.data <= UInt<1>("h00") gnt_arb.io.in[1].bits <- T_1161 node T_1195 = eq(io.nasti.r.valid, UInt<1>("h00")) node T_1197 = eq(io.nasti.r.bits.resp, UInt<1>("h00")) node T_1198 = or(T_1195, T_1197) node T_1200 = eq(reset, UInt<1>("h00")) when T_1200 : node T_1202 = eq(T_1198, UInt<1>("h00")) when T_1202 : node T_1204 = eq(reset, UInt<1>("h00")) when T_1204 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI read error") skip stop(clk, UInt<1>(1), 1) skip skip node T_1206 = eq(io.nasti.b.valid, UInt<1>("h00")) node T_1208 = eq(io.nasti.b.bits.resp, UInt<1>("h00")) node T_1209 = or(T_1206, T_1208) node T_1211 = eq(reset, UInt<1>("h00")) when T_1211 : node T_1213 = eq(T_1209, UInt<1>("h00")) when T_1213 : node T_1215 = eq(reset, UInt<1>("h00")) when T_1215 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI write error") skip stop(clk, UInt<1>(1), 1) skip skip module ClientTileLinkIOWrapper_71 : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} io.out.release.bits.data <= UInt<1>("h00") io.out.release.bits.r_type <= UInt<1>("h00") io.out.release.bits.voluntary <= UInt<1>("h00") io.out.release.bits.client_xact_id <= UInt<1>("h00") io.out.release.bits.addr_block <= UInt<1>("h00") io.out.release.bits.addr_beat <= UInt<1>("h00") io.out.release.valid <= UInt<1>("h00") io.out.probe.ready <= UInt<1>("h00") io.out.grant.ready <= UInt<1>("h00") io.out.acquire.bits.data <= UInt<1>("h00") io.out.acquire.bits.union <= UInt<1>("h00") io.out.acquire.bits.a_type <= UInt<1>("h00") io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") io.out.acquire.bits.addr_beat <= UInt<1>("h00") io.out.acquire.bits.client_xact_id <= UInt<1>("h00") io.out.acquire.bits.addr_block <= UInt<1>("h00") io.out.acquire.valid <= UInt<1>("h00") io.in.grant.bits.data <= UInt<1>("h00") io.in.grant.bits.g_type <= UInt<1>("h00") io.in.grant.bits.is_builtin_type <= UInt<1>("h00") io.in.grant.bits.manager_xact_id <= UInt<1>("h00") io.in.grant.bits.client_xact_id <= UInt<1>("h00") io.in.grant.bits.addr_beat <= UInt<1>("h00") io.in.grant.valid <= UInt<1>("h00") io.in.acquire.ready <= UInt<1>("h00") io.out.acquire <- io.in.acquire io.in.grant <- io.out.grant io.out.probe.ready <= UInt<1>("h01") io.out.release.valid <= UInt<1>("h00") module ClientTileLinkEnqueuer : input clk : Clock input reset : UInt<1> output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} io.outer.release.bits.data <= UInt<1>("h00") io.outer.release.bits.r_type <= UInt<1>("h00") io.outer.release.bits.voluntary <= UInt<1>("h00") io.outer.release.bits.client_xact_id <= UInt<1>("h00") io.outer.release.bits.addr_block <= UInt<1>("h00") io.outer.release.bits.addr_beat <= UInt<1>("h00") io.outer.release.valid <= UInt<1>("h00") io.outer.probe.ready <= UInt<1>("h00") io.outer.grant.ready <= UInt<1>("h00") io.outer.acquire.bits.data <= UInt<1>("h00") io.outer.acquire.bits.union <= UInt<1>("h00") io.outer.acquire.bits.a_type <= UInt<1>("h00") io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") io.outer.acquire.bits.addr_beat <= UInt<1>("h00") io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") io.outer.acquire.bits.addr_block <= UInt<1>("h00") io.outer.acquire.valid <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.probe.bits.p_type <= UInt<1>("h00") io.inner.probe.bits.addr_block <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") io.inner.grant.bits.data <= UInt<1>("h00") io.inner.grant.bits.g_type <= UInt<1>("h00") io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") io.inner.grant.bits.client_xact_id <= UInt<1>("h00") io.inner.grant.bits.addr_beat <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.acquire.ready <= UInt<1>("h00") io.outer.acquire <- io.inner.acquire io.inner.probe <- io.outer.probe io.outer.release <- io.inner.release io.inner.grant <- io.outer.grant module Queue_74 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, count : UInt<4>} io.count <= UInt<1>("h00") io.deq.bits.user <= UInt<1>("h00") io.deq.bits.strb <= UInt<1>("h00") io.deq.bits.last <= UInt<1>("h00") io.deq.bits.data <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}[8] reg T_62 : UInt<3>, clk, reset, UInt<3>("h00") reg T_64 : UInt<3>, clk, reset, UInt<3>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_62, T_64) node T_69 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_69) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_75 = and(io.enq.ready, io.enq.valid) node T_77 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_75, T_77) node T_79 = and(io.deq.ready, io.deq.valid) node T_81 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_79, T_81) when do_enq : infer mport T_83 = ram[T_62], clk T_83 <- io.enq.bits node T_89 = eq(T_62, UInt<3>("h07")) node T_91 = and(UInt<1>("h00"), T_89) node T_94 = addw(T_62, UInt<1>("h01")) node T_95 = mux(T_91, UInt<1>("h00"), T_94) T_62 <= T_95 skip when do_deq : node T_97 = eq(T_64, UInt<3>("h07")) node T_99 = and(UInt<1>("h00"), T_97) node T_102 = addw(T_64, UInt<1>("h01")) node T_103 = mux(T_99, UInt<1>("h00"), T_102) T_64 <= T_103 skip node T_104 = neq(do_enq, do_deq) when T_104 : maybe_full <= do_enq skip node T_106 = eq(empty, UInt<1>("h00")) node T_108 = and(UInt<1>("h00"), io.enq.valid) node T_109 = or(T_106, T_108) io.deq.valid <= T_109 node T_111 = eq(full, UInt<1>("h00")) node T_113 = and(UInt<1>("h00"), io.deq.ready) node T_114 = or(T_111, T_113) io.enq.ready <= T_114 infer mport T_115 = ram[T_64], clk wire T_125 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} T_125 <- T_115 when maybe_flow : T_125 <- io.enq.bits skip io.deq.bits <- T_125 node ptr_diff = subw(T_62, T_64) node T_131 = and(maybe_full, ptr_match) node T_132 = cat(T_131, ptr_diff) io.count <= T_132 module Queue_75 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<4>} io.count <= UInt<1>("h00") io.deq.bits.user <= UInt<1>("h00") io.deq.bits.id <= UInt<1>("h00") io.deq.bits.last <= UInt<1>("h00") io.deq.bits.data <= UInt<1>("h00") io.deq.bits.resp <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}[8] reg T_71 : UInt<3>, clk, reset, UInt<3>("h00") reg T_73 : UInt<3>, clk, reset, UInt<3>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_71, T_73) node T_78 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_78) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_84 = and(io.enq.ready, io.enq.valid) node T_86 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_84, T_86) node T_88 = and(io.deq.ready, io.deq.valid) node T_90 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_88, T_90) when do_enq : infer mport T_92 = ram[T_71], clk T_92 <- io.enq.bits node T_99 = eq(T_71, UInt<3>("h07")) node T_101 = and(UInt<1>("h00"), T_99) node T_104 = addw(T_71, UInt<1>("h01")) node T_105 = mux(T_101, UInt<1>("h00"), T_104) T_71 <= T_105 skip when do_deq : node T_107 = eq(T_73, UInt<3>("h07")) node T_109 = and(UInt<1>("h00"), T_107) node T_112 = addw(T_73, UInt<1>("h01")) node T_113 = mux(T_109, UInt<1>("h00"), T_112) T_73 <= T_113 skip node T_114 = neq(do_enq, do_deq) when T_114 : maybe_full <= do_enq skip node T_116 = eq(empty, UInt<1>("h00")) node T_118 = and(UInt<1>("h00"), io.enq.valid) node T_119 = or(T_116, T_118) io.deq.valid <= T_119 node T_121 = eq(full, UInt<1>("h00")) node T_123 = and(UInt<1>("h00"), io.deq.ready) node T_124 = or(T_121, T_123) io.enq.ready <= T_124 infer mport T_125 = ram[T_73], clk wire T_137 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} T_137 <- T_125 when maybe_flow : T_137 <- io.enq.bits skip io.deq.bits <- T_137 node ptr_diff = subw(T_71, T_73) node T_144 = and(maybe_full, ptr_match) node T_145 = cat(T_144, ptr_diff) io.count <= T_145 module Queue_76 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.user <= UInt<1>("h00") io.deq.bits.id <= UInt<1>("h00") io.deq.bits.resp <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}[2] reg T_53 : UInt<1>, clk, reset, UInt<1>("h00") reg T_55 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_66 = and(io.enq.ready, io.enq.valid) node T_68 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_66, T_68) node T_70 = and(io.deq.ready, io.deq.valid) node T_72 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_70, T_72) when do_enq : infer mport T_74 = ram[T_53], clk T_74 <- io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) node T_84 = addw(T_53, UInt<1>("h01")) node T_85 = mux(T_81, UInt<1>("h00"), T_84) T_53 <= T_85 skip when do_deq : node T_87 = eq(T_55, UInt<1>("h01")) node T_89 = and(UInt<1>("h00"), T_87) node T_92 = addw(T_55, UInt<1>("h01")) node T_93 = mux(T_89, UInt<1>("h00"), T_92) T_55 <= T_93 skip node T_94 = neq(do_enq, do_deq) when T_94 : maybe_full <= do_enq skip node T_96 = eq(empty, UInt<1>("h00")) node T_98 = and(UInt<1>("h00"), io.enq.valid) node T_99 = or(T_96, T_98) io.deq.valid <= T_99 node T_101 = eq(full, UInt<1>("h00")) node T_103 = and(UInt<1>("h00"), io.deq.ready) node T_104 = or(T_101, T_103) io.enq.ready <= T_104 infer mport T_105 = ram[T_55], clk wire T_113 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} T_113 <- T_105 when maybe_flow : T_113 <- io.enq.bits skip io.deq.bits <- T_113 node ptr_diff = subw(T_53, T_55) node T_118 = and(maybe_full, ptr_match) node T_119 = cat(T_118, ptr_diff) io.count <= T_119 module RTC : input clk : Clock input reset : UInt<1> output io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.r.ready <= UInt<1>("h00") io.ar.bits.user <= UInt<1>("h00") io.ar.bits.id <= UInt<1>("h00") io.ar.bits.region <= UInt<1>("h00") io.ar.bits.qos <= UInt<1>("h00") io.ar.bits.prot <= UInt<1>("h00") io.ar.bits.cache <= UInt<1>("h00") io.ar.bits.lock <= UInt<1>("h00") io.ar.bits.burst <= UInt<1>("h00") io.ar.bits.size <= UInt<1>("h00") io.ar.bits.len <= UInt<1>("h00") io.ar.bits.addr <= UInt<1>("h00") io.ar.valid <= UInt<1>("h00") io.b.ready <= UInt<1>("h00") io.w.bits.user <= UInt<1>("h00") io.w.bits.strb <= UInt<1>("h00") io.w.bits.last <= UInt<1>("h00") io.w.bits.data <= UInt<1>("h00") io.w.valid <= UInt<1>("h00") io.aw.bits.user <= UInt<1>("h00") io.aw.bits.id <= UInt<1>("h00") io.aw.bits.region <= UInt<1>("h00") io.aw.bits.qos <= UInt<1>("h00") io.aw.bits.prot <= UInt<1>("h00") io.aw.bits.cache <= UInt<1>("h00") io.aw.bits.lock <= UInt<1>("h00") io.aw.bits.burst <= UInt<1>("h00") io.aw.bits.size <= UInt<1>("h00") io.aw.bits.len <= UInt<1>("h00") io.aw.bits.addr <= UInt<1>("h00") io.aw.valid <= UInt<1>("h00") wire addrTable : UInt<31>[1] addrTable[0] <= UInt<31>("h04000b808") reg rtc : UInt<64>, clk, reset, UInt<64>("h00") reg T_217 : UInt<7>, clk, reset, UInt<7>("h00") node rtc_tick = eq(T_217, UInt<7>("h063")) node T_221 = and(UInt<1>("h01"), rtc_tick) node T_224 = addw(T_217, UInt<1>("h01")) node T_225 = mux(T_221, UInt<1>("h00"), T_224) T_217 <= T_225 reg sending_addr : UInt<1>, clk, reset, UInt<1>("h00") reg sending_data : UInt<1>, clk, reset, UInt<1>("h00") wire T_232 : UInt<1>[1] T_232[0] <= UInt<1>("h01") reg send_acked : UInt<1>[1], clk, reset, T_232 wire coreId : UInt<1> coreId <= UInt<1>("h00") when rtc_tick : node T_244 = addw(rtc, UInt<1>("h01")) rtc <= T_244 wire T_247 : UInt<1>[1] T_247[0] <= UInt<1>("h00") send_acked <= T_247 sending_addr <= UInt<1>("h01") sending_data <= UInt<1>("h01") skip node T_252 = and(io.aw.ready, io.aw.valid) when T_252 : sending_addr <= UInt<1>("h00") skip node T_254 = and(io.w.ready, io.w.valid) when T_254 : sending_addr <= UInt<1>("h00") skip coreId <= UInt<1>("h00") node T_257 = and(io.b.ready, io.b.valid) when T_257 : send_acked[io.b.bits.id] <= UInt<1>("h01") skip io.aw.valid <= sending_addr wire T_275 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} T_275.user <= UInt<1>("h00") T_275.id <= UInt<1>("h00") T_275.region <= UInt<1>("h00") T_275.qos <= UInt<1>("h00") T_275.prot <= UInt<1>("h00") T_275.cache <= UInt<1>("h00") T_275.lock <= UInt<1>("h00") T_275.burst <= UInt<1>("h00") T_275.size <= UInt<1>("h00") T_275.len <= UInt<1>("h00") T_275.addr <= UInt<1>("h00") T_275.id <= coreId T_275.addr <= addrTable[coreId] T_275.len <= UInt<1>("h00") T_275.size <= UInt<2>("h03") T_275.burst <= UInt<2>("h01") T_275.lock <= UInt<1>("h00") T_275.cache <= UInt<4>("h00") T_275.prot <= UInt<3>("h00") T_275.qos <= UInt<4>("h00") T_275.region <= UInt<4>("h00") T_275.user <= UInt<1>("h00") io.aw.bits <- T_275 io.w.valid <= sending_data wire T_310 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} T_310.user <= UInt<1>("h00") T_310.strb <= UInt<1>("h00") T_310.last <= UInt<1>("h00") T_310.data <= UInt<1>("h00") node T_320 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_321 = cat(T_320, T_320) node T_322 = cat(T_321, T_321) T_310.strb <= T_322 T_310.data <= rtc T_310.last <= UInt<1>("h01") T_310.user <= UInt<1>("h00") io.w.bits <- T_310 io.b.ready <= UInt<1>("h01") io.ar.valid <= UInt<1>("h00") io.r.ready <= UInt<1>("h00") node T_328 = eq(rtc_tick, UInt<1>("h00")) node T_329 = or(T_328, send_acked[0]) node T_331 = eq(reset, UInt<1>("h00")) when T_331 : node T_333 = eq(T_329, UInt<1>("h00")) when T_333 : node T_335 = eq(reset, UInt<1>("h00")) when T_335 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick") skip stop(clk, UInt<1>(1), 1) skip skip module SmiIONastiReadIOConverter : input clk : Clock input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.r.bits.user <= UInt<1>("h00") io.r.bits.id <= UInt<1>("h00") io.r.bits.last <= UInt<1>("h00") io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<1>("h00") io.r.valid <= UInt<1>("h00") io.ar.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg nWords : UInt<1>, clk, UInt<1>("h00"), nWords reg nBeats : UInt<8>, clk, UInt<1>("h00"), nBeats reg addr : UInt<12>, clk, UInt<1>("h00"), addr reg id : UInt<5>, clk, UInt<1>("h00"), id reg byteOff : UInt<3>, clk, UInt<1>("h00"), byteOff reg sendInd : UInt<1>, clk, reset, UInt<1>("h00") reg recvInd : UInt<1>, clk, reset, UInt<1>("h00") reg sendDone : UInt<1>, clk, reset, UInt<1>("h00") wire T_141 : UInt<64>[1] T_141[0] <= UInt<64>("h00") reg buffer : UInt<64>[1], clk, reset, T_141 node T_149 = eq(state, UInt<1>("h00")) io.ar.ready <= T_149 node T_150 = eq(state, UInt<1>("h01")) node T_152 = eq(sendDone, UInt<1>("h00")) node T_153 = and(T_150, T_152) io.smi.req.valid <= T_153 io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.bits.addr <= addr node T_155 = eq(state, UInt<1>("h01")) io.smi.resp.ready <= T_155 node T_156 = eq(state, UInt<2>("h02")) io.r.valid <= T_156 node T_158 = eq(nBeats, UInt<1>("h00")) wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} T_166.user <= UInt<1>("h00") T_166.id <= UInt<1>("h00") T_166.last <= UInt<1>("h00") T_166.data <= UInt<1>("h00") T_166.resp <= UInt<1>("h00") T_166.id <= id T_166.data <= buffer[0] T_166.last <= T_158 T_166.resp <= UInt<1>("h00") T_166.user <= UInt<1>("h00") io.r.bits <- T_166 node T_178 = and(io.ar.ready, io.ar.valid) when T_178 : node T_180 = lt(io.ar.bits.size, UInt<2>("h03")) when T_180 : nWords <= UInt<1>("h00") node T_182 = bits(io.ar.bits.addr, 2, 0) byteOff <= T_182 skip node T_184 = eq(T_180, UInt<1>("h00")) when T_184 : node T_187 = subw(io.ar.bits.size, UInt<2>("h03")) node T_188 = dshl(UInt<1>("h01"), T_187) node T_190 = subw(T_188, UInt<1>("h01")) nWords <= T_190 byteOff <= UInt<1>("h00") skip nBeats <= io.ar.bits.len node T_192 = bits(io.ar.bits.addr, 14, 3) addr <= T_192 id <= io.ar.bits.id state <= UInt<1>("h01") skip node T_193 = and(io.smi.req.ready, io.smi.req.valid) when T_193 : node T_195 = addw(addr, UInt<1>("h01")) addr <= T_195 node T_197 = addw(sendInd, UInt<1>("h01")) sendInd <= T_197 node T_198 = eq(sendInd, nWords) sendDone <= T_198 skip node T_199 = and(io.smi.resp.ready, io.smi.resp.valid) when T_199 : node T_201 = addw(recvInd, UInt<1>("h01")) recvInd <= T_201 node T_204 = cat(byteOff, UInt<3>("h00")) node T_205 = dshr(io.smi.resp.bits, T_204) buffer[recvInd] <= T_205 node T_206 = eq(recvInd, nWords) when T_206 : state <= UInt<2>("h02") skip skip node T_207 = and(io.r.ready, io.r.valid) when T_207 : recvInd <= UInt<1>("h00") sendInd <= UInt<1>("h00") sendDone <= UInt<1>("h00") buffer[0] <= UInt<1>("h00") node T_213 = subw(nBeats, UInt<1>("h01")) nBeats <= T_213 node T_214 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) state <= T_214 skip module SmiIONastiWriteIOConverter : input clk : Clock input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.b.bits.user <= UInt<1>("h00") io.b.bits.id <= UInt<1>("h00") io.b.bits.resp <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.aw.ready <= UInt<1>("h00") node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) node T_149 = eq(reset, UInt<1>("h00")) when T_149 : node T_151 = eq(T_147, UInt<1>("h00")) when T_151 : node T_153 = eq(reset, UInt<1>("h00")) when T_153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") skip stop(clk, UInt<1>(1), 1) skip skip reg id : UInt<5>, clk, UInt<1>("h00"), id reg addr : UInt<12>, clk, UInt<1>("h00"), addr reg size : UInt<3>, clk, UInt<1>("h00"), size reg strb : UInt<1>, clk, UInt<1>("h00"), strb reg data : UInt<64>, clk, UInt<1>("h00"), data reg last : UInt<1>, clk, UInt<1>("h00"), last reg state : UInt, clk, reset, UInt<1>("h00") node T_173 = eq(state, UInt<1>("h00")) io.aw.ready <= T_173 node T_174 = eq(state, UInt<1>("h01")) io.w.ready <= T_174 node T_175 = eq(state, UInt<2>("h02")) node T_176 = bit(strb, 0) node T_177 = and(T_175, T_176) io.smi.req.valid <= T_177 io.smi.req.bits.rw <= UInt<1>("h01") io.smi.req.bits.addr <= addr node T_179 = bits(data, 63, 0) io.smi.req.bits.data <= T_179 node T_180 = eq(state, UInt<2>("h03")) io.smi.resp.ready <= T_180 node T_181 = eq(state, UInt<3>("h04")) io.b.valid <= T_181 wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} T_187.user <= UInt<1>("h00") T_187.id <= UInt<1>("h00") T_187.resp <= UInt<1>("h00") T_187.id <= id T_187.resp <= UInt<1>("h00") T_187.user <= UInt<1>("h00") io.b.bits <- T_187 node T_196 = and(io.aw.ready, io.aw.valid) when T_196 : node T_197 = bits(io.aw.bits.addr, 14, 3) addr <= T_197 id <= io.aw.bits.id size <= io.aw.bits.size last <= UInt<1>("h00") state <= UInt<1>("h01") skip node T_199 = and(io.w.ready, io.w.valid) when T_199 : last <= io.w.bits.last node T_202 = dshl(UInt<1>("h01"), size) node T_203 = dshl(UInt<1>("h01"), T_202) node T_205 = subw(T_203, UInt<1>("h01")) node T_206 = and(T_205, io.w.bits.strb) node T_207 = bit(T_206, 0) wire T_209 : UInt<1>[1] T_209[0] <= T_207 strb <= T_209[0] data <= io.w.bits.data state <= UInt<2>("h02") skip node T_212 = eq(state, UInt<2>("h02")) when T_212 : node T_214 = eq(strb, UInt<1>("h00")) when T_214 : node T_215 = mux(last, UInt<2>("h03"), UInt<1>("h01")) state <= T_215 skip node T_216 = bit(strb, 0) node T_218 = eq(T_216, UInt<1>("h00")) node T_219 = or(io.smi.req.ready, T_218) node T_221 = eq(T_214, UInt<1>("h00")) node T_222 = and(T_221, T_219) when T_222 : node T_223 = dshr(strb, UInt<1>("h01")) strb <= T_223 node T_225 = cat(UInt<1>("h01"), UInt<6>("h00")) node T_226 = dshr(data, T_225) data <= T_226 node T_227 = addw(addr, UInt<1>("h01")) addr <= T_227 skip skip node T_228 = and(io.smi.resp.ready, io.smi.resp.valid) when T_228 : state <= UInt<3>("h04") skip node T_229 = and(io.b.ready, io.b.valid) when T_229 : state <= UInt<1>("h00") skip module RRArbiter_77 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.bits.rw <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_130 : UInt<1> T_130 <= UInt<1>("h00") io.out.valid <= io.in[T_130].valid io.out.bits <- io.in[T_130].bits io.chosen <= T_130 io.in[T_130].ready <= UInt<1>("h00") reg T_168 : UInt<1>, clk, reset, UInt<1>("h00") node T_169 = gt(UInt<1>("h00"), T_168) node T_170 = and(io.in[0].valid, T_169) node T_172 = gt(UInt<1>("h01"), T_168) node T_173 = and(io.in[1].valid, T_172) node T_176 = or(UInt<1>("h00"), T_170) node T_178 = eq(T_176, UInt<1>("h00")) node T_180 = or(UInt<1>("h00"), T_170) node T_181 = or(T_180, T_173) node T_183 = eq(T_181, UInt<1>("h00")) node T_185 = or(UInt<1>("h00"), T_170) node T_186 = or(T_185, T_173) node T_187 = or(T_186, io.in[0].valid) node T_189 = eq(T_187, UInt<1>("h00")) node T_191 = gt(UInt<1>("h00"), T_168) node T_192 = and(UInt<1>("h01"), T_191) node T_193 = or(T_192, T_183) node T_195 = gt(UInt<1>("h01"), T_168) node T_196 = and(T_178, T_195) node T_197 = or(T_196, T_189) node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_200 = mux(UInt<1>("h00"), T_199, T_193) node T_201 = and(T_200, io.out.ready) io.in[0].ready <= T_201 node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_204 = mux(UInt<1>("h00"), T_203, T_197) node T_205 = and(T_204, io.out.ready) io.in[1].ready <= T_205 node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_210 = gt(UInt<1>("h01"), T_168) node T_211 = and(io.in[1].valid, T_210) node T_213 = mux(T_211, UInt<1>("h01"), T_208) node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) T_130 <= T_214 node T_215 = and(io.out.ready, io.out.valid) when T_215 : T_168 <= T_130 skip module SmiArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.out.resp.ready <= UInt<1>("h00") io.out.req.bits.data <= UInt<1>("h00") io.out.req.bits.addr <= UInt<1>("h00") io.out.req.bits.rw <= UInt<1>("h00") io.out.req.valid <= UInt<1>("h00") io.in[0].resp.bits <= UInt<1>("h00") io.in[0].resp.valid <= UInt<1>("h00") io.in[0].req.ready <= UInt<1>("h00") io.in[1].resp.bits <= UInt<1>("h00") io.in[1].resp.valid <= UInt<1>("h00") io.in[1].req.ready <= UInt<1>("h00") reg wait_resp : UInt<1>, clk, reset, UInt<1>("h00") reg choice : UInt<1>, clk, UInt<1>("h00"), choice inst req_arb of RRArbiter_77 req_arb.io.out.ready <= UInt<1>("h00") req_arb.io.in[0].bits.data <= UInt<1>("h00") req_arb.io.in[0].bits.addr <= UInt<1>("h00") req_arb.io.in[0].bits.rw <= UInt<1>("h00") req_arb.io.in[0].valid <= UInt<1>("h00") req_arb.io.in[1].bits.data <= UInt<1>("h00") req_arb.io.in[1].bits.addr <= UInt<1>("h00") req_arb.io.in[1].bits.rw <= UInt<1>("h00") req_arb.io.in[1].valid <= UInt<1>("h00") req_arb.clk <= clk req_arb.reset <= reset req_arb.io.in[0] <- io.in[0].req req_arb.io.in[1] <- io.in[1].req node T_322 = eq(wait_resp, UInt<1>("h00")) node T_323 = and(io.out.req.ready, T_322) req_arb.io.out.ready <= T_323 io.out.req.bits <- req_arb.io.out.bits node T_325 = eq(wait_resp, UInt<1>("h00")) node T_326 = and(req_arb.io.out.valid, T_325) io.out.req.valid <= T_326 node T_327 = and(io.out.req.ready, io.out.req.valid) when T_327 : choice <= req_arb.io.chosen wait_resp <= UInt<1>("h01") skip node T_329 = and(io.out.resp.ready, io.out.resp.valid) when T_329 : wait_resp <= UInt<1>("h00") skip io.in[0].resp.bits <= io.out.resp.bits node T_332 = eq(choice, UInt<1>("h00")) node T_333 = and(io.out.resp.valid, T_332) io.in[0].resp.valid <= T_333 io.in[1].resp.bits <= io.out.resp.bits node T_335 = eq(choice, UInt<1>("h01")) node T_336 = and(io.out.resp.valid, T_335) io.in[1].resp.valid <= T_336 io.out.resp.ready <= io.in[choice].resp.ready module SmiIONastiIOConverter : input clk : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.nasti.r.bits.user <= UInt<1>("h00") io.nasti.r.bits.id <= UInt<1>("h00") io.nasti.r.bits.last <= UInt<1>("h00") io.nasti.r.bits.data <= UInt<1>("h00") io.nasti.r.bits.resp <= UInt<1>("h00") io.nasti.r.valid <= UInt<1>("h00") io.nasti.ar.ready <= UInt<1>("h00") io.nasti.b.bits.user <= UInt<1>("h00") io.nasti.b.bits.id <= UInt<1>("h00") io.nasti.b.bits.resp <= UInt<1>("h00") io.nasti.b.valid <= UInt<1>("h00") io.nasti.w.ready <= UInt<1>("h00") io.nasti.aw.ready <= UInt<1>("h00") inst reader of SmiIONastiReadIOConverter reader.io.smi.resp.bits <= UInt<1>("h00") reader.io.smi.resp.valid <= UInt<1>("h00") reader.io.smi.req.ready <= UInt<1>("h00") reader.io.r.ready <= UInt<1>("h00") reader.io.ar.bits.user <= UInt<1>("h00") reader.io.ar.bits.id <= UInt<1>("h00") reader.io.ar.bits.region <= UInt<1>("h00") reader.io.ar.bits.qos <= UInt<1>("h00") reader.io.ar.bits.prot <= UInt<1>("h00") reader.io.ar.bits.cache <= UInt<1>("h00") reader.io.ar.bits.lock <= UInt<1>("h00") reader.io.ar.bits.burst <= UInt<1>("h00") reader.io.ar.bits.size <= UInt<1>("h00") reader.io.ar.bits.len <= UInt<1>("h00") reader.io.ar.bits.addr <= UInt<1>("h00") reader.io.ar.valid <= UInt<1>("h00") reader.clk <= clk reader.reset <= reset reader.io.ar <- io.nasti.ar io.nasti.r <- reader.io.r inst writer of SmiIONastiWriteIOConverter writer.io.smi.resp.bits <= UInt<1>("h00") writer.io.smi.resp.valid <= UInt<1>("h00") writer.io.smi.req.ready <= UInt<1>("h00") writer.io.b.ready <= UInt<1>("h00") writer.io.w.bits.user <= UInt<1>("h00") writer.io.w.bits.strb <= UInt<1>("h00") writer.io.w.bits.last <= UInt<1>("h00") writer.io.w.bits.data <= UInt<1>("h00") writer.io.w.valid <= UInt<1>("h00") writer.io.aw.bits.user <= UInt<1>("h00") writer.io.aw.bits.id <= UInt<1>("h00") writer.io.aw.bits.region <= UInt<1>("h00") writer.io.aw.bits.qos <= UInt<1>("h00") writer.io.aw.bits.prot <= UInt<1>("h00") writer.io.aw.bits.cache <= UInt<1>("h00") writer.io.aw.bits.lock <= UInt<1>("h00") writer.io.aw.bits.burst <= UInt<1>("h00") writer.io.aw.bits.size <= UInt<1>("h00") writer.io.aw.bits.len <= UInt<1>("h00") writer.io.aw.bits.addr <= UInt<1>("h00") writer.io.aw.valid <= UInt<1>("h00") writer.clk <= clk writer.reset <= reset writer.io.aw <- io.nasti.aw writer.io.w <- io.nasti.w io.nasti.b <- writer.io.b inst arb of SmiArbiter arb.io.out.resp.bits <= UInt<1>("h00") arb.io.out.resp.valid <= UInt<1>("h00") arb.io.out.req.ready <= UInt<1>("h00") arb.io.in[0].resp.ready <= UInt<1>("h00") arb.io.in[0].req.bits.data <= UInt<1>("h00") arb.io.in[0].req.bits.addr <= UInt<1>("h00") arb.io.in[0].req.bits.rw <= UInt<1>("h00") arb.io.in[0].req.valid <= UInt<1>("h00") arb.io.in[1].resp.ready <= UInt<1>("h00") arb.io.in[1].req.bits.data <= UInt<1>("h00") arb.io.in[1].req.bits.addr <= UInt<1>("h00") arb.io.in[1].req.bits.rw <= UInt<1>("h00") arb.io.in[1].req.valid <= UInt<1>("h00") arb.clk <= clk arb.reset <= reset arb.io.in[0] <- reader.io.smi arb.io.in[1] <- writer.io.smi io.smi <- arb.io.out module SmiIONastiReadIOConverter_79 : input clk : Clock input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.r.bits.user <= UInt<1>("h00") io.r.bits.id <= UInt<1>("h00") io.r.bits.last <= UInt<1>("h00") io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<1>("h00") io.r.valid <= UInt<1>("h00") io.ar.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg nWords : UInt<1>, clk, UInt<1>("h00"), nWords reg nBeats : UInt<8>, clk, UInt<1>("h00"), nBeats reg addr : UInt<6>, clk, UInt<1>("h00"), addr reg id : UInt<5>, clk, UInt<1>("h00"), id reg byteOff : UInt<3>, clk, UInt<1>("h00"), byteOff reg sendInd : UInt<1>, clk, reset, UInt<1>("h00") reg recvInd : UInt<1>, clk, reset, UInt<1>("h00") reg sendDone : UInt<1>, clk, reset, UInt<1>("h00") wire T_141 : UInt<64>[1] T_141[0] <= UInt<64>("h00") reg buffer : UInt<64>[1], clk, reset, T_141 node T_149 = eq(state, UInt<1>("h00")) io.ar.ready <= T_149 node T_150 = eq(state, UInt<1>("h01")) node T_152 = eq(sendDone, UInt<1>("h00")) node T_153 = and(T_150, T_152) io.smi.req.valid <= T_153 io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.bits.addr <= addr node T_155 = eq(state, UInt<1>("h01")) io.smi.resp.ready <= T_155 node T_156 = eq(state, UInt<2>("h02")) io.r.valid <= T_156 node T_158 = eq(nBeats, UInt<1>("h00")) wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} T_166.user <= UInt<1>("h00") T_166.id <= UInt<1>("h00") T_166.last <= UInt<1>("h00") T_166.data <= UInt<1>("h00") T_166.resp <= UInt<1>("h00") T_166.id <= id T_166.data <= buffer[0] T_166.last <= T_158 T_166.resp <= UInt<1>("h00") T_166.user <= UInt<1>("h00") io.r.bits <- T_166 node T_178 = and(io.ar.ready, io.ar.valid) when T_178 : node T_180 = lt(io.ar.bits.size, UInt<2>("h03")) when T_180 : nWords <= UInt<1>("h00") node T_182 = bits(io.ar.bits.addr, 2, 0) byteOff <= T_182 skip node T_184 = eq(T_180, UInt<1>("h00")) when T_184 : node T_187 = subw(io.ar.bits.size, UInt<2>("h03")) node T_188 = dshl(UInt<1>("h01"), T_187) node T_190 = subw(T_188, UInt<1>("h01")) nWords <= T_190 byteOff <= UInt<1>("h00") skip nBeats <= io.ar.bits.len node T_192 = bits(io.ar.bits.addr, 8, 3) addr <= T_192 id <= io.ar.bits.id state <= UInt<1>("h01") skip node T_193 = and(io.smi.req.ready, io.smi.req.valid) when T_193 : node T_195 = addw(addr, UInt<1>("h01")) addr <= T_195 node T_197 = addw(sendInd, UInt<1>("h01")) sendInd <= T_197 node T_198 = eq(sendInd, nWords) sendDone <= T_198 skip node T_199 = and(io.smi.resp.ready, io.smi.resp.valid) when T_199 : node T_201 = addw(recvInd, UInt<1>("h01")) recvInd <= T_201 node T_204 = cat(byteOff, UInt<3>("h00")) node T_205 = dshr(io.smi.resp.bits, T_204) buffer[recvInd] <= T_205 node T_206 = eq(recvInd, nWords) when T_206 : state <= UInt<2>("h02") skip skip node T_207 = and(io.r.ready, io.r.valid) when T_207 : recvInd <= UInt<1>("h00") sendInd <= UInt<1>("h00") sendDone <= UInt<1>("h00") buffer[0] <= UInt<1>("h00") node T_213 = subw(nBeats, UInt<1>("h01")) nBeats <= T_213 node T_214 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) state <= T_214 skip module SmiIONastiWriteIOConverter_80 : input clk : Clock input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.b.bits.user <= UInt<1>("h00") io.b.bits.id <= UInt<1>("h00") io.b.bits.resp <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.aw.ready <= UInt<1>("h00") node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) node T_149 = eq(reset, UInt<1>("h00")) when T_149 : node T_151 = eq(T_147, UInt<1>("h00")) when T_151 : node T_153 = eq(reset, UInt<1>("h00")) when T_153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size") skip stop(clk, UInt<1>(1), 1) skip skip reg id : UInt<5>, clk, UInt<1>("h00"), id reg addr : UInt<6>, clk, UInt<1>("h00"), addr reg size : UInt<3>, clk, UInt<1>("h00"), size reg strb : UInt<1>, clk, UInt<1>("h00"), strb reg data : UInt<64>, clk, UInt<1>("h00"), data reg last : UInt<1>, clk, UInt<1>("h00"), last reg state : UInt, clk, reset, UInt<1>("h00") node T_173 = eq(state, UInt<1>("h00")) io.aw.ready <= T_173 node T_174 = eq(state, UInt<1>("h01")) io.w.ready <= T_174 node T_175 = eq(state, UInt<2>("h02")) node T_176 = bit(strb, 0) node T_177 = and(T_175, T_176) io.smi.req.valid <= T_177 io.smi.req.bits.rw <= UInt<1>("h01") io.smi.req.bits.addr <= addr node T_179 = bits(data, 63, 0) io.smi.req.bits.data <= T_179 node T_180 = eq(state, UInt<2>("h03")) io.smi.resp.ready <= T_180 node T_181 = eq(state, UInt<3>("h04")) io.b.valid <= T_181 wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} T_187.user <= UInt<1>("h00") T_187.id <= UInt<1>("h00") T_187.resp <= UInt<1>("h00") T_187.id <= id T_187.resp <= UInt<1>("h00") T_187.user <= UInt<1>("h00") io.b.bits <- T_187 node T_196 = and(io.aw.ready, io.aw.valid) when T_196 : node T_197 = bits(io.aw.bits.addr, 8, 3) addr <= T_197 id <= io.aw.bits.id size <= io.aw.bits.size last <= UInt<1>("h00") state <= UInt<1>("h01") skip node T_199 = and(io.w.ready, io.w.valid) when T_199 : last <= io.w.bits.last node T_202 = dshl(UInt<1>("h01"), size) node T_203 = dshl(UInt<1>("h01"), T_202) node T_205 = subw(T_203, UInt<1>("h01")) node T_206 = and(T_205, io.w.bits.strb) node T_207 = bit(T_206, 0) wire T_209 : UInt<1>[1] T_209[0] <= T_207 strb <= T_209[0] data <= io.w.bits.data state <= UInt<2>("h02") skip node T_212 = eq(state, UInt<2>("h02")) when T_212 : node T_214 = eq(strb, UInt<1>("h00")) when T_214 : node T_215 = mux(last, UInt<2>("h03"), UInt<1>("h01")) state <= T_215 skip node T_216 = bit(strb, 0) node T_218 = eq(T_216, UInt<1>("h00")) node T_219 = or(io.smi.req.ready, T_218) node T_221 = eq(T_214, UInt<1>("h00")) node T_222 = and(T_221, T_219) when T_222 : node T_223 = dshr(strb, UInt<1>("h01")) strb <= T_223 node T_225 = cat(UInt<1>("h01"), UInt<6>("h00")) node T_226 = dshr(data, T_225) data <= T_226 node T_227 = addw(addr, UInt<1>("h01")) addr <= T_227 skip skip node T_228 = and(io.smi.resp.ready, io.smi.resp.valid) when T_228 : state <= UInt<3>("h04") skip node T_229 = and(io.b.ready, io.b.valid) when T_229 : state <= UInt<1>("h00") skip module RRArbiter_82 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.bits.rw <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_130 : UInt<1> T_130 <= UInt<1>("h00") io.out.valid <= io.in[T_130].valid io.out.bits <- io.in[T_130].bits io.chosen <= T_130 io.in[T_130].ready <= UInt<1>("h00") reg T_168 : UInt<1>, clk, reset, UInt<1>("h00") node T_169 = gt(UInt<1>("h00"), T_168) node T_170 = and(io.in[0].valid, T_169) node T_172 = gt(UInt<1>("h01"), T_168) node T_173 = and(io.in[1].valid, T_172) node T_176 = or(UInt<1>("h00"), T_170) node T_178 = eq(T_176, UInt<1>("h00")) node T_180 = or(UInt<1>("h00"), T_170) node T_181 = or(T_180, T_173) node T_183 = eq(T_181, UInt<1>("h00")) node T_185 = or(UInt<1>("h00"), T_170) node T_186 = or(T_185, T_173) node T_187 = or(T_186, io.in[0].valid) node T_189 = eq(T_187, UInt<1>("h00")) node T_191 = gt(UInt<1>("h00"), T_168) node T_192 = and(UInt<1>("h01"), T_191) node T_193 = or(T_192, T_183) node T_195 = gt(UInt<1>("h01"), T_168) node T_196 = and(T_178, T_195) node T_197 = or(T_196, T_189) node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_200 = mux(UInt<1>("h00"), T_199, T_193) node T_201 = and(T_200, io.out.ready) io.in[0].ready <= T_201 node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_204 = mux(UInt<1>("h00"), T_203, T_197) node T_205 = and(T_204, io.out.ready) io.in[1].ready <= T_205 node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_210 = gt(UInt<1>("h01"), T_168) node T_211 = and(io.in[1].valid, T_210) node T_213 = mux(T_211, UInt<1>("h01"), T_208) node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) T_130 <= T_214 node T_215 = and(io.out.ready, io.out.valid) when T_215 : T_168 <= T_130 skip module SmiArbiter_81 : input clk : Clock input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.out.resp.ready <= UInt<1>("h00") io.out.req.bits.data <= UInt<1>("h00") io.out.req.bits.addr <= UInt<1>("h00") io.out.req.bits.rw <= UInt<1>("h00") io.out.req.valid <= UInt<1>("h00") io.in[0].resp.bits <= UInt<1>("h00") io.in[0].resp.valid <= UInt<1>("h00") io.in[0].req.ready <= UInt<1>("h00") io.in[1].resp.bits <= UInt<1>("h00") io.in[1].resp.valid <= UInt<1>("h00") io.in[1].req.ready <= UInt<1>("h00") reg wait_resp : UInt<1>, clk, reset, UInt<1>("h00") reg choice : UInt<1>, clk, UInt<1>("h00"), choice inst req_arb of RRArbiter_82 req_arb.io.out.ready <= UInt<1>("h00") req_arb.io.in[0].bits.data <= UInt<1>("h00") req_arb.io.in[0].bits.addr <= UInt<1>("h00") req_arb.io.in[0].bits.rw <= UInt<1>("h00") req_arb.io.in[0].valid <= UInt<1>("h00") req_arb.io.in[1].bits.data <= UInt<1>("h00") req_arb.io.in[1].bits.addr <= UInt<1>("h00") req_arb.io.in[1].bits.rw <= UInt<1>("h00") req_arb.io.in[1].valid <= UInt<1>("h00") req_arb.clk <= clk req_arb.reset <= reset req_arb.io.in[0] <- io.in[0].req req_arb.io.in[1] <- io.in[1].req node T_322 = eq(wait_resp, UInt<1>("h00")) node T_323 = and(io.out.req.ready, T_322) req_arb.io.out.ready <= T_323 io.out.req.bits <- req_arb.io.out.bits node T_325 = eq(wait_resp, UInt<1>("h00")) node T_326 = and(req_arb.io.out.valid, T_325) io.out.req.valid <= T_326 node T_327 = and(io.out.req.ready, io.out.req.valid) when T_327 : choice <= req_arb.io.chosen wait_resp <= UInt<1>("h01") skip node T_329 = and(io.out.resp.ready, io.out.resp.valid) when T_329 : wait_resp <= UInt<1>("h00") skip io.in[0].resp.bits <= io.out.resp.bits node T_332 = eq(choice, UInt<1>("h00")) node T_333 = and(io.out.resp.valid, T_332) io.in[0].resp.valid <= T_333 io.in[1].resp.bits <= io.out.resp.bits node T_335 = eq(choice, UInt<1>("h01")) node T_336 = and(io.out.resp.valid, T_335) io.in[1].resp.valid <= T_336 io.out.resp.ready <= io.in[choice].resp.ready module SmiIONastiIOConverter_78 : input clk : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} io.smi.resp.ready <= UInt<1>("h00") io.smi.req.bits.data <= UInt<1>("h00") io.smi.req.bits.addr <= UInt<1>("h00") io.smi.req.bits.rw <= UInt<1>("h00") io.smi.req.valid <= UInt<1>("h00") io.nasti.r.bits.user <= UInt<1>("h00") io.nasti.r.bits.id <= UInt<1>("h00") io.nasti.r.bits.last <= UInt<1>("h00") io.nasti.r.bits.data <= UInt<1>("h00") io.nasti.r.bits.resp <= UInt<1>("h00") io.nasti.r.valid <= UInt<1>("h00") io.nasti.ar.ready <= UInt<1>("h00") io.nasti.b.bits.user <= UInt<1>("h00") io.nasti.b.bits.id <= UInt<1>("h00") io.nasti.b.bits.resp <= UInt<1>("h00") io.nasti.b.valid <= UInt<1>("h00") io.nasti.w.ready <= UInt<1>("h00") io.nasti.aw.ready <= UInt<1>("h00") inst reader of SmiIONastiReadIOConverter_79 reader.io.smi.resp.bits <= UInt<1>("h00") reader.io.smi.resp.valid <= UInt<1>("h00") reader.io.smi.req.ready <= UInt<1>("h00") reader.io.r.ready <= UInt<1>("h00") reader.io.ar.bits.user <= UInt<1>("h00") reader.io.ar.bits.id <= UInt<1>("h00") reader.io.ar.bits.region <= UInt<1>("h00") reader.io.ar.bits.qos <= UInt<1>("h00") reader.io.ar.bits.prot <= UInt<1>("h00") reader.io.ar.bits.cache <= UInt<1>("h00") reader.io.ar.bits.lock <= UInt<1>("h00") reader.io.ar.bits.burst <= UInt<1>("h00") reader.io.ar.bits.size <= UInt<1>("h00") reader.io.ar.bits.len <= UInt<1>("h00") reader.io.ar.bits.addr <= UInt<1>("h00") reader.io.ar.valid <= UInt<1>("h00") reader.clk <= clk reader.reset <= reset reader.io.ar <- io.nasti.ar io.nasti.r <- reader.io.r inst writer of SmiIONastiWriteIOConverter_80 writer.io.smi.resp.bits <= UInt<1>("h00") writer.io.smi.resp.valid <= UInt<1>("h00") writer.io.smi.req.ready <= UInt<1>("h00") writer.io.b.ready <= UInt<1>("h00") writer.io.w.bits.user <= UInt<1>("h00") writer.io.w.bits.strb <= UInt<1>("h00") writer.io.w.bits.last <= UInt<1>("h00") writer.io.w.bits.data <= UInt<1>("h00") writer.io.w.valid <= UInt<1>("h00") writer.io.aw.bits.user <= UInt<1>("h00") writer.io.aw.bits.id <= UInt<1>("h00") writer.io.aw.bits.region <= UInt<1>("h00") writer.io.aw.bits.qos <= UInt<1>("h00") writer.io.aw.bits.prot <= UInt<1>("h00") writer.io.aw.bits.cache <= UInt<1>("h00") writer.io.aw.bits.lock <= UInt<1>("h00") writer.io.aw.bits.burst <= UInt<1>("h00") writer.io.aw.bits.size <= UInt<1>("h00") writer.io.aw.bits.len <= UInt<1>("h00") writer.io.aw.bits.addr <= UInt<1>("h00") writer.io.aw.valid <= UInt<1>("h00") writer.clk <= clk writer.reset <= reset writer.io.aw <- io.nasti.aw writer.io.w <- io.nasti.w io.nasti.b <- writer.io.b inst arb of SmiArbiter_81 arb.io.out.resp.bits <= UInt<1>("h00") arb.io.out.resp.valid <= UInt<1>("h00") arb.io.out.req.ready <= UInt<1>("h00") arb.io.in[0].resp.ready <= UInt<1>("h00") arb.io.in[0].req.bits.data <= UInt<1>("h00") arb.io.in[0].req.bits.addr <= UInt<1>("h00") arb.io.in[0].req.bits.rw <= UInt<1>("h00") arb.io.in[0].req.valid <= UInt<1>("h00") arb.io.in[1].resp.ready <= UInt<1>("h00") arb.io.in[1].req.bits.data <= UInt<1>("h00") arb.io.in[1].req.bits.addr <= UInt<1>("h00") arb.io.in[1].req.bits.rw <= UInt<1>("h00") arb.io.in[1].req.valid <= UInt<1>("h00") arb.clk <= clk arb.reset <= reset arb.io.in[0] <- reader.io.smi arb.io.in[1] <- writer.io.smi io.smi <- arb.io.out module NastiArbiter_83 : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} io.slave.r.ready <= UInt<1>("h00") io.slave.ar.bits.user <= UInt<1>("h00") io.slave.ar.bits.id <= UInt<1>("h00") io.slave.ar.bits.region <= UInt<1>("h00") io.slave.ar.bits.qos <= UInt<1>("h00") io.slave.ar.bits.prot <= UInt<1>("h00") io.slave.ar.bits.cache <= UInt<1>("h00") io.slave.ar.bits.lock <= UInt<1>("h00") io.slave.ar.bits.burst <= UInt<1>("h00") io.slave.ar.bits.size <= UInt<1>("h00") io.slave.ar.bits.len <= UInt<1>("h00") io.slave.ar.bits.addr <= UInt<1>("h00") io.slave.ar.valid <= UInt<1>("h00") io.slave.b.ready <= UInt<1>("h00") io.slave.w.bits.user <= UInt<1>("h00") io.slave.w.bits.strb <= UInt<1>("h00") io.slave.w.bits.last <= UInt<1>("h00") io.slave.w.bits.data <= UInt<1>("h00") io.slave.w.valid <= UInt<1>("h00") io.slave.aw.bits.user <= UInt<1>("h00") io.slave.aw.bits.id <= UInt<1>("h00") io.slave.aw.bits.region <= UInt<1>("h00") io.slave.aw.bits.qos <= UInt<1>("h00") io.slave.aw.bits.prot <= UInt<1>("h00") io.slave.aw.bits.cache <= UInt<1>("h00") io.slave.aw.bits.lock <= UInt<1>("h00") io.slave.aw.bits.burst <= UInt<1>("h00") io.slave.aw.bits.size <= UInt<1>("h00") io.slave.aw.bits.len <= UInt<1>("h00") io.slave.aw.bits.addr <= UInt<1>("h00") io.slave.aw.valid <= UInt<1>("h00") io.master[0].r.bits.user <= UInt<1>("h00") io.master[0].r.bits.id <= UInt<1>("h00") io.master[0].r.bits.last <= UInt<1>("h00") io.master[0].r.bits.data <= UInt<1>("h00") io.master[0].r.bits.resp <= UInt<1>("h00") io.master[0].r.valid <= UInt<1>("h00") io.master[0].ar.ready <= UInt<1>("h00") io.master[0].b.bits.user <= UInt<1>("h00") io.master[0].b.bits.id <= UInt<1>("h00") io.master[0].b.bits.resp <= UInt<1>("h00") io.master[0].b.valid <= UInt<1>("h00") io.master[0].w.ready <= UInt<1>("h00") io.master[0].aw.ready <= UInt<1>("h00") io.slave <- io.master[0] module MemIONastiIOConverter : input clk : Clock input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}} io.mem.resp.ready <= UInt<1>("h00") io.mem.req_data.bits.data <= UInt<1>("h00") io.mem.req_data.valid <= UInt<1>("h00") io.mem.req_cmd.bits.rw <= UInt<1>("h00") io.mem.req_cmd.bits.tag <= UInt<1>("h00") io.mem.req_cmd.bits.addr <= UInt<1>("h00") io.mem.req_cmd.valid <= UInt<1>("h00") io.nasti.r.bits.user <= UInt<1>("h00") io.nasti.r.bits.id <= UInt<1>("h00") io.nasti.r.bits.last <= UInt<1>("h00") io.nasti.r.bits.data <= UInt<1>("h00") io.nasti.r.bits.resp <= UInt<1>("h00") io.nasti.r.valid <= UInt<1>("h00") io.nasti.ar.ready <= UInt<1>("h00") io.nasti.b.bits.user <= UInt<1>("h00") io.nasti.b.bits.id <= UInt<1>("h00") io.nasti.b.bits.resp <= UInt<1>("h00") io.nasti.b.valid <= UInt<1>("h00") io.nasti.w.ready <= UInt<1>("h00") io.nasti.aw.ready <= UInt<1>("h00") node T_368 = and(io.mem.resp.ready, io.mem.resp.valid) reg mif_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") when T_368 : node T_372 = eq(mif_cnt_out, UInt<3>("h07")) node T_374 = and(UInt<1>("h00"), T_372) node T_377 = addw(mif_cnt_out, UInt<1>("h01")) node T_378 = mux(T_374, UInt<1>("h00"), T_377) mif_cnt_out <= T_378 skip node mif_wrap_out = and(T_368, T_372) node T_381 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_383 = eq(io.nasti.aw.bits.size, UInt<2>("h03")) node T_384 = or(T_381, T_383) node T_386 = eq(reset, UInt<1>("h00")) when T_386 : node T_388 = eq(T_384, UInt<1>("h00")) when T_388 : node T_390 = eq(reset, UInt<1>("h00")) when T_390 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") skip stop(clk, UInt<1>(1), 1) skip skip node T_392 = eq(io.nasti.ar.valid, UInt<1>("h00")) node T_394 = eq(io.nasti.ar.bits.size, UInt<2>("h03")) node T_395 = or(T_392, T_394) node T_397 = eq(reset, UInt<1>("h00")) when T_397 : node T_399 = eq(T_395, UInt<1>("h00")) when T_399 : node T_401 = eq(reset, UInt<1>("h00")) when T_401 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") skip stop(clk, UInt<1>(1), 1) skip skip node T_403 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_405 = eq(io.nasti.aw.bits.len, UInt<3>("h07")) node T_406 = or(T_403, T_405) node T_408 = eq(reset, UInt<1>("h00")) when T_408 : node T_410 = eq(T_406, UInt<1>("h00")) when T_410 : node T_412 = eq(reset, UInt<1>("h00")) when T_412 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") skip stop(clk, UInt<1>(1), 1) skip skip node T_414 = eq(io.nasti.ar.valid, UInt<1>("h00")) node T_416 = eq(io.nasti.ar.bits.len, UInt<3>("h07")) node T_417 = or(T_414, T_416) node T_419 = eq(reset, UInt<1>("h00")) when T_419 : node T_421 = eq(T_417, UInt<1>("h00")) when T_421 : node T_423 = eq(reset, UInt<1>("h00")) when T_423 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") skip stop(clk, UInt<1>(1), 1) skip skip reg b_ok : UInt<1>, clk, reset, UInt<1>("h01") node T_426 = and(io.nasti.aw.ready, io.nasti.aw.valid) when T_426 : b_ok <= UInt<1>("h00") skip node T_428 = and(io.nasti.w.ready, io.nasti.w.valid) node T_429 = and(T_428, io.nasti.w.bits.last) when T_429 : b_ok <= UInt<1>("h01") skip inst id_q of Queue_37 id_q.io.deq.ready <= UInt<1>("h00") id_q.io.enq.bits <= UInt<1>("h00") id_q.io.enq.valid <= UInt<1>("h00") id_q.clk <= clk id_q.reset <= reset node T_436 = and(io.nasti.aw.valid, io.mem.req_cmd.ready) id_q.io.enq.valid <= T_436 id_q.io.enq.bits <= io.nasti.aw.bits.id node T_437 = and(io.nasti.b.ready, b_ok) id_q.io.deq.ready <= T_437 node T_438 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) node T_440 = dshr(T_438, UInt<3>("h06")) io.mem.req_cmd.bits.addr <= T_440 node T_441 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) io.mem.req_cmd.bits.tag <= T_441 io.mem.req_cmd.bits.rw <= io.nasti.aw.valid node T_442 = and(io.nasti.aw.valid, id_q.io.enq.ready) node T_443 = or(T_442, io.nasti.ar.valid) io.mem.req_cmd.valid <= T_443 node T_445 = eq(io.nasti.aw.valid, UInt<1>("h00")) node T_446 = and(io.mem.req_cmd.ready, T_445) io.nasti.ar.ready <= T_446 node T_447 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) io.nasti.aw.ready <= T_447 node T_448 = and(id_q.io.deq.valid, b_ok) io.nasti.b.valid <= T_448 io.nasti.b.bits.id <= id_q.io.deq.bits io.nasti.b.bits.resp <= UInt<1>("h00") io.nasti.w.ready <= io.mem.req_data.ready io.mem.req_data.valid <= io.nasti.w.valid io.mem.req_data.bits.data <= io.nasti.w.bits.data node T_451 = eq(io.nasti.w.valid, UInt<1>("h00")) node T_452 = not(io.nasti.w.bits.strb) node T_454 = eq(T_452, UInt<1>("h00")) node T_455 = or(T_451, T_454) node T_457 = eq(reset, UInt<1>("h00")) when T_457 : node T_459 = eq(T_455, UInt<1>("h00")) when T_459 : node T_461 = eq(reset, UInt<1>("h00")) when T_461 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): MemIO must write full cache line") skip stop(clk, UInt<1>(1), 1) skip skip io.nasti.r.valid <= io.mem.resp.valid io.nasti.r.bits.data <= io.mem.resp.bits.data io.nasti.r.bits.last <= mif_wrap_out io.nasti.r.bits.id <= io.mem.resp.bits.tag io.nasti.r.bits.resp <= UInt<1>("h00") io.mem.resp.ready <= io.nasti.r.ready module MemSerdes : input clk : Clock input reset : UInt<1> output io : {flip wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}, narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}} io.narrow.req.bits <= UInt<1>("h00") io.narrow.req.valid <= UInt<1>("h00") io.wide.resp.bits.tag <= UInt<1>("h00") io.wide.resp.bits.data <= UInt<1>("h00") io.wide.resp.valid <= UInt<1>("h00") io.wide.req_data.ready <= UInt<1>("h00") io.wide.req_cmd.ready <= UInt<1>("h00") node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) node T_113 = cat(io.wide.req_cmd.bits.addr, T_112) reg out_buf : UInt, clk, UInt<1>("h00"), out_buf reg in_buf : UInt, clk, UInt<1>("h00"), in_buf reg state : UInt, clk, reset, UInt<1>("h00") reg send_cnt : UInt<2>, clk, reset, UInt<2>("h00") reg data_send_cnt : UInt<3>, clk, reset, UInt<3>("h00") node T_130 = eq(send_cnt, UInt<1>("h01")) node adone = and(io.narrow.req.ready, T_130) node T_133 = eq(send_cnt, UInt<2>("h03")) node ddone = and(io.narrow.req.ready, T_133) node T_135 = and(io.narrow.req.valid, io.narrow.req.ready) when T_135 : node T_137 = addw(send_cnt, UInt<1>("h01")) send_cnt <= T_137 node T_139 = dshr(out_buf, UInt<5>("h010")) out_buf <= T_139 skip node T_140 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) when T_140 : node T_141 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) node T_142 = cat(io.wide.req_cmd.bits.addr, T_141) out_buf <= T_142 skip node T_143 = and(io.wide.req_data.valid, io.wide.req_data.ready) when T_143 : out_buf <= io.wide.req_data.bits.data skip node T_144 = eq(state, UInt<1>("h00")) io.wide.req_cmd.ready <= T_144 node T_145 = eq(state, UInt<2>("h03")) io.wide.req_data.ready <= T_145 node T_146 = eq(state, UInt<1>("h01")) node T_147 = eq(state, UInt<2>("h02")) node T_148 = or(T_146, T_147) node T_149 = eq(state, UInt<3>("h04")) node T_150 = or(T_148, T_149) io.narrow.req.valid <= T_150 io.narrow.req.bits <= out_buf node T_151 = eq(state, UInt<1>("h00")) node T_152 = and(T_151, io.wide.req_cmd.valid) when T_152 : node T_153 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) state <= T_153 skip node T_154 = eq(state, UInt<1>("h01")) node T_155 = and(T_154, adone) when T_155 : state <= UInt<1>("h00") send_cnt <= UInt<1>("h00") skip node T_157 = eq(state, UInt<2>("h02")) node T_158 = and(T_157, adone) when T_158 : state <= UInt<2>("h03") send_cnt <= UInt<1>("h00") skip node T_160 = eq(state, UInt<2>("h03")) node T_161 = and(T_160, io.wide.req_data.valid) when T_161 : state <= UInt<3>("h04") skip node T_162 = eq(state, UInt<3>("h04")) node T_163 = and(T_162, ddone) when T_163 : node T_165 = addw(data_send_cnt, UInt<1>("h01")) data_send_cnt <= T_165 node T_167 = eq(data_send_cnt, UInt<3>("h07")) node T_168 = mux(T_167, UInt<1>("h00"), UInt<2>("h03")) state <= T_168 send_cnt <= UInt<1>("h00") skip reg recv_cnt : UInt<3>, clk, reset, UInt<3>("h00") reg data_recv_cnt : UInt<3>, clk, reset, UInt<3>("h00") reg resp_val : UInt<1>, clk, reset, UInt<1>("h00") resp_val <= UInt<1>("h00") when io.narrow.resp.valid : node T_178 = addw(recv_cnt, UInt<1>("h01")) recv_cnt <= T_178 node T_180 = eq(recv_cnt, UInt<3>("h04")) when T_180 : recv_cnt <= UInt<1>("h00") node T_183 = addw(data_recv_cnt, UInt<1>("h01")) data_recv_cnt <= T_183 resp_val <= UInt<1>("h01") skip node T_185 = bits(in_buf, 79, 16) node T_186 = cat(io.narrow.resp.bits, T_185) in_buf <= T_186 skip io.wide.resp.valid <= resp_val wire T_190 : {data : UInt<64>, tag : UInt<5>} T_190.tag <= UInt<1>("h00") T_190.data <= UInt<1>("h00") node T_195 = bits(in_buf, 4, 0) T_190.tag <= T_195 node T_196 = bits(in_buf, 68, 5) T_190.data <= T_196 io.wide.resp.bits <- T_190 module OuterMemorySystem : input clk : Clock input reset : UInt<1> output io : {flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, flip incoherent : UInt<1>[1], mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, deviceTree : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} io.dma.resp.bits.status <= UInt<1>("h00") io.dma.resp.bits.client_xact_id <= UInt<1>("h00") io.dma.resp.valid <= UInt<1>("h00") io.dma.req.ready <= UInt<1>("h00") io.deviceTree.r.ready <= UInt<1>("h00") io.deviceTree.ar.bits.user <= UInt<1>("h00") io.deviceTree.ar.bits.id <= UInt<1>("h00") io.deviceTree.ar.bits.region <= UInt<1>("h00") io.deviceTree.ar.bits.qos <= UInt<1>("h00") io.deviceTree.ar.bits.prot <= UInt<1>("h00") io.deviceTree.ar.bits.cache <= UInt<1>("h00") io.deviceTree.ar.bits.lock <= UInt<1>("h00") io.deviceTree.ar.bits.burst <= UInt<1>("h00") io.deviceTree.ar.bits.size <= UInt<1>("h00") io.deviceTree.ar.bits.len <= UInt<1>("h00") io.deviceTree.ar.bits.addr <= UInt<1>("h00") io.deviceTree.ar.valid <= UInt<1>("h00") io.deviceTree.b.ready <= UInt<1>("h00") io.deviceTree.w.bits.user <= UInt<1>("h00") io.deviceTree.w.bits.strb <= UInt<1>("h00") io.deviceTree.w.bits.last <= UInt<1>("h00") io.deviceTree.w.bits.data <= UInt<1>("h00") io.deviceTree.w.valid <= UInt<1>("h00") io.deviceTree.aw.bits.user <= UInt<1>("h00") io.deviceTree.aw.bits.id <= UInt<1>("h00") io.deviceTree.aw.bits.region <= UInt<1>("h00") io.deviceTree.aw.bits.qos <= UInt<1>("h00") io.deviceTree.aw.bits.prot <= UInt<1>("h00") io.deviceTree.aw.bits.cache <= UInt<1>("h00") io.deviceTree.aw.bits.lock <= UInt<1>("h00") io.deviceTree.aw.bits.burst <= UInt<1>("h00") io.deviceTree.aw.bits.size <= UInt<1>("h00") io.deviceTree.aw.bits.len <= UInt<1>("h00") io.deviceTree.aw.bits.addr <= UInt<1>("h00") io.deviceTree.aw.valid <= UInt<1>("h00") io.mmio.r.ready <= UInt<1>("h00") io.mmio.ar.bits.user <= UInt<1>("h00") io.mmio.ar.bits.id <= UInt<1>("h00") io.mmio.ar.bits.region <= UInt<1>("h00") io.mmio.ar.bits.qos <= UInt<1>("h00") io.mmio.ar.bits.prot <= UInt<1>("h00") io.mmio.ar.bits.cache <= UInt<1>("h00") io.mmio.ar.bits.lock <= UInt<1>("h00") io.mmio.ar.bits.burst <= UInt<1>("h00") io.mmio.ar.bits.size <= UInt<1>("h00") io.mmio.ar.bits.len <= UInt<1>("h00") io.mmio.ar.bits.addr <= UInt<1>("h00") io.mmio.ar.valid <= UInt<1>("h00") io.mmio.b.ready <= UInt<1>("h00") io.mmio.w.bits.user <= UInt<1>("h00") io.mmio.w.bits.strb <= UInt<1>("h00") io.mmio.w.bits.last <= UInt<1>("h00") io.mmio.w.bits.data <= UInt<1>("h00") io.mmio.w.valid <= UInt<1>("h00") io.mmio.aw.bits.user <= UInt<1>("h00") io.mmio.aw.bits.id <= UInt<1>("h00") io.mmio.aw.bits.region <= UInt<1>("h00") io.mmio.aw.bits.qos <= UInt<1>("h00") io.mmio.aw.bits.prot <= UInt<1>("h00") io.mmio.aw.bits.cache <= UInt<1>("h00") io.mmio.aw.bits.lock <= UInt<1>("h00") io.mmio.aw.bits.burst <= UInt<1>("h00") io.mmio.aw.bits.size <= UInt<1>("h00") io.mmio.aw.bits.len <= UInt<1>("h00") io.mmio.aw.bits.addr <= UInt<1>("h00") io.mmio.aw.valid <= UInt<1>("h00") io.scr.resp.ready <= UInt<1>("h00") io.scr.req.bits.data <= UInt<1>("h00") io.scr.req.bits.addr <= UInt<1>("h00") io.scr.req.bits.rw <= UInt<1>("h00") io.scr.req.valid <= UInt<1>("h00") io.csr[0].resp.ready <= UInt<1>("h00") io.csr[0].req.bits.data <= UInt<1>("h00") io.csr[0].req.bits.addr <= UInt<1>("h00") io.csr[0].req.bits.rw <= UInt<1>("h00") io.csr[0].req.valid <= UInt<1>("h00") io.mem_backup.req.bits <= UInt<1>("h00") io.mem_backup.req.valid <= UInt<1>("h00") io.mem[0].r.ready <= UInt<1>("h00") io.mem[0].ar.bits.user <= UInt<1>("h00") io.mem[0].ar.bits.id <= UInt<1>("h00") io.mem[0].ar.bits.region <= UInt<1>("h00") io.mem[0].ar.bits.qos <= UInt<1>("h00") io.mem[0].ar.bits.prot <= UInt<1>("h00") io.mem[0].ar.bits.cache <= UInt<1>("h00") io.mem[0].ar.bits.lock <= UInt<1>("h00") io.mem[0].ar.bits.burst <= UInt<1>("h00") io.mem[0].ar.bits.size <= UInt<1>("h00") io.mem[0].ar.bits.len <= UInt<1>("h00") io.mem[0].ar.bits.addr <= UInt<1>("h00") io.mem[0].ar.valid <= UInt<1>("h00") io.mem[0].b.ready <= UInt<1>("h00") io.mem[0].w.bits.user <= UInt<1>("h00") io.mem[0].w.bits.strb <= UInt<1>("h00") io.mem[0].w.bits.last <= UInt<1>("h00") io.mem[0].w.bits.data <= UInt<1>("h00") io.mem[0].w.valid <= UInt<1>("h00") io.mem[0].aw.bits.user <= UInt<1>("h00") io.mem[0].aw.bits.id <= UInt<1>("h00") io.mem[0].aw.bits.region <= UInt<1>("h00") io.mem[0].aw.bits.qos <= UInt<1>("h00") io.mem[0].aw.bits.prot <= UInt<1>("h00") io.mem[0].aw.bits.cache <= UInt<1>("h00") io.mem[0].aw.bits.lock <= UInt<1>("h00") io.mem[0].aw.bits.burst <= UInt<1>("h00") io.mem[0].aw.bits.size <= UInt<1>("h00") io.mem[0].aw.bits.len <= UInt<1>("h00") io.mem[0].aw.bits.addr <= UInt<1>("h00") io.mem[0].aw.valid <= UInt<1>("h00") io.htif_uncached.grant.bits.data <= UInt<1>("h00") io.htif_uncached.grant.bits.g_type <= UInt<1>("h00") io.htif_uncached.grant.bits.is_builtin_type <= UInt<1>("h00") io.htif_uncached.grant.bits.manager_xact_id <= UInt<1>("h00") io.htif_uncached.grant.bits.client_xact_id <= UInt<1>("h00") io.htif_uncached.grant.bits.addr_beat <= UInt<1>("h00") io.htif_uncached.grant.valid <= UInt<1>("h00") io.htif_uncached.acquire.ready <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.data <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.g_type <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.addr_beat <= UInt<1>("h00") io.tiles_uncached[0].grant.valid <= UInt<1>("h00") io.tiles_uncached[0].acquire.ready <= UInt<1>("h00") io.tiles_cached[0].release.ready <= UInt<1>("h00") io.tiles_cached[0].probe.bits.p_type <= UInt<1>("h00") io.tiles_cached[0].probe.bits.addr_block <= UInt<1>("h00") io.tiles_cached[0].probe.valid <= UInt<1>("h00") io.tiles_cached[0].grant.bits.data <= UInt<1>("h00") io.tiles_cached[0].grant.bits.g_type <= UInt<1>("h00") io.tiles_cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.tiles_cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.tiles_cached[0].grant.bits.client_xact_id <= UInt<1>("h00") io.tiles_cached[0].grant.bits.addr_beat <= UInt<1>("h00") io.tiles_cached[0].grant.valid <= UInt<1>("h00") io.tiles_cached[0].acquire.ready <= UInt<1>("h00") inst T_8064 of ClientTileLinkIOWrapper T_8064.io.out.release.ready <= UInt<1>("h00") T_8064.io.out.probe.bits.p_type <= UInt<1>("h00") T_8064.io.out.probe.bits.addr_block <= UInt<1>("h00") T_8064.io.out.probe.valid <= UInt<1>("h00") T_8064.io.out.grant.bits.data <= UInt<1>("h00") T_8064.io.out.grant.bits.g_type <= UInt<1>("h00") T_8064.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") T_8064.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") T_8064.io.out.grant.bits.client_xact_id <= UInt<1>("h00") T_8064.io.out.grant.bits.addr_beat <= UInt<1>("h00") T_8064.io.out.grant.valid <= UInt<1>("h00") T_8064.io.out.acquire.ready <= UInt<1>("h00") T_8064.io.in.grant.ready <= UInt<1>("h00") T_8064.io.in.acquire.bits.data <= UInt<1>("h00") T_8064.io.in.acquire.bits.union <= UInt<1>("h00") T_8064.io.in.acquire.bits.a_type <= UInt<1>("h00") T_8064.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8064.io.in.acquire.bits.addr_beat <= UInt<1>("h00") T_8064.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") T_8064.io.in.acquire.bits.addr_block <= UInt<1>("h00") T_8064.io.in.acquire.valid <= UInt<1>("h00") T_8064.clk <= clk T_8064.reset <= reset T_8064.io.in <- io.tiles_uncached[0] inst T_8086 of ClientTileLinkIOWrapper T_8086.io.out.release.ready <= UInt<1>("h00") T_8086.io.out.probe.bits.p_type <= UInt<1>("h00") T_8086.io.out.probe.bits.addr_block <= UInt<1>("h00") T_8086.io.out.probe.valid <= UInt<1>("h00") T_8086.io.out.grant.bits.data <= UInt<1>("h00") T_8086.io.out.grant.bits.g_type <= UInt<1>("h00") T_8086.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") T_8086.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") T_8086.io.out.grant.bits.client_xact_id <= UInt<1>("h00") T_8086.io.out.grant.bits.addr_beat <= UInt<1>("h00") T_8086.io.out.grant.valid <= UInt<1>("h00") T_8086.io.out.acquire.ready <= UInt<1>("h00") T_8086.io.in.grant.ready <= UInt<1>("h00") T_8086.io.in.acquire.bits.data <= UInt<1>("h00") T_8086.io.in.acquire.bits.union <= UInt<1>("h00") T_8086.io.in.acquire.bits.a_type <= UInt<1>("h00") T_8086.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8086.io.in.acquire.bits.addr_beat <= UInt<1>("h00") T_8086.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") T_8086.io.in.acquire.bits.addr_block <= UInt<1>("h00") T_8086.io.in.acquire.valid <= UInt<1>("h00") T_8086.clk <= clk T_8086.reset <= reset T_8086.io.in <- io.htif_uncached inst l1tol2net of RocketChipTileLinkArbiter l1tol2net.io.managers[0].release.ready <= UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.client_id <= UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.p_type <= UInt<1>("h00") l1tol2net.io.managers[0].probe.bits.addr_block <= UInt<1>("h00") l1tol2net.io.managers[0].probe.valid <= UInt<1>("h00") l1tol2net.io.managers[0].finish.ready <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.client_id <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.data <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.g_type <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.is_builtin_type <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.manager_xact_id <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.managers[0].grant.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.managers[0].grant.valid <= UInt<1>("h00") l1tol2net.io.managers[0].acquire.ready <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.data <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.r_type <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.voluntary <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[0].release.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[0].release.valid <= UInt<1>("h00") l1tol2net.io.clients[0].probe.ready <= UInt<1>("h00") l1tol2net.io.clients[0].grant.ready <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.data <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.union <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.a_type <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.is_builtin_type <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[0].acquire.valid <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.data <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.r_type <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.voluntary <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[1].release.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[1].release.valid <= UInt<1>("h00") l1tol2net.io.clients[1].probe.ready <= UInt<1>("h00") l1tol2net.io.clients[1].grant.ready <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.data <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.union <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.a_type <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.is_builtin_type <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[1].acquire.valid <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.data <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.r_type <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.voluntary <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[2].release.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[2].release.valid <= UInt<1>("h00") l1tol2net.io.clients[2].probe.ready <= UInt<1>("h00") l1tol2net.io.clients[2].grant.ready <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.data <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.union <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.a_type <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.is_builtin_type <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.addr_beat <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.client_xact_id <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.bits.addr_block <= UInt<1>("h00") l1tol2net.io.clients[2].acquire.valid <= UInt<1>("h00") l1tol2net.clk <= clk l1tol2net.reset <= reset inst T_8175 of L2BroadcastHub T_8175.io.outer.grant.bits.data <= UInt<1>("h00") T_8175.io.outer.grant.bits.g_type <= UInt<1>("h00") T_8175.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_8175.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_8175.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_8175.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_8175.io.outer.grant.valid <= UInt<1>("h00") T_8175.io.outer.acquire.ready <= UInt<1>("h00") T_8175.io.incoherent[0] <= UInt<1>("h00") T_8175.io.inner.release.bits.client_id <= UInt<1>("h00") T_8175.io.inner.release.bits.data <= UInt<1>("h00") T_8175.io.inner.release.bits.r_type <= UInt<1>("h00") T_8175.io.inner.release.bits.voluntary <= UInt<1>("h00") T_8175.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_8175.io.inner.release.bits.addr_block <= UInt<1>("h00") T_8175.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_8175.io.inner.release.valid <= UInt<1>("h00") T_8175.io.inner.probe.ready <= UInt<1>("h00") T_8175.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") T_8175.io.inner.finish.valid <= UInt<1>("h00") T_8175.io.inner.grant.ready <= UInt<1>("h00") T_8175.io.inner.acquire.bits.client_id <= UInt<1>("h00") T_8175.io.inner.acquire.bits.data <= UInt<1>("h00") T_8175.io.inner.acquire.bits.union <= UInt<1>("h00") T_8175.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_8175.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8175.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_8175.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_8175.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_8175.io.inner.acquire.valid <= UInt<1>("h00") T_8175.clk <= clk T_8175.reset <= reset T_8175.io.incoherent <= io.incoherent l1tol2net.io.clients[0] <- io.tiles_cached[0] l1tol2net.io.clients[1] <- T_8064.io.out l1tol2net.io.clients[2] <- T_8086.io.out l1tol2net.io.managers[0] <- T_8175.io.inner inst interconnect of NastiRecursiveInterconnect interconnect.io.slaves[0].r.bits.user <= UInt<1>("h00") interconnect.io.slaves[0].r.bits.id <= UInt<1>("h00") interconnect.io.slaves[0].r.bits.last <= UInt<1>("h00") interconnect.io.slaves[0].r.bits.data <= UInt<1>("h00") interconnect.io.slaves[0].r.bits.resp <= UInt<1>("h00") interconnect.io.slaves[0].r.valid <= UInt<1>("h00") interconnect.io.slaves[0].ar.ready <= UInt<1>("h00") interconnect.io.slaves[0].b.bits.user <= UInt<1>("h00") interconnect.io.slaves[0].b.bits.id <= UInt<1>("h00") interconnect.io.slaves[0].b.bits.resp <= UInt<1>("h00") interconnect.io.slaves[0].b.valid <= UInt<1>("h00") interconnect.io.slaves[0].w.ready <= UInt<1>("h00") interconnect.io.slaves[0].aw.ready <= UInt<1>("h00") interconnect.io.slaves[1].r.bits.user <= UInt<1>("h00") interconnect.io.slaves[1].r.bits.id <= UInt<1>("h00") interconnect.io.slaves[1].r.bits.last <= UInt<1>("h00") interconnect.io.slaves[1].r.bits.data <= UInt<1>("h00") interconnect.io.slaves[1].r.bits.resp <= UInt<1>("h00") interconnect.io.slaves[1].r.valid <= UInt<1>("h00") interconnect.io.slaves[1].ar.ready <= UInt<1>("h00") interconnect.io.slaves[1].b.bits.user <= UInt<1>("h00") interconnect.io.slaves[1].b.bits.id <= UInt<1>("h00") interconnect.io.slaves[1].b.bits.resp <= UInt<1>("h00") interconnect.io.slaves[1].b.valid <= UInt<1>("h00") interconnect.io.slaves[1].w.ready <= UInt<1>("h00") interconnect.io.slaves[1].aw.ready <= UInt<1>("h00") interconnect.io.slaves[2].r.bits.user <= UInt<1>("h00") interconnect.io.slaves[2].r.bits.id <= UInt<1>("h00") interconnect.io.slaves[2].r.bits.last <= UInt<1>("h00") interconnect.io.slaves[2].r.bits.data <= UInt<1>("h00") interconnect.io.slaves[2].r.bits.resp <= UInt<1>("h00") interconnect.io.slaves[2].r.valid <= UInt<1>("h00") interconnect.io.slaves[2].ar.ready <= UInt<1>("h00") interconnect.io.slaves[2].b.bits.user <= UInt<1>("h00") interconnect.io.slaves[2].b.bits.id <= UInt<1>("h00") interconnect.io.slaves[2].b.bits.resp <= UInt<1>("h00") interconnect.io.slaves[2].b.valid <= UInt<1>("h00") interconnect.io.slaves[2].w.ready <= UInt<1>("h00") interconnect.io.slaves[2].aw.ready <= UInt<1>("h00") interconnect.io.slaves[3].r.bits.user <= UInt<1>("h00") interconnect.io.slaves[3].r.bits.id <= UInt<1>("h00") interconnect.io.slaves[3].r.bits.last <= UInt<1>("h00") interconnect.io.slaves[3].r.bits.data <= UInt<1>("h00") interconnect.io.slaves[3].r.bits.resp <= UInt<1>("h00") interconnect.io.slaves[3].r.valid <= UInt<1>("h00") interconnect.io.slaves[3].ar.ready <= UInt<1>("h00") interconnect.io.slaves[3].b.bits.user <= UInt<1>("h00") interconnect.io.slaves[3].b.bits.id <= UInt<1>("h00") interconnect.io.slaves[3].b.bits.resp <= UInt<1>("h00") interconnect.io.slaves[3].b.valid <= UInt<1>("h00") interconnect.io.slaves[3].w.ready <= UInt<1>("h00") interconnect.io.slaves[3].aw.ready <= UInt<1>("h00") interconnect.io.slaves[4].r.bits.user <= UInt<1>("h00") interconnect.io.slaves[4].r.bits.id <= UInt<1>("h00") interconnect.io.slaves[4].r.bits.last <= UInt<1>("h00") interconnect.io.slaves[4].r.bits.data <= UInt<1>("h00") interconnect.io.slaves[4].r.bits.resp <= UInt<1>("h00") interconnect.io.slaves[4].r.valid <= UInt<1>("h00") interconnect.io.slaves[4].ar.ready <= UInt<1>("h00") interconnect.io.slaves[4].b.bits.user <= UInt<1>("h00") interconnect.io.slaves[4].b.bits.id <= UInt<1>("h00") interconnect.io.slaves[4].b.bits.resp <= UInt<1>("h00") interconnect.io.slaves[4].b.valid <= UInt<1>("h00") interconnect.io.slaves[4].w.ready <= UInt<1>("h00") interconnect.io.slaves[4].aw.ready <= UInt<1>("h00") interconnect.io.masters[0].r.ready <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.user <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.id <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.region <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.qos <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.prot <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.cache <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.lock <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.burst <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.size <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.len <= UInt<1>("h00") interconnect.io.masters[0].ar.bits.addr <= UInt<1>("h00") interconnect.io.masters[0].ar.valid <= UInt<1>("h00") interconnect.io.masters[0].b.ready <= UInt<1>("h00") interconnect.io.masters[0].w.bits.user <= UInt<1>("h00") interconnect.io.masters[0].w.bits.strb <= UInt<1>("h00") interconnect.io.masters[0].w.bits.last <= UInt<1>("h00") interconnect.io.masters[0].w.bits.data <= UInt<1>("h00") interconnect.io.masters[0].w.valid <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.user <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.id <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.region <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.qos <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.prot <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.cache <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.lock <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.burst <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.size <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.len <= UInt<1>("h00") interconnect.io.masters[0].aw.bits.addr <= UInt<1>("h00") interconnect.io.masters[0].aw.valid <= UInt<1>("h00") interconnect.io.masters[1].r.ready <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.user <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.id <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.region <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.qos <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.prot <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.cache <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.lock <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.burst <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.size <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.len <= UInt<1>("h00") interconnect.io.masters[1].ar.bits.addr <= UInt<1>("h00") interconnect.io.masters[1].ar.valid <= UInt<1>("h00") interconnect.io.masters[1].b.ready <= UInt<1>("h00") interconnect.io.masters[1].w.bits.user <= UInt<1>("h00") interconnect.io.masters[1].w.bits.strb <= UInt<1>("h00") interconnect.io.masters[1].w.bits.last <= UInt<1>("h00") interconnect.io.masters[1].w.bits.data <= UInt<1>("h00") interconnect.io.masters[1].w.valid <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.user <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.id <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.region <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.qos <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.prot <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.cache <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.lock <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.burst <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.size <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.len <= UInt<1>("h00") interconnect.io.masters[1].aw.bits.addr <= UInt<1>("h00") interconnect.io.masters[1].aw.valid <= UInt<1>("h00") interconnect.clk <= clk interconnect.reset <= reset inst T_8334 of ClientTileLinkIOUnwrapper T_8334.io.out.grant.bits.data <= UInt<1>("h00") T_8334.io.out.grant.bits.g_type <= UInt<1>("h00") T_8334.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") T_8334.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") T_8334.io.out.grant.bits.client_xact_id <= UInt<1>("h00") T_8334.io.out.grant.bits.addr_beat <= UInt<1>("h00") T_8334.io.out.grant.valid <= UInt<1>("h00") T_8334.io.out.acquire.ready <= UInt<1>("h00") T_8334.io.in.release.bits.data <= UInt<1>("h00") T_8334.io.in.release.bits.r_type <= UInt<1>("h00") T_8334.io.in.release.bits.voluntary <= UInt<1>("h00") T_8334.io.in.release.bits.client_xact_id <= UInt<1>("h00") T_8334.io.in.release.bits.addr_block <= UInt<1>("h00") T_8334.io.in.release.bits.addr_beat <= UInt<1>("h00") T_8334.io.in.release.valid <= UInt<1>("h00") T_8334.io.in.probe.ready <= UInt<1>("h00") T_8334.io.in.grant.ready <= UInt<1>("h00") T_8334.io.in.acquire.bits.data <= UInt<1>("h00") T_8334.io.in.acquire.bits.union <= UInt<1>("h00") T_8334.io.in.acquire.bits.a_type <= UInt<1>("h00") T_8334.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8334.io.in.acquire.bits.addr_beat <= UInt<1>("h00") T_8334.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") T_8334.io.in.acquire.bits.addr_block <= UInt<1>("h00") T_8334.io.in.acquire.valid <= UInt<1>("h00") T_8334.clk <= clk T_8334.reset <= reset inst T_8360 of TileLinkIONarrower T_8360.io.out.grant.bits.data <= UInt<1>("h00") T_8360.io.out.grant.bits.g_type <= UInt<1>("h00") T_8360.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") T_8360.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") T_8360.io.out.grant.bits.client_xact_id <= UInt<1>("h00") T_8360.io.out.grant.bits.addr_beat <= UInt<1>("h00") T_8360.io.out.grant.valid <= UInt<1>("h00") T_8360.io.out.acquire.ready <= UInt<1>("h00") T_8360.io.in.grant.ready <= UInt<1>("h00") T_8360.io.in.acquire.bits.data <= UInt<1>("h00") T_8360.io.in.acquire.bits.union <= UInt<1>("h00") T_8360.io.in.acquire.bits.a_type <= UInt<1>("h00") T_8360.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8360.io.in.acquire.bits.addr_beat <= UInt<1>("h00") T_8360.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") T_8360.io.in.acquire.bits.addr_block <= UInt<1>("h00") T_8360.io.in.acquire.valid <= UInt<1>("h00") T_8360.clk <= clk T_8360.reset <= reset inst T_8378 of NastiIOTileLinkIOConverter T_8378.io.nasti.r.bits.user <= UInt<1>("h00") T_8378.io.nasti.r.bits.id <= UInt<1>("h00") T_8378.io.nasti.r.bits.last <= UInt<1>("h00") T_8378.io.nasti.r.bits.data <= UInt<1>("h00") T_8378.io.nasti.r.bits.resp <= UInt<1>("h00") T_8378.io.nasti.r.valid <= UInt<1>("h00") T_8378.io.nasti.ar.ready <= UInt<1>("h00") T_8378.io.nasti.b.bits.user <= UInt<1>("h00") T_8378.io.nasti.b.bits.id <= UInt<1>("h00") T_8378.io.nasti.b.bits.resp <= UInt<1>("h00") T_8378.io.nasti.b.valid <= UInt<1>("h00") T_8378.io.nasti.w.ready <= UInt<1>("h00") T_8378.io.nasti.aw.ready <= UInt<1>("h00") T_8378.io.tl.grant.ready <= UInt<1>("h00") T_8378.io.tl.acquire.bits.data <= UInt<1>("h00") T_8378.io.tl.acquire.bits.union <= UInt<1>("h00") T_8378.io.tl.acquire.bits.a_type <= UInt<1>("h00") T_8378.io.tl.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8378.io.tl.acquire.bits.addr_beat <= UInt<1>("h00") T_8378.io.tl.acquire.bits.client_xact_id <= UInt<1>("h00") T_8378.io.tl.acquire.bits.addr_block <= UInt<1>("h00") T_8378.io.tl.acquire.valid <= UInt<1>("h00") T_8378.clk <= clk T_8378.reset <= reset inst T_8401 of ClientTileLinkIOWrapper_71 T_8401.io.out.release.ready <= UInt<1>("h00") T_8401.io.out.probe.bits.p_type <= UInt<1>("h00") T_8401.io.out.probe.bits.addr_block <= UInt<1>("h00") T_8401.io.out.probe.valid <= UInt<1>("h00") T_8401.io.out.grant.bits.data <= UInt<1>("h00") T_8401.io.out.grant.bits.g_type <= UInt<1>("h00") T_8401.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") T_8401.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") T_8401.io.out.grant.bits.client_xact_id <= UInt<1>("h00") T_8401.io.out.grant.bits.addr_beat <= UInt<1>("h00") T_8401.io.out.grant.valid <= UInt<1>("h00") T_8401.io.out.acquire.ready <= UInt<1>("h00") T_8401.io.in.grant.ready <= UInt<1>("h00") T_8401.io.in.acquire.bits.data <= UInt<1>("h00") T_8401.io.in.acquire.bits.union <= UInt<1>("h00") T_8401.io.in.acquire.bits.a_type <= UInt<1>("h00") T_8401.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8401.io.in.acquire.bits.addr_beat <= UInt<1>("h00") T_8401.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") T_8401.io.in.acquire.bits.addr_block <= UInt<1>("h00") T_8401.io.in.acquire.valid <= UInt<1>("h00") T_8401.clk <= clk T_8401.reset <= reset T_8401.io.in <- T_8175.io.outer inst T_8423 of ClientTileLinkEnqueuer T_8423.io.outer.release.ready <= UInt<1>("h00") T_8423.io.outer.probe.bits.p_type <= UInt<1>("h00") T_8423.io.outer.probe.bits.addr_block <= UInt<1>("h00") T_8423.io.outer.probe.valid <= UInt<1>("h00") T_8423.io.outer.grant.bits.data <= UInt<1>("h00") T_8423.io.outer.grant.bits.g_type <= UInt<1>("h00") T_8423.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") T_8423.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") T_8423.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") T_8423.io.outer.grant.bits.addr_beat <= UInt<1>("h00") T_8423.io.outer.grant.valid <= UInt<1>("h00") T_8423.io.outer.acquire.ready <= UInt<1>("h00") T_8423.io.inner.release.bits.data <= UInt<1>("h00") T_8423.io.inner.release.bits.r_type <= UInt<1>("h00") T_8423.io.inner.release.bits.voluntary <= UInt<1>("h00") T_8423.io.inner.release.bits.client_xact_id <= UInt<1>("h00") T_8423.io.inner.release.bits.addr_block <= UInt<1>("h00") T_8423.io.inner.release.bits.addr_beat <= UInt<1>("h00") T_8423.io.inner.release.valid <= UInt<1>("h00") T_8423.io.inner.probe.ready <= UInt<1>("h00") T_8423.io.inner.grant.ready <= UInt<1>("h00") T_8423.io.inner.acquire.bits.data <= UInt<1>("h00") T_8423.io.inner.acquire.bits.union <= UInt<1>("h00") T_8423.io.inner.acquire.bits.a_type <= UInt<1>("h00") T_8423.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") T_8423.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") T_8423.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") T_8423.io.inner.acquire.bits.addr_block <= UInt<1>("h00") T_8423.io.inner.acquire.valid <= UInt<1>("h00") T_8423.clk <= clk T_8423.reset <= reset T_8423.io.inner <- T_8401.io.out T_8334.io.in <- T_8423.io.outer T_8360.io.in <- T_8334.io.out T_8378.io.tl <- T_8360.io.out inst T_8465 of Queue_36 T_8465.io.deq.ready <= UInt<1>("h00") T_8465.io.enq.bits.user <= UInt<1>("h00") T_8465.io.enq.bits.id <= UInt<1>("h00") T_8465.io.enq.bits.region <= UInt<1>("h00") T_8465.io.enq.bits.qos <= UInt<1>("h00") T_8465.io.enq.bits.prot <= UInt<1>("h00") T_8465.io.enq.bits.cache <= UInt<1>("h00") T_8465.io.enq.bits.lock <= UInt<1>("h00") T_8465.io.enq.bits.burst <= UInt<1>("h00") T_8465.io.enq.bits.size <= UInt<1>("h00") T_8465.io.enq.bits.len <= UInt<1>("h00") T_8465.io.enq.bits.addr <= UInt<1>("h00") T_8465.io.enq.valid <= UInt<1>("h00") T_8465.clk <= clk T_8465.reset <= reset T_8465.io.enq.valid <= T_8378.io.nasti.ar.valid T_8465.io.enq.bits <- T_8378.io.nasti.ar.bits T_8378.io.nasti.ar.ready <= T_8465.io.enq.ready interconnect.io.masters[0].ar <- T_8465.io.deq inst T_8491 of Queue_36 T_8491.io.deq.ready <= UInt<1>("h00") T_8491.io.enq.bits.user <= UInt<1>("h00") T_8491.io.enq.bits.id <= UInt<1>("h00") T_8491.io.enq.bits.region <= UInt<1>("h00") T_8491.io.enq.bits.qos <= UInt<1>("h00") T_8491.io.enq.bits.prot <= UInt<1>("h00") T_8491.io.enq.bits.cache <= UInt<1>("h00") T_8491.io.enq.bits.lock <= UInt<1>("h00") T_8491.io.enq.bits.burst <= UInt<1>("h00") T_8491.io.enq.bits.size <= UInt<1>("h00") T_8491.io.enq.bits.len <= UInt<1>("h00") T_8491.io.enq.bits.addr <= UInt<1>("h00") T_8491.io.enq.valid <= UInt<1>("h00") T_8491.clk <= clk T_8491.reset <= reset T_8491.io.enq.valid <= T_8378.io.nasti.aw.valid T_8491.io.enq.bits <- T_8378.io.nasti.aw.bits T_8378.io.nasti.aw.ready <= T_8491.io.enq.ready interconnect.io.masters[0].aw <- T_8491.io.deq inst T_8510 of Queue_74 T_8510.io.deq.ready <= UInt<1>("h00") T_8510.io.enq.bits.user <= UInt<1>("h00") T_8510.io.enq.bits.strb <= UInt<1>("h00") T_8510.io.enq.bits.last <= UInt<1>("h00") T_8510.io.enq.bits.data <= UInt<1>("h00") T_8510.io.enq.valid <= UInt<1>("h00") T_8510.clk <= clk T_8510.reset <= reset T_8510.io.enq.valid <= T_8378.io.nasti.w.valid T_8510.io.enq.bits <- T_8378.io.nasti.w.bits T_8378.io.nasti.w.ready <= T_8510.io.enq.ready interconnect.io.masters[0].w <- T_8510.io.deq inst T_8523 of Queue_75 T_8523.io.deq.ready <= UInt<1>("h00") T_8523.io.enq.bits.user <= UInt<1>("h00") T_8523.io.enq.bits.id <= UInt<1>("h00") T_8523.io.enq.bits.last <= UInt<1>("h00") T_8523.io.enq.bits.data <= UInt<1>("h00") T_8523.io.enq.bits.resp <= UInt<1>("h00") T_8523.io.enq.valid <= UInt<1>("h00") T_8523.clk <= clk T_8523.reset <= reset T_8523.io.enq.valid <= interconnect.io.masters[0].r.valid T_8523.io.enq.bits <- interconnect.io.masters[0].r.bits interconnect.io.masters[0].r.ready <= T_8523.io.enq.ready T_8378.io.nasti.r <- T_8523.io.deq inst T_8535 of Queue_76 T_8535.io.deq.ready <= UInt<1>("h00") T_8535.io.enq.bits.user <= UInt<1>("h00") T_8535.io.enq.bits.id <= UInt<1>("h00") T_8535.io.enq.bits.resp <= UInt<1>("h00") T_8535.io.enq.valid <= UInt<1>("h00") T_8535.clk <= clk T_8535.reset <= reset T_8535.io.enq.valid <= interconnect.io.masters[0].b.valid T_8535.io.enq.bits <- interconnect.io.masters[0].b.bits interconnect.io.masters[0].b.ready <= T_8535.io.enq.ready T_8378.io.nasti.b <- T_8535.io.deq inst rtc of RTC rtc.io.r.bits.user <= UInt<1>("h00") rtc.io.r.bits.id <= UInt<1>("h00") rtc.io.r.bits.last <= UInt<1>("h00") rtc.io.r.bits.data <= UInt<1>("h00") rtc.io.r.bits.resp <= UInt<1>("h00") rtc.io.r.valid <= UInt<1>("h00") rtc.io.ar.ready <= UInt<1>("h00") rtc.io.b.bits.user <= UInt<1>("h00") rtc.io.b.bits.id <= UInt<1>("h00") rtc.io.b.bits.resp <= UInt<1>("h00") rtc.io.b.valid <= UInt<1>("h00") rtc.io.w.ready <= UInt<1>("h00") rtc.io.aw.ready <= UInt<1>("h00") rtc.clk <= clk rtc.reset <= reset interconnect.io.masters[1] <- rtc.io inst T_8555 of SmiIONastiIOConverter T_8555.io.smi.resp.bits <= UInt<1>("h00") T_8555.io.smi.resp.valid <= UInt<1>("h00") T_8555.io.smi.req.ready <= UInt<1>("h00") T_8555.io.nasti.r.ready <= UInt<1>("h00") T_8555.io.nasti.ar.bits.user <= UInt<1>("h00") T_8555.io.nasti.ar.bits.id <= UInt<1>("h00") T_8555.io.nasti.ar.bits.region <= UInt<1>("h00") T_8555.io.nasti.ar.bits.qos <= UInt<1>("h00") T_8555.io.nasti.ar.bits.prot <= UInt<1>("h00") T_8555.io.nasti.ar.bits.cache <= UInt<1>("h00") T_8555.io.nasti.ar.bits.lock <= UInt<1>("h00") T_8555.io.nasti.ar.bits.burst <= UInt<1>("h00") T_8555.io.nasti.ar.bits.size <= UInt<1>("h00") T_8555.io.nasti.ar.bits.len <= UInt<1>("h00") T_8555.io.nasti.ar.bits.addr <= UInt<1>("h00") T_8555.io.nasti.ar.valid <= UInt<1>("h00") T_8555.io.nasti.b.ready <= UInt<1>("h00") T_8555.io.nasti.w.bits.user <= UInt<1>("h00") T_8555.io.nasti.w.bits.strb <= UInt<1>("h00") T_8555.io.nasti.w.bits.last <= UInt<1>("h00") T_8555.io.nasti.w.bits.data <= UInt<1>("h00") T_8555.io.nasti.w.valid <= UInt<1>("h00") T_8555.io.nasti.aw.bits.user <= UInt<1>("h00") T_8555.io.nasti.aw.bits.id <= UInt<1>("h00") T_8555.io.nasti.aw.bits.region <= UInt<1>("h00") T_8555.io.nasti.aw.bits.qos <= UInt<1>("h00") T_8555.io.nasti.aw.bits.prot <= UInt<1>("h00") T_8555.io.nasti.aw.bits.cache <= UInt<1>("h00") T_8555.io.nasti.aw.bits.lock <= UInt<1>("h00") T_8555.io.nasti.aw.bits.burst <= UInt<1>("h00") T_8555.io.nasti.aw.bits.size <= UInt<1>("h00") T_8555.io.nasti.aw.bits.len <= UInt<1>("h00") T_8555.io.nasti.aw.bits.addr <= UInt<1>("h00") T_8555.io.nasti.aw.valid <= UInt<1>("h00") T_8555.clk <= clk T_8555.reset <= reset T_8555.io.nasti <- interconnect.io.slaves[2] io.csr[0] <- T_8555.io.smi inst src_conv of SmiIONastiIOConverter_78 src_conv.io.smi.resp.bits <= UInt<1>("h00") src_conv.io.smi.resp.valid <= UInt<1>("h00") src_conv.io.smi.req.ready <= UInt<1>("h00") src_conv.io.nasti.r.ready <= UInt<1>("h00") src_conv.io.nasti.ar.bits.user <= UInt<1>("h00") src_conv.io.nasti.ar.bits.id <= UInt<1>("h00") src_conv.io.nasti.ar.bits.region <= UInt<1>("h00") src_conv.io.nasti.ar.bits.qos <= UInt<1>("h00") src_conv.io.nasti.ar.bits.prot <= UInt<1>("h00") src_conv.io.nasti.ar.bits.cache <= UInt<1>("h00") src_conv.io.nasti.ar.bits.lock <= UInt<1>("h00") src_conv.io.nasti.ar.bits.burst <= UInt<1>("h00") src_conv.io.nasti.ar.bits.size <= UInt<1>("h00") src_conv.io.nasti.ar.bits.len <= UInt<1>("h00") src_conv.io.nasti.ar.bits.addr <= UInt<1>("h00") src_conv.io.nasti.ar.valid <= UInt<1>("h00") src_conv.io.nasti.b.ready <= UInt<1>("h00") src_conv.io.nasti.w.bits.user <= UInt<1>("h00") src_conv.io.nasti.w.bits.strb <= UInt<1>("h00") src_conv.io.nasti.w.bits.last <= UInt<1>("h00") src_conv.io.nasti.w.bits.data <= UInt<1>("h00") src_conv.io.nasti.w.valid <= UInt<1>("h00") src_conv.io.nasti.aw.bits.user <= UInt<1>("h00") src_conv.io.nasti.aw.bits.id <= UInt<1>("h00") src_conv.io.nasti.aw.bits.region <= UInt<1>("h00") src_conv.io.nasti.aw.bits.qos <= UInt<1>("h00") src_conv.io.nasti.aw.bits.prot <= UInt<1>("h00") src_conv.io.nasti.aw.bits.cache <= UInt<1>("h00") src_conv.io.nasti.aw.bits.lock <= UInt<1>("h00") src_conv.io.nasti.aw.bits.burst <= UInt<1>("h00") src_conv.io.nasti.aw.bits.size <= UInt<1>("h00") src_conv.io.nasti.aw.bits.len <= UInt<1>("h00") src_conv.io.nasti.aw.bits.addr <= UInt<1>("h00") src_conv.io.nasti.aw.valid <= UInt<1>("h00") src_conv.clk <= clk src_conv.reset <= reset src_conv.io.nasti <- interconnect.io.slaves[3] io.scr <- src_conv.io.smi io.mmio <- interconnect.io.slaves[4] io.deviceTree <- interconnect.io.slaves[1] inst T_8625 of NastiArbiter_83 T_8625.io.slave.r.bits.user <= UInt<1>("h00") T_8625.io.slave.r.bits.id <= UInt<1>("h00") T_8625.io.slave.r.bits.last <= UInt<1>("h00") T_8625.io.slave.r.bits.data <= UInt<1>("h00") T_8625.io.slave.r.bits.resp <= UInt<1>("h00") T_8625.io.slave.r.valid <= UInt<1>("h00") T_8625.io.slave.ar.ready <= UInt<1>("h00") T_8625.io.slave.b.bits.user <= UInt<1>("h00") T_8625.io.slave.b.bits.id <= UInt<1>("h00") T_8625.io.slave.b.bits.resp <= UInt<1>("h00") T_8625.io.slave.b.valid <= UInt<1>("h00") T_8625.io.slave.w.ready <= UInt<1>("h00") T_8625.io.slave.aw.ready <= UInt<1>("h00") T_8625.io.master[0].r.ready <= UInt<1>("h00") T_8625.io.master[0].ar.bits.user <= UInt<1>("h00") T_8625.io.master[0].ar.bits.id <= UInt<1>("h00") T_8625.io.master[0].ar.bits.region <= UInt<1>("h00") T_8625.io.master[0].ar.bits.qos <= UInt<1>("h00") T_8625.io.master[0].ar.bits.prot <= UInt<1>("h00") T_8625.io.master[0].ar.bits.cache <= UInt<1>("h00") T_8625.io.master[0].ar.bits.lock <= UInt<1>("h00") T_8625.io.master[0].ar.bits.burst <= UInt<1>("h00") T_8625.io.master[0].ar.bits.size <= UInt<1>("h00") T_8625.io.master[0].ar.bits.len <= UInt<1>("h00") T_8625.io.master[0].ar.bits.addr <= UInt<1>("h00") T_8625.io.master[0].ar.valid <= UInt<1>("h00") T_8625.io.master[0].b.ready <= UInt<1>("h00") T_8625.io.master[0].w.bits.user <= UInt<1>("h00") T_8625.io.master[0].w.bits.strb <= UInt<1>("h00") T_8625.io.master[0].w.bits.last <= UInt<1>("h00") T_8625.io.master[0].w.bits.data <= UInt<1>("h00") T_8625.io.master[0].w.valid <= UInt<1>("h00") T_8625.io.master[0].aw.bits.user <= UInt<1>("h00") T_8625.io.master[0].aw.bits.id <= UInt<1>("h00") T_8625.io.master[0].aw.bits.region <= UInt<1>("h00") T_8625.io.master[0].aw.bits.qos <= UInt<1>("h00") T_8625.io.master[0].aw.bits.prot <= UInt<1>("h00") T_8625.io.master[0].aw.bits.cache <= UInt<1>("h00") T_8625.io.master[0].aw.bits.lock <= UInt<1>("h00") T_8625.io.master[0].aw.bits.burst <= UInt<1>("h00") T_8625.io.master[0].aw.bits.size <= UInt<1>("h00") T_8625.io.master[0].aw.bits.len <= UInt<1>("h00") T_8625.io.master[0].aw.bits.addr <= UInt<1>("h00") T_8625.io.master[0].aw.valid <= UInt<1>("h00") T_8625.clk <= clk T_8625.reset <= reset inst T_8670 of MemIONastiIOConverter T_8670.io.mem.resp.bits.tag <= UInt<1>("h00") T_8670.io.mem.resp.bits.data <= UInt<1>("h00") T_8670.io.mem.resp.valid <= UInt<1>("h00") T_8670.io.mem.req_data.ready <= UInt<1>("h00") T_8670.io.mem.req_cmd.ready <= UInt<1>("h00") T_8670.io.nasti.r.ready <= UInt<1>("h00") T_8670.io.nasti.ar.bits.user <= UInt<1>("h00") T_8670.io.nasti.ar.bits.id <= UInt<1>("h00") T_8670.io.nasti.ar.bits.region <= UInt<1>("h00") T_8670.io.nasti.ar.bits.qos <= UInt<1>("h00") T_8670.io.nasti.ar.bits.prot <= UInt<1>("h00") T_8670.io.nasti.ar.bits.cache <= UInt<1>("h00") T_8670.io.nasti.ar.bits.lock <= UInt<1>("h00") T_8670.io.nasti.ar.bits.burst <= UInt<1>("h00") T_8670.io.nasti.ar.bits.size <= UInt<1>("h00") T_8670.io.nasti.ar.bits.len <= UInt<1>("h00") T_8670.io.nasti.ar.bits.addr <= UInt<1>("h00") T_8670.io.nasti.ar.valid <= UInt<1>("h00") T_8670.io.nasti.b.ready <= UInt<1>("h00") T_8670.io.nasti.w.bits.user <= UInt<1>("h00") T_8670.io.nasti.w.bits.strb <= UInt<1>("h00") T_8670.io.nasti.w.bits.last <= UInt<1>("h00") T_8670.io.nasti.w.bits.data <= UInt<1>("h00") T_8670.io.nasti.w.valid <= UInt<1>("h00") T_8670.io.nasti.aw.bits.user <= UInt<1>("h00") T_8670.io.nasti.aw.bits.id <= UInt<1>("h00") T_8670.io.nasti.aw.bits.region <= UInt<1>("h00") T_8670.io.nasti.aw.bits.qos <= UInt<1>("h00") T_8670.io.nasti.aw.bits.prot <= UInt<1>("h00") T_8670.io.nasti.aw.bits.cache <= UInt<1>("h00") T_8670.io.nasti.aw.bits.lock <= UInt<1>("h00") T_8670.io.nasti.aw.bits.burst <= UInt<1>("h00") T_8670.io.nasti.aw.bits.size <= UInt<1>("h00") T_8670.io.nasti.aw.bits.len <= UInt<1>("h00") T_8670.io.nasti.aw.bits.addr <= UInt<1>("h00") T_8670.io.nasti.aw.valid <= UInt<1>("h00") T_8670.clk <= clk T_8670.reset <= reset inst T_8707 of MemSerdes T_8707.io.narrow.resp.bits <= UInt<1>("h00") T_8707.io.narrow.resp.valid <= UInt<1>("h00") T_8707.io.narrow.req.ready <= UInt<1>("h00") T_8707.io.wide.resp.ready <= UInt<1>("h00") T_8707.io.wide.req_data.bits.data <= UInt<1>("h00") T_8707.io.wide.req_data.valid <= UInt<1>("h00") T_8707.io.wide.req_cmd.bits.rw <= UInt<1>("h00") T_8707.io.wide.req_cmd.bits.tag <= UInt<1>("h00") T_8707.io.wide.req_cmd.bits.addr <= UInt<1>("h00") T_8707.io.wide.req_cmd.valid <= UInt<1>("h00") T_8707.clk <= clk T_8707.reset <= reset T_8670.io.nasti <- T_8625.io.slave T_8707.io.wide <- T_8670.io.mem io.mem_backup <- T_8707.io.narrow node T_8718 = mux(io.mem_backup_en, T_8625.io.master[0].ar.ready, io.mem[0].ar.ready) interconnect.io.slaves[0].ar.ready <= T_8718 node T_8720 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8721 = and(interconnect.io.slaves[0].ar.valid, T_8720) io.mem[0].ar.valid <= T_8721 io.mem[0].ar.bits <- interconnect.io.slaves[0].ar.bits node T_8722 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) T_8625.io.master[0].ar.valid <= T_8722 T_8625.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits node T_8723 = mux(io.mem_backup_en, T_8625.io.master[0].aw.ready, io.mem[0].aw.ready) interconnect.io.slaves[0].aw.ready <= T_8723 node T_8725 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8726 = and(interconnect.io.slaves[0].aw.valid, T_8725) io.mem[0].aw.valid <= T_8726 io.mem[0].aw.bits <- interconnect.io.slaves[0].aw.bits node T_8727 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) T_8625.io.master[0].aw.valid <= T_8727 T_8625.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits node T_8728 = mux(io.mem_backup_en, T_8625.io.master[0].w.ready, io.mem[0].w.ready) interconnect.io.slaves[0].w.ready <= T_8728 node T_8730 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8731 = and(interconnect.io.slaves[0].w.valid, T_8730) io.mem[0].w.valid <= T_8731 io.mem[0].w.bits <- interconnect.io.slaves[0].w.bits node T_8732 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) T_8625.io.master[0].w.valid <= T_8732 T_8625.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits node T_8733 = mux(io.mem_backup_en, T_8625.io.master[0].b.valid, io.mem[0].b.valid) interconnect.io.slaves[0].b.valid <= T_8733 wire T_8738 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} T_8738 <- io.mem[0].b.bits when io.mem_backup_en : T_8738 <- T_8625.io.master[0].b.bits skip interconnect.io.slaves[0].b.bits <- T_8738 node T_8743 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8744 = and(interconnect.io.slaves[0].b.ready, T_8743) io.mem[0].b.ready <= T_8744 node T_8745 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) T_8625.io.master[0].b.ready <= T_8745 node T_8746 = mux(io.mem_backup_en, T_8625.io.master[0].r.valid, io.mem[0].r.valid) interconnect.io.slaves[0].r.valid <= T_8746 wire T_8753 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} T_8753 <- io.mem[0].r.bits when io.mem_backup_en : T_8753 <- T_8625.io.master[0].r.bits skip interconnect.io.slaves[0].r.bits <- T_8753 node T_8760 = eq(io.mem_backup_en, UInt<1>("h00")) node T_8761 = and(interconnect.io.slaves[0].r.ready, T_8760) io.mem[0].r.ready <= T_8761 node T_8762 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) T_8625.io.master[0].r.ready <= T_8762 module SCRFile : input clk : Clock input reset : UInt<1> output io : {flip smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}} io.scr.wdata <= UInt<1>("h00") io.scr.waddr <= UInt<1>("h00") io.scr.wen <= UInt<1>("h00") io.smi.resp.bits <= UInt<1>("h00") io.smi.resp.valid <= UInt<1>("h00") io.smi.req.ready <= UInt<1>("h00") wire scr_rdata : UInt<64>[64] scr_rdata[0] <= UInt<1>("h00") scr_rdata[1] <= UInt<1>("h00") scr_rdata[2] <= UInt<1>("h00") scr_rdata[3] <= UInt<1>("h00") scr_rdata[4] <= UInt<1>("h00") scr_rdata[5] <= UInt<1>("h00") scr_rdata[6] <= UInt<1>("h00") scr_rdata[7] <= UInt<1>("h00") scr_rdata[8] <= UInt<1>("h00") scr_rdata[9] <= UInt<1>("h00") scr_rdata[10] <= UInt<1>("h00") scr_rdata[11] <= UInt<1>("h00") scr_rdata[12] <= UInt<1>("h00") scr_rdata[13] <= UInt<1>("h00") scr_rdata[14] <= UInt<1>("h00") scr_rdata[15] <= UInt<1>("h00") scr_rdata[16] <= UInt<1>("h00") scr_rdata[17] <= UInt<1>("h00") scr_rdata[18] <= UInt<1>("h00") scr_rdata[19] <= UInt<1>("h00") scr_rdata[20] <= UInt<1>("h00") scr_rdata[21] <= UInt<1>("h00") scr_rdata[22] <= UInt<1>("h00") scr_rdata[23] <= UInt<1>("h00") scr_rdata[24] <= UInt<1>("h00") scr_rdata[25] <= UInt<1>("h00") scr_rdata[26] <= UInt<1>("h00") scr_rdata[27] <= UInt<1>("h00") scr_rdata[28] <= UInt<1>("h00") scr_rdata[29] <= UInt<1>("h00") scr_rdata[30] <= UInt<1>("h00") scr_rdata[31] <= UInt<1>("h00") scr_rdata[32] <= UInt<1>("h00") scr_rdata[33] <= UInt<1>("h00") scr_rdata[34] <= UInt<1>("h00") scr_rdata[35] <= UInt<1>("h00") scr_rdata[36] <= UInt<1>("h00") scr_rdata[37] <= UInt<1>("h00") scr_rdata[38] <= UInt<1>("h00") scr_rdata[39] <= UInt<1>("h00") scr_rdata[40] <= UInt<1>("h00") scr_rdata[41] <= UInt<1>("h00") scr_rdata[42] <= UInt<1>("h00") scr_rdata[43] <= UInt<1>("h00") scr_rdata[44] <= UInt<1>("h00") scr_rdata[45] <= UInt<1>("h00") scr_rdata[46] <= UInt<1>("h00") scr_rdata[47] <= UInt<1>("h00") scr_rdata[48] <= UInt<1>("h00") scr_rdata[49] <= UInt<1>("h00") scr_rdata[50] <= UInt<1>("h00") scr_rdata[51] <= UInt<1>("h00") scr_rdata[52] <= UInt<1>("h00") scr_rdata[53] <= UInt<1>("h00") scr_rdata[54] <= UInt<1>("h00") scr_rdata[55] <= UInt<1>("h00") scr_rdata[56] <= UInt<1>("h00") scr_rdata[57] <= UInt<1>("h00") scr_rdata[58] <= UInt<1>("h00") scr_rdata[59] <= UInt<1>("h00") scr_rdata[60] <= UInt<1>("h00") scr_rdata[61] <= UInt<1>("h00") scr_rdata[62] <= UInt<1>("h00") scr_rdata[63] <= UInt<1>("h00") scr_rdata[0] <= io.scr.rdata[0] scr_rdata[1] <= io.scr.rdata[1] scr_rdata[2] <= io.scr.rdata[2] scr_rdata[3] <= io.scr.rdata[3] scr_rdata[4] <= io.scr.rdata[4] scr_rdata[5] <= io.scr.rdata[5] scr_rdata[6] <= io.scr.rdata[6] scr_rdata[7] <= io.scr.rdata[7] scr_rdata[8] <= io.scr.rdata[8] scr_rdata[9] <= io.scr.rdata[9] scr_rdata[10] <= io.scr.rdata[10] scr_rdata[11] <= io.scr.rdata[11] scr_rdata[12] <= io.scr.rdata[12] scr_rdata[13] <= io.scr.rdata[13] scr_rdata[14] <= io.scr.rdata[14] scr_rdata[15] <= io.scr.rdata[15] scr_rdata[16] <= io.scr.rdata[16] scr_rdata[17] <= io.scr.rdata[17] scr_rdata[18] <= io.scr.rdata[18] scr_rdata[19] <= io.scr.rdata[19] scr_rdata[20] <= io.scr.rdata[20] scr_rdata[21] <= io.scr.rdata[21] scr_rdata[22] <= io.scr.rdata[22] scr_rdata[23] <= io.scr.rdata[23] scr_rdata[24] <= io.scr.rdata[24] scr_rdata[25] <= io.scr.rdata[25] scr_rdata[26] <= io.scr.rdata[26] scr_rdata[27] <= io.scr.rdata[27] scr_rdata[28] <= io.scr.rdata[28] scr_rdata[29] <= io.scr.rdata[29] scr_rdata[30] <= io.scr.rdata[30] scr_rdata[31] <= io.scr.rdata[31] scr_rdata[32] <= io.scr.rdata[32] scr_rdata[33] <= io.scr.rdata[33] scr_rdata[34] <= io.scr.rdata[34] scr_rdata[35] <= io.scr.rdata[35] scr_rdata[36] <= io.scr.rdata[36] scr_rdata[37] <= io.scr.rdata[37] scr_rdata[38] <= io.scr.rdata[38] scr_rdata[39] <= io.scr.rdata[39] scr_rdata[40] <= io.scr.rdata[40] scr_rdata[41] <= io.scr.rdata[41] scr_rdata[42] <= io.scr.rdata[42] scr_rdata[43] <= io.scr.rdata[43] scr_rdata[44] <= io.scr.rdata[44] scr_rdata[45] <= io.scr.rdata[45] scr_rdata[46] <= io.scr.rdata[46] scr_rdata[47] <= io.scr.rdata[47] scr_rdata[48] <= io.scr.rdata[48] scr_rdata[49] <= io.scr.rdata[49] scr_rdata[50] <= io.scr.rdata[50] scr_rdata[51] <= io.scr.rdata[51] scr_rdata[52] <= io.scr.rdata[52] scr_rdata[53] <= io.scr.rdata[53] scr_rdata[54] <= io.scr.rdata[54] scr_rdata[55] <= io.scr.rdata[55] scr_rdata[56] <= io.scr.rdata[56] scr_rdata[57] <= io.scr.rdata[57] scr_rdata[58] <= io.scr.rdata[58] scr_rdata[59] <= io.scr.rdata[59] scr_rdata[60] <= io.scr.rdata[60] scr_rdata[61] <= io.scr.rdata[61] scr_rdata[62] <= io.scr.rdata[62] scr_rdata[63] <= io.scr.rdata[63] scr_rdata[0] <= UInt<1>("h01") scr_rdata[1] <= UInt<11>("h0400") reg read_addr : UInt<6>, clk, reset, UInt<6>("h00") reg resp_valid : UInt<1>, clk, reset, UInt<1>("h00") node T_429 = eq(resp_valid, UInt<1>("h00")) io.smi.req.ready <= T_429 io.smi.resp.valid <= resp_valid io.smi.resp.bits <= scr_rdata[read_addr] node T_431 = and(io.smi.req.ready, io.smi.req.valid) node T_432 = and(T_431, io.smi.req.bits.rw) io.scr.wen <= T_432 io.scr.wdata <= io.smi.req.bits.data io.scr.waddr <= io.smi.req.bits.addr node T_433 = and(io.smi.req.ready, io.smi.req.valid) when T_433 : read_addr <= io.smi.req.bits.addr resp_valid <= UInt<1>("h01") skip node T_435 = and(io.smi.resp.ready, io.smi.resp.valid) when T_435 : resp_valid <= UInt<1>("h00") skip module Queue_89 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} io.count <= UInt<1>("h00") io.deq.bits.user <= UInt<1>("h00") io.deq.bits.id <= UInt<1>("h00") io.deq.bits.region <= UInt<1>("h00") io.deq.bits.qos <= UInt<1>("h00") io.deq.bits.prot <= UInt<1>("h00") io.deq.bits.cache <= UInt<1>("h00") io.deq.bits.lock <= UInt<1>("h00") io.deq.bits.burst <= UInt<1>("h00") io.deq.bits.size <= UInt<1>("h00") io.deq.bits.len <= UInt<1>("h00") io.deq.bits.addr <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[1] reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_130 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_130) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_136 = and(io.enq.ready, io.enq.valid) node T_138 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_136, T_138) node T_140 = and(io.deq.ready, io.deq.valid) node T_142 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_140, T_142) when do_enq : infer mport T_144 = ram[UInt<1>("h00")], clk T_144 <- io.enq.bits skip when do_deq : skip node T_158 = neq(do_enq, do_deq) when T_158 : maybe_full <= do_enq skip node T_160 = eq(empty, UInt<1>("h00")) node T_162 = and(UInt<1>("h00"), io.enq.valid) node T_163 = or(T_160, T_162) io.deq.valid <= T_163 node T_165 = eq(full, UInt<1>("h00")) node T_167 = and(UInt<1>("h00"), io.deq.ready) node T_168 = or(T_165, T_167) io.enq.ready <= T_168 infer mport T_169 = ram[UInt<1>("h00")], clk wire T_193 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} T_193 <- T_169 when maybe_flow : T_193 <- io.enq.bits skip io.deq.bits <- T_193 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_206 = and(maybe_full, ptr_match) node T_207 = cat(T_206, ptr_diff) io.count <= T_207 module NastiROM : input clk : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} io.r.bits.user <= UInt<1>("h00") io.r.bits.id <= UInt<1>("h00") io.r.bits.last <= UInt<1>("h00") io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<1>("h00") io.r.valid <= UInt<1>("h00") io.ar.ready <= UInt<1>("h00") io.b.bits.user <= UInt<1>("h00") io.b.bits.id <= UInt<1>("h00") io.b.bits.resp <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.aw.ready <= UInt<1>("h00") inst T_334 of Queue_89 T_334.io.deq.ready <= UInt<1>("h00") T_334.io.enq.bits.user <= UInt<1>("h00") T_334.io.enq.bits.id <= UInt<1>("h00") T_334.io.enq.bits.region <= UInt<1>("h00") T_334.io.enq.bits.qos <= UInt<1>("h00") T_334.io.enq.bits.prot <= UInt<1>("h00") T_334.io.enq.bits.cache <= UInt<1>("h00") T_334.io.enq.bits.lock <= UInt<1>("h00") T_334.io.enq.bits.burst <= UInt<1>("h00") T_334.io.enq.bits.size <= UInt<1>("h00") T_334.io.enq.bits.len <= UInt<1>("h00") T_334.io.enq.bits.addr <= UInt<1>("h00") T_334.io.enq.valid <= UInt<1>("h00") T_334.clk <= clk T_334.reset <= reset T_334.io.enq.valid <= io.ar.valid T_334.io.enq.bits <- io.ar.bits io.ar.ready <= T_334.io.enq.ready when T_334.io.deq.valid : node T_349 = eq(T_334.io.deq.bits.len, UInt<1>("h00")) node T_351 = eq(reset, UInt<1>("h00")) when T_351 : node T_353 = eq(T_349, UInt<1>("h00")) when T_353 : node T_355 = eq(reset, UInt<1>("h00")) when T_355 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM") skip stop(clk, UInt<1>(1), 1) skip skip skip node T_356 = or(io.aw.valid, io.w.valid) node T_358 = eq(T_356, UInt<1>("h00")) node T_360 = eq(reset, UInt<1>("h00")) when T_360 : node T_362 = eq(T_358, UInt<1>("h00")) when T_362 : node T_364 = eq(reset, UInt<1>("h00")) when T_364 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't write to NastiROM") skip stop(clk, UInt<1>(1), 1) skip skip io.aw.ready <= UInt<1>("h00") io.w.ready <= UInt<1>("h00") io.b.valid <= UInt<1>("h00") wire rom : UInt<64>[67] rom[0] <= UInt<60>("h0b020000edfe0dd0") rom[1] <= UInt<64>("h0c001000038000000") rom[2] <= UInt<61>("h01100000028000000") rom[3] <= UInt<29>("h010000000") rom[4] <= UInt<64>("h0880100004b000000") rom[5] <= UInt<1>("h00") rom[6] <= UInt<1>("h00") rom[7] <= UInt<25>("h01000000") rom[8] <= UInt<59>("h0400000003000000") rom[9] <= UInt<58>("h0200000000000000") rom[10] <= UInt<59>("h0400000003000000") rom[11] <= UInt<58>("h020000000f000000") rom[12] <= UInt<60>("h0c00000003000000") rom[13] <= UInt<63>("h06b636f521b000000") rom[14] <= UInt<55>("h0706968432d7465") rom[15] <= UInt<63>("h06f6d656d01000000") rom[16] <= UInt<30>("h030407972") rom[17] <= UInt<59>("h0700000003000000") rom[18] <= UInt<63>("h06f6d656d21000000") rom[19] <= UInt<58>("h0300000000007972") rom[20] <= UInt<62>("h02d00000010000000") rom[21] <= UInt<1>("h00") rom[22] <= UInt<39>("h04000000000") rom[23] <= UInt<57>("h0100000002000000") rom[24] <= UInt<31>("h073757063") rom[25] <= UInt<59>("h0400000003000000") rom[26] <= UInt<58>("h0200000000000000") rom[27] <= UInt<59>("h0400000003000000") rom[28] <= UInt<58>("h020000000f000000") rom[29] <= UInt<63>("h04075706301000000") rom[30] <= UInt<62>("h03030303830303034") rom[31] <= UInt<58>("h0300000000000000") rom[32] <= UInt<62>("h02100000004000000") rom[33] <= UInt<58>("h0300000000757063") rom[34] <= UInt<62>("h03100000006000000") rom[35] <= UInt<39>("h07663736972") rom[36] <= UInt<59>("h0500000003000000") rom[37] <= UInt<62>("h0343676723c000000") rom[38] <= UInt<58>("h0300000000000000") rom[39] <= UInt<62>("h02d00000008000000") rom[40] <= UInt<56>("h080004000000000") rom[41] <= UInt<58>("h0200000002000000") rom[42] <= UInt<63>("h04072637301000000") rom[43] <= UInt<62>("h03030303031303034") rom[44] <= UInt<58>("h0300000000000000") rom[45] <= UInt<62>("h02100000004000000") rom[46] <= UInt<58>("h0300000000726373") rom[47] <= UInt<62>("h03100000006000000") rom[48] <= UInt<39>("h07663736972") rom[49] <= UInt<59>("h0400000003000000") rom[50] <= UInt<58>("h0300000040000000") rom[51] <= UInt<61>("h01000000003000000") rom[52] <= UInt<30>("h02d000000") rom[53] <= UInt<9>("h0140") rom[54] <= UInt<58>("h0200000000020000") rom[55] <= UInt<60>("h0900000002000000") rom[56] <= UInt<63>("h07373657264646123") rom[57] <= UInt<62>("h02300736c6c65632d") rom[58] <= UInt<63>("h06c65632d657a6973") rom[59] <= UInt<63>("h06c65646f6d00736c") rom[60] <= UInt<63>("h05f65636976656400") rom[61] <= UInt<63>("h06765720065707974") rom[62] <= UInt<63>("h0697461706d6f6300") rom[63] <= UInt<55>("h061736900656c62") rom[64] <= UInt<63>("h069746365746f7270") rom[65] <= UInt<15>("h06e6f") rom[66] <= UInt<1>("h00") node T_505 = bits(T_334.io.deq.bits.addr, 9, 3) node T_508 = cat(UInt<1>("h01"), T_334.io.deq.bits.size) node T_510 = bits(T_508, 1, 0) node T_511 = asSInt(T_508) node T_513 = geq(T_511, asSInt(UInt<1>("h00"))) node T_514 = bit(T_334.io.deq.bits.addr, 2) node T_515 = bits(rom[T_505], 63, 32) node T_516 = bits(rom[T_505], 31, 0) node T_517 = mux(T_514, T_515, T_516) node T_519 = and(UInt<1>("h00"), UInt<1>("h00")) node T_521 = mux(T_519, UInt<1>("h00"), T_517) node T_523 = eq(T_510, UInt<2>("h02")) node T_524 = or(T_523, T_519) node T_525 = bit(T_521, 31) node T_526 = and(T_513, T_525) node T_528 = subw(UInt<32>("h00"), T_526) node T_529 = bits(rom[T_505], 63, 32) node T_530 = mux(T_524, T_528, T_529) node T_531 = cat(T_530, T_521) node T_532 = bit(T_334.io.deq.bits.addr, 1) node T_533 = bits(T_531, 31, 16) node T_534 = bits(T_531, 15, 0) node T_535 = mux(T_532, T_533, T_534) node T_537 = and(UInt<1>("h00"), UInt<1>("h00")) node T_539 = mux(T_537, UInt<1>("h00"), T_535) node T_541 = eq(T_510, UInt<1>("h01")) node T_542 = or(T_541, T_537) node T_543 = bit(T_539, 15) node T_544 = and(T_513, T_543) node T_546 = subw(UInt<48>("h00"), T_544) node T_547 = bits(T_531, 63, 16) node T_548 = mux(T_542, T_546, T_547) node T_549 = cat(T_548, T_539) node T_550 = bit(T_334.io.deq.bits.addr, 0) node T_551 = bits(T_549, 15, 8) node T_552 = bits(T_549, 7, 0) node T_553 = mux(T_550, T_551, T_552) node T_555 = and(UInt<1>("h01"), UInt<1>("h00")) node T_557 = mux(T_555, UInt<1>("h00"), T_553) node T_559 = eq(T_510, UInt<1>("h00")) node T_560 = or(T_559, T_555) node T_561 = bit(T_557, 7) node T_562 = and(T_513, T_561) node T_564 = subw(UInt<56>("h00"), T_562) node T_565 = bits(T_549, 63, 8) node T_566 = mux(T_560, T_564, T_565) node rdata = cat(T_566, T_557) io.r <- T_334.io.deq wire T_576 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} T_576.user <= UInt<1>("h00") T_576.id <= UInt<1>("h00") T_576.last <= UInt<1>("h00") T_576.data <= UInt<1>("h00") T_576.resp <= UInt<1>("h00") T_576.id <= T_334.io.deq.bits.id T_576.data <= rdata T_576.last <= UInt<1>("h01") T_576.resp <= UInt<1>("h00") T_576.user <= UInt<1>("h00") io.r.bits <- T_576 module Queue_90 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>} io.count <= UInt<1>("h00") io.deq.bits <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : UInt<17>[1] reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_31 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_31) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_37 = and(io.enq.ready, io.enq.valid) node T_39 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_37, T_39) node T_41 = and(io.deq.ready, io.deq.valid) node T_43 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_41, T_43) when do_enq : infer mport T_45 = ram[UInt<1>("h00")], clk T_45 <= io.enq.bits skip when do_deq : skip node T_48 = neq(do_enq, do_deq) when T_48 : maybe_full <= do_enq skip node T_50 = eq(empty, UInt<1>("h00")) node T_52 = and(UInt<1>("h00"), io.enq.valid) node T_53 = or(T_50, T_52) io.deq.valid <= T_53 node T_55 = eq(full, UInt<1>("h00")) node T_57 = and(UInt<1>("h00"), io.deq.ready) node T_58 = or(T_55, T_57) io.enq.ready <= T_58 infer mport T_59 = ram[UInt<1>("h00")], clk node T_60 = mux(maybe_flow, io.enq.bits, T_59) io.deq.bits <= T_60 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_62 = and(maybe_full, ptr_match) node T_63 = cat(T_62, ptr_diff) io.count <= T_63 module SlowIO : input clk : Clock input reset : UInt<1> output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>} io.divisor <= UInt<1>("h00") io.clk_slow <= UInt<1>("h00") io.in_slow.ready <= UInt<1>("h00") io.in_fast.bits <= UInt<1>("h00") io.in_fast.valid <= UInt<1>("h00") io.out_slow.bits <= UInt<1>("h00") io.out_slow.valid <= UInt<1>("h00") io.out_fast.ready <= UInt<1>("h00") reg divisor : UInt, clk, reset, UInt<9>("h01ff") reg d_shadow : UInt, clk, reset, UInt<9>("h01ff") reg hold : UInt, clk, reset, UInt<7>("h07f") reg h_shadow : UInt, clk, reset, UInt<7>("h07f") when io.set_divisor.valid : node T_57 = bits(io.set_divisor.bits, 8, 0) d_shadow <= T_57 node T_58 = bits(io.set_divisor.bits, 24, 16) h_shadow <= T_58 skip node T_59 = shl(hold, 16) node T_60 = or(T_59, divisor) io.divisor <= T_60 reg count : UInt<9>, clk, UInt<1>("h00"), count reg myclock : UInt<1>, clk, UInt<1>("h00"), myclock node T_66 = addw(count, UInt<1>("h01")) count <= T_66 node T_67 = shr(divisor, 1) node rising = eq(count, T_67) node falling = eq(count, divisor) node T_70 = shr(divisor, 1) node T_71 = addw(T_70, hold) node held = eq(count, T_71) when falling : divisor <= d_shadow hold <= h_shadow count <= UInt<1>("h00") myclock <= UInt<1>("h00") skip when rising : myclock <= UInt<1>("h01") skip reg in_slow_rdy : UInt<1>, clk, reset, UInt<1>("h00") reg out_slow_val : UInt<1>, clk, reset, UInt<1>("h00") reg out_slow_bits : UInt<17>, clk, UInt<1>("h00"), out_slow_bits inst fromhost_q of Queue_90 fromhost_q.io.deq.ready <= UInt<1>("h00") fromhost_q.io.enq.bits <= UInt<1>("h00") fromhost_q.io.enq.valid <= UInt<1>("h00") fromhost_q.clk <= clk fromhost_q.reset <= reset node T_87 = and(io.in_slow.valid, in_slow_rdy) node T_88 = or(T_87, reset) node T_89 = and(rising, T_88) fromhost_q.io.enq.valid <= T_89 fromhost_q.io.enq.bits <= io.in_slow.bits io.in_fast <- fromhost_q.io.deq inst tohost_q of Queue_90 tohost_q.io.deq.ready <= UInt<1>("h00") tohost_q.io.enq.bits <= UInt<1>("h00") tohost_q.io.enq.valid <= UInt<1>("h00") tohost_q.clk <= clk tohost_q.reset <= reset tohost_q.io.enq <- io.out_fast node T_95 = and(rising, io.out_slow.ready) node T_96 = and(T_95, out_slow_val) tohost_q.io.deq.ready <= T_96 when held : in_slow_rdy <= fromhost_q.io.enq.ready out_slow_val <= tohost_q.io.deq.valid node T_97 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) out_slow_bits <= T_97 skip io.in_slow.ready <= in_slow_rdy io.out_slow.valid <= out_slow_val io.out_slow.bits <= out_slow_bits io.clk_slow <= myclock module Uncore : input clk : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}[1]} io.dma[0].resp.bits.status <= UInt<1>("h00") io.dma[0].resp.bits.client_xact_id <= UInt<1>("h00") io.dma[0].resp.valid <= UInt<1>("h00") io.dma[0].req.ready <= UInt<1>("h00") io.mmio.r.ready <= UInt<1>("h00") io.mmio.ar.bits.user <= UInt<1>("h00") io.mmio.ar.bits.id <= UInt<1>("h00") io.mmio.ar.bits.region <= UInt<1>("h00") io.mmio.ar.bits.qos <= UInt<1>("h00") io.mmio.ar.bits.prot <= UInt<1>("h00") io.mmio.ar.bits.cache <= UInt<1>("h00") io.mmio.ar.bits.lock <= UInt<1>("h00") io.mmio.ar.bits.burst <= UInt<1>("h00") io.mmio.ar.bits.size <= UInt<1>("h00") io.mmio.ar.bits.len <= UInt<1>("h00") io.mmio.ar.bits.addr <= UInt<1>("h00") io.mmio.ar.valid <= UInt<1>("h00") io.mmio.b.ready <= UInt<1>("h00") io.mmio.w.bits.user <= UInt<1>("h00") io.mmio.w.bits.strb <= UInt<1>("h00") io.mmio.w.bits.last <= UInt<1>("h00") io.mmio.w.bits.data <= UInt<1>("h00") io.mmio.w.valid <= UInt<1>("h00") io.mmio.aw.bits.user <= UInt<1>("h00") io.mmio.aw.bits.id <= UInt<1>("h00") io.mmio.aw.bits.region <= UInt<1>("h00") io.mmio.aw.bits.qos <= UInt<1>("h00") io.mmio.aw.bits.prot <= UInt<1>("h00") io.mmio.aw.bits.cache <= UInt<1>("h00") io.mmio.aw.bits.lock <= UInt<1>("h00") io.mmio.aw.bits.burst <= UInt<1>("h00") io.mmio.aw.bits.size <= UInt<1>("h00") io.mmio.aw.bits.len <= UInt<1>("h00") io.mmio.aw.bits.addr <= UInt<1>("h00") io.mmio.aw.valid <= UInt<1>("h00") io.mem_backup_ctrl.out_valid <= UInt<1>("h00") io.htif[0].csr.resp.ready <= UInt<1>("h00") io.htif[0].csr.req.bits.data <= UInt<1>("h00") io.htif[0].csr.req.bits.addr <= UInt<1>("h00") io.htif[0].csr.req.bits.rw <= UInt<1>("h00") io.htif[0].csr.req.valid <= UInt<1>("h00") io.htif[0].id <= UInt<1>("h00") io.htif[0].reset <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.data <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.g_type <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") io.tiles_uncached[0].grant.bits.addr_beat <= UInt<1>("h00") io.tiles_uncached[0].grant.valid <= UInt<1>("h00") io.tiles_uncached[0].acquire.ready <= UInt<1>("h00") io.tiles_cached[0].release.ready <= UInt<1>("h00") io.tiles_cached[0].probe.bits.p_type <= UInt<1>("h00") io.tiles_cached[0].probe.bits.addr_block <= UInt<1>("h00") io.tiles_cached[0].probe.valid <= UInt<1>("h00") io.tiles_cached[0].grant.bits.data <= UInt<1>("h00") io.tiles_cached[0].grant.bits.g_type <= UInt<1>("h00") io.tiles_cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") io.tiles_cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") io.tiles_cached[0].grant.bits.client_xact_id <= UInt<1>("h00") io.tiles_cached[0].grant.bits.addr_beat <= UInt<1>("h00") io.tiles_cached[0].grant.valid <= UInt<1>("h00") io.tiles_cached[0].acquire.ready <= UInt<1>("h00") io.mem[0].r.ready <= UInt<1>("h00") io.mem[0].ar.bits.user <= UInt<1>("h00") io.mem[0].ar.bits.id <= UInt<1>("h00") io.mem[0].ar.bits.region <= UInt<1>("h00") io.mem[0].ar.bits.qos <= UInt<1>("h00") io.mem[0].ar.bits.prot <= UInt<1>("h00") io.mem[0].ar.bits.cache <= UInt<1>("h00") io.mem[0].ar.bits.lock <= UInt<1>("h00") io.mem[0].ar.bits.burst <= UInt<1>("h00") io.mem[0].ar.bits.size <= UInt<1>("h00") io.mem[0].ar.bits.len <= UInt<1>("h00") io.mem[0].ar.bits.addr <= UInt<1>("h00") io.mem[0].ar.valid <= UInt<1>("h00") io.mem[0].b.ready <= UInt<1>("h00") io.mem[0].w.bits.user <= UInt<1>("h00") io.mem[0].w.bits.strb <= UInt<1>("h00") io.mem[0].w.bits.last <= UInt<1>("h00") io.mem[0].w.bits.data <= UInt<1>("h00") io.mem[0].w.valid <= UInt<1>("h00") io.mem[0].aw.bits.user <= UInt<1>("h00") io.mem[0].aw.bits.id <= UInt<1>("h00") io.mem[0].aw.bits.region <= UInt<1>("h00") io.mem[0].aw.bits.qos <= UInt<1>("h00") io.mem[0].aw.bits.prot <= UInt<1>("h00") io.mem[0].aw.bits.cache <= UInt<1>("h00") io.mem[0].aw.bits.lock <= UInt<1>("h00") io.mem[0].aw.bits.burst <= UInt<1>("h00") io.mem[0].aw.bits.size <= UInt<1>("h00") io.mem[0].aw.bits.len <= UInt<1>("h00") io.mem[0].aw.bits.addr <= UInt<1>("h00") io.mem[0].aw.valid <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.out.bits <= UInt<1>("h00") io.host.out.valid <= UInt<1>("h00") io.host.in.ready <= UInt<1>("h00") io.host.clk_edge <= UInt<1>("h00") io.host.clk <= UInt<1>("h00") inst htif of Htif htif.io.scr.resp.bits <= UInt<1>("h00") htif.io.scr.resp.valid <= UInt<1>("h00") htif.io.scr.req.ready <= UInt<1>("h00") htif.io.mem.grant.bits.data <= UInt<1>("h00") htif.io.mem.grant.bits.g_type <= UInt<1>("h00") htif.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") htif.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") htif.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") htif.io.mem.grant.bits.addr_beat <= UInt<1>("h00") htif.io.mem.grant.valid <= UInt<1>("h00") htif.io.mem.acquire.ready <= UInt<1>("h00") htif.io.cpu[0].debug_stats_csr <= UInt<1>("h00") htif.io.cpu[0].csr.resp.bits <= UInt<1>("h00") htif.io.cpu[0].csr.resp.valid <= UInt<1>("h00") htif.io.cpu[0].csr.req.ready <= UInt<1>("h00") htif.io.host.out.ready <= UInt<1>("h00") htif.io.host.in.bits <= UInt<1>("h00") htif.io.host.in.valid <= UInt<1>("h00") htif.clk <= clk htif.reset <= reset inst outmemsys of OuterMemorySystem outmemsys.io.dma.resp.ready <= UInt<1>("h00") outmemsys.io.dma.req.bits.size <= UInt<1>("h00") outmemsys.io.dma.req.bits.length <= UInt<1>("h00") outmemsys.io.dma.req.bits.dest <= UInt<1>("h00") outmemsys.io.dma.req.bits.source <= UInt<1>("h00") outmemsys.io.dma.req.bits.cmd <= UInt<1>("h00") outmemsys.io.dma.req.bits.client_xact_id <= UInt<1>("h00") outmemsys.io.dma.req.valid <= UInt<1>("h00") outmemsys.io.deviceTree.r.bits.user <= UInt<1>("h00") outmemsys.io.deviceTree.r.bits.id <= UInt<1>("h00") outmemsys.io.deviceTree.r.bits.last <= UInt<1>("h00") outmemsys.io.deviceTree.r.bits.data <= UInt<1>("h00") outmemsys.io.deviceTree.r.bits.resp <= UInt<1>("h00") outmemsys.io.deviceTree.r.valid <= UInt<1>("h00") outmemsys.io.deviceTree.ar.ready <= UInt<1>("h00") outmemsys.io.deviceTree.b.bits.user <= UInt<1>("h00") outmemsys.io.deviceTree.b.bits.id <= UInt<1>("h00") outmemsys.io.deviceTree.b.bits.resp <= UInt<1>("h00") outmemsys.io.deviceTree.b.valid <= UInt<1>("h00") outmemsys.io.deviceTree.w.ready <= UInt<1>("h00") outmemsys.io.deviceTree.aw.ready <= UInt<1>("h00") outmemsys.io.mmio.r.bits.user <= UInt<1>("h00") outmemsys.io.mmio.r.bits.id <= UInt<1>("h00") outmemsys.io.mmio.r.bits.last <= UInt<1>("h00") outmemsys.io.mmio.r.bits.data <= UInt<1>("h00") outmemsys.io.mmio.r.bits.resp <= UInt<1>("h00") outmemsys.io.mmio.r.valid <= UInt<1>("h00") outmemsys.io.mmio.ar.ready <= UInt<1>("h00") outmemsys.io.mmio.b.bits.user <= UInt<1>("h00") outmemsys.io.mmio.b.bits.id <= UInt<1>("h00") outmemsys.io.mmio.b.bits.resp <= UInt<1>("h00") outmemsys.io.mmio.b.valid <= UInt<1>("h00") outmemsys.io.mmio.w.ready <= UInt<1>("h00") outmemsys.io.mmio.aw.ready <= UInt<1>("h00") outmemsys.io.scr.resp.bits <= UInt<1>("h00") outmemsys.io.scr.resp.valid <= UInt<1>("h00") outmemsys.io.scr.req.ready <= UInt<1>("h00") outmemsys.io.csr[0].resp.bits <= UInt<1>("h00") outmemsys.io.csr[0].resp.valid <= UInt<1>("h00") outmemsys.io.csr[0].req.ready <= UInt<1>("h00") outmemsys.io.mem_backup_en <= UInt<1>("h00") outmemsys.io.mem_backup.resp.bits <= UInt<1>("h00") outmemsys.io.mem_backup.resp.valid <= UInt<1>("h00") outmemsys.io.mem_backup.req.ready <= UInt<1>("h00") outmemsys.io.mem[0].r.bits.user <= UInt<1>("h00") outmemsys.io.mem[0].r.bits.id <= UInt<1>("h00") outmemsys.io.mem[0].r.bits.last <= UInt<1>("h00") outmemsys.io.mem[0].r.bits.data <= UInt<1>("h00") outmemsys.io.mem[0].r.bits.resp <= UInt<1>("h00") outmemsys.io.mem[0].r.valid <= UInt<1>("h00") outmemsys.io.mem[0].ar.ready <= UInt<1>("h00") outmemsys.io.mem[0].b.bits.user <= UInt<1>("h00") outmemsys.io.mem[0].b.bits.id <= UInt<1>("h00") outmemsys.io.mem[0].b.bits.resp <= UInt<1>("h00") outmemsys.io.mem[0].b.valid <= UInt<1>("h00") outmemsys.io.mem[0].w.ready <= UInt<1>("h00") outmemsys.io.mem[0].aw.ready <= UInt<1>("h00") outmemsys.io.incoherent[0] <= UInt<1>("h00") outmemsys.io.htif_uncached.grant.ready <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.data <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.union <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.a_type <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.is_builtin_type <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.addr_beat <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.client_xact_id <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.bits.addr_block <= UInt<1>("h00") outmemsys.io.htif_uncached.acquire.valid <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].grant.ready <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.data <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.union <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.a_type <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.bits.addr_block <= UInt<1>("h00") outmemsys.io.tiles_uncached[0].acquire.valid <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.data <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.r_type <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.voluntary <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.client_xact_id <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.addr_block <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.bits.addr_beat <= UInt<1>("h00") outmemsys.io.tiles_cached[0].release.valid <= UInt<1>("h00") outmemsys.io.tiles_cached[0].probe.ready <= UInt<1>("h00") outmemsys.io.tiles_cached[0].grant.ready <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.data <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.union <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.a_type <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.addr_beat <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.bits.addr_block <= UInt<1>("h00") outmemsys.io.tiles_cached[0].acquire.valid <= UInt<1>("h00") outmemsys.clk <= clk outmemsys.reset <= reset outmemsys.io.incoherent[0] <= htif.io.cpu[0].reset outmemsys.io.htif_uncached <- htif.io.mem outmemsys.io.tiles_uncached <- io.tiles_uncached outmemsys.io.tiles_cached <- io.tiles_cached io.htif[0].reset <= htif.io.cpu[0].reset io.htif[0].id <= htif.io.cpu[0].id htif.io.cpu[0].debug_stats_csr <= io.htif[0].debug_stats_csr inst T_8473 of SmiArbiter T_8473.io.out.resp.bits <= UInt<1>("h00") T_8473.io.out.resp.valid <= UInt<1>("h00") T_8473.io.out.req.ready <= UInt<1>("h00") T_8473.io.in[0].resp.ready <= UInt<1>("h00") T_8473.io.in[0].req.bits.data <= UInt<1>("h00") T_8473.io.in[0].req.bits.addr <= UInt<1>("h00") T_8473.io.in[0].req.bits.rw <= UInt<1>("h00") T_8473.io.in[0].req.valid <= UInt<1>("h00") T_8473.io.in[1].resp.ready <= UInt<1>("h00") T_8473.io.in[1].req.bits.data <= UInt<1>("h00") T_8473.io.in[1].req.bits.addr <= UInt<1>("h00") T_8473.io.in[1].req.bits.rw <= UInt<1>("h00") T_8473.io.in[1].req.valid <= UInt<1>("h00") T_8473.clk <= clk T_8473.reset <= reset T_8473.io.in[0] <- htif.io.cpu[0].csr T_8473.io.in[1] <- outmemsys.io.csr[0] io.htif[0].csr <- T_8473.io.out inst scrFile of SCRFile scrFile.io.scr.rdata[0] <= UInt<1>("h00") scrFile.io.scr.rdata[1] <= UInt<1>("h00") scrFile.io.scr.rdata[2] <= UInt<1>("h00") scrFile.io.scr.rdata[3] <= UInt<1>("h00") scrFile.io.scr.rdata[4] <= UInt<1>("h00") scrFile.io.scr.rdata[5] <= UInt<1>("h00") scrFile.io.scr.rdata[6] <= UInt<1>("h00") scrFile.io.scr.rdata[7] <= UInt<1>("h00") scrFile.io.scr.rdata[8] <= UInt<1>("h00") scrFile.io.scr.rdata[9] <= UInt<1>("h00") scrFile.io.scr.rdata[10] <= UInt<1>("h00") scrFile.io.scr.rdata[11] <= UInt<1>("h00") scrFile.io.scr.rdata[12] <= UInt<1>("h00") scrFile.io.scr.rdata[13] <= UInt<1>("h00") scrFile.io.scr.rdata[14] <= UInt<1>("h00") scrFile.io.scr.rdata[15] <= UInt<1>("h00") scrFile.io.scr.rdata[16] <= UInt<1>("h00") scrFile.io.scr.rdata[17] <= UInt<1>("h00") scrFile.io.scr.rdata[18] <= UInt<1>("h00") scrFile.io.scr.rdata[19] <= UInt<1>("h00") scrFile.io.scr.rdata[20] <= UInt<1>("h00") scrFile.io.scr.rdata[21] <= UInt<1>("h00") scrFile.io.scr.rdata[22] <= UInt<1>("h00") scrFile.io.scr.rdata[23] <= UInt<1>("h00") scrFile.io.scr.rdata[24] <= UInt<1>("h00") scrFile.io.scr.rdata[25] <= UInt<1>("h00") scrFile.io.scr.rdata[26] <= UInt<1>("h00") scrFile.io.scr.rdata[27] <= UInt<1>("h00") scrFile.io.scr.rdata[28] <= UInt<1>("h00") scrFile.io.scr.rdata[29] <= UInt<1>("h00") scrFile.io.scr.rdata[30] <= UInt<1>("h00") scrFile.io.scr.rdata[31] <= UInt<1>("h00") scrFile.io.scr.rdata[32] <= UInt<1>("h00") scrFile.io.scr.rdata[33] <= UInt<1>("h00") scrFile.io.scr.rdata[34] <= UInt<1>("h00") scrFile.io.scr.rdata[35] <= UInt<1>("h00") scrFile.io.scr.rdata[36] <= UInt<1>("h00") scrFile.io.scr.rdata[37] <= UInt<1>("h00") scrFile.io.scr.rdata[38] <= UInt<1>("h00") scrFile.io.scr.rdata[39] <= UInt<1>("h00") scrFile.io.scr.rdata[40] <= UInt<1>("h00") scrFile.io.scr.rdata[41] <= UInt<1>("h00") scrFile.io.scr.rdata[42] <= UInt<1>("h00") scrFile.io.scr.rdata[43] <= UInt<1>("h00") scrFile.io.scr.rdata[44] <= UInt<1>("h00") scrFile.io.scr.rdata[45] <= UInt<1>("h00") scrFile.io.scr.rdata[46] <= UInt<1>("h00") scrFile.io.scr.rdata[47] <= UInt<1>("h00") scrFile.io.scr.rdata[48] <= UInt<1>("h00") scrFile.io.scr.rdata[49] <= UInt<1>("h00") scrFile.io.scr.rdata[50] <= UInt<1>("h00") scrFile.io.scr.rdata[51] <= UInt<1>("h00") scrFile.io.scr.rdata[52] <= UInt<1>("h00") scrFile.io.scr.rdata[53] <= UInt<1>("h00") scrFile.io.scr.rdata[54] <= UInt<1>("h00") scrFile.io.scr.rdata[55] <= UInt<1>("h00") scrFile.io.scr.rdata[56] <= UInt<1>("h00") scrFile.io.scr.rdata[57] <= UInt<1>("h00") scrFile.io.scr.rdata[58] <= UInt<1>("h00") scrFile.io.scr.rdata[59] <= UInt<1>("h00") scrFile.io.scr.rdata[60] <= UInt<1>("h00") scrFile.io.scr.rdata[61] <= UInt<1>("h00") scrFile.io.scr.rdata[62] <= UInt<1>("h00") scrFile.io.scr.rdata[63] <= UInt<1>("h00") scrFile.io.smi.resp.ready <= UInt<1>("h00") scrFile.io.smi.req.bits.data <= UInt<1>("h00") scrFile.io.smi.req.bits.addr <= UInt<1>("h00") scrFile.io.smi.req.bits.rw <= UInt<1>("h00") scrFile.io.smi.req.valid <= UInt<1>("h00") scrFile.clk <= clk scrFile.reset <= reset inst scrArb of SmiArbiter_81 scrArb.io.out.resp.bits <= UInt<1>("h00") scrArb.io.out.resp.valid <= UInt<1>("h00") scrArb.io.out.req.ready <= UInt<1>("h00") scrArb.io.in[0].resp.ready <= UInt<1>("h00") scrArb.io.in[0].req.bits.data <= UInt<1>("h00") scrArb.io.in[0].req.bits.addr <= UInt<1>("h00") scrArb.io.in[0].req.bits.rw <= UInt<1>("h00") scrArb.io.in[0].req.valid <= UInt<1>("h00") scrArb.io.in[1].resp.ready <= UInt<1>("h00") scrArb.io.in[1].req.bits.data <= UInt<1>("h00") scrArb.io.in[1].req.bits.addr <= UInt<1>("h00") scrArb.io.in[1].req.bits.rw <= UInt<1>("h00") scrArb.io.in[1].req.valid <= UInt<1>("h00") scrArb.clk <= clk scrArb.reset <= reset scrArb.io.in[0] <- htif.io.scr scrArb.io.in[1] <- outmemsys.io.scr scrFile.io.smi <- scrArb.io.out inst deviceTree of NastiROM deviceTree.io.r.ready <= UInt<1>("h00") deviceTree.io.ar.bits.user <= UInt<1>("h00") deviceTree.io.ar.bits.id <= UInt<1>("h00") deviceTree.io.ar.bits.region <= UInt<1>("h00") deviceTree.io.ar.bits.qos <= UInt<1>("h00") deviceTree.io.ar.bits.prot <= UInt<1>("h00") deviceTree.io.ar.bits.cache <= UInt<1>("h00") deviceTree.io.ar.bits.lock <= UInt<1>("h00") deviceTree.io.ar.bits.burst <= UInt<1>("h00") deviceTree.io.ar.bits.size <= UInt<1>("h00") deviceTree.io.ar.bits.len <= UInt<1>("h00") deviceTree.io.ar.bits.addr <= UInt<1>("h00") deviceTree.io.ar.valid <= UInt<1>("h00") deviceTree.io.b.ready <= UInt<1>("h00") deviceTree.io.w.bits.user <= UInt<1>("h00") deviceTree.io.w.bits.strb <= UInt<1>("h00") deviceTree.io.w.bits.last <= UInt<1>("h00") deviceTree.io.w.bits.data <= UInt<1>("h00") deviceTree.io.w.valid <= UInt<1>("h00") deviceTree.io.aw.bits.user <= UInt<1>("h00") deviceTree.io.aw.bits.id <= UInt<1>("h00") deviceTree.io.aw.bits.region <= UInt<1>("h00") deviceTree.io.aw.bits.qos <= UInt<1>("h00") deviceTree.io.aw.bits.prot <= UInt<1>("h00") deviceTree.io.aw.bits.cache <= UInt<1>("h00") deviceTree.io.aw.bits.lock <= UInt<1>("h00") deviceTree.io.aw.bits.burst <= UInt<1>("h00") deviceTree.io.aw.bits.size <= UInt<1>("h00") deviceTree.io.aw.bits.len <= UInt<1>("h00") deviceTree.io.aw.bits.addr <= UInt<1>("h00") deviceTree.io.aw.valid <= UInt<1>("h00") deviceTree.clk <= clk deviceTree.reset <= reset deviceTree.io <- outmemsys.io.deviceTree io.host.debug_stats_csr <= htif.io.host.debug_stats_csr io.mem <- outmemsys.io.mem io.mmio <- outmemsys.io.mmio outmemsys.io.mem_backup_en <= io.mem_backup_ctrl.en inst T_8603 of SlowIO T_8603.io.set_divisor.bits <= UInt<1>("h00") T_8603.io.set_divisor.valid <= UInt<1>("h00") T_8603.io.in_slow.bits <= UInt<1>("h00") T_8603.io.in_slow.valid <= UInt<1>("h00") T_8603.io.in_fast.ready <= UInt<1>("h00") T_8603.io.out_slow.ready <= UInt<1>("h00") T_8603.io.out_fast.bits <= UInt<1>("h00") T_8603.io.out_fast.valid <= UInt<1>("h00") T_8603.clk <= clk T_8603.reset <= reset node T_8613 = eq(scrFile.io.scr.waddr, UInt<6>("h03f")) node T_8614 = and(scrFile.io.scr.wen, T_8613) T_8603.io.set_divisor.valid <= T_8614 T_8603.io.set_divisor.bits <= scrFile.io.scr.wdata scrFile.io.scr.rdata[63] <= T_8603.io.divisor node T_8615 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) T_8603.io.out_fast.valid <= T_8615 node T_8616 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) node T_8617 = cat(htif.io.host.out.valid, T_8616) T_8603.io.out_fast.bits <= T_8617 htif.io.host.out.ready <= T_8603.io.out_fast.ready node T_8619 = eq(htif.io.host.out.valid, UInt<1>("h00")) node T_8620 = and(T_8603.io.out_fast.ready, T_8619) outmemsys.io.mem_backup.req.ready <= T_8620 node T_8621 = bit(T_8603.io.out_slow.bits, 16) node T_8622 = and(T_8603.io.out_slow.valid, T_8621) io.host.out.valid <= T_8622 io.host.out.bits <= T_8603.io.out_slow.bits node T_8623 = bit(T_8603.io.out_slow.bits, 16) node T_8625 = eq(T_8623, UInt<1>("h00")) node T_8626 = and(T_8603.io.out_slow.valid, T_8625) io.mem_backup_ctrl.out_valid <= T_8626 node T_8627 = bit(T_8603.io.out_slow.bits, 16) node T_8628 = mux(T_8627, io.host.out.ready, io.mem_backup_ctrl.out_ready) T_8603.io.out_slow.ready <= T_8628 node T_8629 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) node T_8630 = or(T_8629, io.host.in.valid) T_8603.io.in_slow.valid <= T_8630 node T_8631 = cat(T_8629, io.host.in.bits) T_8603.io.in_slow.bits <= T_8631 io.host.in.ready <= T_8603.io.in_slow.ready node T_8632 = bit(T_8603.io.in_fast.bits, 16) node T_8633 = and(T_8603.io.in_fast.valid, T_8632) outmemsys.io.mem_backup.resp.valid <= T_8633 outmemsys.io.mem_backup.resp.bits <= T_8603.io.in_fast.bits node T_8634 = bit(T_8603.io.in_fast.bits, 16) node T_8636 = eq(T_8634, UInt<1>("h00")) node T_8637 = and(T_8603.io.in_fast.valid, T_8636) htif.io.host.in.valid <= T_8637 htif.io.host.in.bits <= T_8603.io.in_fast.bits node T_8638 = bit(T_8603.io.in_fast.bits, 16) node T_8640 = mux(T_8638, UInt<1>("h01"), htif.io.host.in.ready) T_8603.io.in_fast.ready <= T_8640 io.host.clk <= T_8603.io.clk_slow reg T_8641 : UInt<1>, clk, UInt<1>("h00"), T_8641 T_8641 <= io.host.clk node T_8643 = eq(T_8641, UInt<1>("h00")) node T_8644 = and(io.host.clk, T_8643) reg T_8645 : UInt<1>, clk, UInt<1>("h00"), T_8645 T_8645 <= T_8644 io.host.clk_edge <= T_8645 module CSRFile : input clk : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}, interrupt : UInt<1>, interrupt_cause : UInt<64>} io.interrupt_cause <= UInt<1>("h00") io.interrupt <= UInt<1>("h00") io.rocc.dma.resp.bits.status <= UInt<1>("h00") io.rocc.dma.resp.bits.client_xact_id <= UInt<1>("h00") io.rocc.dma.resp.valid <= UInt<1>("h00") io.rocc.dma.req.ready <= UInt<1>("h00") io.rocc.exception <= UInt<1>("h00") io.rocc.fpu_resp.bits.exc <= UInt<1>("h00") io.rocc.fpu_resp.bits.data <= UInt<1>("h00") io.rocc.fpu_resp.valid <= UInt<1>("h00") io.rocc.fpu_req.ready <= UInt<1>("h00") io.rocc.pptw.invalidate <= UInt<1>("h00") io.rocc.pptw.status.ie <= UInt<1>("h00") io.rocc.pptw.status.prv <= UInt<1>("h00") io.rocc.pptw.status.ie1 <= UInt<1>("h00") io.rocc.pptw.status.prv1 <= UInt<1>("h00") io.rocc.pptw.status.ie2 <= UInt<1>("h00") io.rocc.pptw.status.prv2 <= UInt<1>("h00") io.rocc.pptw.status.ie3 <= UInt<1>("h00") io.rocc.pptw.status.prv3 <= UInt<1>("h00") io.rocc.pptw.status.fs <= UInt<1>("h00") io.rocc.pptw.status.xs <= UInt<1>("h00") io.rocc.pptw.status.mprv <= UInt<1>("h00") io.rocc.pptw.status.vm <= UInt<1>("h00") io.rocc.pptw.status.zero1 <= UInt<1>("h00") io.rocc.pptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.pptw.status.zero2 <= UInt<1>("h00") io.rocc.pptw.status.sd <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.pptw.resp.bits.error <= UInt<1>("h00") io.rocc.pptw.resp.valid <= UInt<1>("h00") io.rocc.pptw.req.ready <= UInt<1>("h00") io.rocc.dptw.invalidate <= UInt<1>("h00") io.rocc.dptw.status.ie <= UInt<1>("h00") io.rocc.dptw.status.prv <= UInt<1>("h00") io.rocc.dptw.status.ie1 <= UInt<1>("h00") io.rocc.dptw.status.prv1 <= UInt<1>("h00") io.rocc.dptw.status.ie2 <= UInt<1>("h00") io.rocc.dptw.status.prv2 <= UInt<1>("h00") io.rocc.dptw.status.ie3 <= UInt<1>("h00") io.rocc.dptw.status.prv3 <= UInt<1>("h00") io.rocc.dptw.status.fs <= UInt<1>("h00") io.rocc.dptw.status.xs <= UInt<1>("h00") io.rocc.dptw.status.mprv <= UInt<1>("h00") io.rocc.dptw.status.vm <= UInt<1>("h00") io.rocc.dptw.status.zero1 <= UInt<1>("h00") io.rocc.dptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.dptw.status.zero2 <= UInt<1>("h00") io.rocc.dptw.status.sd <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.dptw.resp.bits.error <= UInt<1>("h00") io.rocc.dptw.resp.valid <= UInt<1>("h00") io.rocc.dptw.req.ready <= UInt<1>("h00") io.rocc.iptw.invalidate <= UInt<1>("h00") io.rocc.iptw.status.ie <= UInt<1>("h00") io.rocc.iptw.status.prv <= UInt<1>("h00") io.rocc.iptw.status.ie1 <= UInt<1>("h00") io.rocc.iptw.status.prv1 <= UInt<1>("h00") io.rocc.iptw.status.ie2 <= UInt<1>("h00") io.rocc.iptw.status.prv2 <= UInt<1>("h00") io.rocc.iptw.status.ie3 <= UInt<1>("h00") io.rocc.iptw.status.prv3 <= UInt<1>("h00") io.rocc.iptw.status.fs <= UInt<1>("h00") io.rocc.iptw.status.xs <= UInt<1>("h00") io.rocc.iptw.status.mprv <= UInt<1>("h00") io.rocc.iptw.status.vm <= UInt<1>("h00") io.rocc.iptw.status.zero1 <= UInt<1>("h00") io.rocc.iptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.iptw.status.zero2 <= UInt<1>("h00") io.rocc.iptw.status.sd <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.iptw.resp.bits.error <= UInt<1>("h00") io.rocc.iptw.resp.valid <= UInt<1>("h00") io.rocc.iptw.req.ready <= UInt<1>("h00") io.rocc.autl.grant.bits.data <= UInt<1>("h00") io.rocc.autl.grant.bits.g_type <= UInt<1>("h00") io.rocc.autl.grant.bits.is_builtin_type <= UInt<1>("h00") io.rocc.autl.grant.bits.manager_xact_id <= UInt<1>("h00") io.rocc.autl.grant.bits.client_xact_id <= UInt<1>("h00") io.rocc.autl.grant.bits.addr_beat <= UInt<1>("h00") io.rocc.autl.grant.valid <= UInt<1>("h00") io.rocc.autl.acquire.ready <= UInt<1>("h00") io.rocc.s <= UInt<1>("h00") io.rocc.mem.ordered <= UInt<1>("h00") io.rocc.mem.xcpt.pf.st <= UInt<1>("h00") io.rocc.mem.xcpt.pf.ld <= UInt<1>("h00") io.rocc.mem.xcpt.ma.st <= UInt<1>("h00") io.rocc.mem.xcpt.ma.ld <= UInt<1>("h00") io.rocc.mem.replay_next.bits <= UInt<1>("h00") io.rocc.mem.replay_next.valid <= UInt<1>("h00") io.rocc.mem.resp.bits.store_data <= UInt<1>("h00") io.rocc.mem.resp.bits.data_word_bypass <= UInt<1>("h00") io.rocc.mem.resp.bits.has_data <= UInt<1>("h00") io.rocc.mem.resp.bits.replay <= UInt<1>("h00") io.rocc.mem.resp.bits.nack <= UInt<1>("h00") io.rocc.mem.resp.bits.data <= UInt<1>("h00") io.rocc.mem.resp.bits.typ <= UInt<1>("h00") io.rocc.mem.resp.bits.cmd <= UInt<1>("h00") io.rocc.mem.resp.bits.tag <= UInt<1>("h00") io.rocc.mem.resp.bits.addr <= UInt<1>("h00") io.rocc.mem.resp.valid <= UInt<1>("h00") io.rocc.mem.req.ready <= UInt<1>("h00") io.rocc.resp.ready <= UInt<1>("h00") io.rocc.cmd.bits.rs2 <= UInt<1>("h00") io.rocc.cmd.bits.rs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.opcode <= UInt<1>("h00") io.rocc.cmd.bits.inst.rd <= UInt<1>("h00") io.rocc.cmd.bits.inst.xs2 <= UInt<1>("h00") io.rocc.cmd.bits.inst.xs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.xd <= UInt<1>("h00") io.rocc.cmd.bits.inst.rs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.rs2 <= UInt<1>("h00") io.rocc.cmd.bits.inst.funct <= UInt<1>("h00") io.rocc.cmd.valid <= UInt<1>("h00") io.fcsr_rm <= UInt<1>("h00") io.time <= UInt<1>("h00") io.fatc <= UInt<1>("h00") io.evec <= UInt<1>("h00") io.ptbr <= UInt<1>("h00") io.status.ie <= UInt<1>("h00") io.status.prv <= UInt<1>("h00") io.status.ie1 <= UInt<1>("h00") io.status.prv1 <= UInt<1>("h00") io.status.ie2 <= UInt<1>("h00") io.status.prv2 <= UInt<1>("h00") io.status.ie3 <= UInt<1>("h00") io.status.prv3 <= UInt<1>("h00") io.status.fs <= UInt<1>("h00") io.status.xs <= UInt<1>("h00") io.status.mprv <= UInt<1>("h00") io.status.vm <= UInt<1>("h00") io.status.zero1 <= UInt<1>("h00") io.status.sd_rv32 <= UInt<1>("h00") io.status.zero2 <= UInt<1>("h00") io.status.sd <= UInt<1>("h00") io.eret <= UInt<1>("h00") io.csr_xcpt <= UInt<1>("h00") io.csr_stall <= UInt<1>("h00") io.rw.rdata <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.csr.resp.bits <= UInt<1>("h00") io.host.csr.resp.valid <= UInt<1>("h00") io.host.csr.req.ready <= UInt<1>("h00") reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk, UInt<1>("h00"), reg_mstatus wire T_4480 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_4480.usip <= UInt<1>("h00") T_4480.ssip <= UInt<1>("h00") T_4480.hsip <= UInt<1>("h00") T_4480.msip <= UInt<1>("h00") T_4480.utip <= UInt<1>("h00") T_4480.stip <= UInt<1>("h00") T_4480.htip <= UInt<1>("h00") T_4480.mtip <= UInt<1>("h00") T_4480.usip <= UInt<1>("h00") T_4480.ssip <= UInt<1>("h00") T_4480.hsip <= UInt<1>("h00") T_4480.msip <= UInt<1>("h00") T_4480.utip <= UInt<1>("h00") T_4480.stip <= UInt<1>("h00") T_4480.htip <= UInt<1>("h00") T_4480.mtip <= UInt<1>("h00") reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk, reset, T_4480 wire T_4533 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_4533.usip <= UInt<1>("h00") T_4533.ssip <= UInt<1>("h00") T_4533.hsip <= UInt<1>("h00") T_4533.msip <= UInt<1>("h00") T_4533.utip <= UInt<1>("h00") T_4533.stip <= UInt<1>("h00") T_4533.htip <= UInt<1>("h00") T_4533.mtip <= UInt<1>("h00") T_4533.usip <= UInt<1>("h00") T_4533.ssip <= UInt<1>("h00") T_4533.hsip <= UInt<1>("h00") T_4533.msip <= UInt<1>("h00") T_4533.utip <= UInt<1>("h00") T_4533.stip <= UInt<1>("h00") T_4533.htip <= UInt<1>("h00") T_4533.mtip <= UInt<1>("h00") reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk, reset, T_4533 reg reg_mepc : UInt<40>, clk, UInt<1>("h00"), reg_mepc reg reg_mcause : UInt<64>, clk, UInt<1>("h00"), reg_mcause reg reg_mbadaddr : UInt<40>, clk, UInt<1>("h00"), reg_mbadaddr reg reg_mscratch : UInt<64>, clk, UInt<1>("h00"), reg_mscratch reg reg_sepc : UInt<40>, clk, UInt<1>("h00"), reg_sepc reg reg_scause : UInt<64>, clk, UInt<1>("h00"), reg_scause reg reg_sbadaddr : UInt<40>, clk, UInt<1>("h00"), reg_sbadaddr reg reg_sscratch : UInt<64>, clk, UInt<1>("h00"), reg_sscratch reg reg_stvec : UInt<39>, clk, UInt<1>("h00"), reg_stvec reg reg_mtimecmp : UInt<64>, clk, UInt<1>("h00"), reg_mtimecmp reg reg_sptbr : UInt<32>, clk, UInt<1>("h00"), reg_sptbr reg reg_wfi : UInt<1>, clk, reset, UInt<1>("h00") reg reg_tohost : UInt<64>, clk, reset, UInt<64>("h00") reg reg_fromhost : UInt<64>, clk, reset, UInt<64>("h00") reg reg_stats : UInt<1>, clk, reset, UInt<1>("h00") reg reg_time : UInt<64>, clk, UInt<1>("h00"), reg_time reg T_4600 : UInt<6>, clk, reset, UInt<6>("h00") node T_4602 = neq(io.retire, UInt<1>("h00")) node T_4604 = addw(T_4600, UInt<7>("h01")) when T_4602 : node T_4605 = bits(T_4604, 5, 0) T_4600 <= T_4605 skip reg T_4607 : UInt<58>, clk, reset, UInt<58>("h00") node T_4608 = bit(T_4604, 6) node T_4609 = and(T_4602, T_4608) when T_4609 : node T_4611 = addw(T_4607, UInt<1>("h01")) T_4607 <= T_4611 skip node T_4612 = cat(T_4607, T_4600) reg T_4615 : UInt<6>, clk, reset, UInt<6>("h00") node T_4617 = neq(UInt<1>("h01"), UInt<1>("h00")) node T_4619 = addw(T_4615, UInt<7>("h01")) when T_4617 : node T_4620 = bits(T_4619, 5, 0) T_4615 <= T_4620 skip reg T_4622 : UInt<58>, clk, reset, UInt<58>("h00") node T_4623 = bit(T_4619, 6) node T_4624 = and(T_4617, T_4623) when T_4624 : node T_4626 = addw(T_4622, UInt<1>("h01")) T_4622 <= T_4626 skip node T_4627 = cat(T_4622, T_4615) reg T_4629 : UInt<6>, clk, reset, UInt<6>("h00") node T_4631 = neq(io.uarch_counters[0], UInt<1>("h00")) node T_4633 = addw(T_4629, UInt<7>("h01")) when T_4631 : node T_4634 = bits(T_4633, 5, 0) T_4629 <= T_4634 skip reg T_4636 : UInt<58>, clk, reset, UInt<58>("h00") node T_4637 = bit(T_4633, 6) node T_4638 = and(T_4631, T_4637) when T_4638 : node T_4640 = addw(T_4636, UInt<1>("h01")) T_4636 <= T_4640 skip node T_4641 = cat(T_4636, T_4629) reg T_4643 : UInt<6>, clk, reset, UInt<6>("h00") node T_4645 = neq(io.uarch_counters[1], UInt<1>("h00")) node T_4647 = addw(T_4643, UInt<7>("h01")) when T_4645 : node T_4648 = bits(T_4647, 5, 0) T_4643 <= T_4648 skip reg T_4650 : UInt<58>, clk, reset, UInt<58>("h00") node T_4651 = bit(T_4647, 6) node T_4652 = and(T_4645, T_4651) when T_4652 : node T_4654 = addw(T_4650, UInt<1>("h01")) T_4650 <= T_4654 skip node T_4655 = cat(T_4650, T_4643) reg T_4657 : UInt<6>, clk, reset, UInt<6>("h00") node T_4659 = neq(io.uarch_counters[2], UInt<1>("h00")) node T_4661 = addw(T_4657, UInt<7>("h01")) when T_4659 : node T_4662 = bits(T_4661, 5, 0) T_4657 <= T_4662 skip reg T_4664 : UInt<58>, clk, reset, UInt<58>("h00") node T_4665 = bit(T_4661, 6) node T_4666 = and(T_4659, T_4665) when T_4666 : node T_4668 = addw(T_4664, UInt<1>("h01")) T_4664 <= T_4668 skip node T_4669 = cat(T_4664, T_4657) reg T_4671 : UInt<6>, clk, reset, UInt<6>("h00") node T_4673 = neq(io.uarch_counters[3], UInt<1>("h00")) node T_4675 = addw(T_4671, UInt<7>("h01")) when T_4673 : node T_4676 = bits(T_4675, 5, 0) T_4671 <= T_4676 skip reg T_4678 : UInt<58>, clk, reset, UInt<58>("h00") node T_4679 = bit(T_4675, 6) node T_4680 = and(T_4673, T_4679) when T_4680 : node T_4682 = addw(T_4678, UInt<1>("h01")) T_4678 <= T_4682 skip node T_4683 = cat(T_4678, T_4671) reg T_4685 : UInt<6>, clk, reset, UInt<6>("h00") node T_4687 = neq(io.uarch_counters[4], UInt<1>("h00")) node T_4689 = addw(T_4685, UInt<7>("h01")) when T_4687 : node T_4690 = bits(T_4689, 5, 0) T_4685 <= T_4690 skip reg T_4692 : UInt<58>, clk, reset, UInt<58>("h00") node T_4693 = bit(T_4689, 6) node T_4694 = and(T_4687, T_4693) when T_4694 : node T_4696 = addw(T_4692, UInt<1>("h01")) T_4692 <= T_4696 skip node T_4697 = cat(T_4692, T_4685) reg T_4699 : UInt<6>, clk, reset, UInt<6>("h00") node T_4701 = neq(io.uarch_counters[5], UInt<1>("h00")) node T_4703 = addw(T_4699, UInt<7>("h01")) when T_4701 : node T_4704 = bits(T_4703, 5, 0) T_4699 <= T_4704 skip reg T_4706 : UInt<58>, clk, reset, UInt<58>("h00") node T_4707 = bit(T_4703, 6) node T_4708 = and(T_4701, T_4707) when T_4708 : node T_4710 = addw(T_4706, UInt<1>("h01")) T_4706 <= T_4710 skip node T_4711 = cat(T_4706, T_4699) reg T_4713 : UInt<6>, clk, reset, UInt<6>("h00") node T_4715 = neq(io.uarch_counters[6], UInt<1>("h00")) node T_4717 = addw(T_4713, UInt<7>("h01")) when T_4715 : node T_4718 = bits(T_4717, 5, 0) T_4713 <= T_4718 skip reg T_4720 : UInt<58>, clk, reset, UInt<58>("h00") node T_4721 = bit(T_4717, 6) node T_4722 = and(T_4715, T_4721) when T_4722 : node T_4724 = addw(T_4720, UInt<1>("h01")) T_4720 <= T_4724 skip node T_4725 = cat(T_4720, T_4713) reg T_4727 : UInt<6>, clk, reset, UInt<6>("h00") node T_4729 = neq(io.uarch_counters[7], UInt<1>("h00")) node T_4731 = addw(T_4727, UInt<7>("h01")) when T_4729 : node T_4732 = bits(T_4731, 5, 0) T_4727 <= T_4732 skip reg T_4734 : UInt<58>, clk, reset, UInt<58>("h00") node T_4735 = bit(T_4731, 6) node T_4736 = and(T_4729, T_4735) when T_4736 : node T_4738 = addw(T_4734, UInt<1>("h01")) T_4734 <= T_4738 skip node T_4739 = cat(T_4734, T_4727) reg T_4741 : UInt<6>, clk, reset, UInt<6>("h00") node T_4743 = neq(io.uarch_counters[8], UInt<1>("h00")) node T_4745 = addw(T_4741, UInt<7>("h01")) when T_4743 : node T_4746 = bits(T_4745, 5, 0) T_4741 <= T_4746 skip reg T_4748 : UInt<58>, clk, reset, UInt<58>("h00") node T_4749 = bit(T_4745, 6) node T_4750 = and(T_4743, T_4749) when T_4750 : node T_4752 = addw(T_4748, UInt<1>("h01")) T_4748 <= T_4752 skip node T_4753 = cat(T_4748, T_4741) reg T_4755 : UInt<6>, clk, reset, UInt<6>("h00") node T_4757 = neq(io.uarch_counters[9], UInt<1>("h00")) node T_4759 = addw(T_4755, UInt<7>("h01")) when T_4757 : node T_4760 = bits(T_4759, 5, 0) T_4755 <= T_4760 skip reg T_4762 : UInt<58>, clk, reset, UInt<58>("h00") node T_4763 = bit(T_4759, 6) node T_4764 = and(T_4757, T_4763) when T_4764 : node T_4766 = addw(T_4762, UInt<1>("h01")) T_4762 <= T_4766 skip node T_4767 = cat(T_4762, T_4755) reg T_4769 : UInt<6>, clk, reset, UInt<6>("h00") node T_4771 = neq(io.uarch_counters[10], UInt<1>("h00")) node T_4773 = addw(T_4769, UInt<7>("h01")) when T_4771 : node T_4774 = bits(T_4773, 5, 0) T_4769 <= T_4774 skip reg T_4776 : UInt<58>, clk, reset, UInt<58>("h00") node T_4777 = bit(T_4773, 6) node T_4778 = and(T_4771, T_4777) when T_4778 : node T_4780 = addw(T_4776, UInt<1>("h01")) T_4776 <= T_4780 skip node T_4781 = cat(T_4776, T_4769) reg T_4783 : UInt<6>, clk, reset, UInt<6>("h00") node T_4785 = neq(io.uarch_counters[11], UInt<1>("h00")) node T_4787 = addw(T_4783, UInt<7>("h01")) when T_4785 : node T_4788 = bits(T_4787, 5, 0) T_4783 <= T_4788 skip reg T_4790 : UInt<58>, clk, reset, UInt<58>("h00") node T_4791 = bit(T_4787, 6) node T_4792 = and(T_4785, T_4791) when T_4792 : node T_4794 = addw(T_4790, UInt<1>("h01")) T_4790 <= T_4794 skip node T_4795 = cat(T_4790, T_4783) reg T_4797 : UInt<6>, clk, reset, UInt<6>("h00") node T_4799 = neq(io.uarch_counters[12], UInt<1>("h00")) node T_4801 = addw(T_4797, UInt<7>("h01")) when T_4799 : node T_4802 = bits(T_4801, 5, 0) T_4797 <= T_4802 skip reg T_4804 : UInt<58>, clk, reset, UInt<58>("h00") node T_4805 = bit(T_4801, 6) node T_4806 = and(T_4799, T_4805) when T_4806 : node T_4808 = addw(T_4804, UInt<1>("h01")) T_4804 <= T_4808 skip node T_4809 = cat(T_4804, T_4797) reg T_4811 : UInt<6>, clk, reset, UInt<6>("h00") node T_4813 = neq(io.uarch_counters[13], UInt<1>("h00")) node T_4815 = addw(T_4811, UInt<7>("h01")) when T_4813 : node T_4816 = bits(T_4815, 5, 0) T_4811 <= T_4816 skip reg T_4818 : UInt<58>, clk, reset, UInt<58>("h00") node T_4819 = bit(T_4815, 6) node T_4820 = and(T_4813, T_4819) when T_4820 : node T_4822 = addw(T_4818, UInt<1>("h01")) T_4818 <= T_4822 skip node T_4823 = cat(T_4818, T_4811) reg T_4825 : UInt<6>, clk, reset, UInt<6>("h00") node T_4827 = neq(io.uarch_counters[14], UInt<1>("h00")) node T_4829 = addw(T_4825, UInt<7>("h01")) when T_4827 : node T_4830 = bits(T_4829, 5, 0) T_4825 <= T_4830 skip reg T_4832 : UInt<58>, clk, reset, UInt<58>("h00") node T_4833 = bit(T_4829, 6) node T_4834 = and(T_4827, T_4833) when T_4834 : node T_4836 = addw(T_4832, UInt<1>("h01")) T_4832 <= T_4836 skip node T_4837 = cat(T_4832, T_4825) reg T_4839 : UInt<6>, clk, reset, UInt<6>("h00") node T_4841 = neq(io.uarch_counters[15], UInt<1>("h00")) node T_4843 = addw(T_4839, UInt<7>("h01")) when T_4841 : node T_4844 = bits(T_4843, 5, 0) T_4839 <= T_4844 skip reg T_4846 : UInt<58>, clk, reset, UInt<58>("h00") node T_4847 = bit(T_4843, 6) node T_4848 = and(T_4841, T_4847) when T_4848 : node T_4850 = addw(T_4846, UInt<1>("h01")) T_4846 <= T_4850 skip node T_4851 = cat(T_4846, T_4839) reg reg_fflags : UInt<5>, clk, UInt<1>("h00"), reg_fflags reg reg_frm : UInt<3>, clk, UInt<1>("h00"), reg_frm node irq_rocc = and(UInt<1>("h00"), io.rocc.interrupt) io.interrupt_cause <= UInt<1>("h00") node T_4859 = bit(io.interrupt_cause, 63) io.interrupt <= T_4859 wire some_interrupt_pending : UInt<1> some_interrupt_pending <= UInt<1>("h00") node T_4863 = and(reg_mie.ssip, reg_mip.ssip) node T_4864 = lt(reg_mstatus.prv, UInt<1>("h01")) node T_4865 = eq(reg_mstatus.prv, UInt<1>("h01")) node T_4866 = and(T_4865, reg_mstatus.ie) node T_4867 = or(T_4864, T_4866) node T_4868 = and(T_4863, T_4867) when T_4868 : io.interrupt_cause <= UInt<64>("h08000000000000000") skip node T_4870 = leq(reg_mstatus.prv, UInt<1>("h01")) node T_4871 = and(T_4863, T_4870) when T_4871 : some_interrupt_pending <= UInt<1>("h01") skip node T_4874 = and(reg_mie.msip, reg_mip.msip) node T_4875 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_4876 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_4877 = and(T_4876, reg_mstatus.ie) node T_4878 = or(T_4875, T_4877) node T_4879 = and(T_4874, T_4878) when T_4879 : io.interrupt_cause <= UInt<64>("h08000000000000000") skip node T_4881 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_4882 = and(T_4874, T_4881) when T_4882 : some_interrupt_pending <= UInt<1>("h01") skip node T_4885 = and(reg_mie.stip, reg_mip.stip) node T_4886 = lt(reg_mstatus.prv, UInt<1>("h01")) node T_4887 = eq(reg_mstatus.prv, UInt<1>("h01")) node T_4888 = and(T_4887, reg_mstatus.ie) node T_4889 = or(T_4886, T_4888) node T_4890 = and(T_4885, T_4889) when T_4890 : io.interrupt_cause <= UInt<64>("h08000000000000001") skip node T_4892 = leq(reg_mstatus.prv, UInt<1>("h01")) node T_4893 = and(T_4885, T_4892) when T_4893 : some_interrupt_pending <= UInt<1>("h01") skip node T_4896 = and(reg_mie.mtip, reg_mip.mtip) node T_4897 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_4898 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_4899 = and(T_4898, reg_mstatus.ie) node T_4900 = or(T_4897, T_4899) node T_4901 = and(T_4896, T_4900) when T_4901 : io.interrupt_cause <= UInt<64>("h08000000000000001") skip node T_4903 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_4904 = and(T_4896, T_4903) when T_4904 : some_interrupt_pending <= UInt<1>("h01") skip node T_4908 = neq(reg_fromhost, UInt<1>("h00")) node T_4909 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_4910 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_4911 = and(T_4910, reg_mstatus.ie) node T_4912 = or(T_4909, T_4911) node T_4913 = and(T_4908, T_4912) when T_4913 : io.interrupt_cause <= UInt<64>("h08000000000000002") skip node T_4915 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_4916 = and(T_4908, T_4915) when T_4916 : some_interrupt_pending <= UInt<1>("h01") skip node T_4919 = lt(reg_mstatus.prv, UInt<2>("h03")) node T_4920 = eq(reg_mstatus.prv, UInt<2>("h03")) node T_4921 = and(T_4920, reg_mstatus.ie) node T_4922 = or(T_4919, T_4921) node T_4923 = and(irq_rocc, T_4922) when T_4923 : io.interrupt_cause <= UInt<64>("h08000000000000003") skip node T_4925 = leq(reg_mstatus.prv, UInt<2>("h03")) node T_4926 = and(irq_rocc, T_4925) when T_4926 : some_interrupt_pending <= UInt<1>("h01") skip node system_insn = eq(io.rw.cmd, UInt<3>("h04")) node T_4929 = neq(io.rw.cmd, UInt<3>("h00")) node T_4931 = eq(system_insn, UInt<1>("h00")) node cpu_ren = and(T_4929, T_4931) reg host_csr_req_valid : UInt<1>, clk, UInt<1>("h00"), host_csr_req_valid node T_4936 = eq(cpu_ren, UInt<1>("h00")) node host_csr_req_fire = and(host_csr_req_valid, T_4936) reg host_csr_rep_valid : UInt<1>, clk, UInt<1>("h00"), host_csr_rep_valid reg host_csr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk, UInt<1>("h00"), host_csr_bits node T_4945 = eq(host_csr_req_valid, UInt<1>("h00")) node T_4947 = eq(host_csr_rep_valid, UInt<1>("h00")) node T_4948 = and(T_4945, T_4947) io.host.csr.req.ready <= T_4948 io.host.csr.resp.valid <= host_csr_rep_valid io.host.csr.resp.bits <= host_csr_bits.data node T_4949 = and(io.host.csr.req.ready, io.host.csr.req.valid) when T_4949 : host_csr_req_valid <= UInt<1>("h01") host_csr_bits <- io.host.csr.req.bits skip when host_csr_req_fire : host_csr_req_valid <= UInt<1>("h00") host_csr_rep_valid <= UInt<1>("h01") host_csr_bits.data <= io.rw.rdata skip node T_4953 = and(io.host.csr.resp.ready, io.host.csr.resp.valid) when T_4953 : host_csr_rep_valid <= UInt<1>("h00") skip io.host.debug_stats_csr <= reg_stats node T_4955 = cat(io.status.sd, io.status.zero2) node T_4956 = cat(io.status.sd_rv32, io.status.zero1) node T_4957 = cat(T_4955, T_4956) node T_4958 = cat(io.status.vm, io.status.mprv) node T_4959 = cat(io.status.xs, io.status.fs) node T_4960 = cat(T_4958, T_4959) node T_4961 = cat(T_4957, T_4960) node T_4962 = cat(io.status.prv3, io.status.ie3) node T_4963 = cat(io.status.prv2, io.status.ie2) node T_4964 = cat(T_4962, T_4963) node T_4965 = cat(io.status.prv1, io.status.ie1) node T_4966 = cat(io.status.prv, io.status.ie) node T_4967 = cat(T_4965, T_4966) node T_4968 = cat(T_4964, T_4967) node read_mstatus = cat(T_4961, T_4968) node T_4970 = cat(reg_frm, reg_fflags) node T_4978 = cat(reg_mip.mtip, reg_mip.htip) node T_4979 = cat(reg_mip.stip, reg_mip.utip) node T_4980 = cat(T_4978, T_4979) node T_4981 = cat(reg_mip.msip, reg_mip.hsip) node T_4982 = cat(reg_mip.ssip, reg_mip.usip) node T_4983 = cat(T_4981, T_4982) node T_4984 = cat(T_4980, T_4983) node T_4985 = cat(reg_mie.mtip, reg_mie.htip) node T_4986 = cat(reg_mie.stip, reg_mie.utip) node T_4987 = cat(T_4985, T_4986) node T_4988 = cat(reg_mie.msip, reg_mie.hsip) node T_4989 = cat(reg_mie.ssip, reg_mie.usip) node T_4990 = cat(T_4988, T_4989) node T_4991 = cat(T_4987, T_4990) node T_4992 = bit(reg_mepc, 39) node T_4994 = subw(UInt<24>("h00"), T_4992) node T_4995 = cat(T_4994, reg_mepc) node T_4996 = bit(reg_mbadaddr, 39) node T_4998 = subw(UInt<24>("h00"), T_4996) node T_4999 = cat(T_4998, reg_mbadaddr) wire T_5026 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_5026.ie <= UInt<1>("h00") T_5026.zero1 <= UInt<1>("h00") T_5026.pie <= UInt<1>("h00") T_5026.ps <= UInt<1>("h00") T_5026.zero2 <= UInt<1>("h00") T_5026.fs <= UInt<1>("h00") T_5026.xs <= UInt<1>("h00") T_5026.mprv <= UInt<1>("h00") T_5026.zero3 <= UInt<1>("h00") T_5026.sd_rv32 <= UInt<1>("h00") T_5026.zero4 <= UInt<1>("h00") T_5026.sd <= UInt<1>("h00") node T_5051 = bits(read_mstatus, 0, 0) T_5026.ie <= T_5051 node T_5052 = bits(read_mstatus, 2, 1) T_5026.zero1 <= T_5052 node T_5053 = bits(read_mstatus, 3, 3) T_5026.pie <= T_5053 node T_5054 = bits(read_mstatus, 4, 4) T_5026.ps <= T_5054 node T_5055 = bits(read_mstatus, 11, 5) T_5026.zero2 <= T_5055 node T_5056 = bits(read_mstatus, 13, 12) T_5026.fs <= T_5056 node T_5057 = bits(read_mstatus, 15, 14) T_5026.xs <= T_5057 node T_5058 = bits(read_mstatus, 16, 16) T_5026.mprv <= T_5058 node T_5059 = bits(read_mstatus, 30, 17) T_5026.zero3 <= T_5059 node T_5060 = bits(read_mstatus, 31, 31) T_5026.sd_rv32 <= T_5060 node T_5061 = bits(read_mstatus, 62, 32) T_5026.zero4 <= T_5061 node T_5062 = bits(read_mstatus, 63, 63) T_5026.sd <= T_5062 wire T_5063 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_5063 <- T_5026 T_5063.zero1 <= UInt<1>("h00") T_5063.zero2 <= UInt<1>("h00") T_5063.zero3 <= UInt<1>("h00") T_5063.zero4 <= UInt<1>("h00") wire T_5099 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5099.usip <= UInt<1>("h00") T_5099.ssip <= UInt<1>("h00") T_5099.hsip <= UInt<1>("h00") T_5099.msip <= UInt<1>("h00") T_5099.utip <= UInt<1>("h00") T_5099.stip <= UInt<1>("h00") T_5099.htip <= UInt<1>("h00") T_5099.mtip <= UInt<1>("h00") T_5099.usip <= UInt<1>("h00") T_5099.ssip <= UInt<1>("h00") T_5099.hsip <= UInt<1>("h00") T_5099.msip <= UInt<1>("h00") T_5099.utip <= UInt<1>("h00") T_5099.stip <= UInt<1>("h00") T_5099.htip <= UInt<1>("h00") T_5099.mtip <= UInt<1>("h00") wire T_5124 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5124 <- T_5099 T_5124.ssip <= reg_mip.ssip T_5124.stip <= reg_mip.stip wire T_5152 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5152.usip <= UInt<1>("h00") T_5152.ssip <= UInt<1>("h00") T_5152.hsip <= UInt<1>("h00") T_5152.msip <= UInt<1>("h00") T_5152.utip <= UInt<1>("h00") T_5152.stip <= UInt<1>("h00") T_5152.htip <= UInt<1>("h00") T_5152.mtip <= UInt<1>("h00") T_5152.usip <= UInt<1>("h00") T_5152.ssip <= UInt<1>("h00") T_5152.hsip <= UInt<1>("h00") T_5152.msip <= UInt<1>("h00") T_5152.utip <= UInt<1>("h00") T_5152.stip <= UInt<1>("h00") T_5152.htip <= UInt<1>("h00") T_5152.mtip <= UInt<1>("h00") wire T_5177 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5177 <- T_5152 T_5177.ssip <= reg_mie.ssip T_5177.stip <= reg_mie.stip node T_5186 = cat(T_5063.zero4, T_5063.sd_rv32) node T_5187 = cat(T_5063.sd, T_5186) node T_5188 = cat(T_5063.mprv, T_5063.xs) node T_5189 = cat(T_5063.zero3, T_5188) node T_5190 = cat(T_5187, T_5189) node T_5191 = cat(T_5063.zero2, T_5063.ps) node T_5192 = cat(T_5063.fs, T_5191) node T_5193 = cat(T_5063.zero1, T_5063.ie) node T_5194 = cat(T_5063.pie, T_5193) node T_5195 = cat(T_5192, T_5194) node T_5196 = cat(T_5190, T_5195) node T_5197 = cat(T_5124.mtip, T_5124.htip) node T_5198 = cat(T_5124.stip, T_5124.utip) node T_5199 = cat(T_5197, T_5198) node T_5200 = cat(T_5124.msip, T_5124.hsip) node T_5201 = cat(T_5124.ssip, T_5124.usip) node T_5202 = cat(T_5200, T_5201) node T_5203 = cat(T_5199, T_5202) node T_5204 = cat(T_5177.mtip, T_5177.htip) node T_5205 = cat(T_5177.stip, T_5177.utip) node T_5206 = cat(T_5204, T_5205) node T_5207 = cat(T_5177.msip, T_5177.hsip) node T_5208 = cat(T_5177.ssip, T_5177.usip) node T_5209 = cat(T_5207, T_5208) node T_5210 = cat(T_5206, T_5209) node T_5211 = bit(reg_sbadaddr, 39) node T_5213 = subw(UInt<24>("h00"), T_5211) node T_5214 = cat(T_5213, reg_sbadaddr) node T_5216 = bit(reg_sepc, 39) node T_5218 = subw(UInt<24>("h00"), T_5216) node T_5219 = cat(T_5218, reg_sepc) node T_5220 = bit(reg_stvec, 38) node T_5222 = subw(UInt<25>("h00"), T_5220) node T_5223 = cat(T_5222, reg_stvec) node addr = mux(cpu_ren, io.rw.addr, host_csr_bits.addr) node T_5226 = eq(addr, UInt<1>("h01")) node T_5228 = eq(addr, UInt<2>("h02")) node T_5230 = eq(addr, UInt<2>("h03")) node T_5232 = eq(addr, UInt<12>("h0c00")) node T_5234 = eq(addr, UInt<12>("h0900")) node T_5236 = eq(addr, UInt<12>("h0c01")) node T_5238 = eq(addr, UInt<12>("h0901")) node T_5240 = eq(addr, UInt<12>("h0d01")) node T_5242 = eq(addr, UInt<12>("h0a01")) node T_5244 = eq(addr, UInt<11>("h0701")) node T_5246 = eq(addr, UInt<12>("h0f00")) node T_5248 = eq(addr, UInt<12>("h0f01")) node T_5250 = eq(addr, UInt<10>("h0300")) node T_5252 = eq(addr, UInt<10>("h0302")) node T_5254 = eq(addr, UInt<11>("h0782")) node T_5256 = eq(addr, UInt<10>("h0301")) node T_5258 = eq(addr, UInt<11>("h0784")) node T_5260 = eq(addr, UInt<11>("h0783")) node T_5262 = eq(addr, UInt<10>("h0344")) node T_5264 = eq(addr, UInt<10>("h0304")) node T_5266 = eq(addr, UInt<10>("h0340")) node T_5268 = eq(addr, UInt<10>("h0341")) node T_5270 = eq(addr, UInt<10>("h0343")) node T_5272 = eq(addr, UInt<10>("h0342")) node T_5274 = eq(addr, UInt<10>("h0321")) node T_5276 = eq(addr, UInt<12>("h0f10")) node T_5278 = eq(addr, UInt<8>("h0c0")) node T_5280 = eq(addr, UInt<11>("h0780")) node T_5282 = eq(addr, UInt<11>("h0781")) node T_5284 = eq(addr, UInt<12>("h0c02")) node T_5286 = eq(addr, UInt<12>("h0902")) node T_5288 = eq(addr, UInt<12>("h0cc0")) node T_5290 = eq(addr, UInt<12>("h0cc1")) node T_5292 = eq(addr, UInt<12>("h0cc2")) node T_5294 = eq(addr, UInt<12>("h0cc3")) node T_5296 = eq(addr, UInt<12>("h0cc4")) node T_5298 = eq(addr, UInt<12>("h0cc5")) node T_5300 = eq(addr, UInt<12>("h0cc6")) node T_5302 = eq(addr, UInt<12>("h0cc7")) node T_5304 = eq(addr, UInt<12>("h0cc8")) node T_5306 = eq(addr, UInt<12>("h0cc9")) node T_5308 = eq(addr, UInt<12>("h0cca")) node T_5310 = eq(addr, UInt<12>("h0ccb")) node T_5312 = eq(addr, UInt<12>("h0ccc")) node T_5314 = eq(addr, UInt<12>("h0ccd")) node T_5316 = eq(addr, UInt<12>("h0cce")) node T_5318 = eq(addr, UInt<12>("h0ccf")) node T_5320 = eq(addr, UInt<9>("h0100")) node T_5322 = eq(addr, UInt<9>("h0144")) node T_5324 = eq(addr, UInt<9>("h0104")) node T_5326 = eq(addr, UInt<9>("h0140")) node T_5328 = eq(addr, UInt<12>("h0d42")) node T_5330 = eq(addr, UInt<12>("h0d43")) node T_5332 = eq(addr, UInt<9>("h0180")) node T_5334 = eq(addr, UInt<9>("h0181")) node T_5336 = eq(addr, UInt<9>("h0141")) node T_5338 = eq(addr, UInt<9>("h0101")) node T_5339 = or(T_5226, T_5228) node T_5340 = or(T_5339, T_5230) node T_5341 = or(T_5340, T_5232) node T_5342 = or(T_5341, T_5234) node T_5343 = or(T_5342, T_5236) node T_5344 = or(T_5343, T_5238) node T_5345 = or(T_5344, T_5240) node T_5346 = or(T_5345, T_5242) node T_5347 = or(T_5346, T_5244) node T_5348 = or(T_5347, T_5246) node T_5349 = or(T_5348, T_5248) node T_5350 = or(T_5349, T_5250) node T_5351 = or(T_5350, T_5252) node T_5352 = or(T_5351, T_5254) node T_5353 = or(T_5352, T_5256) node T_5354 = or(T_5353, T_5258) node T_5355 = or(T_5354, T_5260) node T_5356 = or(T_5355, T_5262) node T_5357 = or(T_5356, T_5264) node T_5358 = or(T_5357, T_5266) node T_5359 = or(T_5358, T_5268) node T_5360 = or(T_5359, T_5270) node T_5361 = or(T_5360, T_5272) node T_5362 = or(T_5361, T_5274) node T_5363 = or(T_5362, T_5276) node T_5364 = or(T_5363, T_5278) node T_5365 = or(T_5364, T_5280) node T_5366 = or(T_5365, T_5282) node T_5367 = or(T_5366, T_5284) node T_5368 = or(T_5367, T_5286) node T_5369 = or(T_5368, T_5288) node T_5370 = or(T_5369, T_5290) node T_5371 = or(T_5370, T_5292) node T_5372 = or(T_5371, T_5294) node T_5373 = or(T_5372, T_5296) node T_5374 = or(T_5373, T_5298) node T_5375 = or(T_5374, T_5300) node T_5376 = or(T_5375, T_5302) node T_5377 = or(T_5376, T_5304) node T_5378 = or(T_5377, T_5306) node T_5379 = or(T_5378, T_5308) node T_5380 = or(T_5379, T_5310) node T_5381 = or(T_5380, T_5312) node T_5382 = or(T_5381, T_5314) node T_5383 = or(T_5382, T_5316) node T_5384 = or(T_5383, T_5318) node T_5385 = or(T_5384, T_5320) node T_5386 = or(T_5385, T_5322) node T_5387 = or(T_5386, T_5324) node T_5388 = or(T_5387, T_5326) node T_5389 = or(T_5388, T_5328) node T_5390 = or(T_5389, T_5330) node T_5391 = or(T_5390, T_5332) node T_5392 = or(T_5391, T_5334) node T_5393 = or(T_5392, T_5336) node addr_valid = or(T_5393, T_5338) node T_5395 = or(T_5226, T_5228) node fp_csr = or(T_5395, T_5230) node csr_addr_priv = bits(io.rw.addr, 9, 8) node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) node T_5399 = bits(io.rw.addr, 11, 10) node T_5400 = not(T_5399) node read_only = eq(T_5400, UInt<1>("h00")) node T_5403 = neq(io.rw.cmd, UInt<3>("h05")) node T_5404 = and(cpu_ren, T_5403) node cpu_wen = and(T_5404, priv_sufficient) node T_5407 = eq(read_only, UInt<1>("h00")) node T_5408 = and(cpu_wen, T_5407) node T_5409 = and(host_csr_req_fire, host_csr_bits.rw) node wen = or(T_5408, T_5409) node T_5411 = eq(io.rw.cmd, UInt<3>("h01")) node T_5412 = eq(io.rw.cmd, UInt<3>("h03")) node T_5413 = not(io.rw.wdata) node T_5414 = and(io.rw.rdata, T_5413) node T_5415 = eq(io.rw.cmd, UInt<3>("h02")) node T_5416 = or(io.rw.rdata, io.rw.wdata) node T_5417 = mux(T_5415, T_5416, host_csr_bits.data) node T_5418 = mux(T_5412, T_5414, T_5417) node wdata = mux(T_5411, io.rw.wdata, T_5418) node T_5420 = bit(io.rw.addr, 8) node T_5422 = eq(T_5420, UInt<1>("h00")) node T_5423 = bit(io.rw.addr, 0) node T_5425 = eq(T_5423, UInt<1>("h00")) node T_5426 = and(T_5422, T_5425) node insn_call = and(T_5426, system_insn) node T_5428 = bit(io.rw.addr, 8) node T_5430 = eq(T_5428, UInt<1>("h00")) node T_5431 = bit(io.rw.addr, 0) node T_5432 = and(T_5430, T_5431) node insn_break = and(T_5432, system_insn) node T_5434 = bit(io.rw.addr, 8) node T_5435 = bit(io.rw.addr, 1) node T_5437 = eq(T_5435, UInt<1>("h00")) node T_5438 = and(T_5434, T_5437) node T_5439 = bit(io.rw.addr, 0) node T_5441 = eq(T_5439, UInt<1>("h00")) node T_5442 = and(T_5438, T_5441) node T_5443 = and(T_5442, system_insn) node insn_ret = and(T_5443, priv_sufficient) node T_5445 = bit(io.rw.addr, 8) node T_5446 = bit(io.rw.addr, 1) node T_5448 = eq(T_5446, UInt<1>("h00")) node T_5449 = and(T_5445, T_5448) node T_5450 = bit(io.rw.addr, 0) node T_5451 = and(T_5449, T_5450) node T_5452 = and(T_5451, system_insn) node insn_sfence_vm = and(T_5452, priv_sufficient) node T_5454 = bit(io.rw.addr, 2) node maybe_insn_redirect_trap = and(T_5454, system_insn) node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) node T_5457 = bit(io.rw.addr, 8) node T_5458 = bit(io.rw.addr, 1) node T_5459 = and(T_5457, T_5458) node T_5460 = bit(io.rw.addr, 0) node T_5462 = eq(T_5460, UInt<1>("h00")) node T_5463 = and(T_5459, T_5462) node T_5464 = and(T_5463, system_insn) node insn_wfi = and(T_5464, priv_sufficient) node T_5466 = and(cpu_wen, read_only) node T_5468 = eq(priv_sufficient, UInt<1>("h00")) node T_5470 = eq(addr_valid, UInt<1>("h00")) node T_5471 = or(T_5468, T_5470) node T_5473 = neq(io.status.fs, UInt<1>("h00")) node T_5475 = eq(T_5473, UInt<1>("h00")) node T_5476 = and(fp_csr, T_5475) node T_5477 = or(T_5471, T_5476) node T_5478 = and(cpu_ren, T_5477) node T_5479 = or(T_5466, T_5478) node T_5481 = eq(priv_sufficient, UInt<1>("h00")) node T_5482 = and(system_insn, T_5481) node T_5483 = or(T_5479, T_5482) node T_5484 = or(T_5483, insn_call) node csr_xcpt = or(T_5484, insn_break) when insn_wfi : reg_wfi <= UInt<1>("h01") skip when some_interrupt_pending : reg_wfi <= UInt<1>("h00") skip io.fatc <= insn_sfence_vm node T_5488 = or(io.exception, csr_xcpt) node T_5489 = shl(reg_mstatus.prv, 6) node T_5491 = addw(T_5489, UInt<9>("h0100")) node T_5492 = bit(reg_stvec, 38) node T_5493 = cat(T_5492, reg_stvec) node T_5494 = bit(reg_mstatus.prv, 1) node T_5496 = or(T_5494, UInt<1>("h00")) node T_5497 = mux(T_5496, reg_mepc, reg_sepc) node T_5498 = mux(maybe_insn_redirect_trap, T_5493, T_5497) node T_5499 = mux(T_5488, T_5491, T_5498) io.evec <= T_5499 io.ptbr <= reg_sptbr io.csr_xcpt <= csr_xcpt node T_5500 = or(insn_ret, insn_redirect_trap) io.eret <= T_5500 io.status <- reg_mstatus node T_5502 = neq(reg_mstatus.fs, UInt<1>("h00")) node T_5504 = subw(UInt<2>("h00"), T_5502) io.status.fs <= T_5504 node T_5506 = neq(reg_mstatus.xs, UInt<1>("h00")) node T_5508 = subw(UInt<2>("h00"), T_5506) io.status.xs <= T_5508 node T_5509 = not(io.status.fs) node T_5511 = eq(T_5509, UInt<1>("h00")) node T_5512 = not(io.status.xs) node T_5514 = eq(T_5512, UInt<1>("h00")) node T_5515 = or(T_5511, T_5514) io.status.sd <= T_5515 node T_5516 = or(io.exception, csr_xcpt) when T_5516 : reg_mstatus.ie <= UInt<1>("h00") reg_mstatus.prv <= UInt<2>("h03") reg_mstatus.mprv <= UInt<1>("h00") reg_mstatus.prv1 <= reg_mstatus.prv reg_mstatus.ie1 <= reg_mstatus.ie reg_mstatus.prv2 <= reg_mstatus.prv1 reg_mstatus.ie2 <= reg_mstatus.ie1 node T_5520 = not(io.pc) node T_5522 = or(T_5520, UInt<2>("h03")) node T_5523 = not(T_5522) reg_mepc <= T_5523 reg_mcause <= io.cause when csr_xcpt : reg_mcause <= UInt<2>("h02") when insn_break : reg_mcause <= UInt<2>("h03") skip when insn_call : node T_5527 = addw(reg_mstatus.prv, UInt<4>("h08")) reg_mcause <= T_5527 skip skip reg_mbadaddr <= io.pc node T_5529 = eq(io.cause, UInt<3>("h05")) node T_5531 = eq(io.cause, UInt<3>("h04")) node T_5532 = or(T_5529, T_5531) node T_5534 = eq(io.cause, UInt<3>("h07")) node T_5535 = or(T_5532, T_5534) node T_5537 = eq(io.cause, UInt<3>("h06")) node T_5538 = or(T_5535, T_5537) when T_5538 : node T_5539 = bits(io.rw.wdata, 63, 39) node T_5540 = bits(io.rw.wdata, 38, 0) node T_5541 = asSInt(T_5540) node T_5543 = lt(T_5541, asSInt(UInt<1>("h00"))) node T_5544 = not(T_5539) node T_5546 = eq(T_5544, UInt<1>("h00")) node T_5548 = neq(T_5539, UInt<1>("h00")) node T_5549 = mux(T_5543, T_5546, T_5548) node T_5550 = cat(T_5549, T_5540) reg_mbadaddr <= T_5550 skip skip when insn_ret : reg_mstatus.ie <= reg_mstatus.ie1 reg_mstatus.prv <= reg_mstatus.prv1 reg_mstatus.prv1 <= reg_mstatus.prv2 reg_mstatus.ie1 <= reg_mstatus.ie2 reg_mstatus.prv2 <= UInt<1>("h00") reg_mstatus.ie2 <= UInt<1>("h01") skip when insn_redirect_trap : reg_mstatus.prv <= UInt<1>("h01") reg_sbadaddr <= reg_mbadaddr reg_scause <= reg_mcause reg_sepc <= reg_mepc skip node T_5555 = cat(UInt<1>("h00"), insn_redirect_trap) node T_5556 = addw(insn_ret, T_5555) node T_5559 = cat(UInt<1>("h00"), csr_xcpt) node T_5560 = addw(io.exception, T_5559) node T_5561 = cat(UInt<1>("h00"), T_5560) node T_5562 = addw(T_5556, T_5561) node T_5564 = leq(T_5562, UInt<1>("h01")) node T_5566 = eq(reset, UInt<1>("h00")) when T_5566 : node T_5568 = eq(T_5564, UInt<1>("h00")) when T_5568 : node T_5570 = eq(reset, UInt<1>("h00")) when T_5570 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive") skip stop(clk, UInt<1>(1), 1) skip skip node T_5571 = geq(reg_time, reg_mtimecmp) when T_5571 : reg_mip.mtip <= UInt<1>("h01") skip io.time <= T_4627 io.csr_stall <= reg_wfi node T_5574 = eq(host_csr_bits.rw, UInt<1>("h00")) node T_5575 = and(host_csr_req_fire, T_5574) node T_5576 = and(T_5575, T_5280) when T_5576 : reg_tohost <= UInt<1>("h00") skip node T_5579 = mux(T_5226, reg_fflags, UInt<1>("h00")) node T_5581 = mux(T_5228, reg_frm, UInt<1>("h00")) node T_5583 = mux(T_5230, T_4970, UInt<1>("h00")) node T_5585 = mux(T_5232, T_4627, UInt<1>("h00")) node T_5587 = mux(T_5234, T_4627, UInt<1>("h00")) node T_5589 = mux(T_5236, reg_time, UInt<1>("h00")) node T_5591 = mux(T_5238, reg_time, UInt<1>("h00")) node T_5593 = mux(T_5240, reg_time, UInt<1>("h00")) node T_5595 = mux(T_5242, reg_time, UInt<1>("h00")) node T_5597 = mux(T_5244, reg_time, UInt<1>("h00")) node T_5599 = mux(T_5246, UInt<64>("h08000000000041129"), UInt<1>("h00")) node T_5601 = mux(T_5248, UInt<1>("h01"), UInt<1>("h00")) node T_5603 = mux(T_5250, read_mstatus, UInt<1>("h00")) node T_5605 = mux(T_5252, UInt<1>("h00"), UInt<1>("h00")) node T_5607 = mux(T_5254, UInt<1>("h00"), UInt<1>("h00")) node T_5609 = mux(T_5256, UInt<9>("h0100"), UInt<1>("h00")) node T_5611 = mux(T_5258, UInt<31>("h040000000"), UInt<1>("h00")) node T_5613 = mux(T_5260, UInt<1>("h00"), UInt<1>("h00")) node T_5615 = mux(T_5262, T_4984, UInt<1>("h00")) node T_5617 = mux(T_5264, T_4991, UInt<1>("h00")) node T_5619 = mux(T_5266, reg_mscratch, UInt<1>("h00")) node T_5621 = mux(T_5268, T_4995, UInt<1>("h00")) node T_5623 = mux(T_5270, T_4999, UInt<1>("h00")) node T_5625 = mux(T_5272, reg_mcause, UInt<1>("h00")) node T_5627 = mux(T_5274, reg_mtimecmp, UInt<1>("h00")) node T_5629 = mux(T_5276, io.host.id, UInt<1>("h00")) node T_5631 = shl(reg_stats, 0) node T_5632 = mux(T_5278, T_5631, UInt<1>("h00")) node T_5634 = mux(T_5280, reg_tohost, UInt<1>("h00")) node T_5636 = mux(T_5282, reg_fromhost, UInt<1>("h00")) node T_5638 = mux(T_5284, T_4612, UInt<1>("h00")) node T_5640 = mux(T_5286, T_4612, UInt<1>("h00")) node T_5642 = mux(T_5288, T_4641, UInt<1>("h00")) node T_5644 = mux(T_5290, T_4655, UInt<1>("h00")) node T_5646 = mux(T_5292, T_4669, UInt<1>("h00")) node T_5648 = mux(T_5294, T_4683, UInt<1>("h00")) node T_5650 = mux(T_5296, T_4697, UInt<1>("h00")) node T_5652 = mux(T_5298, T_4711, UInt<1>("h00")) node T_5654 = mux(T_5300, T_4725, UInt<1>("h00")) node T_5656 = mux(T_5302, T_4739, UInt<1>("h00")) node T_5658 = mux(T_5304, T_4753, UInt<1>("h00")) node T_5660 = mux(T_5306, T_4767, UInt<1>("h00")) node T_5662 = mux(T_5308, T_4781, UInt<1>("h00")) node T_5664 = mux(T_5310, T_4795, UInt<1>("h00")) node T_5666 = mux(T_5312, T_4809, UInt<1>("h00")) node T_5668 = mux(T_5314, T_4823, UInt<1>("h00")) node T_5670 = mux(T_5316, T_4837, UInt<1>("h00")) node T_5672 = mux(T_5318, T_4851, UInt<1>("h00")) node T_5674 = mux(T_5320, T_5196, UInt<1>("h00")) node T_5676 = mux(T_5322, T_5203, UInt<1>("h00")) node T_5678 = mux(T_5324, T_5210, UInt<1>("h00")) node T_5680 = mux(T_5326, reg_sscratch, UInt<1>("h00")) node T_5682 = mux(T_5328, reg_scause, UInt<1>("h00")) node T_5684 = mux(T_5330, T_5214, UInt<1>("h00")) node T_5686 = mux(T_5332, reg_sptbr, UInt<1>("h00")) node T_5688 = mux(T_5334, UInt<1>("h00"), UInt<1>("h00")) node T_5690 = mux(T_5336, T_5219, UInt<1>("h00")) node T_5692 = mux(T_5338, T_5223, UInt<1>("h00")) node T_5694 = or(T_5579, T_5581) node T_5695 = or(T_5694, T_5583) node T_5696 = or(T_5695, T_5585) node T_5697 = or(T_5696, T_5587) node T_5698 = or(T_5697, T_5589) node T_5699 = or(T_5698, T_5591) node T_5700 = or(T_5699, T_5593) node T_5701 = or(T_5700, T_5595) node T_5702 = or(T_5701, T_5597) node T_5703 = or(T_5702, T_5599) node T_5704 = or(T_5703, T_5601) node T_5705 = or(T_5704, T_5603) node T_5706 = or(T_5705, T_5605) node T_5707 = or(T_5706, T_5607) node T_5708 = or(T_5707, T_5609) node T_5709 = or(T_5708, T_5611) node T_5710 = or(T_5709, T_5613) node T_5711 = or(T_5710, T_5615) node T_5712 = or(T_5711, T_5617) node T_5713 = or(T_5712, T_5619) node T_5714 = or(T_5713, T_5621) node T_5715 = or(T_5714, T_5623) node T_5716 = or(T_5715, T_5625) node T_5717 = or(T_5716, T_5627) node T_5718 = or(T_5717, T_5629) node T_5719 = or(T_5718, T_5632) node T_5720 = or(T_5719, T_5634) node T_5721 = or(T_5720, T_5636) node T_5722 = or(T_5721, T_5638) node T_5723 = or(T_5722, T_5640) node T_5724 = or(T_5723, T_5642) node T_5725 = or(T_5724, T_5644) node T_5726 = or(T_5725, T_5646) node T_5727 = or(T_5726, T_5648) node T_5728 = or(T_5727, T_5650) node T_5729 = or(T_5728, T_5652) node T_5730 = or(T_5729, T_5654) node T_5731 = or(T_5730, T_5656) node T_5732 = or(T_5731, T_5658) node T_5733 = or(T_5732, T_5660) node T_5734 = or(T_5733, T_5662) node T_5735 = or(T_5734, T_5664) node T_5736 = or(T_5735, T_5666) node T_5737 = or(T_5736, T_5668) node T_5738 = or(T_5737, T_5670) node T_5739 = or(T_5738, T_5672) node T_5740 = or(T_5739, T_5674) node T_5741 = or(T_5740, T_5676) node T_5742 = or(T_5741, T_5678) node T_5743 = or(T_5742, T_5680) node T_5744 = or(T_5743, T_5682) node T_5745 = or(T_5744, T_5684) node T_5746 = or(T_5745, T_5686) node T_5747 = or(T_5746, T_5688) node T_5748 = or(T_5747, T_5690) node T_5749 = or(T_5748, T_5692) wire T_5750 : UInt<64> T_5750 <= UInt<1>("h00") T_5750 <= T_5749 io.rw.rdata <= T_5750 io.fcsr_rm <= reg_frm when io.fcsr_flags.valid : node T_5752 = or(reg_fflags, io.fcsr_flags.bits) reg_fflags <= T_5752 skip when wen : when T_5250 : wire T_5787 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} T_5787.ie <= UInt<1>("h00") T_5787.prv <= UInt<1>("h00") T_5787.ie1 <= UInt<1>("h00") T_5787.prv1 <= UInt<1>("h00") T_5787.ie2 <= UInt<1>("h00") T_5787.prv2 <= UInt<1>("h00") T_5787.ie3 <= UInt<1>("h00") T_5787.prv3 <= UInt<1>("h00") T_5787.fs <= UInt<1>("h00") T_5787.xs <= UInt<1>("h00") T_5787.mprv <= UInt<1>("h00") T_5787.vm <= UInt<1>("h00") T_5787.zero1 <= UInt<1>("h00") T_5787.sd_rv32 <= UInt<1>("h00") T_5787.zero2 <= UInt<1>("h00") T_5787.sd <= UInt<1>("h00") node T_5820 = bits(wdata, 0, 0) T_5787.ie <= T_5820 node T_5821 = bits(wdata, 2, 1) T_5787.prv <= T_5821 node T_5822 = bits(wdata, 3, 3) T_5787.ie1 <= T_5822 node T_5823 = bits(wdata, 5, 4) T_5787.prv1 <= T_5823 node T_5824 = bits(wdata, 6, 6) T_5787.ie2 <= T_5824 node T_5825 = bits(wdata, 8, 7) T_5787.prv2 <= T_5825 node T_5826 = bits(wdata, 9, 9) T_5787.ie3 <= T_5826 node T_5827 = bits(wdata, 11, 10) T_5787.prv3 <= T_5827 node T_5828 = bits(wdata, 13, 12) T_5787.fs <= T_5828 node T_5829 = bits(wdata, 15, 14) T_5787.xs <= T_5829 node T_5830 = bits(wdata, 16, 16) T_5787.mprv <= T_5830 node T_5831 = bits(wdata, 21, 17) T_5787.vm <= T_5831 node T_5832 = bits(wdata, 30, 22) T_5787.zero1 <= T_5832 node T_5833 = bits(wdata, 31, 31) T_5787.sd_rv32 <= T_5833 node T_5834 = bits(wdata, 62, 32) T_5787.zero2 <= T_5834 node T_5835 = bits(wdata, 63, 63) T_5787.sd <= T_5835 reg_mstatus.ie <= T_5787.ie reg_mstatus.ie1 <= T_5787.ie1 wire T_5840 : UInt<2>[3] T_5840[0] <= UInt<2>("h03") T_5840[1] <= UInt<1>("h00") T_5840[2] <= UInt<1>("h01") reg_mstatus.mprv <= T_5787.mprv node T_5845 = eq(T_5840[0], T_5787.prv) node T_5846 = eq(T_5840[1], T_5787.prv) node T_5847 = eq(T_5840[2], T_5787.prv) node T_5849 = or(UInt<1>("h00"), T_5845) node T_5850 = or(T_5849, T_5846) node T_5851 = or(T_5850, T_5847) when T_5851 : reg_mstatus.prv <= T_5787.prv skip node T_5852 = eq(T_5840[0], T_5787.prv1) node T_5853 = eq(T_5840[1], T_5787.prv1) node T_5854 = eq(T_5840[2], T_5787.prv1) node T_5856 = or(UInt<1>("h00"), T_5852) node T_5857 = or(T_5856, T_5853) node T_5858 = or(T_5857, T_5854) when T_5858 : reg_mstatus.prv1 <= T_5787.prv1 skip node T_5859 = eq(T_5840[0], T_5787.prv2) node T_5860 = eq(T_5840[1], T_5787.prv2) node T_5861 = eq(T_5840[2], T_5787.prv2) node T_5863 = or(UInt<1>("h00"), T_5859) node T_5864 = or(T_5863, T_5860) node T_5865 = or(T_5864, T_5861) when T_5865 : reg_mstatus.prv2 <= T_5787.prv2 skip reg_mstatus.ie2 <= T_5787.ie2 node T_5867 = eq(T_5787.vm, UInt<1>("h00")) when T_5867 : reg_mstatus.vm <= UInt<1>("h00") skip node T_5870 = eq(T_5787.vm, UInt<4>("h09")) when T_5870 : reg_mstatus.vm <= UInt<4>("h09") skip reg_mstatus.fs <= T_5787.fs skip when T_5262 : wire T_5890 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5890.usip <= UInt<1>("h00") T_5890.ssip <= UInt<1>("h00") T_5890.hsip <= UInt<1>("h00") T_5890.msip <= UInt<1>("h00") T_5890.utip <= UInt<1>("h00") T_5890.stip <= UInt<1>("h00") T_5890.htip <= UInt<1>("h00") T_5890.mtip <= UInt<1>("h00") node T_5907 = bits(wdata, 0, 0) T_5890.usip <= T_5907 node T_5908 = bits(wdata, 1, 1) T_5890.ssip <= T_5908 node T_5909 = bits(wdata, 2, 2) T_5890.hsip <= T_5909 node T_5910 = bits(wdata, 3, 3) T_5890.msip <= T_5910 node T_5911 = bits(wdata, 4, 4) T_5890.utip <= T_5911 node T_5912 = bits(wdata, 5, 5) T_5890.stip <= T_5912 node T_5913 = bits(wdata, 6, 6) T_5890.htip <= T_5913 node T_5914 = bits(wdata, 7, 7) T_5890.mtip <= T_5914 reg_mip.ssip <= T_5890.ssip reg_mip.stip <= T_5890.stip reg_mip.msip <= T_5890.msip skip when T_5260 : node T_5915 = bit(wdata, 0) reg_mip.msip <= T_5915 skip when T_5264 : wire T_5934 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_5934.usip <= UInt<1>("h00") T_5934.ssip <= UInt<1>("h00") T_5934.hsip <= UInt<1>("h00") T_5934.msip <= UInt<1>("h00") T_5934.utip <= UInt<1>("h00") T_5934.stip <= UInt<1>("h00") T_5934.htip <= UInt<1>("h00") T_5934.mtip <= UInt<1>("h00") node T_5951 = bits(wdata, 0, 0) T_5934.usip <= T_5951 node T_5952 = bits(wdata, 1, 1) T_5934.ssip <= T_5952 node T_5953 = bits(wdata, 2, 2) T_5934.hsip <= T_5953 node T_5954 = bits(wdata, 3, 3) T_5934.msip <= T_5954 node T_5955 = bits(wdata, 4, 4) T_5934.utip <= T_5955 node T_5956 = bits(wdata, 5, 5) T_5934.stip <= T_5956 node T_5957 = bits(wdata, 6, 6) T_5934.htip <= T_5957 node T_5958 = bits(wdata, 7, 7) T_5934.mtip <= T_5958 reg_mie.ssip <= T_5934.ssip reg_mie.stip <= T_5934.stip reg_mie.msip <= T_5934.msip reg_mie.mtip <= T_5934.mtip skip when T_5226 : reg_fflags <= wdata skip when T_5228 : reg_frm <= wdata skip when T_5230 : reg_fflags <= wdata node T_5959 = shr(wdata, 5) reg_frm <= T_5959 skip when T_5268 : node T_5960 = not(wdata) node T_5962 = or(T_5960, UInt<2>("h03")) node T_5963 = not(T_5962) reg_mepc <= T_5963 skip when T_5266 : reg_mscratch <= wdata skip when T_5272 : node T_5965 = and(wdata, UInt<64>("h0800000000000001f")) reg_mcause <= T_5965 skip when T_5270 : node T_5966 = bits(wdata, 39, 0) reg_mbadaddr <= T_5966 skip when T_5286 : node T_5967 = bits(wdata, 5, 0) T_4600 <= T_5967 node T_5968 = bits(wdata, 63, 6) T_4607 <= T_5968 skip when T_5274 : reg_mtimecmp <= wdata reg_mip.mtip <= UInt<1>("h00") skip when T_5244 : reg_time <= wdata skip when T_5282 : node T_5971 = eq(reg_fromhost, UInt<1>("h00")) node T_5973 = eq(host_csr_req_fire, UInt<1>("h00")) node T_5974 = or(T_5971, T_5973) when T_5974 : reg_fromhost <= wdata skip skip when T_5280 : node T_5976 = eq(reg_tohost, UInt<1>("h00")) node T_5977 = or(T_5976, host_csr_req_fire) when T_5977 : reg_tohost <= wdata skip skip when T_5278 : node T_5978 = bit(wdata, 0) reg_stats <= T_5978 skip when T_5320 : wire T_6005 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} T_6005.ie <= UInt<1>("h00") T_6005.zero1 <= UInt<1>("h00") T_6005.pie <= UInt<1>("h00") T_6005.ps <= UInt<1>("h00") T_6005.zero2 <= UInt<1>("h00") T_6005.fs <= UInt<1>("h00") T_6005.xs <= UInt<1>("h00") T_6005.mprv <= UInt<1>("h00") T_6005.zero3 <= UInt<1>("h00") T_6005.sd_rv32 <= UInt<1>("h00") T_6005.zero4 <= UInt<1>("h00") T_6005.sd <= UInt<1>("h00") node T_6030 = bits(wdata, 0, 0) T_6005.ie <= T_6030 node T_6031 = bits(wdata, 2, 1) T_6005.zero1 <= T_6031 node T_6032 = bits(wdata, 3, 3) T_6005.pie <= T_6032 node T_6033 = bits(wdata, 4, 4) T_6005.ps <= T_6033 node T_6034 = bits(wdata, 11, 5) T_6005.zero2 <= T_6034 node T_6035 = bits(wdata, 13, 12) T_6005.fs <= T_6035 node T_6036 = bits(wdata, 15, 14) T_6005.xs <= T_6036 node T_6037 = bits(wdata, 16, 16) T_6005.mprv <= T_6037 node T_6038 = bits(wdata, 30, 17) T_6005.zero3 <= T_6038 node T_6039 = bits(wdata, 31, 31) T_6005.sd_rv32 <= T_6039 node T_6040 = bits(wdata, 62, 32) T_6005.zero4 <= T_6040 node T_6041 = bits(wdata, 63, 63) T_6005.sd <= T_6041 reg_mstatus.ie <= T_6005.ie reg_mstatus.ie1 <= T_6005.pie node T_6044 = mux(T_6005.ps, UInt<1>("h01"), UInt<1>("h00")) reg_mstatus.prv1 <= T_6044 reg_mstatus.mprv <= T_6005.mprv reg_mstatus.fs <= T_6005.fs skip when T_5322 : wire T_6063 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_6063.usip <= UInt<1>("h00") T_6063.ssip <= UInt<1>("h00") T_6063.hsip <= UInt<1>("h00") T_6063.msip <= UInt<1>("h00") T_6063.utip <= UInt<1>("h00") T_6063.stip <= UInt<1>("h00") T_6063.htip <= UInt<1>("h00") T_6063.mtip <= UInt<1>("h00") node T_6080 = bits(wdata, 0, 0) T_6063.usip <= T_6080 node T_6081 = bits(wdata, 1, 1) T_6063.ssip <= T_6081 node T_6082 = bits(wdata, 2, 2) T_6063.hsip <= T_6082 node T_6083 = bits(wdata, 3, 3) T_6063.msip <= T_6083 node T_6084 = bits(wdata, 4, 4) T_6063.utip <= T_6084 node T_6085 = bits(wdata, 5, 5) T_6063.stip <= T_6085 node T_6086 = bits(wdata, 6, 6) T_6063.htip <= T_6086 node T_6087 = bits(wdata, 7, 7) T_6063.mtip <= T_6087 reg_mip.ssip <= T_6063.ssip skip when T_5324 : wire T_6106 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} T_6106.usip <= UInt<1>("h00") T_6106.ssip <= UInt<1>("h00") T_6106.hsip <= UInt<1>("h00") T_6106.msip <= UInt<1>("h00") T_6106.utip <= UInt<1>("h00") T_6106.stip <= UInt<1>("h00") T_6106.htip <= UInt<1>("h00") T_6106.mtip <= UInt<1>("h00") node T_6123 = bits(wdata, 0, 0) T_6106.usip <= T_6123 node T_6124 = bits(wdata, 1, 1) T_6106.ssip <= T_6124 node T_6125 = bits(wdata, 2, 2) T_6106.hsip <= T_6125 node T_6126 = bits(wdata, 3, 3) T_6106.msip <= T_6126 node T_6127 = bits(wdata, 4, 4) T_6106.utip <= T_6127 node T_6128 = bits(wdata, 5, 5) T_6106.stip <= T_6128 node T_6129 = bits(wdata, 6, 6) T_6106.htip <= T_6129 node T_6130 = bits(wdata, 7, 7) T_6106.mtip <= T_6130 reg_mie.ssip <= T_6106.ssip reg_mie.stip <= T_6106.stip skip when T_5326 : reg_sscratch <= wdata skip when T_5332 : node T_6131 = bits(wdata, 31, 12) node T_6133 = cat(T_6131, UInt<12>("h00")) reg_sptbr <= T_6133 skip when T_5336 : node T_6134 = not(wdata) node T_6136 = or(T_6134, UInt<2>("h03")) node T_6137 = not(T_6136) reg_sepc <= T_6137 skip when T_5338 : node T_6138 = not(wdata) node T_6140 = or(T_6138, UInt<2>("h03")) node T_6141 = not(T_6140) reg_stvec <= T_6141 skip skip when reset : reg_mstatus.zero1 <= UInt<1>("h00") reg_mstatus.zero2 <= UInt<1>("h00") reg_mstatus.ie <= UInt<1>("h00") reg_mstatus.prv <= UInt<2>("h03") reg_mstatus.ie1 <= UInt<1>("h00") reg_mstatus.prv1 <= UInt<2>("h03") reg_mstatus.ie2 <= UInt<1>("h00") reg_mstatus.prv2 <= UInt<1>("h00") reg_mstatus.ie3 <= UInt<1>("h00") reg_mstatus.prv3 <= UInt<1>("h00") reg_mstatus.mprv <= UInt<1>("h00") reg_mstatus.vm <= UInt<1>("h00") reg_mstatus.fs <= UInt<1>("h00") reg_mstatus.xs <= UInt<1>("h00") reg_mstatus.sd_rv32 <= UInt<1>("h00") reg_mstatus.sd <= UInt<1>("h00") skip module ALU : input clk : Clock input reset : UInt<1> output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} io.cmp_out <= UInt<1>("h00") io.adder_out <= UInt<1>("h00") io.out <= UInt<1>("h00") node T_11 = bit(io.fn, 3) node T_12 = not(io.in2) node in2_inv = mux(T_11, T_12, io.in2) node in1_xor_in2 = xor(io.in1, in2_inv) node T_15 = addw(io.in1, in2_inv) node T_16 = bit(io.fn, 3) node T_17 = addw(T_15, T_16) io.adder_out <= T_17 node T_18 = bit(io.fn, 0) node T_19 = bit(io.fn, 3) node T_21 = eq(T_19, UInt<1>("h00")) node T_23 = eq(in1_xor_in2, UInt<1>("h00")) node T_24 = bit(io.in1, 63) node T_25 = bit(io.in2, 63) node T_26 = eq(T_24, T_25) node T_27 = bit(io.adder_out, 63) node T_28 = bit(io.fn, 1) node T_29 = bit(io.in2, 63) node T_30 = bit(io.in1, 63) node T_31 = mux(T_28, T_29, T_30) node T_32 = mux(T_26, T_27, T_31) node T_33 = mux(T_21, T_23, T_32) node T_34 = xor(T_18, T_33) io.cmp_out <= T_34 node T_35 = bit(io.fn, 3) node T_36 = bit(io.in1, 31) node T_37 = and(T_35, T_36) node T_39 = subw(UInt<32>("h00"), T_37) node T_42 = and(io.dw, UInt<1>("h01")) node T_43 = eq(UInt<1>("h01"), T_42) node T_44 = bits(io.in1, 63, 32) node T_45 = mux(T_43, T_44, T_39) node T_46 = bit(io.in2, 5) node T_49 = and(io.dw, UInt<1>("h01")) node T_50 = eq(UInt<1>("h01"), T_49) node T_51 = and(T_46, T_50) node T_52 = bits(io.in2, 4, 0) node shamt = cat(T_51, T_52) node T_54 = bits(io.in1, 31, 0) node shin_r = cat(T_45, T_54) node T_56 = eq(io.fn, UInt<3>("h05")) node T_57 = eq(io.fn, UInt<4>("h0b")) node T_58 = or(T_56, T_57) node T_61 = shl(UInt<32>("h0ffffffff"), 32) node T_62 = xor(UInt<64>("h0ffffffffffffffff"), T_61) node T_63 = shr(shin_r, 32) node T_64 = and(T_63, T_62) node T_65 = bits(shin_r, 31, 0) node T_66 = shl(T_65, 32) node T_67 = not(T_62) node T_68 = and(T_66, T_67) node T_69 = or(T_64, T_68) node T_70 = bits(T_62, 47, 0) node T_71 = shl(T_70, 16) node T_72 = xor(T_62, T_71) node T_73 = shr(T_69, 16) node T_74 = and(T_73, T_72) node T_75 = bits(T_69, 47, 0) node T_76 = shl(T_75, 16) node T_77 = not(T_72) node T_78 = and(T_76, T_77) node T_79 = or(T_74, T_78) node T_80 = bits(T_72, 55, 0) node T_81 = shl(T_80, 8) node T_82 = xor(T_72, T_81) node T_83 = shr(T_79, 8) node T_84 = and(T_83, T_82) node T_85 = bits(T_79, 55, 0) node T_86 = shl(T_85, 8) node T_87 = not(T_82) node T_88 = and(T_86, T_87) node T_89 = or(T_84, T_88) node T_90 = bits(T_82, 59, 0) node T_91 = shl(T_90, 4) node T_92 = xor(T_82, T_91) node T_93 = shr(T_89, 4) node T_94 = and(T_93, T_92) node T_95 = bits(T_89, 59, 0) node T_96 = shl(T_95, 4) node T_97 = not(T_92) node T_98 = and(T_96, T_97) node T_99 = or(T_94, T_98) node T_100 = bits(T_92, 61, 0) node T_101 = shl(T_100, 2) node T_102 = xor(T_92, T_101) node T_103 = shr(T_99, 2) node T_104 = and(T_103, T_102) node T_105 = bits(T_99, 61, 0) node T_106 = shl(T_105, 2) node T_107 = not(T_102) node T_108 = and(T_106, T_107) node T_109 = or(T_104, T_108) node T_110 = bits(T_102, 62, 0) node T_111 = shl(T_110, 1) node T_112 = xor(T_102, T_111) node T_113 = shr(T_109, 1) node T_114 = and(T_113, T_112) node T_115 = bits(T_109, 62, 0) node T_116 = shl(T_115, 1) node T_117 = not(T_112) node T_118 = and(T_116, T_117) node T_119 = or(T_114, T_118) node shin = mux(T_58, shin_r, T_119) node T_121 = bit(io.fn, 3) node T_122 = bit(shin, 63) node T_123 = and(T_121, T_122) node T_124 = cat(T_123, shin) node T_125 = asSInt(T_124) node T_126 = dshr(T_125, shamt) node shout_r = bits(T_126, 63, 0) node T_130 = shl(UInt<32>("h0ffffffff"), 32) node T_131 = xor(UInt<64>("h0ffffffffffffffff"), T_130) node T_132 = shr(shout_r, 32) node T_133 = and(T_132, T_131) node T_134 = bits(shout_r, 31, 0) node T_135 = shl(T_134, 32) node T_136 = not(T_131) node T_137 = and(T_135, T_136) node T_138 = or(T_133, T_137) node T_139 = bits(T_131, 47, 0) node T_140 = shl(T_139, 16) node T_141 = xor(T_131, T_140) node T_142 = shr(T_138, 16) node T_143 = and(T_142, T_141) node T_144 = bits(T_138, 47, 0) node T_145 = shl(T_144, 16) node T_146 = not(T_141) node T_147 = and(T_145, T_146) node T_148 = or(T_143, T_147) node T_149 = bits(T_141, 55, 0) node T_150 = shl(T_149, 8) node T_151 = xor(T_141, T_150) node T_152 = shr(T_148, 8) node T_153 = and(T_152, T_151) node T_154 = bits(T_148, 55, 0) node T_155 = shl(T_154, 8) node T_156 = not(T_151) node T_157 = and(T_155, T_156) node T_158 = or(T_153, T_157) node T_159 = bits(T_151, 59, 0) node T_160 = shl(T_159, 4) node T_161 = xor(T_151, T_160) node T_162 = shr(T_158, 4) node T_163 = and(T_162, T_161) node T_164 = bits(T_158, 59, 0) node T_165 = shl(T_164, 4) node T_166 = not(T_161) node T_167 = and(T_165, T_166) node T_168 = or(T_163, T_167) node T_169 = bits(T_161, 61, 0) node T_170 = shl(T_169, 2) node T_171 = xor(T_161, T_170) node T_172 = shr(T_168, 2) node T_173 = and(T_172, T_171) node T_174 = bits(T_168, 61, 0) node T_175 = shl(T_174, 2) node T_176 = not(T_171) node T_177 = and(T_175, T_176) node T_178 = or(T_173, T_177) node T_179 = bits(T_171, 62, 0) node T_180 = shl(T_179, 1) node T_181 = xor(T_171, T_180) node T_182 = shr(T_178, 1) node T_183 = and(T_182, T_181) node T_184 = bits(T_178, 62, 0) node T_185 = shl(T_184, 1) node T_186 = not(T_181) node T_187 = and(T_185, T_186) node shout_l = or(T_183, T_187) node T_189 = eq(io.fn, UInt<3>("h05")) node T_190 = eq(io.fn, UInt<4>("h0b")) node T_191 = or(T_189, T_190) node T_193 = mux(T_191, shout_r, UInt<1>("h00")) node T_194 = eq(io.fn, UInt<1>("h01")) node T_196 = mux(T_194, shout_l, UInt<1>("h00")) node shout = or(T_193, T_196) node T_198 = eq(io.fn, UInt<3>("h04")) node T_199 = eq(io.fn, UInt<3>("h06")) node T_200 = or(T_198, T_199) node T_202 = mux(T_200, in1_xor_in2, UInt<1>("h00")) node T_203 = eq(io.fn, UInt<3>("h06")) node T_204 = eq(io.fn, UInt<3>("h07")) node T_205 = or(T_203, T_204) node T_206 = and(io.in1, io.in2) node T_208 = mux(T_205, T_206, UInt<1>("h00")) node logic = or(T_202, T_208) node T_210 = eq(io.fn, UInt<2>("h02")) node T_211 = eq(io.fn, UInt<2>("h03")) node T_212 = or(T_210, T_211) node T_213 = geq(io.fn, UInt<4>("h0c")) node T_214 = or(T_212, T_213) node T_215 = and(T_214, io.cmp_out) node T_216 = or(T_215, logic) node shift_logic = or(T_216, shout) node T_218 = eq(io.fn, UInt<1>("h00")) node T_219 = eq(io.fn, UInt<4>("h0a")) node T_220 = or(T_218, T_219) node out = mux(T_220, io.adder_out, shift_logic) io.out <= out node T_224 = and(io.dw, UInt<1>("h01")) node T_225 = eq(UInt<1>("h00"), T_224) when T_225 : node T_226 = bit(out, 31) node T_228 = subw(UInt<32>("h00"), T_226) node T_229 = bits(out, 31, 0) node T_230 = cat(T_228, T_229) io.out <= T_230 skip module MulDiv : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} io.resp.bits.tag <= UInt<1>("h00") io.resp.bits.data <= UInt<1>("h00") io.resp.valid <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk, UInt<1>("h00"), req reg count : UInt<7>, clk, UInt<1>("h00"), count reg neg_out : UInt<1>, clk, UInt<1>("h00"), neg_out reg isMul : UInt<1>, clk, UInt<1>("h00"), isMul reg isHi : UInt<1>, clk, UInt<1>("h00"), isHi reg divisor : UInt<65>, clk, UInt<1>("h00"), divisor reg remainder : UInt<130>, clk, UInt<1>("h00"), remainder node T_81 = and(io.req.bits.fn, UInt<4>("h04")) node T_83 = eq(T_81, UInt<4>("h00")) node T_85 = and(io.req.bits.fn, UInt<4>("h08")) node T_87 = eq(T_85, UInt<4>("h08")) node T_89 = or(UInt<1>("h00"), T_83) node T_90 = or(T_89, T_87) node T_92 = and(io.req.bits.fn, UInt<4>("h05")) node T_94 = eq(T_92, UInt<4>("h01")) node T_96 = and(io.req.bits.fn, UInt<4>("h02")) node T_98 = eq(T_96, UInt<4>("h02")) node T_100 = or(UInt<1>("h00"), T_94) node T_101 = or(T_100, T_98) node T_102 = or(T_101, T_87) node T_104 = and(io.req.bits.fn, UInt<4>("h09")) node T_106 = eq(T_104, UInt<4>("h00")) node T_108 = and(io.req.bits.fn, UInt<4>("h03")) node T_110 = eq(T_108, UInt<4>("h00")) node T_112 = or(UInt<1>("h00"), T_106) node T_113 = or(T_112, T_83) node T_114 = or(T_113, T_110) node T_116 = or(UInt<1>("h00"), T_106) node T_117 = or(T_116, T_83) node cmdMul = bit(T_90, 0) node cmdHi = bit(T_102, 0) node lhsSigned = bit(T_114, 0) node rhsSigned = bit(T_117, 0) node T_124 = and(io.req.bits.dw, UInt<1>("h01")) node T_125 = eq(UInt<1>("h01"), T_124) node T_126 = bit(io.req.bits.in1, 63) node T_127 = bit(io.req.bits.in1, 31) node T_128 = mux(T_125, T_126, T_127) node lhs_sign = and(lhsSigned, T_128) node T_132 = and(io.req.bits.dw, UInt<1>("h01")) node T_133 = eq(UInt<1>("h01"), T_132) node T_134 = bits(io.req.bits.in1, 63, 32) node T_136 = subw(UInt<32>("h00"), lhs_sign) node T_137 = mux(T_133, T_134, T_136) node T_138 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(T_137, T_138) node T_142 = and(io.req.bits.dw, UInt<1>("h01")) node T_143 = eq(UInt<1>("h01"), T_142) node T_144 = bit(io.req.bits.in2, 63) node T_145 = bit(io.req.bits.in2, 31) node T_146 = mux(T_143, T_144, T_145) node rhs_sign = and(rhsSigned, T_146) node T_150 = and(io.req.bits.dw, UInt<1>("h01")) node T_151 = eq(UInt<1>("h01"), T_150) node T_152 = bits(io.req.bits.in2, 63, 32) node T_154 = subw(UInt<32>("h00"), rhs_sign) node T_155 = mux(T_151, T_152, T_154) node T_156 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(T_155, T_156) node T_158 = bits(remainder, 128, 64) node T_159 = bits(divisor, 64, 0) node subtractor = subw(T_158, T_159) node less = bit(subtractor, 64) node T_162 = bits(remainder, 63, 0) node negated_remainder = subw(UInt<1>("h00"), T_162) node T_165 = eq(state, UInt<1>("h01")) when T_165 : node T_166 = bit(remainder, 63) node T_167 = or(T_166, isMul) when T_167 : remainder <= negated_remainder skip node T_168 = bit(divisor, 63) node T_169 = or(T_168, isMul) when T_169 : divisor <= subtractor skip state <= UInt<2>("h02") skip node T_170 = eq(state, UInt<3>("h04")) when T_170 : remainder <= negated_remainder state <= UInt<3>("h05") skip node T_171 = eq(state, UInt<2>("h03")) when T_171 : node T_172 = bits(remainder, 128, 65) remainder <= T_172 node T_173 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) state <= T_173 skip node T_174 = eq(state, UInt<2>("h02")) node T_175 = and(T_174, isMul) when T_175 : node T_176 = bits(remainder, 129, 65) node T_177 = bits(remainder, 63, 0) node T_178 = cat(T_176, T_177) node T_179 = bits(T_178, 63, 0) node T_180 = bits(T_178, 128, 64) node T_181 = asSInt(T_180) node T_182 = asSInt(divisor) node T_183 = bits(T_179, 7, 0) node T_184 = mul(T_182, T_183) node T_185 = addw(T_184, T_181) node T_186 = bits(T_179, 63, 8) node T_187 = asUInt(T_185) node T_188 = cat(T_187, T_186) node T_191 = mul(count, UInt<4>("h08")) node T_192 = bits(T_191, 5, 0) node T_193 = dshr(asSInt(UInt<65>("h010000000000000000")), T_192) node T_194 = bits(T_193, 63, 0) node T_197 = neq(count, UInt<3>("h07")) node T_198 = and(UInt<1>("h01"), T_197) node T_200 = neq(count, UInt<1>("h00")) node T_201 = and(T_198, T_200) node T_203 = eq(isHi, UInt<1>("h00")) node T_204 = and(T_201, T_203) node T_205 = not(T_194) node T_206 = and(T_179, T_205) node T_208 = eq(T_206, UInt<1>("h00")) node T_209 = and(T_204, T_208) node T_212 = mul(count, UInt<4>("h08")) node T_213 = subw(UInt<7>("h040"), T_212) node T_214 = bits(T_213, 5, 0) node T_215 = dshr(T_178, T_214) node T_216 = bits(T_188, 128, 64) node T_217 = mux(T_209, T_215, T_188) node T_218 = bits(T_217, 63, 0) node T_219 = cat(T_216, T_218) node T_220 = shr(T_219, 64) node T_222 = bits(T_219, 63, 0) node T_223 = cat(UInt<1>("h00"), T_222) node T_224 = cat(T_220, T_223) remainder <= T_224 node T_226 = addw(count, UInt<1>("h01")) count <= T_226 node T_228 = eq(count, UInt<3>("h07")) node T_229 = or(T_209, T_228) when T_229 : node T_230 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) state <= T_230 skip skip node T_231 = eq(state, UInt<2>("h02")) node T_233 = eq(isMul, UInt<1>("h00")) node T_234 = and(T_231, T_233) when T_234 : node T_236 = eq(count, UInt<7>("h040")) when T_236 : node T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) node T_238 = mux(isHi, UInt<2>("h03"), T_237) state <= T_238 skip node T_240 = addw(count, UInt<1>("h01")) count <= T_240 node T_241 = bits(remainder, 127, 64) node T_242 = bits(subtractor, 63, 0) node T_243 = mux(less, T_241, T_242) node T_244 = bits(remainder, 63, 0) node T_246 = eq(less, UInt<1>("h00")) node T_247 = cat(T_244, T_246) node T_248 = cat(T_243, T_247) remainder <= T_248 node T_249 = bits(divisor, 63, 0) node T_250 = bit(T_249, 63) node T_252 = bit(T_249, 62) node T_254 = bit(T_249, 61) node T_256 = bit(T_249, 60) node T_258 = bit(T_249, 59) node T_260 = bit(T_249, 58) node T_262 = bit(T_249, 57) node T_264 = bit(T_249, 56) node T_266 = bit(T_249, 55) node T_268 = bit(T_249, 54) node T_270 = bit(T_249, 53) node T_272 = bit(T_249, 52) node T_274 = bit(T_249, 51) node T_276 = bit(T_249, 50) node T_278 = bit(T_249, 49) node T_280 = bit(T_249, 48) node T_282 = bit(T_249, 47) node T_284 = bit(T_249, 46) node T_286 = bit(T_249, 45) node T_288 = bit(T_249, 44) node T_290 = bit(T_249, 43) node T_292 = bit(T_249, 42) node T_294 = bit(T_249, 41) node T_296 = bit(T_249, 40) node T_298 = bit(T_249, 39) node T_300 = bit(T_249, 38) node T_302 = bit(T_249, 37) node T_304 = bit(T_249, 36) node T_306 = bit(T_249, 35) node T_308 = bit(T_249, 34) node T_310 = bit(T_249, 33) node T_312 = bit(T_249, 32) node T_314 = bit(T_249, 31) node T_316 = bit(T_249, 30) node T_318 = bit(T_249, 29) node T_320 = bit(T_249, 28) node T_322 = bit(T_249, 27) node T_324 = bit(T_249, 26) node T_326 = bit(T_249, 25) node T_328 = bit(T_249, 24) node T_330 = bit(T_249, 23) node T_332 = bit(T_249, 22) node T_334 = bit(T_249, 21) node T_336 = bit(T_249, 20) node T_338 = bit(T_249, 19) node T_340 = bit(T_249, 18) node T_342 = bit(T_249, 17) node T_344 = bit(T_249, 16) node T_346 = bit(T_249, 15) node T_348 = bit(T_249, 14) node T_350 = bit(T_249, 13) node T_352 = bit(T_249, 12) node T_354 = bit(T_249, 11) node T_356 = bit(T_249, 10) node T_358 = bit(T_249, 9) node T_360 = bit(T_249, 8) node T_362 = bit(T_249, 7) node T_364 = bit(T_249, 6) node T_366 = bit(T_249, 5) node T_368 = bit(T_249, 4) node T_370 = bit(T_249, 3) node T_372 = bit(T_249, 2) node T_374 = bit(T_249, 1) node T_375 = shl(T_374, 0) node T_376 = mux(T_372, UInt<2>("h02"), T_375) node T_377 = mux(T_370, UInt<2>("h03"), T_376) node T_378 = mux(T_368, UInt<3>("h04"), T_377) node T_379 = mux(T_366, UInt<3>("h05"), T_378) node T_380 = mux(T_364, UInt<3>("h06"), T_379) node T_381 = mux(T_362, UInt<3>("h07"), T_380) node T_382 = mux(T_360, UInt<4>("h08"), T_381) node T_383 = mux(T_358, UInt<4>("h09"), T_382) node T_384 = mux(T_356, UInt<4>("h0a"), T_383) node T_385 = mux(T_354, UInt<4>("h0b"), T_384) node T_386 = mux(T_352, UInt<4>("h0c"), T_385) node T_387 = mux(T_350, UInt<4>("h0d"), T_386) node T_388 = mux(T_348, UInt<4>("h0e"), T_387) node T_389 = mux(T_346, UInt<4>("h0f"), T_388) node T_390 = mux(T_344, UInt<5>("h010"), T_389) node T_391 = mux(T_342, UInt<5>("h011"), T_390) node T_392 = mux(T_340, UInt<5>("h012"), T_391) node T_393 = mux(T_338, UInt<5>("h013"), T_392) node T_394 = mux(T_336, UInt<5>("h014"), T_393) node T_395 = mux(T_334, UInt<5>("h015"), T_394) node T_396 = mux(T_332, UInt<5>("h016"), T_395) node T_397 = mux(T_330, UInt<5>("h017"), T_396) node T_398 = mux(T_328, UInt<5>("h018"), T_397) node T_399 = mux(T_326, UInt<5>("h019"), T_398) node T_400 = mux(T_324, UInt<5>("h01a"), T_399) node T_401 = mux(T_322, UInt<5>("h01b"), T_400) node T_402 = mux(T_320, UInt<5>("h01c"), T_401) node T_403 = mux(T_318, UInt<5>("h01d"), T_402) node T_404 = mux(T_316, UInt<5>("h01e"), T_403) node T_405 = mux(T_314, UInt<5>("h01f"), T_404) node T_406 = mux(T_312, UInt<6>("h020"), T_405) node T_407 = mux(T_310, UInt<6>("h021"), T_406) node T_408 = mux(T_308, UInt<6>("h022"), T_407) node T_409 = mux(T_306, UInt<6>("h023"), T_408) node T_410 = mux(T_304, UInt<6>("h024"), T_409) node T_411 = mux(T_302, UInt<6>("h025"), T_410) node T_412 = mux(T_300, UInt<6>("h026"), T_411) node T_413 = mux(T_298, UInt<6>("h027"), T_412) node T_414 = mux(T_296, UInt<6>("h028"), T_413) node T_415 = mux(T_294, UInt<6>("h029"), T_414) node T_416 = mux(T_292, UInt<6>("h02a"), T_415) node T_417 = mux(T_290, UInt<6>("h02b"), T_416) node T_418 = mux(T_288, UInt<6>("h02c"), T_417) node T_419 = mux(T_286, UInt<6>("h02d"), T_418) node T_420 = mux(T_284, UInt<6>("h02e"), T_419) node T_421 = mux(T_282, UInt<6>("h02f"), T_420) node T_422 = mux(T_280, UInt<6>("h030"), T_421) node T_423 = mux(T_278, UInt<6>("h031"), T_422) node T_424 = mux(T_276, UInt<6>("h032"), T_423) node T_425 = mux(T_274, UInt<6>("h033"), T_424) node T_426 = mux(T_272, UInt<6>("h034"), T_425) node T_427 = mux(T_270, UInt<6>("h035"), T_426) node T_428 = mux(T_268, UInt<6>("h036"), T_427) node T_429 = mux(T_266, UInt<6>("h037"), T_428) node T_430 = mux(T_264, UInt<6>("h038"), T_429) node T_431 = mux(T_262, UInt<6>("h039"), T_430) node T_432 = mux(T_260, UInt<6>("h03a"), T_431) node T_433 = mux(T_258, UInt<6>("h03b"), T_432) node T_434 = mux(T_256, UInt<6>("h03c"), T_433) node T_435 = mux(T_254, UInt<6>("h03d"), T_434) node T_436 = mux(T_252, UInt<6>("h03e"), T_435) node T_437 = mux(T_250, UInt<6>("h03f"), T_436) node T_438 = bits(remainder, 63, 0) node T_439 = bit(T_438, 63) node T_441 = bit(T_438, 62) node T_443 = bit(T_438, 61) node T_445 = bit(T_438, 60) node T_447 = bit(T_438, 59) node T_449 = bit(T_438, 58) node T_451 = bit(T_438, 57) node T_453 = bit(T_438, 56) node T_455 = bit(T_438, 55) node T_457 = bit(T_438, 54) node T_459 = bit(T_438, 53) node T_461 = bit(T_438, 52) node T_463 = bit(T_438, 51) node T_465 = bit(T_438, 50) node T_467 = bit(T_438, 49) node T_469 = bit(T_438, 48) node T_471 = bit(T_438, 47) node T_473 = bit(T_438, 46) node T_475 = bit(T_438, 45) node T_477 = bit(T_438, 44) node T_479 = bit(T_438, 43) node T_481 = bit(T_438, 42) node T_483 = bit(T_438, 41) node T_485 = bit(T_438, 40) node T_487 = bit(T_438, 39) node T_489 = bit(T_438, 38) node T_491 = bit(T_438, 37) node T_493 = bit(T_438, 36) node T_495 = bit(T_438, 35) node T_497 = bit(T_438, 34) node T_499 = bit(T_438, 33) node T_501 = bit(T_438, 32) node T_503 = bit(T_438, 31) node T_505 = bit(T_438, 30) node T_507 = bit(T_438, 29) node T_509 = bit(T_438, 28) node T_511 = bit(T_438, 27) node T_513 = bit(T_438, 26) node T_515 = bit(T_438, 25) node T_517 = bit(T_438, 24) node T_519 = bit(T_438, 23) node T_521 = bit(T_438, 22) node T_523 = bit(T_438, 21) node T_525 = bit(T_438, 20) node T_527 = bit(T_438, 19) node T_529 = bit(T_438, 18) node T_531 = bit(T_438, 17) node T_533 = bit(T_438, 16) node T_535 = bit(T_438, 15) node T_537 = bit(T_438, 14) node T_539 = bit(T_438, 13) node T_541 = bit(T_438, 12) node T_543 = bit(T_438, 11) node T_545 = bit(T_438, 10) node T_547 = bit(T_438, 9) node T_549 = bit(T_438, 8) node T_551 = bit(T_438, 7) node T_553 = bit(T_438, 6) node T_555 = bit(T_438, 5) node T_557 = bit(T_438, 4) node T_559 = bit(T_438, 3) node T_561 = bit(T_438, 2) node T_563 = bit(T_438, 1) node T_564 = shl(T_563, 0) node T_565 = mux(T_561, UInt<2>("h02"), T_564) node T_566 = mux(T_559, UInt<2>("h03"), T_565) node T_567 = mux(T_557, UInt<3>("h04"), T_566) node T_568 = mux(T_555, UInt<3>("h05"), T_567) node T_569 = mux(T_553, UInt<3>("h06"), T_568) node T_570 = mux(T_551, UInt<3>("h07"), T_569) node T_571 = mux(T_549, UInt<4>("h08"), T_570) node T_572 = mux(T_547, UInt<4>("h09"), T_571) node T_573 = mux(T_545, UInt<4>("h0a"), T_572) node T_574 = mux(T_543, UInt<4>("h0b"), T_573) node T_575 = mux(T_541, UInt<4>("h0c"), T_574) node T_576 = mux(T_539, UInt<4>("h0d"), T_575) node T_577 = mux(T_537, UInt<4>("h0e"), T_576) node T_578 = mux(T_535, UInt<4>("h0f"), T_577) node T_579 = mux(T_533, UInt<5>("h010"), T_578) node T_580 = mux(T_531, UInt<5>("h011"), T_579) node T_581 = mux(T_529, UInt<5>("h012"), T_580) node T_582 = mux(T_527, UInt<5>("h013"), T_581) node T_583 = mux(T_525, UInt<5>("h014"), T_582) node T_584 = mux(T_523, UInt<5>("h015"), T_583) node T_585 = mux(T_521, UInt<5>("h016"), T_584) node T_586 = mux(T_519, UInt<5>("h017"), T_585) node T_587 = mux(T_517, UInt<5>("h018"), T_586) node T_588 = mux(T_515, UInt<5>("h019"), T_587) node T_589 = mux(T_513, UInt<5>("h01a"), T_588) node T_590 = mux(T_511, UInt<5>("h01b"), T_589) node T_591 = mux(T_509, UInt<5>("h01c"), T_590) node T_592 = mux(T_507, UInt<5>("h01d"), T_591) node T_593 = mux(T_505, UInt<5>("h01e"), T_592) node T_594 = mux(T_503, UInt<5>("h01f"), T_593) node T_595 = mux(T_501, UInt<6>("h020"), T_594) node T_596 = mux(T_499, UInt<6>("h021"), T_595) node T_597 = mux(T_497, UInt<6>("h022"), T_596) node T_598 = mux(T_495, UInt<6>("h023"), T_597) node T_599 = mux(T_493, UInt<6>("h024"), T_598) node T_600 = mux(T_491, UInt<6>("h025"), T_599) node T_601 = mux(T_489, UInt<6>("h026"), T_600) node T_602 = mux(T_487, UInt<6>("h027"), T_601) node T_603 = mux(T_485, UInt<6>("h028"), T_602) node T_604 = mux(T_483, UInt<6>("h029"), T_603) node T_605 = mux(T_481, UInt<6>("h02a"), T_604) node T_606 = mux(T_479, UInt<6>("h02b"), T_605) node T_607 = mux(T_477, UInt<6>("h02c"), T_606) node T_608 = mux(T_475, UInt<6>("h02d"), T_607) node T_609 = mux(T_473, UInt<6>("h02e"), T_608) node T_610 = mux(T_471, UInt<6>("h02f"), T_609) node T_611 = mux(T_469, UInt<6>("h030"), T_610) node T_612 = mux(T_467, UInt<6>("h031"), T_611) node T_613 = mux(T_465, UInt<6>("h032"), T_612) node T_614 = mux(T_463, UInt<6>("h033"), T_613) node T_615 = mux(T_461, UInt<6>("h034"), T_614) node T_616 = mux(T_459, UInt<6>("h035"), T_615) node T_617 = mux(T_457, UInt<6>("h036"), T_616) node T_618 = mux(T_455, UInt<6>("h037"), T_617) node T_619 = mux(T_453, UInt<6>("h038"), T_618) node T_620 = mux(T_451, UInt<6>("h039"), T_619) node T_621 = mux(T_449, UInt<6>("h03a"), T_620) node T_622 = mux(T_447, UInt<6>("h03b"), T_621) node T_623 = mux(T_445, UInt<6>("h03c"), T_622) node T_624 = mux(T_443, UInt<6>("h03d"), T_623) node T_625 = mux(T_441, UInt<6>("h03e"), T_624) node T_626 = mux(T_439, UInt<6>("h03f"), T_625) node T_628 = addw(UInt<6>("h03f"), T_437) node T_629 = subw(T_628, T_626) node T_630 = gt(T_437, T_626) node T_632 = eq(count, UInt<1>("h00")) node T_633 = and(T_632, less) node T_635 = gt(T_629, UInt<1>("h00")) node T_636 = or(T_635, T_630) node T_637 = and(T_633, T_636) node T_639 = and(UInt<1>("h01"), T_637) when T_639 : node T_641 = bits(T_629, 5, 0) node T_642 = mux(T_630, UInt<6>("h03f"), T_641) node T_643 = bits(remainder, 63, 0) node T_644 = dshl(T_643, T_642) remainder <= T_644 count <= T_642 skip node T_646 = eq(count, UInt<1>("h00")) node T_648 = eq(less, UInt<1>("h00")) node T_649 = and(T_646, T_648) node T_651 = eq(isHi, UInt<1>("h00")) node T_652 = and(T_649, T_651) when T_652 : neg_out <= UInt<1>("h00") skip skip node T_654 = and(io.resp.ready, io.resp.valid) node T_655 = or(T_654, io.kill) when T_655 : state <= UInt<1>("h00") skip node T_656 = and(io.req.ready, io.req.valid) when T_656 : node T_658 = eq(cmdMul, UInt<1>("h00")) node T_659 = and(rhs_sign, T_658) node T_660 = or(lhs_sign, T_659) node T_661 = mux(T_660, UInt<1>("h01"), UInt<2>("h02")) state <= T_661 isMul <= cmdMul isHi <= cmdHi count <= UInt<1>("h00") node T_664 = eq(cmdMul, UInt<1>("h00")) node T_665 = neq(lhs_sign, rhs_sign) node T_666 = mux(cmdHi, lhs_sign, T_665) node T_667 = and(T_664, T_666) neg_out <= T_667 node T_668 = cat(rhs_sign, rhs_in) divisor <= T_668 remainder <= lhs_in req <- io.req.bits skip io.resp.bits <- req node T_671 = and(req.dw, UInt<1>("h01")) node T_672 = eq(UInt<1>("h00"), T_671) node T_673 = bit(remainder, 31) node T_675 = subw(UInt<32>("h00"), T_673) node T_676 = bits(remainder, 31, 0) node T_677 = cat(T_675, T_676) node T_678 = bits(remainder, 63, 0) node T_679 = mux(T_672, T_677, T_678) io.resp.bits.data <= T_679 node T_680 = eq(state, UInt<3>("h05")) io.resp.valid <= T_680 node T_681 = eq(state, UInt<1>("h00")) io.req.ready <= T_681 module Rocket : input clk : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}} io.rocc.dma.resp.bits.status <= UInt<1>("h00") io.rocc.dma.resp.bits.client_xact_id <= UInt<1>("h00") io.rocc.dma.resp.valid <= UInt<1>("h00") io.rocc.dma.req.ready <= UInt<1>("h00") io.rocc.exception <= UInt<1>("h00") io.rocc.fpu_resp.bits.exc <= UInt<1>("h00") io.rocc.fpu_resp.bits.data <= UInt<1>("h00") io.rocc.fpu_resp.valid <= UInt<1>("h00") io.rocc.fpu_req.ready <= UInt<1>("h00") io.rocc.pptw.invalidate <= UInt<1>("h00") io.rocc.pptw.status.ie <= UInt<1>("h00") io.rocc.pptw.status.prv <= UInt<1>("h00") io.rocc.pptw.status.ie1 <= UInt<1>("h00") io.rocc.pptw.status.prv1 <= UInt<1>("h00") io.rocc.pptw.status.ie2 <= UInt<1>("h00") io.rocc.pptw.status.prv2 <= UInt<1>("h00") io.rocc.pptw.status.ie3 <= UInt<1>("h00") io.rocc.pptw.status.prv3 <= UInt<1>("h00") io.rocc.pptw.status.fs <= UInt<1>("h00") io.rocc.pptw.status.xs <= UInt<1>("h00") io.rocc.pptw.status.mprv <= UInt<1>("h00") io.rocc.pptw.status.vm <= UInt<1>("h00") io.rocc.pptw.status.zero1 <= UInt<1>("h00") io.rocc.pptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.pptw.status.zero2 <= UInt<1>("h00") io.rocc.pptw.status.sd <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.pptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.pptw.resp.bits.error <= UInt<1>("h00") io.rocc.pptw.resp.valid <= UInt<1>("h00") io.rocc.pptw.req.ready <= UInt<1>("h00") io.rocc.dptw.invalidate <= UInt<1>("h00") io.rocc.dptw.status.ie <= UInt<1>("h00") io.rocc.dptw.status.prv <= UInt<1>("h00") io.rocc.dptw.status.ie1 <= UInt<1>("h00") io.rocc.dptw.status.prv1 <= UInt<1>("h00") io.rocc.dptw.status.ie2 <= UInt<1>("h00") io.rocc.dptw.status.prv2 <= UInt<1>("h00") io.rocc.dptw.status.ie3 <= UInt<1>("h00") io.rocc.dptw.status.prv3 <= UInt<1>("h00") io.rocc.dptw.status.fs <= UInt<1>("h00") io.rocc.dptw.status.xs <= UInt<1>("h00") io.rocc.dptw.status.mprv <= UInt<1>("h00") io.rocc.dptw.status.vm <= UInt<1>("h00") io.rocc.dptw.status.zero1 <= UInt<1>("h00") io.rocc.dptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.dptw.status.zero2 <= UInt<1>("h00") io.rocc.dptw.status.sd <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.dptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.dptw.resp.bits.error <= UInt<1>("h00") io.rocc.dptw.resp.valid <= UInt<1>("h00") io.rocc.dptw.req.ready <= UInt<1>("h00") io.rocc.iptw.invalidate <= UInt<1>("h00") io.rocc.iptw.status.ie <= UInt<1>("h00") io.rocc.iptw.status.prv <= UInt<1>("h00") io.rocc.iptw.status.ie1 <= UInt<1>("h00") io.rocc.iptw.status.prv1 <= UInt<1>("h00") io.rocc.iptw.status.ie2 <= UInt<1>("h00") io.rocc.iptw.status.prv2 <= UInt<1>("h00") io.rocc.iptw.status.ie3 <= UInt<1>("h00") io.rocc.iptw.status.prv3 <= UInt<1>("h00") io.rocc.iptw.status.fs <= UInt<1>("h00") io.rocc.iptw.status.xs <= UInt<1>("h00") io.rocc.iptw.status.mprv <= UInt<1>("h00") io.rocc.iptw.status.vm <= UInt<1>("h00") io.rocc.iptw.status.zero1 <= UInt<1>("h00") io.rocc.iptw.status.sd_rv32 <= UInt<1>("h00") io.rocc.iptw.status.zero2 <= UInt<1>("h00") io.rocc.iptw.status.sd <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.v <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.typ <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.r <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.d <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.rocc.iptw.resp.bits.pte.ppn <= UInt<1>("h00") io.rocc.iptw.resp.bits.error <= UInt<1>("h00") io.rocc.iptw.resp.valid <= UInt<1>("h00") io.rocc.iptw.req.ready <= UInt<1>("h00") io.rocc.autl.grant.bits.data <= UInt<1>("h00") io.rocc.autl.grant.bits.g_type <= UInt<1>("h00") io.rocc.autl.grant.bits.is_builtin_type <= UInt<1>("h00") io.rocc.autl.grant.bits.manager_xact_id <= UInt<1>("h00") io.rocc.autl.grant.bits.client_xact_id <= UInt<1>("h00") io.rocc.autl.grant.bits.addr_beat <= UInt<1>("h00") io.rocc.autl.grant.valid <= UInt<1>("h00") io.rocc.autl.acquire.ready <= UInt<1>("h00") io.rocc.s <= UInt<1>("h00") io.rocc.mem.ordered <= UInt<1>("h00") io.rocc.mem.xcpt.pf.st <= UInt<1>("h00") io.rocc.mem.xcpt.pf.ld <= UInt<1>("h00") io.rocc.mem.xcpt.ma.st <= UInt<1>("h00") io.rocc.mem.xcpt.ma.ld <= UInt<1>("h00") io.rocc.mem.replay_next.bits <= UInt<1>("h00") io.rocc.mem.replay_next.valid <= UInt<1>("h00") io.rocc.mem.resp.bits.store_data <= UInt<1>("h00") io.rocc.mem.resp.bits.data_word_bypass <= UInt<1>("h00") io.rocc.mem.resp.bits.has_data <= UInt<1>("h00") io.rocc.mem.resp.bits.replay <= UInt<1>("h00") io.rocc.mem.resp.bits.nack <= UInt<1>("h00") io.rocc.mem.resp.bits.data <= UInt<1>("h00") io.rocc.mem.resp.bits.typ <= UInt<1>("h00") io.rocc.mem.resp.bits.cmd <= UInt<1>("h00") io.rocc.mem.resp.bits.tag <= UInt<1>("h00") io.rocc.mem.resp.bits.addr <= UInt<1>("h00") io.rocc.mem.resp.valid <= UInt<1>("h00") io.rocc.mem.req.ready <= UInt<1>("h00") io.rocc.resp.ready <= UInt<1>("h00") io.rocc.cmd.bits.rs2 <= UInt<1>("h00") io.rocc.cmd.bits.rs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.opcode <= UInt<1>("h00") io.rocc.cmd.bits.inst.rd <= UInt<1>("h00") io.rocc.cmd.bits.inst.xs2 <= UInt<1>("h00") io.rocc.cmd.bits.inst.xs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.xd <= UInt<1>("h00") io.rocc.cmd.bits.inst.rs1 <= UInt<1>("h00") io.rocc.cmd.bits.inst.rs2 <= UInt<1>("h00") io.rocc.cmd.bits.inst.funct <= UInt<1>("h00") io.rocc.cmd.valid <= UInt<1>("h00") io.fpu.cp_resp.ready <= UInt<1>("h00") io.fpu.cp_req.bits.in3 <= UInt<1>("h00") io.fpu.cp_req.bits.in2 <= UInt<1>("h00") io.fpu.cp_req.bits.in1 <= UInt<1>("h00") io.fpu.cp_req.bits.typ <= UInt<1>("h00") io.fpu.cp_req.bits.rm <= UInt<1>("h00") io.fpu.cp_req.bits.wflags <= UInt<1>("h00") io.fpu.cp_req.bits.round <= UInt<1>("h00") io.fpu.cp_req.bits.sqrt <= UInt<1>("h00") io.fpu.cp_req.bits.div <= UInt<1>("h00") io.fpu.cp_req.bits.fma <= UInt<1>("h00") io.fpu.cp_req.bits.fastpipe <= UInt<1>("h00") io.fpu.cp_req.bits.toint <= UInt<1>("h00") io.fpu.cp_req.bits.fromint <= UInt<1>("h00") io.fpu.cp_req.bits.single <= UInt<1>("h00") io.fpu.cp_req.bits.swap23 <= UInt<1>("h00") io.fpu.cp_req.bits.swap12 <= UInt<1>("h00") io.fpu.cp_req.bits.ren3 <= UInt<1>("h00") io.fpu.cp_req.bits.ren2 <= UInt<1>("h00") io.fpu.cp_req.bits.ren1 <= UInt<1>("h00") io.fpu.cp_req.bits.wen <= UInt<1>("h00") io.fpu.cp_req.bits.ldst <= UInt<1>("h00") io.fpu.cp_req.bits.cmd <= UInt<1>("h00") io.fpu.cp_req.valid <= UInt<1>("h00") io.fpu.killm <= UInt<1>("h00") io.fpu.killx <= UInt<1>("h00") io.fpu.valid <= UInt<1>("h00") io.fpu.dmem_resp_data <= UInt<1>("h00") io.fpu.dmem_resp_tag <= UInt<1>("h00") io.fpu.dmem_resp_type <= UInt<1>("h00") io.fpu.dmem_resp_val <= UInt<1>("h00") io.fpu.fcsr_rm <= UInt<1>("h00") io.fpu.fromint_data <= UInt<1>("h00") io.fpu.inst <= UInt<1>("h00") io.ptw.status.ie <= UInt<1>("h00") io.ptw.status.prv <= UInt<1>("h00") io.ptw.status.ie1 <= UInt<1>("h00") io.ptw.status.prv1 <= UInt<1>("h00") io.ptw.status.ie2 <= UInt<1>("h00") io.ptw.status.prv2 <= UInt<1>("h00") io.ptw.status.ie3 <= UInt<1>("h00") io.ptw.status.prv3 <= UInt<1>("h00") io.ptw.status.fs <= UInt<1>("h00") io.ptw.status.xs <= UInt<1>("h00") io.ptw.status.mprv <= UInt<1>("h00") io.ptw.status.vm <= UInt<1>("h00") io.ptw.status.zero1 <= UInt<1>("h00") io.ptw.status.sd_rv32 <= UInt<1>("h00") io.ptw.status.zero2 <= UInt<1>("h00") io.ptw.status.sd <= UInt<1>("h00") io.ptw.invalidate <= UInt<1>("h00") io.ptw.ptbr <= UInt<1>("h00") io.dmem.invalidate_lr <= UInt<1>("h00") io.dmem.req.bits.data <= UInt<1>("h00") io.dmem.req.bits.phys <= UInt<1>("h00") io.dmem.req.bits.kill <= UInt<1>("h00") io.dmem.req.bits.typ <= UInt<1>("h00") io.dmem.req.bits.cmd <= UInt<1>("h00") io.dmem.req.bits.tag <= UInt<1>("h00") io.dmem.req.bits.addr <= UInt<1>("h00") io.dmem.req.valid <= UInt<1>("h00") io.imem.invalidate <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.target <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") io.imem.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") io.imem.ras_update.bits.prediction.valid <= UInt<1>("h00") io.imem.ras_update.bits.returnAddr <= UInt<1>("h00") io.imem.ras_update.bits.isReturn <= UInt<1>("h00") io.imem.ras_update.bits.isCall <= UInt<1>("h00") io.imem.ras_update.valid <= UInt<1>("h00") io.imem.bht_update.bits.mispredict <= UInt<1>("h00") io.imem.bht_update.bits.taken <= UInt<1>("h00") io.imem.bht_update.bits.pc <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.target <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") io.imem.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") io.imem.bht_update.bits.prediction.valid <= UInt<1>("h00") io.imem.bht_update.valid <= UInt<1>("h00") io.imem.btb_update.bits.br_pc <= UInt<1>("h00") io.imem.btb_update.bits.isReturn <= UInt<1>("h00") io.imem.btb_update.bits.isJump <= UInt<1>("h00") io.imem.btb_update.bits.taken <= UInt<1>("h00") io.imem.btb_update.bits.target <= UInt<1>("h00") io.imem.btb_update.bits.pc <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.target <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") io.imem.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") io.imem.btb_update.bits.prediction.valid <= UInt<1>("h00") io.imem.btb_update.valid <= UInt<1>("h00") io.imem.resp.ready <= UInt<1>("h00") io.imem.req.bits.pc <= UInt<1>("h00") io.imem.req.valid <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.csr.resp.bits <= UInt<1>("h00") io.host.csr.resp.valid <= UInt<1>("h00") io.host.csr.req.ready <= UInt<1>("h00") reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), ex_ctrl reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), mem_ctrl reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), wb_ctrl reg ex_reg_xcpt_interrupt : UInt<1>, clk, UInt<1>("h00"), ex_reg_xcpt_interrupt reg ex_reg_valid : UInt<1>, clk, UInt<1>("h00"), ex_reg_valid reg ex_reg_btb_hit : UInt<1>, clk, UInt<1>("h00"), ex_reg_btb_hit reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), ex_reg_btb_resp reg ex_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), ex_reg_xcpt reg ex_reg_flush_pipe : UInt<1>, clk, UInt<1>("h00"), ex_reg_flush_pipe reg ex_reg_load_use : UInt<1>, clk, UInt<1>("h00"), ex_reg_load_use reg ex_reg_cause : UInt, clk, UInt<1>("h00"), ex_reg_cause reg ex_reg_pc : UInt, clk, UInt<1>("h00"), ex_reg_pc reg ex_reg_inst : UInt, clk, UInt<1>("h00"), ex_reg_inst reg mem_reg_xcpt_interrupt : UInt<1>, clk, UInt<1>("h00"), mem_reg_xcpt_interrupt reg mem_reg_valid : UInt<1>, clk, UInt<1>("h00"), mem_reg_valid reg mem_reg_btb_hit : UInt<1>, clk, UInt<1>("h00"), mem_reg_btb_hit reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), mem_reg_btb_resp reg mem_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), mem_reg_xcpt reg mem_reg_replay : UInt<1>, clk, UInt<1>("h00"), mem_reg_replay reg mem_reg_flush_pipe : UInt<1>, clk, UInt<1>("h00"), mem_reg_flush_pipe reg mem_reg_cause : UInt, clk, UInt<1>("h00"), mem_reg_cause reg mem_reg_slow_bypass : UInt<1>, clk, UInt<1>("h00"), mem_reg_slow_bypass reg mem_reg_pc : UInt, clk, UInt<1>("h00"), mem_reg_pc reg mem_reg_inst : UInt, clk, UInt<1>("h00"), mem_reg_inst reg mem_reg_wdata : UInt, clk, UInt<1>("h00"), mem_reg_wdata reg mem_reg_rs2 : UInt, clk, UInt<1>("h00"), mem_reg_rs2 wire take_pc_mem : UInt<1> take_pc_mem <= UInt<1>("h00") reg wb_reg_valid : UInt<1>, clk, UInt<1>("h00"), wb_reg_valid reg wb_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), wb_reg_xcpt reg wb_reg_replay : UInt<1>, clk, UInt<1>("h00"), wb_reg_replay reg wb_reg_cause : UInt, clk, UInt<1>("h00"), wb_reg_cause reg wb_reg_rocc_pending : UInt<1>, clk, reset, UInt<1>("h00") reg wb_reg_pc : UInt, clk, UInt<1>("h00"), wb_reg_pc reg wb_reg_inst : UInt, clk, UInt<1>("h00"), wb_reg_inst reg wb_reg_wdata : UInt, clk, UInt<1>("h00"), wb_reg_wdata reg wb_reg_rs2 : UInt, clk, UInt<1>("h00"), wb_reg_rs2 wire take_pc_wb : UInt<1> take_pc_wb <= UInt<1>("h00") node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} id_ctrl.amo <= UInt<1>("h00") id_ctrl.fence <= UInt<1>("h00") id_ctrl.fence_i <= UInt<1>("h00") id_ctrl.csr <= UInt<1>("h00") id_ctrl.wxd <= UInt<1>("h00") id_ctrl.div <= UInt<1>("h00") id_ctrl.wfd <= UInt<1>("h00") id_ctrl.rfs3 <= UInt<1>("h00") id_ctrl.rfs2 <= UInt<1>("h00") id_ctrl.rfs1 <= UInt<1>("h00") id_ctrl.mem_type <= UInt<1>("h00") id_ctrl.mem_cmd <= UInt<1>("h00") id_ctrl.mem <= UInt<1>("h00") id_ctrl.alu_fn <= UInt<1>("h00") id_ctrl.alu_dw <= UInt<1>("h00") id_ctrl.sel_imm <= UInt<1>("h00") id_ctrl.sel_alu1 <= UInt<1>("h00") id_ctrl.sel_alu2 <= UInt<1>("h00") id_ctrl.rxs1 <= UInt<1>("h00") id_ctrl.rxs2 <= UInt<1>("h00") id_ctrl.jalr <= UInt<1>("h00") id_ctrl.jal <= UInt<1>("h00") id_ctrl.branch <= UInt<1>("h00") id_ctrl.rocc <= UInt<1>("h00") id_ctrl.fp <= UInt<1>("h00") id_ctrl.legal <= UInt<1>("h00") node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_6101 = eq(T_6099, UInt<32>("h03")) node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f")) node T_6105 = eq(T_6103, UInt<32>("h03")) node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f")) node T_6109 = eq(T_6107, UInt<32>("h0f")) node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h07077")) node T_6113 = eq(T_6111, UInt<32>("h013")) node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("h05f")) node T_6117 = eq(T_6115, UInt<32>("h017")) node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f")) node T_6121 = eq(T_6119, UInt<32>("h033")) node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) node T_6125 = eq(T_6123, UInt<32>("h033")) node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073")) node T_6129 = eq(T_6127, UInt<32>("h043")) node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f")) node T_6133 = eq(T_6131, UInt<32>("h053")) node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b")) node T_6137 = eq(T_6135, UInt<32>("h063")) node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h07f")) node T_6141 = eq(T_6139, UInt<32>("h06f")) node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff")) node T_6145 = eq(T_6143, UInt<32>("h073")) node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f")) node T_6149 = eq(T_6147, UInt<32>("h01013")) node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f")) node T_6153 = eq(T_6151, UInt<32>("h0101b")) node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b")) node T_6157 = eq(T_6155, UInt<32>("h02003")) node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_6161 = eq(T_6159, UInt<32>("h02013")) node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f")) node T_6165 = eq(T_6163, UInt<32>("h0202f")) node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) node T_6169 = eq(T_6167, UInt<32>("h02073")) node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f")) node T_6173 = eq(T_6171, UInt<32>("h05013")) node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f")) node T_6177 = eq(T_6175, UInt<32>("h0501b")) node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) node T_6181 = eq(T_6179, UInt<32>("h05033")) node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077")) node T_6185 = eq(T_6183, UInt<32>("h02004033")) node T_6187 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f")) node T_6189 = eq(T_6187, UInt<32>("h0800202f")) node T_6191 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) node T_6193 = eq(T_6191, UInt<32>("h010000073")) node T_6195 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) node T_6197 = eq(T_6195, UInt<32>("h01000202f")) node T_6199 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff")) node T_6201 = eq(T_6199, UInt<32>("h010100073")) node T_6203 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f")) node T_6205 = eq(T_6203, UInt<32>("h020000053")) node T_6207 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f")) node T_6209 = eq(T_6207, UInt<32>("h020000053")) node T_6211 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f")) node T_6213 = eq(T_6211, UInt<32>("h020000053")) node T_6215 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073")) node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) node T_6219 = eq(T_6217, UInt<32>("h040100053")) node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) node T_6223 = eq(T_6221, UInt<32>("h042000053")) node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) node T_6227 = eq(T_6225, UInt<32>("h058000053")) node T_6229 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f")) node T_6231 = eq(T_6229, UInt<32>("h0c0000053")) node T_6233 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) node T_6235 = eq(T_6233, UInt<32>("h0e0000053")) node T_6237 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f")) node T_6239 = eq(T_6237, UInt<32>("h0e0000053")) node T_6241 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f")) node T_6243 = eq(T_6241, UInt<32>("h023")) node T_6245 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f")) node T_6247 = eq(T_6245, UInt<32>("h01063")) node T_6249 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f")) node T_6251 = eq(T_6249, UInt<32>("h04063")) node T_6253 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077")) node T_6255 = eq(T_6253, UInt<32>("h033")) node T_6257 = or(UInt<1>("h00"), T_6101) node T_6258 = or(T_6257, T_6105) node T_6259 = or(T_6258, T_6109) node T_6260 = or(T_6259, T_6113) node T_6261 = or(T_6260, T_6117) node T_6262 = or(T_6261, T_6121) node T_6263 = or(T_6262, T_6125) node T_6264 = or(T_6263, T_6129) node T_6265 = or(T_6264, T_6133) node T_6266 = or(T_6265, T_6137) node T_6267 = or(T_6266, T_6141) node T_6268 = or(T_6267, T_6145) node T_6269 = or(T_6268, T_6149) node T_6270 = or(T_6269, T_6153) node T_6271 = or(T_6270, T_6157) node T_6272 = or(T_6271, T_6161) node T_6273 = or(T_6272, T_6165) node T_6274 = or(T_6273, T_6169) node T_6275 = or(T_6274, T_6173) node T_6276 = or(T_6275, T_6177) node T_6277 = or(T_6276, T_6181) node T_6278 = or(T_6277, T_6185) node T_6279 = or(T_6278, T_6189) node T_6280 = or(T_6279, T_6193) node T_6281 = or(T_6280, T_6197) node T_6282 = or(T_6281, T_6201) node T_6283 = or(T_6282, T_6205) node T_6284 = or(T_6283, T_6209) node T_6285 = or(T_6284, T_6213) node T_6286 = or(T_6285, T_6215) node T_6287 = or(T_6286, T_6219) node T_6288 = or(T_6287, T_6223) node T_6289 = or(T_6288, T_6227) node T_6290 = or(T_6289, T_6231) node T_6291 = or(T_6290, T_6235) node T_6292 = or(T_6291, T_6239) node T_6293 = or(T_6292, T_6243) node T_6294 = or(T_6293, T_6247) node T_6295 = or(T_6294, T_6251) node T_6296 = or(T_6295, T_6255) node T_6298 = and(io.imem.resp.bits.data[0], UInt<32>("h05c")) node T_6300 = eq(T_6298, UInt<32>("h04")) node T_6302 = and(io.imem.resp.bits.data[0], UInt<32>("h060")) node T_6304 = eq(T_6302, UInt<32>("h040")) node T_6306 = or(UInt<1>("h00"), T_6300) node T_6307 = or(T_6306, T_6304) node T_6310 = and(io.imem.resp.bits.data[0], UInt<32>("h074")) node T_6312 = eq(T_6310, UInt<32>("h060")) node T_6314 = or(UInt<1>("h00"), T_6312) node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h068")) node T_6318 = eq(T_6316, UInt<32>("h068")) node T_6320 = or(UInt<1>("h00"), T_6318) node T_6322 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c")) node T_6324 = eq(T_6322, UInt<32>("h024")) node T_6326 = or(UInt<1>("h00"), T_6324) node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) node T_6330 = eq(T_6328, UInt<32>("h020")) node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) node T_6334 = eq(T_6332, UInt<32>("h020")) node T_6336 = and(io.imem.resp.bits.data[0], UInt<32>("h02048")) node T_6338 = eq(T_6336, UInt<32>("h02008")) node T_6340 = or(UInt<1>("h00"), T_6330) node T_6341 = or(T_6340, T_6334) node T_6342 = or(T_6341, T_6338) node T_6344 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) node T_6346 = eq(T_6344, UInt<32>("h00")) node T_6348 = and(io.imem.resp.bits.data[0], UInt<32>("h04024")) node T_6350 = eq(T_6348, UInt<32>("h020")) node T_6352 = and(io.imem.resp.bits.data[0], UInt<32>("h038")) node T_6354 = eq(T_6352, UInt<32>("h020")) node T_6356 = and(io.imem.resp.bits.data[0], UInt<32>("h02050")) node T_6358 = eq(T_6356, UInt<32>("h02000")) node T_6360 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034")) node T_6362 = eq(T_6360, UInt<32>("h090000010")) node T_6364 = or(UInt<1>("h00"), T_6346) node T_6365 = or(T_6364, T_6350) node T_6366 = or(T_6365, T_6354) node T_6367 = or(T_6366, T_6358) node T_6368 = or(T_6367, T_6362) node T_6370 = and(io.imem.resp.bits.data[0], UInt<32>("h058")) node T_6372 = eq(T_6370, UInt<32>("h00")) node T_6374 = and(io.imem.resp.bits.data[0], UInt<32>("h020")) node T_6376 = eq(T_6374, UInt<32>("h00")) node T_6378 = and(io.imem.resp.bits.data[0], UInt<32>("h0c")) node T_6380 = eq(T_6378, UInt<32>("h04")) node T_6382 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) node T_6384 = eq(T_6382, UInt<32>("h048")) node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h04050")) node T_6388 = eq(T_6386, UInt<32>("h04050")) node T_6390 = or(UInt<1>("h00"), T_6372) node T_6391 = or(T_6390, T_6376) node T_6392 = or(T_6391, T_6380) node T_6393 = or(T_6392, T_6384) node T_6394 = or(T_6393, T_6388) node T_6396 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) node T_6398 = eq(T_6396, UInt<32>("h00")) node T_6400 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) node T_6402 = eq(T_6400, UInt<32>("h00")) node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h04008")) node T_6406 = eq(T_6404, UInt<32>("h04000")) node T_6408 = or(UInt<1>("h00"), T_6398) node T_6409 = or(T_6408, T_6346) node T_6410 = or(T_6409, T_6402) node T_6411 = or(T_6410, T_6406) node T_6412 = cat(T_6411, T_6394) node T_6414 = and(io.imem.resp.bits.data[0], UInt<32>("h04004")) node T_6416 = eq(T_6414, UInt<32>("h00")) node T_6418 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) node T_6420 = eq(T_6418, UInt<32>("h00")) node T_6422 = and(io.imem.resp.bits.data[0], UInt<32>("h024")) node T_6424 = eq(T_6422, UInt<32>("h00")) node T_6426 = or(UInt<1>("h00"), T_6416) node T_6427 = or(T_6426, T_6420) node T_6428 = or(T_6427, T_6346) node T_6429 = or(T_6428, T_6424) node T_6430 = or(T_6429, T_6402) node T_6432 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) node T_6434 = eq(T_6432, UInt<32>("h014")) node T_6436 = or(UInt<1>("h00"), T_6434) node T_6437 = or(T_6436, T_6384) node T_6438 = cat(T_6437, T_6430) node T_6440 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) node T_6442 = eq(T_6440, UInt<32>("h08")) node T_6444 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) node T_6446 = eq(T_6444, UInt<32>("h040")) node T_6448 = or(UInt<1>("h00"), T_6442) node T_6449 = or(T_6448, T_6446) node T_6451 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) node T_6453 = eq(T_6451, UInt<32>("h014")) node T_6455 = or(UInt<1>("h00"), T_6442) node T_6456 = or(T_6455, T_6453) node T_6458 = and(io.imem.resp.bits.data[0], UInt<32>("h030")) node T_6460 = eq(T_6458, UInt<32>("h00")) node T_6462 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c")) node T_6464 = eq(T_6462, UInt<32>("h04")) node T_6466 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) node T_6468 = eq(T_6466, UInt<32>("h010")) node T_6470 = or(UInt<1>("h00"), T_6460) node T_6471 = or(T_6470, T_6464) node T_6472 = or(T_6471, T_6468) node T_6473 = cat(T_6456, T_6449) node T_6474 = cat(T_6472, T_6473) node T_6476 = and(io.imem.resp.bits.data[0], UInt<32>("h010")) node T_6478 = eq(T_6476, UInt<32>("h00")) node T_6480 = and(io.imem.resp.bits.data[0], UInt<32>("h08")) node T_6482 = eq(T_6480, UInt<32>("h00")) node T_6484 = or(UInt<1>("h00"), T_6478) node T_6485 = or(T_6484, T_6482) node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) node T_6489 = eq(T_6487, UInt<32>("h01010")) node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h01058")) node T_6493 = eq(T_6491, UInt<32>("h01040")) node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h07044")) node T_6497 = eq(T_6495, UInt<32>("h07000")) node T_6499 = or(UInt<1>("h00"), T_6489) node T_6500 = or(T_6499, T_6493) node T_6501 = or(T_6500, T_6497) node T_6503 = and(io.imem.resp.bits.data[0], UInt<32>("h04054")) node T_6505 = eq(T_6503, UInt<32>("h040")) node T_6507 = and(io.imem.resp.bits.data[0], UInt<32>("h02058")) node T_6509 = eq(T_6507, UInt<32>("h02040")) node T_6511 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) node T_6513 = eq(T_6511, UInt<32>("h03010")) node T_6515 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) node T_6517 = eq(T_6515, UInt<32>("h06010")) node T_6519 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034")) node T_6521 = eq(T_6519, UInt<32>("h040000030")) node T_6523 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054")) node T_6525 = eq(T_6523, UInt<32>("h040001010")) node T_6527 = or(UInt<1>("h00"), T_6505) node T_6528 = or(T_6527, T_6509) node T_6529 = or(T_6528, T_6513) node T_6530 = or(T_6529, T_6517) node T_6531 = or(T_6530, T_6521) node T_6532 = or(T_6531, T_6525) node T_6534 = and(io.imem.resp.bits.data[0], UInt<32>("h02054")) node T_6536 = eq(T_6534, UInt<32>("h02010")) node T_6538 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054")) node T_6540 = eq(T_6538, UInt<32>("h04010")) node T_6542 = and(io.imem.resp.bits.data[0], UInt<32>("h05054")) node T_6544 = eq(T_6542, UInt<32>("h04010")) node T_6546 = and(io.imem.resp.bits.data[0], UInt<32>("h04058")) node T_6548 = eq(T_6546, UInt<32>("h04040")) node T_6550 = or(UInt<1>("h00"), T_6536) node T_6551 = or(T_6550, T_6540) node T_6552 = or(T_6551, T_6544) node T_6553 = or(T_6552, T_6548) node T_6555 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) node T_6557 = eq(T_6555, UInt<32>("h02010")) node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054")) node T_6561 = eq(T_6559, UInt<32>("h040001010")) node T_6563 = or(UInt<1>("h00"), T_6557) node T_6564 = or(T_6563, T_6548) node T_6565 = or(T_6564, T_6521) node T_6566 = or(T_6565, T_6561) node T_6567 = cat(T_6532, T_6501) node T_6568 = cat(T_6553, T_6567) node T_6569 = cat(T_6566, T_6568) node T_6571 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f")) node T_6573 = eq(T_6571, UInt<32>("h03")) node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f")) node T_6577 = eq(T_6575, UInt<32>("h03")) node T_6579 = or(UInt<1>("h00"), T_6573) node T_6580 = or(T_6579, T_6101) node T_6581 = or(T_6580, T_6577) node T_6582 = or(T_6581, T_6157) node T_6583 = or(T_6582, T_6165) node T_6584 = or(T_6583, T_6189) node T_6585 = or(T_6584, T_6197) node T_6587 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) node T_6589 = eq(T_6587, UInt<32>("h020")) node T_6591 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020")) node T_6593 = eq(T_6591, UInt<32>("h018000020")) node T_6595 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020")) node T_6597 = eq(T_6595, UInt<32>("h020000020")) node T_6599 = or(UInt<1>("h00"), T_6589) node T_6600 = or(T_6599, T_6593) node T_6601 = or(T_6600, T_6597) node T_6603 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008")) node T_6605 = eq(T_6603, UInt<32>("h010000008")) node T_6607 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008")) node T_6609 = eq(T_6607, UInt<32>("h040000008")) node T_6611 = or(UInt<1>("h00"), T_6605) node T_6612 = or(T_6611, T_6609) node T_6614 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008")) node T_6616 = eq(T_6614, UInt<32>("h08000008")) node T_6618 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008")) node T_6620 = eq(T_6618, UInt<32>("h080000008")) node T_6622 = or(UInt<1>("h00"), T_6616) node T_6623 = or(T_6622, T_6605) node T_6624 = or(T_6623, T_6620) node T_6626 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008")) node T_6628 = eq(T_6626, UInt<32>("h08")) node T_6630 = or(UInt<1>("h00"), T_6628) node T_6632 = cat(T_6612, T_6601) node T_6633 = cat(T_6624, T_6632) node T_6634 = cat(T_6630, T_6633) node T_6635 = cat(UInt<1>("h00"), T_6634) node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h01000")) node T_6639 = eq(T_6637, UInt<32>("h01000")) node T_6641 = or(UInt<1>("h00"), T_6639) node T_6643 = and(io.imem.resp.bits.data[0], UInt<32>("h02000")) node T_6645 = eq(T_6643, UInt<32>("h02000")) node T_6647 = or(UInt<1>("h00"), T_6645) node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h04000")) node T_6651 = eq(T_6649, UInt<32>("h04000")) node T_6653 = or(UInt<1>("h00"), T_6651) node T_6654 = cat(T_6647, T_6641) node T_6655 = cat(T_6653, T_6654) node T_6657 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060")) node T_6659 = eq(T_6657, UInt<32>("h040")) node T_6661 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) node T_6663 = eq(T_6661, UInt<32>("h040")) node T_6665 = and(io.imem.resp.bits.data[0], UInt<32>("h070")) node T_6667 = eq(T_6665, UInt<32>("h040")) node T_6669 = or(UInt<1>("h00"), T_6659) node T_6670 = or(T_6669, T_6663) node T_6671 = or(T_6670, T_6667) node T_6673 = and(io.imem.resp.bits.data[0], UInt<32>("h07c")) node T_6675 = eq(T_6673, UInt<32>("h024")) node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060")) node T_6679 = eq(T_6677, UInt<32>("h040")) node T_6681 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060")) node T_6683 = eq(T_6681, UInt<32>("h010000040")) node T_6685 = or(UInt<1>("h00"), T_6675) node T_6686 = or(T_6685, T_6679) node T_6687 = or(T_6686, T_6667) node T_6688 = or(T_6687, T_6683) node T_6690 = or(UInt<1>("h00"), T_6667) node T_6692 = and(io.imem.resp.bits.data[0], UInt<32>("h03c")) node T_6694 = eq(T_6692, UInt<32>("h04")) node T_6696 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) node T_6698 = eq(T_6696, UInt<32>("h010000040")) node T_6700 = or(UInt<1>("h00"), T_6694) node T_6701 = or(T_6700, T_6659) node T_6702 = or(T_6701, T_6667) node T_6703 = or(T_6702, T_6698) node T_6705 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074")) node T_6707 = eq(T_6705, UInt<32>("h02000030")) node T_6709 = or(UInt<1>("h00"), T_6707) node T_6711 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) node T_6713 = eq(T_6711, UInt<32>("h00")) node T_6715 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) node T_6717 = eq(T_6715, UInt<32>("h010")) node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h02024")) node T_6721 = eq(T_6719, UInt<32>("h024")) node T_6723 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) node T_6725 = eq(T_6723, UInt<32>("h028")) node T_6727 = and(io.imem.resp.bits.data[0], UInt<32>("h01030")) node T_6729 = eq(T_6727, UInt<32>("h01030")) node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h02030")) node T_6733 = eq(T_6731, UInt<32>("h02030")) node T_6735 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010")) node T_6737 = eq(T_6735, UInt<32>("h080000010")) node T_6739 = or(UInt<1>("h00"), T_6713) node T_6740 = or(T_6739, T_6717) node T_6741 = or(T_6740, T_6721) node T_6742 = or(T_6741, T_6725) node T_6743 = or(T_6742, T_6729) node T_6744 = or(T_6743, T_6733) node T_6745 = or(T_6744, T_6737) node T_6747 = and(io.imem.resp.bits.data[0], UInt<32>("h01070")) node T_6749 = eq(T_6747, UInt<32>("h01070")) node T_6751 = or(UInt<1>("h00"), T_6749) node T_6753 = and(io.imem.resp.bits.data[0], UInt<32>("h02070")) node T_6755 = eq(T_6753, UInt<32>("h02070")) node T_6757 = or(UInt<1>("h00"), T_6755) node T_6759 = and(io.imem.resp.bits.data[0], UInt<32>("h03070")) node T_6761 = eq(T_6759, UInt<32>("h070")) node T_6763 = or(UInt<1>("h00"), T_6761) node T_6764 = cat(T_6757, T_6751) node T_6765 = cat(T_6763, T_6764) node T_6767 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) node T_6769 = eq(T_6767, UInt<32>("h01008")) node T_6771 = or(UInt<1>("h00"), T_6769) node T_6773 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) node T_6775 = eq(T_6773, UInt<32>("h08")) node T_6777 = or(UInt<1>("h00"), T_6775) node T_6779 = and(io.imem.resp.bits.data[0], UInt<32>("h06048")) node T_6781 = eq(T_6779, UInt<32>("h02008")) node T_6783 = or(UInt<1>("h00"), T_6781) id_ctrl.legal <= T_6296 id_ctrl.fp <= T_6307 id_ctrl.rocc <= UInt<1>("h00") id_ctrl.branch <= T_6314 id_ctrl.jal <= T_6320 id_ctrl.jalr <= T_6326 id_ctrl.rxs2 <= T_6342 id_ctrl.rxs1 <= T_6368 id_ctrl.sel_alu2 <= T_6412 id_ctrl.sel_alu1 <= T_6438 id_ctrl.sel_imm <= T_6474 id_ctrl.alu_dw <= T_6485 id_ctrl.alu_fn <= T_6569 id_ctrl.mem <= T_6585 id_ctrl.mem_cmd <= T_6635 id_ctrl.mem_type <= T_6655 id_ctrl.rfs1 <= T_6671 id_ctrl.rfs2 <= T_6688 id_ctrl.rfs3 <= T_6690 id_ctrl.wfd <= T_6703 id_ctrl.div <= T_6709 id_ctrl.wxd <= T_6745 id_ctrl.csr <= T_6765 id_ctrl.fence_i <= T_6771 id_ctrl.fence <= T_6777 id_ctrl.amo <= T_6783 node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27) node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20) node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15) node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7) wire id_load_use : UInt<1> id_load_use <= UInt<1>("h00") reg id_reg_fence : UInt<1>, clk, reset, UInt<1>("h00") cmem T_6795 : UInt<64>[31] wire T_6797 : UInt T_6797 <= UInt<1>("h00") node T_6801 = eq(id_raddr1, UInt<1>("h00")) node T_6802 = and(UInt<1>("h00"), T_6801) node T_6804 = bits(id_raddr1, 4, 0) node T_6805 = not(T_6804) infer mport T_6806 = T_6795[T_6805], clk node T_6807 = mux(T_6802, UInt<1>("h00"), T_6806) T_6797 <= T_6807 wire T_6809 : UInt T_6809 <= UInt<1>("h00") node T_6813 = eq(id_raddr2, UInt<1>("h00")) node T_6814 = and(UInt<1>("h00"), T_6813) node T_6816 = bits(id_raddr2, 4, 0) node T_6817 = not(T_6816) infer mport T_6818 = T_6795[T_6817], clk node T_6819 = mux(T_6814, UInt<1>("h00"), T_6818) T_6809 <= T_6819 wire ctrl_killd : UInt<1> ctrl_killd <= UInt<1>("h00") inst csr of CSRFile csr.io.rocc.dma.resp.ready <= UInt<1>("h00") csr.io.rocc.dma.req.bits.size <= UInt<1>("h00") csr.io.rocc.dma.req.bits.length <= UInt<1>("h00") csr.io.rocc.dma.req.bits.dest <= UInt<1>("h00") csr.io.rocc.dma.req.bits.source <= UInt<1>("h00") csr.io.rocc.dma.req.bits.cmd <= UInt<1>("h00") csr.io.rocc.dma.req.bits.client_xact_id <= UInt<1>("h00") csr.io.rocc.dma.req.valid <= UInt<1>("h00") csr.io.rocc.fpu_resp.ready <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.in3 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.in2 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.in1 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.typ <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.rm <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.wflags <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.round <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.sqrt <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.div <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.fma <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.fastpipe <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.toint <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.fromint <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.single <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.swap23 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.swap12 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.ren3 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.ren2 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.ren1 <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.wen <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.ldst <= UInt<1>("h00") csr.io.rocc.fpu_req.bits.cmd <= UInt<1>("h00") csr.io.rocc.fpu_req.valid <= UInt<1>("h00") csr.io.rocc.pptw.req.bits.fetch <= UInt<1>("h00") csr.io.rocc.pptw.req.bits.store <= UInt<1>("h00") csr.io.rocc.pptw.req.bits.prv <= UInt<1>("h00") csr.io.rocc.pptw.req.bits.addr <= UInt<1>("h00") csr.io.rocc.pptw.req.valid <= UInt<1>("h00") csr.io.rocc.dptw.req.bits.fetch <= UInt<1>("h00") csr.io.rocc.dptw.req.bits.store <= UInt<1>("h00") csr.io.rocc.dptw.req.bits.prv <= UInt<1>("h00") csr.io.rocc.dptw.req.bits.addr <= UInt<1>("h00") csr.io.rocc.dptw.req.valid <= UInt<1>("h00") csr.io.rocc.iptw.req.bits.fetch <= UInt<1>("h00") csr.io.rocc.iptw.req.bits.store <= UInt<1>("h00") csr.io.rocc.iptw.req.bits.prv <= UInt<1>("h00") csr.io.rocc.iptw.req.bits.addr <= UInt<1>("h00") csr.io.rocc.iptw.req.valid <= UInt<1>("h00") csr.io.rocc.autl.grant.ready <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.data <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.union <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.a_type <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.is_builtin_type <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.addr_beat <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.client_xact_id <= UInt<1>("h00") csr.io.rocc.autl.acquire.bits.addr_block <= UInt<1>("h00") csr.io.rocc.autl.acquire.valid <= UInt<1>("h00") csr.io.rocc.interrupt <= UInt<1>("h00") csr.io.rocc.busy <= UInt<1>("h00") csr.io.rocc.mem.invalidate_lr <= UInt<1>("h00") csr.io.rocc.mem.req.bits.data <= UInt<1>("h00") csr.io.rocc.mem.req.bits.phys <= UInt<1>("h00") csr.io.rocc.mem.req.bits.kill <= UInt<1>("h00") csr.io.rocc.mem.req.bits.typ <= UInt<1>("h00") csr.io.rocc.mem.req.bits.cmd <= UInt<1>("h00") csr.io.rocc.mem.req.bits.tag <= UInt<1>("h00") csr.io.rocc.mem.req.bits.addr <= UInt<1>("h00") csr.io.rocc.mem.req.valid <= UInt<1>("h00") csr.io.rocc.resp.bits.data <= UInt<1>("h00") csr.io.rocc.resp.bits.rd <= UInt<1>("h00") csr.io.rocc.resp.valid <= UInt<1>("h00") csr.io.rocc.cmd.ready <= UInt<1>("h00") csr.io.fcsr_flags.bits <= UInt<1>("h00") csr.io.fcsr_flags.valid <= UInt<1>("h00") csr.io.pc <= UInt<1>("h00") csr.io.cause <= UInt<1>("h00") csr.io.uarch_counters[0] <= UInt<1>("h00") csr.io.uarch_counters[1] <= UInt<1>("h00") csr.io.uarch_counters[2] <= UInt<1>("h00") csr.io.uarch_counters[3] <= UInt<1>("h00") csr.io.uarch_counters[4] <= UInt<1>("h00") csr.io.uarch_counters[5] <= UInt<1>("h00") csr.io.uarch_counters[6] <= UInt<1>("h00") csr.io.uarch_counters[7] <= UInt<1>("h00") csr.io.uarch_counters[8] <= UInt<1>("h00") csr.io.uarch_counters[9] <= UInt<1>("h00") csr.io.uarch_counters[10] <= UInt<1>("h00") csr.io.uarch_counters[11] <= UInt<1>("h00") csr.io.uarch_counters[12] <= UInt<1>("h00") csr.io.uarch_counters[13] <= UInt<1>("h00") csr.io.uarch_counters[14] <= UInt<1>("h00") csr.io.uarch_counters[15] <= UInt<1>("h00") csr.io.retire <= UInt<1>("h00") csr.io.exception <= UInt<1>("h00") csr.io.rw.wdata <= UInt<1>("h00") csr.io.rw.cmd <= UInt<1>("h00") csr.io.rw.addr <= UInt<1>("h00") csr.io.host.csr.resp.ready <= UInt<1>("h00") csr.io.host.csr.req.bits.data <= UInt<1>("h00") csr.io.host.csr.req.bits.addr <= UInt<1>("h00") csr.io.host.csr.req.bits.rw <= UInt<1>("h00") csr.io.host.csr.req.valid <= UInt<1>("h00") csr.io.host.id <= UInt<1>("h00") csr.io.host.reset <= UInt<1>("h00") csr.clk <= clk csr.reset <= reset node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) node T_6929 = eq(id_ctrl.csr, UInt<3>("h02")) node T_6930 = eq(id_ctrl.csr, UInt<3>("h03")) node T_6931 = or(T_6929, T_6930) node T_6933 = eq(id_raddr1, UInt<1>("h00")) node id_csr_ren = and(T_6931, T_6933) node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20) node T_6938 = eq(id_csr_ren, UInt<1>("h00")) node T_6939 = and(id_csr_en, T_6938) node T_6998 = and(id_csr_addr, UInt<12>("h08c4")) node T_7000 = eq(T_6998, UInt<12>("h040")) node T_7002 = or(UInt<1>("h00"), T_7000) node T_7003 = bit(T_7002, 0) node T_7005 = eq(T_7003, UInt<1>("h00")) node T_7006 = and(T_6939, T_7005) node id_csr_flush = or(id_system_insn, T_7006) node T_7009 = eq(id_ctrl.legal, UInt<1>("h00")) node T_7011 = neq(csr.io.status.fs, UInt<1>("h00")) node T_7013 = eq(T_7011, UInt<1>("h00")) node T_7014 = and(id_ctrl.fp, T_7013) node T_7015 = or(T_7009, T_7014) node T_7017 = neq(csr.io.status.xs, UInt<1>("h00")) node T_7019 = eq(T_7017, UInt<1>("h00")) node T_7020 = and(id_ctrl.rocc, T_7019) node id_illegal_insn = or(T_7015, T_7020) node id_amo_aq = bit(io.imem.resp.bits.data[0], 26) node id_amo_rl = bit(io.imem.resp.bits.data[0], 25) node T_7024 = and(id_ctrl.amo, id_amo_rl) node id_fence_next = or(id_ctrl.fence, T_7024) node T_7027 = eq(io.dmem.ordered, UInt<1>("h00")) node id_mem_busy = or(T_7027, io.dmem.req.valid) node T_7030 = and(ex_reg_valid, ex_ctrl.rocc) node T_7031 = or(io.rocc.busy, T_7030) node T_7032 = and(mem_reg_valid, mem_ctrl.rocc) node T_7033 = or(T_7031, T_7032) node T_7034 = and(wb_reg_valid, wb_ctrl.rocc) node T_7035 = or(T_7033, T_7034) node id_rocc_busy = and(UInt<1>("h00"), T_7035) node T_7037 = and(id_reg_fence, id_mem_busy) node T_7038 = or(id_fence_next, T_7037) id_reg_fence <= T_7038 node T_7039 = and(id_rocc_busy, id_ctrl.fence) node T_7040 = and(id_ctrl.amo, id_amo_aq) node T_7041 = or(T_7040, id_ctrl.fence_i) node T_7042 = or(id_ctrl.mem, id_ctrl.rocc) node T_7043 = and(id_reg_fence, T_7042) node T_7044 = or(T_7041, T_7043) node T_7045 = or(T_7044, id_csr_en) node T_7046 = and(id_mem_busy, T_7045) node id_do_fence = or(T_7039, T_7046) node T_7050 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) node id_xcpt = or(T_7050, id_illegal_insn) node T_7052 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_7052) node ex_waddr = bits(ex_reg_inst, 11, 7) node mem_waddr = bits(mem_reg_inst, 11, 7) node wb_waddr = bits(wb_reg_inst, 11, 7) node T_7060 = and(ex_reg_valid, ex_ctrl.wxd) node T_7061 = and(mem_reg_valid, mem_ctrl.wxd) node T_7063 = eq(mem_ctrl.mem, UInt<1>("h00")) node T_7064 = and(T_7061, T_7063) node T_7065 = and(mem_reg_valid, mem_ctrl.wxd) node T_7066 = eq(UInt<1>("h00"), id_raddr1) node T_7067 = and(UInt<1>("h01"), T_7066) node T_7068 = eq(ex_waddr, id_raddr1) node T_7069 = and(T_7060, T_7068) node T_7070 = eq(mem_waddr, id_raddr1) node T_7071 = and(T_7064, T_7070) node T_7072 = eq(mem_waddr, id_raddr1) node T_7073 = and(T_7065, T_7072) node T_7074 = eq(UInt<1>("h00"), id_raddr2) node T_7075 = and(UInt<1>("h01"), T_7074) node T_7076 = eq(ex_waddr, id_raddr2) node T_7077 = and(T_7060, T_7076) node T_7078 = eq(mem_waddr, id_raddr2) node T_7079 = and(T_7064, T_7078) node T_7080 = eq(mem_waddr, id_raddr2) node T_7081 = and(T_7065, T_7080) wire bypass_mux : UInt[4] bypass_mux[0] <= UInt<1>("h00") bypass_mux[1] <= mem_reg_wdata bypass_mux[2] <= wb_reg_wdata bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass reg ex_reg_rs_bypass : UInt<1>[2], clk, UInt<1>("h00"), ex_reg_rs_bypass reg ex_reg_rs_lsb : UInt[2], clk, UInt<1>("h00"), ex_reg_rs_lsb reg ex_reg_rs_msb : UInt[2], clk, UInt<1>("h00"), ex_reg_rs_msb node T_7126 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) node T_7127 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_7126) node T_7129 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) node T_7130 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_7129) node T_7131 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_7133 = bit(ex_reg_inst, 31) node T_7134 = asSInt(T_7133) node T_7135 = mux(T_7131, asSInt(UInt<1>("h00")), T_7134) node T_7136 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_7137 = bits(ex_reg_inst, 30, 20) node T_7138 = asSInt(T_7137) node T_7139 = mux(T_7136, T_7138, T_7135) node T_7140 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_7141 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) node T_7142 = and(T_7140, T_7141) node T_7143 = bits(ex_reg_inst, 19, 12) node T_7144 = asSInt(T_7143) node T_7145 = mux(T_7142, T_7135, T_7144) node T_7146 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_7147 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_7148 = or(T_7146, T_7147) node T_7150 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) node T_7151 = bit(ex_reg_inst, 20) node T_7152 = asSInt(T_7151) node T_7153 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) node T_7154 = bit(ex_reg_inst, 7) node T_7155 = asSInt(T_7154) node T_7156 = mux(T_7153, T_7155, T_7135) node T_7157 = mux(T_7150, T_7152, T_7156) node T_7158 = mux(T_7148, asSInt(UInt<1>("h00")), T_7157) node T_7159 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_7160 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_7161 = or(T_7159, T_7160) node T_7163 = bits(ex_reg_inst, 30, 25) node T_7164 = mux(T_7161, UInt<1>("h00"), T_7163) node T_7165 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) node T_7167 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) node T_7168 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) node T_7169 = or(T_7167, T_7168) node T_7170 = bits(ex_reg_inst, 11, 8) node T_7171 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_7172 = bits(ex_reg_inst, 19, 16) node T_7173 = bits(ex_reg_inst, 24, 21) node T_7174 = mux(T_7171, T_7172, T_7173) node T_7175 = mux(T_7169, T_7170, T_7174) node T_7176 = mux(T_7165, UInt<1>("h00"), T_7175) node T_7177 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) node T_7178 = bit(ex_reg_inst, 7) node T_7179 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) node T_7180 = bit(ex_reg_inst, 20) node T_7181 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) node T_7182 = bit(ex_reg_inst, 15) node T_7184 = shl(T_7182, 0) node T_7185 = mux(T_7181, T_7184, UInt<1>("h00")) node T_7186 = shl(T_7180, 0) node T_7187 = mux(T_7179, T_7186, T_7185) node T_7188 = shl(T_7178, 0) node T_7189 = mux(T_7177, T_7188, T_7187) node T_7190 = asUInt(T_7135) node T_7191 = asUInt(T_7139) node T_7192 = asUInt(T_7145) node T_7193 = cat(T_7191, T_7192) node T_7194 = cat(T_7190, T_7193) node T_7195 = asUInt(T_7158) node T_7196 = cat(T_7195, T_7164) node T_7197 = cat(T_7176, T_7189) node T_7198 = cat(T_7196, T_7197) node T_7199 = cat(T_7194, T_7198) node ex_imm = asSInt(T_7199) node T_7202 = asSInt(T_7127) node T_7203 = asSInt(ex_reg_pc) node T_7204 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) node T_7205 = mux(T_7204, T_7203, asSInt(UInt<1>("h00"))) node T_7206 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) node ex_op1 = mux(T_7206, T_7202, T_7205) node T_7209 = asSInt(T_7130) node T_7211 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) node T_7212 = mux(T_7211, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) node T_7213 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) node T_7214 = mux(T_7213, ex_imm, T_7212) node T_7215 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) node ex_op2 = mux(T_7215, T_7209, T_7214) inst alu of ALU alu.io.in1 <= UInt<1>("h00") alu.io.in2 <= UInt<1>("h00") alu.io.fn <= UInt<1>("h00") alu.io.dw <= UInt<1>("h00") alu.clk <= clk alu.reset <= reset alu.io.dw <= ex_ctrl.alu_dw alu.io.fn <= ex_ctrl.alu_fn node T_7222 = asUInt(ex_op2) alu.io.in2 <= T_7222 node T_7223 = asUInt(ex_op1) alu.io.in1 <= T_7223 inst div of MulDiv div.io.resp.ready <= UInt<1>("h00") div.io.kill <= UInt<1>("h00") div.io.req.bits.tag <= UInt<1>("h00") div.io.req.bits.in2 <= UInt<1>("h00") div.io.req.bits.in1 <= UInt<1>("h00") div.io.req.bits.dw <= UInt<1>("h00") div.io.req.bits.fn <= UInt<1>("h00") div.io.req.valid <= UInt<1>("h00") div.clk <= clk div.reset <= reset node T_7233 = and(ex_reg_valid, ex_ctrl.div) div.io.req.valid <= T_7233 div.io.req.bits.dw <= ex_ctrl.alu_dw div.io.req.bits.fn <= ex_ctrl.alu_fn div.io.req.bits.in1 <= T_7127 div.io.req.bits.in2 <= T_7130 div.io.req.bits.tag <= ex_waddr node T_7235 = eq(ctrl_killd, UInt<1>("h00")) ex_reg_valid <= T_7235 node T_7237 = eq(ctrl_killd, UInt<1>("h00")) node T_7238 = and(T_7237, id_xcpt) ex_reg_xcpt <= T_7238 node T_7240 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_7241 = and(csr.io.interrupt, T_7240) node T_7242 = and(T_7241, io.imem.resp.valid) ex_reg_xcpt_interrupt <= T_7242 when id_xcpt : ex_reg_cause <= id_cause skip node T_7244 = eq(ctrl_killd, UInt<1>("h00")) when T_7244 : ex_ctrl <- id_ctrl ex_ctrl.csr <= id_csr ex_reg_btb_hit <= io.imem.btb_resp.valid when io.imem.btb_resp.valid : ex_reg_btb_resp <- io.imem.btb_resp.bits skip node T_7245 = or(id_ctrl.fence_i, id_csr_flush) ex_reg_flush_pipe <= T_7245 ex_reg_load_use <= id_load_use node T_7246 = or(T_7067, T_7069) node T_7247 = or(T_7246, T_7071) node T_7248 = or(T_7247, T_7073) node T_7253 = mux(T_7071, UInt<2>("h02"), UInt<2>("h03")) node T_7254 = mux(T_7069, UInt<1>("h01"), T_7253) node T_7255 = mux(T_7067, UInt<1>("h00"), T_7254) ex_reg_rs_bypass[0] <= T_7248 ex_reg_rs_lsb[0] <= T_7255 node T_7257 = eq(T_7248, UInt<1>("h00")) node T_7258 = and(id_ctrl.rxs1, T_7257) when T_7258 : node T_7259 = bits(T_6797, 1, 0) ex_reg_rs_lsb[0] <= T_7259 node T_7260 = shr(T_6797, 2) ex_reg_rs_msb[0] <= T_7260 skip node T_7261 = or(T_7075, T_7077) node T_7262 = or(T_7261, T_7079) node T_7263 = or(T_7262, T_7081) node T_7268 = mux(T_7079, UInt<2>("h02"), UInt<2>("h03")) node T_7269 = mux(T_7077, UInt<1>("h01"), T_7268) node T_7270 = mux(T_7075, UInt<1>("h00"), T_7269) ex_reg_rs_bypass[1] <= T_7263 ex_reg_rs_lsb[1] <= T_7270 node T_7272 = eq(T_7263, UInt<1>("h00")) node T_7273 = and(id_ctrl.rxs2, T_7272) when T_7273 : node T_7274 = bits(T_6809, 1, 0) ex_reg_rs_lsb[1] <= T_7274 node T_7275 = shr(T_6809, 2) ex_reg_rs_msb[1] <= T_7275 skip skip node T_7277 = eq(ctrl_killd, UInt<1>("h00")) node T_7278 = or(T_7277, csr.io.interrupt) when T_7278 : ex_reg_inst <= io.imem.resp.bits.data[0] ex_reg_pc <= io.imem.resp.bits.pc skip node T_7280 = eq(io.dmem.resp.valid, UInt<1>("h00")) node wb_dcache_miss = and(wb_ctrl.mem, T_7280) node T_7283 = eq(io.dmem.req.ready, UInt<1>("h00")) node T_7284 = and(ex_ctrl.mem, T_7283) node T_7286 = eq(div.io.req.ready, UInt<1>("h00")) node T_7287 = and(ex_ctrl.div, T_7286) node replay_ex_structural = or(T_7284, T_7287) node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) node T_7290 = or(replay_ex_structural, replay_ex_load_use) node replay_ex = and(ex_reg_valid, T_7290) node T_7292 = or(take_pc_mem_wb, replay_ex) node T_7294 = eq(ex_reg_valid, UInt<1>("h00")) node ctrl_killx = or(T_7292, T_7294) node T_7296 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) wire T_7298 : UInt<3>[4] T_7298[0] <= UInt<3>("h00") T_7298[1] <= UInt<3>("h04") T_7298[2] <= UInt<3>("h01") T_7298[3] <= UInt<3>("h05") node T_7304 = eq(T_7298[0], ex_ctrl.mem_type) node T_7305 = eq(T_7298[1], ex_ctrl.mem_type) node T_7306 = eq(T_7298[2], ex_ctrl.mem_type) node T_7307 = eq(T_7298[3], ex_ctrl.mem_type) node T_7309 = or(UInt<1>("h00"), T_7304) node T_7310 = or(T_7309, T_7305) node T_7311 = or(T_7310, T_7306) node T_7312 = or(T_7311, T_7307) node ex_slow_bypass = or(T_7296, T_7312) node T_7314 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) node T_7315 = and(ex_ctrl.fp, io.fpu.illegal_rm) node ex_xcpt = or(T_7314, T_7315) node ex_cause = mux(T_7314, ex_reg_cause, UInt<2>("h02")) node mem_br_taken = bit(mem_reg_wdata, 0) node T_7320 = asSInt(mem_reg_pc) node T_7321 = and(mem_ctrl.branch, mem_br_taken) node T_7322 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_7324 = bit(mem_reg_inst, 31) node T_7325 = asSInt(T_7324) node T_7326 = mux(T_7322, asSInt(UInt<1>("h00")), T_7325) node T_7327 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_7328 = bits(mem_reg_inst, 30, 20) node T_7329 = asSInt(T_7328) node T_7330 = mux(T_7327, T_7329, T_7326) node T_7331 = neq(UInt<3>("h01"), UInt<3>("h02")) node T_7332 = neq(UInt<3>("h01"), UInt<3>("h03")) node T_7333 = and(T_7331, T_7332) node T_7334 = bits(mem_reg_inst, 19, 12) node T_7335 = asSInt(T_7334) node T_7336 = mux(T_7333, T_7326, T_7335) node T_7337 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_7338 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_7339 = or(T_7337, T_7338) node T_7341 = eq(UInt<3>("h01"), UInt<3>("h03")) node T_7342 = bit(mem_reg_inst, 20) node T_7343 = asSInt(T_7342) node T_7344 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_7345 = bit(mem_reg_inst, 7) node T_7346 = asSInt(T_7345) node T_7347 = mux(T_7344, T_7346, T_7326) node T_7348 = mux(T_7341, T_7343, T_7347) node T_7349 = mux(T_7339, asSInt(UInt<1>("h00")), T_7348) node T_7350 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_7351 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_7352 = or(T_7350, T_7351) node T_7354 = bits(mem_reg_inst, 30, 25) node T_7355 = mux(T_7352, UInt<1>("h00"), T_7354) node T_7356 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_7358 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_7359 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_7360 = or(T_7358, T_7359) node T_7361 = bits(mem_reg_inst, 11, 8) node T_7362 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_7363 = bits(mem_reg_inst, 19, 16) node T_7364 = bits(mem_reg_inst, 24, 21) node T_7365 = mux(T_7362, T_7363, T_7364) node T_7366 = mux(T_7360, T_7361, T_7365) node T_7367 = mux(T_7356, UInt<1>("h00"), T_7366) node T_7368 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_7369 = bit(mem_reg_inst, 7) node T_7370 = eq(UInt<3>("h01"), UInt<3>("h04")) node T_7371 = bit(mem_reg_inst, 20) node T_7372 = eq(UInt<3>("h01"), UInt<3>("h05")) node T_7373 = bit(mem_reg_inst, 15) node T_7375 = shl(T_7373, 0) node T_7376 = mux(T_7372, T_7375, UInt<1>("h00")) node T_7377 = shl(T_7371, 0) node T_7378 = mux(T_7370, T_7377, T_7376) node T_7379 = shl(T_7369, 0) node T_7380 = mux(T_7368, T_7379, T_7378) node T_7381 = asUInt(T_7326) node T_7382 = asUInt(T_7330) node T_7383 = asUInt(T_7336) node T_7384 = cat(T_7382, T_7383) node T_7385 = cat(T_7381, T_7384) node T_7386 = asUInt(T_7349) node T_7387 = cat(T_7386, T_7355) node T_7388 = cat(T_7367, T_7380) node T_7389 = cat(T_7387, T_7388) node T_7390 = cat(T_7385, T_7389) node T_7391 = asSInt(T_7390) node T_7392 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_7394 = bit(mem_reg_inst, 31) node T_7395 = asSInt(T_7394) node T_7396 = mux(T_7392, asSInt(UInt<1>("h00")), T_7395) node T_7397 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_7398 = bits(mem_reg_inst, 30, 20) node T_7399 = asSInt(T_7398) node T_7400 = mux(T_7397, T_7399, T_7396) node T_7401 = neq(UInt<3>("h03"), UInt<3>("h02")) node T_7402 = neq(UInt<3>("h03"), UInt<3>("h03")) node T_7403 = and(T_7401, T_7402) node T_7404 = bits(mem_reg_inst, 19, 12) node T_7405 = asSInt(T_7404) node T_7406 = mux(T_7403, T_7396, T_7405) node T_7407 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_7408 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_7409 = or(T_7407, T_7408) node T_7411 = eq(UInt<3>("h03"), UInt<3>("h03")) node T_7412 = bit(mem_reg_inst, 20) node T_7413 = asSInt(T_7412) node T_7414 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_7415 = bit(mem_reg_inst, 7) node T_7416 = asSInt(T_7415) node T_7417 = mux(T_7414, T_7416, T_7396) node T_7418 = mux(T_7411, T_7413, T_7417) node T_7419 = mux(T_7409, asSInt(UInt<1>("h00")), T_7418) node T_7420 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_7421 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_7422 = or(T_7420, T_7421) node T_7424 = bits(mem_reg_inst, 30, 25) node T_7425 = mux(T_7422, UInt<1>("h00"), T_7424) node T_7426 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_7428 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_7429 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_7430 = or(T_7428, T_7429) node T_7431 = bits(mem_reg_inst, 11, 8) node T_7432 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_7433 = bits(mem_reg_inst, 19, 16) node T_7434 = bits(mem_reg_inst, 24, 21) node T_7435 = mux(T_7432, T_7433, T_7434) node T_7436 = mux(T_7430, T_7431, T_7435) node T_7437 = mux(T_7426, UInt<1>("h00"), T_7436) node T_7438 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_7439 = bit(mem_reg_inst, 7) node T_7440 = eq(UInt<3>("h03"), UInt<3>("h04")) node T_7441 = bit(mem_reg_inst, 20) node T_7442 = eq(UInt<3>("h03"), UInt<3>("h05")) node T_7443 = bit(mem_reg_inst, 15) node T_7445 = shl(T_7443, 0) node T_7446 = mux(T_7442, T_7445, UInt<1>("h00")) node T_7447 = shl(T_7441, 0) node T_7448 = mux(T_7440, T_7447, T_7446) node T_7449 = shl(T_7439, 0) node T_7450 = mux(T_7438, T_7449, T_7448) node T_7451 = asUInt(T_7396) node T_7452 = asUInt(T_7400) node T_7453 = asUInt(T_7406) node T_7454 = cat(T_7452, T_7453) node T_7455 = cat(T_7451, T_7454) node T_7456 = asUInt(T_7419) node T_7457 = cat(T_7456, T_7425) node T_7458 = cat(T_7437, T_7450) node T_7459 = cat(T_7457, T_7458) node T_7460 = cat(T_7455, T_7459) node T_7461 = asSInt(T_7460) node T_7463 = mux(mem_ctrl.jal, T_7461, asSInt(UInt<4>("h04"))) node T_7464 = mux(T_7321, T_7391, T_7463) node mem_br_target = addw(T_7320, T_7464) node T_7466 = asSInt(mem_reg_wdata) node T_7467 = mux(mem_ctrl.jalr, mem_br_target, T_7466) node mem_int_wdata = asUInt(T_7467) node T_7469 = shr(mem_reg_wdata, 38) node T_7470 = bits(mem_reg_wdata, 39, 38) node T_7472 = eq(T_7469, UInt<1>("h00")) node T_7474 = eq(T_7469, UInt<1>("h01")) node T_7475 = or(T_7472, T_7474) node T_7477 = neq(T_7470, UInt<1>("h00")) node T_7478 = asSInt(T_7469) node T_7480 = eq(T_7478, asSInt(UInt<1>("h01"))) node T_7481 = asSInt(T_7469) node T_7483 = eq(T_7481, asSInt(UInt<2>("h02"))) node T_7484 = or(T_7480, T_7483) node T_7485 = asSInt(T_7470) node T_7487 = eq(T_7485, asSInt(UInt<1>("h01"))) node T_7488 = bit(T_7470, 0) node T_7489 = mux(T_7484, T_7487, T_7488) node T_7490 = mux(T_7475, T_7477, T_7489) node T_7491 = bits(mem_reg_wdata, 38, 0) node T_7492 = cat(T_7490, T_7491) node T_7493 = asSInt(T_7492) node T_7494 = mux(mem_ctrl.jalr, T_7493, mem_br_target) node T_7496 = and(T_7494, asSInt(UInt<2>("h02"))) node mem_npc = asUInt(T_7496) node T_7498 = neq(mem_npc, ex_reg_pc) node T_7500 = eq(ex_reg_valid, UInt<1>("h00")) node mem_wrong_npc = or(T_7498, T_7500) node mem_npc_misaligned = bit(mem_npc, 1) node T_7503 = and(mem_wrong_npc, mem_reg_valid) node T_7504 = or(mem_ctrl.branch, mem_ctrl.jalr) node T_7505 = or(T_7504, mem_ctrl.jal) node mem_misprediction = and(T_7503, T_7505) node T_7507 = or(mem_misprediction, mem_reg_flush_pipe) node want_take_pc_mem = and(mem_reg_valid, T_7507) node T_7510 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_7511 = and(want_take_pc_mem, T_7510) take_pc_mem <= T_7511 node T_7513 = eq(ctrl_killx, UInt<1>("h00")) mem_reg_valid <= T_7513 node T_7515 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_7516 = and(T_7515, replay_ex) mem_reg_replay <= T_7516 node T_7518 = eq(ctrl_killx, UInt<1>("h00")) node T_7519 = and(T_7518, ex_xcpt) mem_reg_xcpt <= T_7519 node T_7521 = eq(take_pc_mem_wb, UInt<1>("h00")) node T_7522 = and(T_7521, ex_reg_xcpt_interrupt) mem_reg_xcpt_interrupt <= T_7522 when ex_xcpt : mem_reg_cause <= ex_cause skip node T_7523 = or(ex_reg_valid, ex_reg_xcpt_interrupt) when T_7523 : mem_ctrl <- ex_ctrl mem_reg_btb_hit <= ex_reg_btb_hit when ex_reg_btb_hit : mem_reg_btb_resp <- ex_reg_btb_resp skip mem_reg_flush_pipe <= ex_reg_flush_pipe mem_reg_slow_bypass <= ex_slow_bypass mem_reg_inst <= ex_reg_inst mem_reg_pc <= ex_reg_pc mem_reg_wdata <= alu.io.out node T_7524 = or(ex_ctrl.mem, ex_ctrl.rocc) node T_7525 = and(ex_ctrl.rxs2, T_7524) when T_7525 : mem_reg_rs2 <= T_7130 skip skip node T_7526 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) node T_7527 = and(want_take_pc_mem, mem_npc_misaligned) node T_7529 = and(mem_reg_valid, mem_ctrl.mem) node T_7530 = and(T_7529, io.dmem.xcpt.ma.st) node T_7532 = and(mem_reg_valid, mem_ctrl.mem) node T_7533 = and(T_7532, io.dmem.xcpt.ma.ld) node T_7535 = and(mem_reg_valid, mem_ctrl.mem) node T_7536 = and(T_7535, io.dmem.xcpt.pf.st) node T_7538 = and(mem_reg_valid, mem_ctrl.mem) node T_7539 = and(T_7538, io.dmem.xcpt.pf.ld) node T_7541 = or(T_7526, T_7527) node T_7542 = or(T_7541, T_7530) node T_7543 = or(T_7542, T_7533) node T_7544 = or(T_7543, T_7536) node mem_xcpt = or(T_7544, T_7539) node T_7546 = mux(T_7536, UInt<3>("h07"), UInt<3>("h05")) node T_7547 = mux(T_7533, UInt<3>("h04"), T_7546) node T_7548 = mux(T_7530, UInt<3>("h06"), T_7547) node T_7549 = mux(T_7527, UInt<1>("h00"), T_7548) node mem_cause = mux(T_7526, mem_reg_cause, T_7549) node T_7551 = and(mem_reg_valid, mem_ctrl.wxd) node dcache_kill_mem = and(T_7551, io.dmem.replay_next.valid) node T_7553 = and(mem_reg_valid, mem_ctrl.fp) node fpu_kill_mem = and(T_7553, io.fpu.nack_mem) node T_7555 = or(dcache_kill_mem, mem_reg_replay) node replay_mem = or(T_7555, fpu_kill_mem) node T_7557 = or(dcache_kill_mem, take_pc_wb) node T_7558 = or(T_7557, mem_reg_xcpt) node T_7560 = eq(mem_reg_valid, UInt<1>("h00")) node killm_common = or(T_7558, T_7560) node T_7562 = and(div.io.req.ready, div.io.req.valid) reg T_7563 : UInt<1>, clk, UInt<1>("h00"), T_7563 T_7563 <= T_7562 node T_7564 = and(killm_common, T_7563) div.io.kill <= T_7564 node T_7565 = or(killm_common, mem_xcpt) node ctrl_killm = or(T_7565, fpu_kill_mem) node T_7568 = eq(ctrl_killm, UInt<1>("h00")) wb_reg_valid <= T_7568 node T_7570 = eq(take_pc_wb, UInt<1>("h00")) node T_7571 = and(replay_mem, T_7570) wb_reg_replay <= T_7571 node T_7573 = eq(take_pc_wb, UInt<1>("h00")) node T_7574 = and(mem_xcpt, T_7573) wb_reg_xcpt <= T_7574 when mem_xcpt : wb_reg_cause <= mem_cause skip node T_7575 = or(mem_reg_valid, mem_reg_replay) node T_7576 = or(T_7575, mem_reg_xcpt_interrupt) when T_7576 : wb_ctrl <- mem_ctrl node T_7577 = and(mem_ctrl.fp, mem_ctrl.wxd) node T_7578 = mux(T_7577, io.fpu.toint_data, mem_int_wdata) wb_reg_wdata <= T_7578 when mem_ctrl.rocc : wb_reg_rs2 <= mem_reg_rs2 skip wb_reg_inst <= mem_reg_inst wb_reg_pc <= mem_reg_pc skip node T_7579 = or(wb_ctrl.div, wb_dcache_miss) node wb_set_sboard = or(T_7579, wb_ctrl.rocc) node replay_wb_common = or(io.dmem.resp.bits.nack, wb_reg_replay) node T_7582 = and(wb_reg_valid, wb_ctrl.rocc) node T_7584 = eq(replay_wb_common, UInt<1>("h00")) node wb_rocc_val = and(T_7582, T_7584) node T_7586 = and(wb_reg_valid, wb_ctrl.rocc) node T_7588 = eq(io.rocc.cmd.ready, UInt<1>("h00")) node T_7589 = and(T_7586, T_7588) node replay_wb = or(replay_wb_common, T_7589) node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) node T_7592 = or(replay_wb, wb_xcpt) node T_7593 = or(T_7592, csr.io.eret) take_pc_wb <= T_7593 when wb_rocc_val : node T_7595 = eq(io.rocc.cmd.ready, UInt<1>("h00")) wb_reg_rocc_pending <= T_7595 skip when wb_reg_xcpt : wb_reg_rocc_pending <= UInt<1>("h00") skip node T_7597 = bit(io.dmem.resp.bits.tag, 0) node T_7598 = bit(T_7597, 0) node dmem_resp_xpu = eq(T_7598, UInt<1>("h00")) node T_7601 = bit(io.dmem.resp.bits.tag, 0) node dmem_resp_fpu = bit(T_7601, 0) node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data) node T_7606 = and(wb_reg_valid, wb_ctrl.wxd) node T_7608 = eq(T_7606, UInt<1>("h00")) div.io.resp.ready <= T_7608 wire ll_wdata : UInt ll_wdata <= div.io.resp.bits.data wire ll_waddr : UInt ll_waddr <= div.io.resp.bits.tag node T_7611 = and(div.io.resp.ready, div.io.resp.valid) wire ll_wen : UInt<1> ll_wen <= T_7611 node T_7613 = and(dmem_resp_replay, dmem_resp_xpu) when T_7613 : div.io.resp.ready <= UInt<1>("h00") ll_waddr <= dmem_resp_waddr ll_wen <= UInt<1>("h01") skip node T_7617 = eq(replay_wb, UInt<1>("h00")) node T_7618 = and(wb_reg_valid, T_7617) node T_7620 = eq(csr.io.csr_xcpt, UInt<1>("h00")) node wb_valid = and(T_7618, T_7620) node wb_wen = and(wb_valid, wb_ctrl.wxd) node rf_wen = or(wb_wen, ll_wen) node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) node T_7625 = and(dmem_resp_valid, dmem_resp_xpu) node T_7626 = neq(wb_ctrl.csr, UInt<3>("h00")) node T_7627 = mux(T_7626, csr.io.rw.rdata, wb_reg_wdata) node T_7628 = mux(ll_wen, ll_wdata, T_7627) node rf_wdata = mux(T_7625, io.dmem.resp.bits.data, T_7628) when rf_wen : node T_7631 = neq(rf_waddr, UInt<1>("h00")) when T_7631 : node T_7632 = bits(rf_waddr, 4, 0) node T_7633 = not(T_7632) infer mport T_7634 = T_6795[T_7633], clk T_7634 <= rf_wdata node T_7635 = eq(rf_waddr, id_raddr1) when T_7635 : T_6797 <= rf_wdata skip node T_7636 = eq(rf_waddr, id_raddr2) when T_7636 : T_6809 <= rf_wdata skip skip skip csr.io.exception <= wb_reg_xcpt csr.io.cause <= wb_reg_cause csr.io.retire <= wb_valid io.host <- csr.io.host io.fpu.fcsr_rm <= csr.io.fcsr_rm csr.io.fcsr_flags <- io.fpu.fcsr_flags csr.io.rocc <- io.rocc csr.io.pc <= wb_reg_pc csr.io.uarch_counters[0] <= UInt<1>("h00") csr.io.uarch_counters[1] <= UInt<1>("h00") csr.io.uarch_counters[2] <= UInt<1>("h00") csr.io.uarch_counters[3] <= UInt<1>("h00") csr.io.uarch_counters[4] <= UInt<1>("h00") csr.io.uarch_counters[5] <= UInt<1>("h00") csr.io.uarch_counters[6] <= UInt<1>("h00") csr.io.uarch_counters[7] <= UInt<1>("h00") csr.io.uarch_counters[8] <= UInt<1>("h00") csr.io.uarch_counters[9] <= UInt<1>("h00") csr.io.uarch_counters[10] <= UInt<1>("h00") csr.io.uarch_counters[11] <= UInt<1>("h00") csr.io.uarch_counters[12] <= UInt<1>("h00") csr.io.uarch_counters[13] <= UInt<1>("h00") csr.io.uarch_counters[14] <= UInt<1>("h00") csr.io.uarch_counters[15] <= UInt<1>("h00") io.ptw.ptbr <= csr.io.ptbr io.ptw.invalidate <= csr.io.fatc io.ptw.status <- csr.io.status node T_7653 = bits(wb_reg_inst, 31, 20) csr.io.rw.addr <= T_7653 node T_7654 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) csr.io.rw.cmd <= T_7654 csr.io.rw.wdata <= wb_reg_wdata node T_7656 = neq(id_raddr1, UInt<1>("h00")) node T_7657 = and(id_ctrl.rxs1, T_7656) node T_7659 = neq(id_raddr2, UInt<1>("h00")) node T_7660 = and(id_ctrl.rxs2, T_7659) node T_7662 = neq(id_waddr, UInt<1>("h00")) node T_7663 = and(id_ctrl.wxd, T_7662) reg T_7665 : UInt<32>, clk, reset, UInt<32>("h00") node T_7668 = dshl(UInt<1>("h01"), ll_waddr) node T_7670 = mux(ll_wen, T_7668, UInt<1>("h00")) node T_7671 = not(T_7670) node T_7672 = and(T_7665, T_7671) node T_7673 = or(UInt<1>("h00"), ll_wen) when T_7673 : T_7665 <= T_7672 skip node T_7674 = dshr(T_7672, id_raddr1) node T_7675 = bit(T_7674, 0) node T_7676 = and(T_7657, T_7675) node T_7677 = dshr(T_7672, id_raddr2) node T_7678 = bit(T_7677, 0) node T_7679 = and(T_7660, T_7678) node T_7680 = dshr(T_7672, id_waddr) node T_7681 = bit(T_7680, 0) node T_7682 = and(T_7663, T_7681) node T_7683 = or(T_7676, T_7679) node id_sboard_hazard = or(T_7683, T_7682) node T_7685 = and(wb_set_sboard, wb_wen) node T_7687 = dshl(UInt<1>("h01"), wb_waddr) node T_7689 = mux(T_7685, T_7687, UInt<1>("h00")) node T_7690 = or(T_7672, T_7689) node T_7691 = or(T_7673, T_7685) when T_7691 : T_7665 <= T_7690 skip node T_7692 = neq(ex_ctrl.csr, UInt<3>("h00")) node T_7693 = or(T_7692, ex_ctrl.jalr) node T_7694 = or(T_7693, ex_ctrl.mem) node T_7695 = or(T_7694, ex_ctrl.div) node T_7696 = or(T_7695, ex_ctrl.fp) node ex_cannot_bypass = or(T_7696, ex_ctrl.rocc) node T_7698 = eq(id_raddr1, ex_waddr) node T_7699 = and(T_7657, T_7698) node T_7700 = eq(id_raddr2, ex_waddr) node T_7701 = and(T_7660, T_7700) node T_7702 = eq(id_waddr, ex_waddr) node T_7703 = and(T_7663, T_7702) node T_7704 = or(T_7699, T_7701) node T_7705 = or(T_7704, T_7703) node data_hazard_ex = and(ex_ctrl.wxd, T_7705) node T_7707 = eq(id_raddr1, ex_waddr) node T_7708 = and(io.fpu.dec.ren1, T_7707) node T_7709 = eq(id_raddr2, ex_waddr) node T_7710 = and(io.fpu.dec.ren2, T_7709) node T_7711 = eq(id_raddr3, ex_waddr) node T_7712 = and(io.fpu.dec.ren3, T_7711) node T_7713 = eq(id_waddr, ex_waddr) node T_7714 = and(io.fpu.dec.wen, T_7713) node T_7715 = or(T_7708, T_7710) node T_7716 = or(T_7715, T_7712) node T_7717 = or(T_7716, T_7714) node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7717) node T_7719 = and(data_hazard_ex, ex_cannot_bypass) node T_7720 = or(T_7719, fp_data_hazard_ex) node id_ex_hazard = and(ex_reg_valid, T_7720) node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) node T_7724 = neq(mem_ctrl.csr, UInt<3>("h00")) node T_7725 = and(mem_ctrl.mem, mem_mem_cmd_bh) node T_7726 = or(T_7724, T_7725) node T_7727 = or(T_7726, mem_ctrl.div) node T_7728 = or(T_7727, mem_ctrl.fp) node mem_cannot_bypass = or(T_7728, mem_ctrl.rocc) node T_7730 = eq(id_raddr1, mem_waddr) node T_7731 = and(T_7657, T_7730) node T_7732 = eq(id_raddr2, mem_waddr) node T_7733 = and(T_7660, T_7732) node T_7734 = eq(id_waddr, mem_waddr) node T_7735 = and(T_7663, T_7734) node T_7736 = or(T_7731, T_7733) node T_7737 = or(T_7736, T_7735) node data_hazard_mem = and(mem_ctrl.wxd, T_7737) node T_7739 = eq(id_raddr1, mem_waddr) node T_7740 = and(io.fpu.dec.ren1, T_7739) node T_7741 = eq(id_raddr2, mem_waddr) node T_7742 = and(io.fpu.dec.ren2, T_7741) node T_7743 = eq(id_raddr3, mem_waddr) node T_7744 = and(io.fpu.dec.ren3, T_7743) node T_7745 = eq(id_waddr, mem_waddr) node T_7746 = and(io.fpu.dec.wen, T_7745) node T_7747 = or(T_7740, T_7742) node T_7748 = or(T_7747, T_7744) node T_7749 = or(T_7748, T_7746) node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7749) node T_7751 = and(data_hazard_mem, mem_cannot_bypass) node T_7752 = or(T_7751, fp_data_hazard_mem) node id_mem_hazard = and(mem_reg_valid, T_7752) node T_7754 = and(mem_reg_valid, data_hazard_mem) node T_7755 = and(T_7754, mem_ctrl.mem) id_load_use <= T_7755 node T_7756 = eq(id_raddr1, wb_waddr) node T_7757 = and(T_7657, T_7756) node T_7758 = eq(id_raddr2, wb_waddr) node T_7759 = and(T_7660, T_7758) node T_7760 = eq(id_waddr, wb_waddr) node T_7761 = and(T_7663, T_7760) node T_7762 = or(T_7757, T_7759) node T_7763 = or(T_7762, T_7761) node data_hazard_wb = and(wb_ctrl.wxd, T_7763) node T_7765 = eq(id_raddr1, wb_waddr) node T_7766 = and(io.fpu.dec.ren1, T_7765) node T_7767 = eq(id_raddr2, wb_waddr) node T_7768 = and(io.fpu.dec.ren2, T_7767) node T_7769 = eq(id_raddr3, wb_waddr) node T_7770 = and(io.fpu.dec.ren3, T_7769) node T_7771 = eq(id_waddr, wb_waddr) node T_7772 = and(io.fpu.dec.wen, T_7771) node T_7773 = or(T_7766, T_7768) node T_7774 = or(T_7773, T_7770) node T_7775 = or(T_7774, T_7772) node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7775) node T_7777 = and(data_hazard_wb, wb_set_sboard) node T_7778 = or(T_7777, fp_data_hazard_wb) node id_wb_hazard = and(wb_reg_valid, T_7778) reg T_7781 : UInt<32>, clk, reset, UInt<32>("h00") node T_7783 = and(wb_dcache_miss, wb_ctrl.wfd) node T_7784 = or(T_7783, io.fpu.sboard_set) node T_7785 = and(T_7784, wb_valid) node T_7787 = dshl(UInt<1>("h01"), wb_waddr) node T_7789 = mux(T_7785, T_7787, UInt<1>("h00")) node T_7790 = or(T_7781, T_7789) node T_7791 = or(UInt<1>("h00"), T_7785) when T_7791 : T_7781 <= T_7790 skip node T_7792 = and(dmem_resp_replay, dmem_resp_fpu) node T_7794 = dshl(UInt<1>("h01"), dmem_resp_waddr) node T_7796 = mux(T_7792, T_7794, UInt<1>("h00")) node T_7797 = not(T_7796) node T_7798 = and(T_7790, T_7797) node T_7799 = or(T_7791, T_7792) when T_7799 : T_7781 <= T_7798 skip node T_7801 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) node T_7803 = mux(io.fpu.sboard_clr, T_7801, UInt<1>("h00")) node T_7804 = not(T_7803) node T_7805 = and(T_7798, T_7804) node T_7806 = or(T_7799, io.fpu.sboard_clr) when T_7806 : T_7781 <= T_7805 skip node T_7808 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) node T_7809 = and(id_csr_en, T_7808) node T_7810 = dshr(T_7781, id_raddr1) node T_7811 = bit(T_7810, 0) node T_7812 = and(io.fpu.dec.ren1, T_7811) node T_7813 = dshr(T_7781, id_raddr2) node T_7814 = bit(T_7813, 0) node T_7815 = and(io.fpu.dec.ren2, T_7814) node T_7816 = dshr(T_7781, id_raddr3) node T_7817 = bit(T_7816, 0) node T_7818 = and(io.fpu.dec.ren3, T_7817) node T_7819 = dshr(T_7781, id_waddr) node T_7820 = bit(T_7819, 0) node T_7821 = and(io.fpu.dec.wen, T_7820) node T_7822 = or(T_7812, T_7815) node T_7823 = or(T_7822, T_7818) node T_7824 = or(T_7823, T_7821) node id_stall_fpu = or(T_7809, T_7824) node T_7826 = or(id_ex_hazard, id_mem_hazard) node T_7827 = or(T_7826, id_wb_hazard) node T_7828 = or(T_7827, id_sboard_hazard) node T_7829 = and(id_ctrl.fp, id_stall_fpu) node T_7830 = or(T_7828, T_7829) node T_7832 = eq(io.dmem.req.ready, UInt<1>("h00")) node T_7833 = and(id_ctrl.mem, T_7832) node T_7834 = or(T_7830, T_7833) node T_7836 = and(UInt<1>("h00"), wb_reg_rocc_pending) node T_7837 = and(T_7836, id_ctrl.rocc) node T_7839 = eq(io.rocc.cmd.ready, UInt<1>("h00")) node T_7840 = and(T_7837, T_7839) node T_7841 = or(T_7834, T_7840) node T_7842 = or(T_7841, id_do_fence) node ctrl_stalld = or(T_7842, csr.io.csr_stall) node T_7845 = eq(io.imem.resp.valid, UInt<1>("h00")) node T_7846 = or(T_7845, take_pc_mem_wb) node T_7847 = or(T_7846, ctrl_stalld) node T_7848 = or(T_7847, csr.io.interrupt) ctrl_killd <= T_7848 io.imem.req.valid <= take_pc_mem_wb node T_7849 = or(wb_xcpt, csr.io.eret) node T_7850 = mux(replay_wb, wb_reg_pc, mem_npc) node T_7851 = mux(T_7849, csr.io.evec, T_7850) io.imem.req.bits.pc <= T_7851 node T_7852 = and(wb_reg_valid, wb_ctrl.fence_i) io.imem.invalidate <= T_7852 node T_7854 = eq(ctrl_stalld, UInt<1>("h00")) node T_7855 = or(T_7854, csr.io.interrupt) io.imem.resp.ready <= T_7855 node T_7857 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_7858 = and(mem_reg_valid, T_7857) node T_7859 = and(T_7858, mem_wrong_npc) node T_7860 = and(mem_ctrl.branch, mem_br_taken) node T_7861 = or(T_7860, mem_ctrl.jalr) node T_7862 = or(T_7861, mem_ctrl.jal) node T_7863 = and(T_7859, T_7862) node T_7865 = eq(take_pc_wb, UInt<1>("h00")) node T_7866 = and(T_7863, T_7865) io.imem.btb_update.valid <= T_7866 node T_7867 = or(mem_ctrl.jal, mem_ctrl.jalr) io.imem.btb_update.bits.isJump <= T_7867 node T_7868 = bits(mem_reg_inst, 19, 15) node T_7871 = and(T_7868, UInt<5>("h019")) node T_7872 = eq(UInt<1>("h01"), T_7871) node T_7873 = and(mem_ctrl.jalr, T_7872) io.imem.btb_update.bits.isReturn <= T_7873 io.imem.btb_update.bits.pc <= mem_reg_pc io.imem.btb_update.bits.target <= io.imem.req.bits.pc io.imem.btb_update.bits.br_pc <= mem_reg_pc io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp node T_7874 = and(mem_reg_valid, mem_ctrl.branch) node T_7876 = eq(take_pc_wb, UInt<1>("h00")) node T_7877 = and(T_7874, T_7876) io.imem.bht_update.valid <= T_7877 io.imem.bht_update.bits.pc <= mem_reg_pc io.imem.bht_update.bits.taken <= mem_br_taken io.imem.bht_update.bits.mispredict <= mem_wrong_npc io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction node T_7878 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) node T_7880 = eq(mem_npc_misaligned, UInt<1>("h00")) node T_7881 = and(T_7878, T_7880) node T_7883 = eq(take_pc_wb, UInt<1>("h00")) node T_7884 = and(T_7881, T_7883) io.imem.ras_update.valid <= T_7884 io.imem.ras_update.bits.returnAddr <= mem_int_wdata node T_7885 = bit(mem_waddr, 0) node T_7886 = and(mem_ctrl.wxd, T_7885) io.imem.ras_update.bits.isCall <= T_7886 io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction node T_7888 = eq(ctrl_killd, UInt<1>("h00")) node T_7889 = and(T_7888, id_ctrl.fp) io.fpu.valid <= T_7889 io.fpu.killx <= ctrl_killx io.fpu.killm <= killm_common io.fpu.inst <= io.imem.resp.bits.data[0] io.fpu.fromint_data <= T_7127 node T_7890 = and(dmem_resp_valid, dmem_resp_fpu) io.fpu.dmem_resp_val <= T_7890 io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ io.fpu.dmem_resp_tag <= dmem_resp_waddr node T_7891 = and(ex_reg_valid, ex_ctrl.mem) io.dmem.req.valid <= T_7891 node T_7892 = or(killm_common, mem_xcpt) io.dmem.req.bits.kill <= T_7892 io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd io.dmem.req.bits.typ <= ex_ctrl.mem_type io.dmem.req.bits.phys <= UInt<1>("h00") node T_7894 = shr(T_7127, 38) node T_7895 = bits(alu.io.adder_out, 39, 38) node T_7897 = eq(T_7894, UInt<1>("h00")) node T_7899 = eq(T_7894, UInt<1>("h01")) node T_7900 = or(T_7897, T_7899) node T_7902 = neq(T_7895, UInt<1>("h00")) node T_7903 = asSInt(T_7894) node T_7905 = eq(T_7903, asSInt(UInt<1>("h01"))) node T_7906 = asSInt(T_7894) node T_7908 = eq(T_7906, asSInt(UInt<2>("h02"))) node T_7909 = or(T_7905, T_7908) node T_7910 = asSInt(T_7895) node T_7912 = eq(T_7910, asSInt(UInt<1>("h01"))) node T_7913 = bit(T_7895, 0) node T_7914 = mux(T_7909, T_7912, T_7913) node T_7915 = mux(T_7900, T_7902, T_7914) node T_7916 = bits(alu.io.adder_out, 38, 0) node T_7917 = cat(T_7915, T_7916) io.dmem.req.bits.addr <= T_7917 node T_7918 = cat(ex_waddr, ex_ctrl.fp) io.dmem.req.bits.tag <= T_7918 node T_7919 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) io.dmem.req.bits.data <= T_7919 io.dmem.invalidate_lr <= wb_xcpt io.rocc.cmd.valid <= wb_rocc_val node T_7921 = neq(csr.io.status.xs, UInt<1>("h00")) node T_7922 = and(wb_xcpt, T_7921) io.rocc.exception <= T_7922 node T_7924 = neq(csr.io.status.prv, UInt<1>("h00")) io.rocc.s <= T_7924 wire T_7943 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} T_7943.opcode <= UInt<1>("h00") T_7943.rd <= UInt<1>("h00") T_7943.xs2 <= UInt<1>("h00") T_7943.xs1 <= UInt<1>("h00") T_7943.xd <= UInt<1>("h00") T_7943.rs1 <= UInt<1>("h00") T_7943.rs2 <= UInt<1>("h00") T_7943.funct <= UInt<1>("h00") node T_7960 = bits(wb_reg_inst, 6, 0) T_7943.opcode <= T_7960 node T_7961 = bits(wb_reg_inst, 11, 7) T_7943.rd <= T_7961 node T_7962 = bits(wb_reg_inst, 12, 12) T_7943.xs2 <= T_7962 node T_7963 = bits(wb_reg_inst, 13, 13) T_7943.xs1 <= T_7963 node T_7964 = bits(wb_reg_inst, 14, 14) T_7943.xd <= T_7964 node T_7965 = bits(wb_reg_inst, 19, 15) T_7943.rs1 <= T_7965 node T_7966 = bits(wb_reg_inst, 24, 20) T_7943.rs2 <= T_7966 node T_7967 = bits(wb_reg_inst, 31, 25) T_7943.funct <= T_7967 io.rocc.cmd.bits.inst <- T_7943 io.rocc.cmd.bits.rs1 <= wb_reg_wdata io.rocc.cmd.bits.rs2 <= wb_reg_rs2 node T_7968 = bits(csr.io.time, 32, 0) node T_7970 = mux(rf_wen, rf_waddr, UInt<1>("h00")) node T_7971 = bits(wb_reg_inst, 19, 15) reg T_7972 : UInt, clk, UInt<1>("h00"), T_7972 T_7972 <= T_7127 reg T_7973 : UInt, clk, UInt<1>("h00"), T_7973 T_7973 <= T_7972 node T_7974 = bits(wb_reg_inst, 24, 20) reg T_7975 : UInt, clk, UInt<1>("h00"), T_7975 T_7975 <= T_7130 reg T_7976 : UInt, clk, UInt<1>("h00"), T_7976 T_7976 <= T_7975 node T_7978 = eq(reset, UInt<1>("h00")) when T_7978 : printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x) ", io.host.id, T_7968, wb_valid, wb_reg_pc, T_7970, rf_wdata, rf_wen, T_7971, T_7973, T_7974, T_7976, wb_reg_inst, wb_reg_inst) skip module BTB : input clk : Clock input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>} io.resp.bits.bht.value <= UInt<1>("h00") io.resp.bits.bht.history <= UInt<1>("h00") io.resp.bits.entry <= UInt<1>("h00") io.resp.bits.target <= UInt<1>("h00") io.resp.bits.bridx <= UInt<1>("h00") io.resp.bits.mask <= UInt<1>("h00") io.resp.bits.taken <= UInt<1>("h00") io.resp.valid <= UInt<1>("h00") reg idxValid : UInt<62>, clk, reset, UInt<62>("h00") cmem idxs : UInt<12>[62] cmem idxPages : UInt<3>[62] cmem tgts : UInt<12>[62] cmem tgtPages : UInt<3>[62] cmem pages : UInt<27>[6] reg pageValid : UInt<6>, clk, reset, UInt<6>("h00") infer mport T_590 = idxPages[UInt<1>("h00")], clk node T_592 = dshl(UInt<1>("h01"), T_590) node T_593 = bits(T_592, 5, 0) infer mport T_595 = idxPages[UInt<1>("h01")], clk node T_597 = dshl(UInt<1>("h01"), T_595) node T_598 = bits(T_597, 5, 0) infer mport T_600 = idxPages[UInt<2>("h02")], clk node T_602 = dshl(UInt<1>("h01"), T_600) node T_603 = bits(T_602, 5, 0) infer mport T_605 = idxPages[UInt<2>("h03")], clk node T_607 = dshl(UInt<1>("h01"), T_605) node T_608 = bits(T_607, 5, 0) infer mport T_610 = idxPages[UInt<3>("h04")], clk node T_612 = dshl(UInt<1>("h01"), T_610) node T_613 = bits(T_612, 5, 0) infer mport T_615 = idxPages[UInt<3>("h05")], clk node T_617 = dshl(UInt<1>("h01"), T_615) node T_618 = bits(T_617, 5, 0) infer mport T_620 = idxPages[UInt<3>("h06")], clk node T_622 = dshl(UInt<1>("h01"), T_620) node T_623 = bits(T_622, 5, 0) infer mport T_625 = idxPages[UInt<3>("h07")], clk node T_627 = dshl(UInt<1>("h01"), T_625) node T_628 = bits(T_627, 5, 0) infer mport T_630 = idxPages[UInt<4>("h08")], clk node T_632 = dshl(UInt<1>("h01"), T_630) node T_633 = bits(T_632, 5, 0) infer mport T_635 = idxPages[UInt<4>("h09")], clk node T_637 = dshl(UInt<1>("h01"), T_635) node T_638 = bits(T_637, 5, 0) infer mport T_640 = idxPages[UInt<4>("h0a")], clk node T_642 = dshl(UInt<1>("h01"), T_640) node T_643 = bits(T_642, 5, 0) infer mport T_645 = idxPages[UInt<4>("h0b")], clk node T_647 = dshl(UInt<1>("h01"), T_645) node T_648 = bits(T_647, 5, 0) infer mport T_650 = idxPages[UInt<4>("h0c")], clk node T_652 = dshl(UInt<1>("h01"), T_650) node T_653 = bits(T_652, 5, 0) infer mport T_655 = idxPages[UInt<4>("h0d")], clk node T_657 = dshl(UInt<1>("h01"), T_655) node T_658 = bits(T_657, 5, 0) infer mport T_660 = idxPages[UInt<4>("h0e")], clk node T_662 = dshl(UInt<1>("h01"), T_660) node T_663 = bits(T_662, 5, 0) infer mport T_665 = idxPages[UInt<4>("h0f")], clk node T_667 = dshl(UInt<1>("h01"), T_665) node T_668 = bits(T_667, 5, 0) infer mport T_670 = idxPages[UInt<5>("h010")], clk node T_672 = dshl(UInt<1>("h01"), T_670) node T_673 = bits(T_672, 5, 0) infer mport T_675 = idxPages[UInt<5>("h011")], clk node T_677 = dshl(UInt<1>("h01"), T_675) node T_678 = bits(T_677, 5, 0) infer mport T_680 = idxPages[UInt<5>("h012")], clk node T_682 = dshl(UInt<1>("h01"), T_680) node T_683 = bits(T_682, 5, 0) infer mport T_685 = idxPages[UInt<5>("h013")], clk node T_687 = dshl(UInt<1>("h01"), T_685) node T_688 = bits(T_687, 5, 0) infer mport T_690 = idxPages[UInt<5>("h014")], clk node T_692 = dshl(UInt<1>("h01"), T_690) node T_693 = bits(T_692, 5, 0) infer mport T_695 = idxPages[UInt<5>("h015")], clk node T_697 = dshl(UInt<1>("h01"), T_695) node T_698 = bits(T_697, 5, 0) infer mport T_700 = idxPages[UInt<5>("h016")], clk node T_702 = dshl(UInt<1>("h01"), T_700) node T_703 = bits(T_702, 5, 0) infer mport T_705 = idxPages[UInt<5>("h017")], clk node T_707 = dshl(UInt<1>("h01"), T_705) node T_708 = bits(T_707, 5, 0) infer mport T_710 = idxPages[UInt<5>("h018")], clk node T_712 = dshl(UInt<1>("h01"), T_710) node T_713 = bits(T_712, 5, 0) infer mport T_715 = idxPages[UInt<5>("h019")], clk node T_717 = dshl(UInt<1>("h01"), T_715) node T_718 = bits(T_717, 5, 0) infer mport T_720 = idxPages[UInt<5>("h01a")], clk node T_722 = dshl(UInt<1>("h01"), T_720) node T_723 = bits(T_722, 5, 0) infer mport T_725 = idxPages[UInt<5>("h01b")], clk node T_727 = dshl(UInt<1>("h01"), T_725) node T_728 = bits(T_727, 5, 0) infer mport T_730 = idxPages[UInt<5>("h01c")], clk node T_732 = dshl(UInt<1>("h01"), T_730) node T_733 = bits(T_732, 5, 0) infer mport T_735 = idxPages[UInt<5>("h01d")], clk node T_737 = dshl(UInt<1>("h01"), T_735) node T_738 = bits(T_737, 5, 0) infer mport T_740 = idxPages[UInt<5>("h01e")], clk node T_742 = dshl(UInt<1>("h01"), T_740) node T_743 = bits(T_742, 5, 0) infer mport T_745 = idxPages[UInt<5>("h01f")], clk node T_747 = dshl(UInt<1>("h01"), T_745) node T_748 = bits(T_747, 5, 0) infer mport T_750 = idxPages[UInt<6>("h020")], clk node T_752 = dshl(UInt<1>("h01"), T_750) node T_753 = bits(T_752, 5, 0) infer mport T_755 = idxPages[UInt<6>("h021")], clk node T_757 = dshl(UInt<1>("h01"), T_755) node T_758 = bits(T_757, 5, 0) infer mport T_760 = idxPages[UInt<6>("h022")], clk node T_762 = dshl(UInt<1>("h01"), T_760) node T_763 = bits(T_762, 5, 0) infer mport T_765 = idxPages[UInt<6>("h023")], clk node T_767 = dshl(UInt<1>("h01"), T_765) node T_768 = bits(T_767, 5, 0) infer mport T_770 = idxPages[UInt<6>("h024")], clk node T_772 = dshl(UInt<1>("h01"), T_770) node T_773 = bits(T_772, 5, 0) infer mport T_775 = idxPages[UInt<6>("h025")], clk node T_777 = dshl(UInt<1>("h01"), T_775) node T_778 = bits(T_777, 5, 0) infer mport T_780 = idxPages[UInt<6>("h026")], clk node T_782 = dshl(UInt<1>("h01"), T_780) node T_783 = bits(T_782, 5, 0) infer mport T_785 = idxPages[UInt<6>("h027")], clk node T_787 = dshl(UInt<1>("h01"), T_785) node T_788 = bits(T_787, 5, 0) infer mport T_790 = idxPages[UInt<6>("h028")], clk node T_792 = dshl(UInt<1>("h01"), T_790) node T_793 = bits(T_792, 5, 0) infer mport T_795 = idxPages[UInt<6>("h029")], clk node T_797 = dshl(UInt<1>("h01"), T_795) node T_798 = bits(T_797, 5, 0) infer mport T_800 = idxPages[UInt<6>("h02a")], clk node T_802 = dshl(UInt<1>("h01"), T_800) node T_803 = bits(T_802, 5, 0) infer mport T_805 = idxPages[UInt<6>("h02b")], clk node T_807 = dshl(UInt<1>("h01"), T_805) node T_808 = bits(T_807, 5, 0) infer mport T_810 = idxPages[UInt<6>("h02c")], clk node T_812 = dshl(UInt<1>("h01"), T_810) node T_813 = bits(T_812, 5, 0) infer mport T_815 = idxPages[UInt<6>("h02d")], clk node T_817 = dshl(UInt<1>("h01"), T_815) node T_818 = bits(T_817, 5, 0) infer mport T_820 = idxPages[UInt<6>("h02e")], clk node T_822 = dshl(UInt<1>("h01"), T_820) node T_823 = bits(T_822, 5, 0) infer mport T_825 = idxPages[UInt<6>("h02f")], clk node T_827 = dshl(UInt<1>("h01"), T_825) node T_828 = bits(T_827, 5, 0) infer mport T_830 = idxPages[UInt<6>("h030")], clk node T_832 = dshl(UInt<1>("h01"), T_830) node T_833 = bits(T_832, 5, 0) infer mport T_835 = idxPages[UInt<6>("h031")], clk node T_837 = dshl(UInt<1>("h01"), T_835) node T_838 = bits(T_837, 5, 0) infer mport T_840 = idxPages[UInt<6>("h032")], clk node T_842 = dshl(UInt<1>("h01"), T_840) node T_843 = bits(T_842, 5, 0) infer mport T_845 = idxPages[UInt<6>("h033")], clk node T_847 = dshl(UInt<1>("h01"), T_845) node T_848 = bits(T_847, 5, 0) infer mport T_850 = idxPages[UInt<6>("h034")], clk node T_852 = dshl(UInt<1>("h01"), T_850) node T_853 = bits(T_852, 5, 0) infer mport T_855 = idxPages[UInt<6>("h035")], clk node T_857 = dshl(UInt<1>("h01"), T_855) node T_858 = bits(T_857, 5, 0) infer mport T_860 = idxPages[UInt<6>("h036")], clk node T_862 = dshl(UInt<1>("h01"), T_860) node T_863 = bits(T_862, 5, 0) infer mport T_865 = idxPages[UInt<6>("h037")], clk node T_867 = dshl(UInt<1>("h01"), T_865) node T_868 = bits(T_867, 5, 0) infer mport T_870 = idxPages[UInt<6>("h038")], clk node T_872 = dshl(UInt<1>("h01"), T_870) node T_873 = bits(T_872, 5, 0) infer mport T_875 = idxPages[UInt<6>("h039")], clk node T_877 = dshl(UInt<1>("h01"), T_875) node T_878 = bits(T_877, 5, 0) infer mport T_880 = idxPages[UInt<6>("h03a")], clk node T_882 = dshl(UInt<1>("h01"), T_880) node T_883 = bits(T_882, 5, 0) infer mport T_885 = idxPages[UInt<6>("h03b")], clk node T_887 = dshl(UInt<1>("h01"), T_885) node T_888 = bits(T_887, 5, 0) infer mport T_890 = idxPages[UInt<6>("h03c")], clk node T_892 = dshl(UInt<1>("h01"), T_890) node T_893 = bits(T_892, 5, 0) infer mport T_895 = idxPages[UInt<6>("h03d")], clk node T_897 = dshl(UInt<1>("h01"), T_895) node T_898 = bits(T_897, 5, 0) infer mport T_900 = tgtPages[UInt<1>("h00")], clk node T_902 = dshl(UInt<1>("h01"), T_900) node T_903 = bits(T_902, 5, 0) infer mport T_905 = tgtPages[UInt<1>("h01")], clk node T_907 = dshl(UInt<1>("h01"), T_905) node T_908 = bits(T_907, 5, 0) infer mport T_910 = tgtPages[UInt<2>("h02")], clk node T_912 = dshl(UInt<1>("h01"), T_910) node T_913 = bits(T_912, 5, 0) infer mport T_915 = tgtPages[UInt<2>("h03")], clk node T_917 = dshl(UInt<1>("h01"), T_915) node T_918 = bits(T_917, 5, 0) infer mport T_920 = tgtPages[UInt<3>("h04")], clk node T_922 = dshl(UInt<1>("h01"), T_920) node T_923 = bits(T_922, 5, 0) infer mport T_925 = tgtPages[UInt<3>("h05")], clk node T_927 = dshl(UInt<1>("h01"), T_925) node T_928 = bits(T_927, 5, 0) infer mport T_930 = tgtPages[UInt<3>("h06")], clk node T_932 = dshl(UInt<1>("h01"), T_930) node T_933 = bits(T_932, 5, 0) infer mport T_935 = tgtPages[UInt<3>("h07")], clk node T_937 = dshl(UInt<1>("h01"), T_935) node T_938 = bits(T_937, 5, 0) infer mport T_940 = tgtPages[UInt<4>("h08")], clk node T_942 = dshl(UInt<1>("h01"), T_940) node T_943 = bits(T_942, 5, 0) infer mport T_945 = tgtPages[UInt<4>("h09")], clk node T_947 = dshl(UInt<1>("h01"), T_945) node T_948 = bits(T_947, 5, 0) infer mport T_950 = tgtPages[UInt<4>("h0a")], clk node T_952 = dshl(UInt<1>("h01"), T_950) node T_953 = bits(T_952, 5, 0) infer mport T_955 = tgtPages[UInt<4>("h0b")], clk node T_957 = dshl(UInt<1>("h01"), T_955) node T_958 = bits(T_957, 5, 0) infer mport T_960 = tgtPages[UInt<4>("h0c")], clk node T_962 = dshl(UInt<1>("h01"), T_960) node T_963 = bits(T_962, 5, 0) infer mport T_965 = tgtPages[UInt<4>("h0d")], clk node T_967 = dshl(UInt<1>("h01"), T_965) node T_968 = bits(T_967, 5, 0) infer mport T_970 = tgtPages[UInt<4>("h0e")], clk node T_972 = dshl(UInt<1>("h01"), T_970) node T_973 = bits(T_972, 5, 0) infer mport T_975 = tgtPages[UInt<4>("h0f")], clk node T_977 = dshl(UInt<1>("h01"), T_975) node T_978 = bits(T_977, 5, 0) infer mport T_980 = tgtPages[UInt<5>("h010")], clk node T_982 = dshl(UInt<1>("h01"), T_980) node T_983 = bits(T_982, 5, 0) infer mport T_985 = tgtPages[UInt<5>("h011")], clk node T_987 = dshl(UInt<1>("h01"), T_985) node T_988 = bits(T_987, 5, 0) infer mport T_990 = tgtPages[UInt<5>("h012")], clk node T_992 = dshl(UInt<1>("h01"), T_990) node T_993 = bits(T_992, 5, 0) infer mport T_995 = tgtPages[UInt<5>("h013")], clk node T_997 = dshl(UInt<1>("h01"), T_995) node T_998 = bits(T_997, 5, 0) infer mport T_1000 = tgtPages[UInt<5>("h014")], clk node T_1002 = dshl(UInt<1>("h01"), T_1000) node T_1003 = bits(T_1002, 5, 0) infer mport T_1005 = tgtPages[UInt<5>("h015")], clk node T_1007 = dshl(UInt<1>("h01"), T_1005) node T_1008 = bits(T_1007, 5, 0) infer mport T_1010 = tgtPages[UInt<5>("h016")], clk node T_1012 = dshl(UInt<1>("h01"), T_1010) node T_1013 = bits(T_1012, 5, 0) infer mport T_1015 = tgtPages[UInt<5>("h017")], clk node T_1017 = dshl(UInt<1>("h01"), T_1015) node T_1018 = bits(T_1017, 5, 0) infer mport T_1020 = tgtPages[UInt<5>("h018")], clk node T_1022 = dshl(UInt<1>("h01"), T_1020) node T_1023 = bits(T_1022, 5, 0) infer mport T_1025 = tgtPages[UInt<5>("h019")], clk node T_1027 = dshl(UInt<1>("h01"), T_1025) node T_1028 = bits(T_1027, 5, 0) infer mport T_1030 = tgtPages[UInt<5>("h01a")], clk node T_1032 = dshl(UInt<1>("h01"), T_1030) node T_1033 = bits(T_1032, 5, 0) infer mport T_1035 = tgtPages[UInt<5>("h01b")], clk node T_1037 = dshl(UInt<1>("h01"), T_1035) node T_1038 = bits(T_1037, 5, 0) infer mport T_1040 = tgtPages[UInt<5>("h01c")], clk node T_1042 = dshl(UInt<1>("h01"), T_1040) node T_1043 = bits(T_1042, 5, 0) infer mport T_1045 = tgtPages[UInt<5>("h01d")], clk node T_1047 = dshl(UInt<1>("h01"), T_1045) node T_1048 = bits(T_1047, 5, 0) infer mport T_1050 = tgtPages[UInt<5>("h01e")], clk node T_1052 = dshl(UInt<1>("h01"), T_1050) node T_1053 = bits(T_1052, 5, 0) infer mport T_1055 = tgtPages[UInt<5>("h01f")], clk node T_1057 = dshl(UInt<1>("h01"), T_1055) node T_1058 = bits(T_1057, 5, 0) infer mport T_1060 = tgtPages[UInt<6>("h020")], clk node T_1062 = dshl(UInt<1>("h01"), T_1060) node T_1063 = bits(T_1062, 5, 0) infer mport T_1065 = tgtPages[UInt<6>("h021")], clk node T_1067 = dshl(UInt<1>("h01"), T_1065) node T_1068 = bits(T_1067, 5, 0) infer mport T_1070 = tgtPages[UInt<6>("h022")], clk node T_1072 = dshl(UInt<1>("h01"), T_1070) node T_1073 = bits(T_1072, 5, 0) infer mport T_1075 = tgtPages[UInt<6>("h023")], clk node T_1077 = dshl(UInt<1>("h01"), T_1075) node T_1078 = bits(T_1077, 5, 0) infer mport T_1080 = tgtPages[UInt<6>("h024")], clk node T_1082 = dshl(UInt<1>("h01"), T_1080) node T_1083 = bits(T_1082, 5, 0) infer mport T_1085 = tgtPages[UInt<6>("h025")], clk node T_1087 = dshl(UInt<1>("h01"), T_1085) node T_1088 = bits(T_1087, 5, 0) infer mport T_1090 = tgtPages[UInt<6>("h026")], clk node T_1092 = dshl(UInt<1>("h01"), T_1090) node T_1093 = bits(T_1092, 5, 0) infer mport T_1095 = tgtPages[UInt<6>("h027")], clk node T_1097 = dshl(UInt<1>("h01"), T_1095) node T_1098 = bits(T_1097, 5, 0) infer mport T_1100 = tgtPages[UInt<6>("h028")], clk node T_1102 = dshl(UInt<1>("h01"), T_1100) node T_1103 = bits(T_1102, 5, 0) infer mport T_1105 = tgtPages[UInt<6>("h029")], clk node T_1107 = dshl(UInt<1>("h01"), T_1105) node T_1108 = bits(T_1107, 5, 0) infer mport T_1110 = tgtPages[UInt<6>("h02a")], clk node T_1112 = dshl(UInt<1>("h01"), T_1110) node T_1113 = bits(T_1112, 5, 0) infer mport T_1115 = tgtPages[UInt<6>("h02b")], clk node T_1117 = dshl(UInt<1>("h01"), T_1115) node T_1118 = bits(T_1117, 5, 0) infer mport T_1120 = tgtPages[UInt<6>("h02c")], clk node T_1122 = dshl(UInt<1>("h01"), T_1120) node T_1123 = bits(T_1122, 5, 0) infer mport T_1125 = tgtPages[UInt<6>("h02d")], clk node T_1127 = dshl(UInt<1>("h01"), T_1125) node T_1128 = bits(T_1127, 5, 0) infer mport T_1130 = tgtPages[UInt<6>("h02e")], clk node T_1132 = dshl(UInt<1>("h01"), T_1130) node T_1133 = bits(T_1132, 5, 0) infer mport T_1135 = tgtPages[UInt<6>("h02f")], clk node T_1137 = dshl(UInt<1>("h01"), T_1135) node T_1138 = bits(T_1137, 5, 0) infer mport T_1140 = tgtPages[UInt<6>("h030")], clk node T_1142 = dshl(UInt<1>("h01"), T_1140) node T_1143 = bits(T_1142, 5, 0) infer mport T_1145 = tgtPages[UInt<6>("h031")], clk node T_1147 = dshl(UInt<1>("h01"), T_1145) node T_1148 = bits(T_1147, 5, 0) infer mport T_1150 = tgtPages[UInt<6>("h032")], clk node T_1152 = dshl(UInt<1>("h01"), T_1150) node T_1153 = bits(T_1152, 5, 0) infer mport T_1155 = tgtPages[UInt<6>("h033")], clk node T_1157 = dshl(UInt<1>("h01"), T_1155) node T_1158 = bits(T_1157, 5, 0) infer mport T_1160 = tgtPages[UInt<6>("h034")], clk node T_1162 = dshl(UInt<1>("h01"), T_1160) node T_1163 = bits(T_1162, 5, 0) infer mport T_1165 = tgtPages[UInt<6>("h035")], clk node T_1167 = dshl(UInt<1>("h01"), T_1165) node T_1168 = bits(T_1167, 5, 0) infer mport T_1170 = tgtPages[UInt<6>("h036")], clk node T_1172 = dshl(UInt<1>("h01"), T_1170) node T_1173 = bits(T_1172, 5, 0) infer mport T_1175 = tgtPages[UInt<6>("h037")], clk node T_1177 = dshl(UInt<1>("h01"), T_1175) node T_1178 = bits(T_1177, 5, 0) infer mport T_1180 = tgtPages[UInt<6>("h038")], clk node T_1182 = dshl(UInt<1>("h01"), T_1180) node T_1183 = bits(T_1182, 5, 0) infer mport T_1185 = tgtPages[UInt<6>("h039")], clk node T_1187 = dshl(UInt<1>("h01"), T_1185) node T_1188 = bits(T_1187, 5, 0) infer mport T_1190 = tgtPages[UInt<6>("h03a")], clk node T_1192 = dshl(UInt<1>("h01"), T_1190) node T_1193 = bits(T_1192, 5, 0) infer mport T_1195 = tgtPages[UInt<6>("h03b")], clk node T_1197 = dshl(UInt<1>("h01"), T_1195) node T_1198 = bits(T_1197, 5, 0) infer mport T_1200 = tgtPages[UInt<6>("h03c")], clk node T_1202 = dshl(UInt<1>("h01"), T_1200) node T_1203 = bits(T_1202, 5, 0) infer mport T_1205 = tgtPages[UInt<6>("h03d")], clk node T_1207 = dshl(UInt<1>("h01"), T_1205) node T_1208 = bits(T_1207, 5, 0) reg useRAS : UInt<1>[62], clk, UInt<1>("h00"), useRAS reg isJump : UInt<1>[62], clk, UInt<1>("h00"), isJump cmem brIdx : UInt<1>[62] reg T_1478 : UInt<1>, clk, reset, UInt<1>("h00") T_1478 <= io.btb_update.valid reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk, UInt<1>("h00"), T_1479 when io.btb_update.valid : T_1479 <- io.btb_update.bits skip wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} r_btb_update.bits.br_pc <= UInt<1>("h00") r_btb_update.bits.isReturn <= UInt<1>("h00") r_btb_update.bits.isJump <= UInt<1>("h00") r_btb_update.bits.taken <= UInt<1>("h00") r_btb_update.bits.target <= UInt<1>("h00") r_btb_update.bits.pc <= UInt<1>("h00") r_btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") r_btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") r_btb_update.bits.prediction.bits.entry <= UInt<1>("h00") r_btb_update.bits.prediction.bits.target <= UInt<1>("h00") r_btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") r_btb_update.bits.prediction.bits.mask <= UInt<1>("h00") r_btb_update.bits.prediction.bits.taken <= UInt<1>("h00") r_btb_update.bits.prediction.valid <= UInt<1>("h00") r_btb_update.valid <= UInt<1>("h00") r_btb_update.valid <= T_1478 r_btb_update.bits <- T_1479 node T_1678 = shr(io.req.bits.addr, 12) infer mport T_1680 = pages[UInt<1>("h00")], clk node T_1681 = eq(T_1680, T_1678) infer mport T_1683 = pages[UInt<1>("h01")], clk node T_1684 = eq(T_1683, T_1678) infer mport T_1686 = pages[UInt<2>("h02")], clk node T_1687 = eq(T_1686, T_1678) infer mport T_1689 = pages[UInt<2>("h03")], clk node T_1690 = eq(T_1689, T_1678) infer mport T_1692 = pages[UInt<3>("h04")], clk node T_1693 = eq(T_1692, T_1678) infer mport T_1695 = pages[UInt<3>("h05")], clk node T_1696 = eq(T_1695, T_1678) wire T_1698 : UInt<1>[6] T_1698[0] <= T_1681 T_1698[1] <= T_1684 T_1698[2] <= T_1687 T_1698[3] <= T_1690 T_1698[4] <= T_1693 T_1698[5] <= T_1696 node T_1706 = cat(T_1698[4], T_1698[3]) node T_1707 = cat(T_1698[5], T_1706) node T_1708 = cat(T_1698[1], T_1698[0]) node T_1709 = cat(T_1698[2], T_1708) node T_1710 = cat(T_1707, T_1709) node pageHit = and(T_1710, pageValid) node T_1712 = bits(io.req.bits.addr, 11, 0) infer mport T_1714 = idxs[UInt<1>("h00")], clk node T_1715 = eq(T_1714, T_1712) infer mport T_1717 = idxs[UInt<1>("h01")], clk node T_1718 = eq(T_1717, T_1712) infer mport T_1720 = idxs[UInt<2>("h02")], clk node T_1721 = eq(T_1720, T_1712) infer mport T_1723 = idxs[UInt<2>("h03")], clk node T_1724 = eq(T_1723, T_1712) infer mport T_1726 = idxs[UInt<3>("h04")], clk node T_1727 = eq(T_1726, T_1712) infer mport T_1729 = idxs[UInt<3>("h05")], clk node T_1730 = eq(T_1729, T_1712) infer mport T_1732 = idxs[UInt<3>("h06")], clk node T_1733 = eq(T_1732, T_1712) infer mport T_1735 = idxs[UInt<3>("h07")], clk node T_1736 = eq(T_1735, T_1712) infer mport T_1738 = idxs[UInt<4>("h08")], clk node T_1739 = eq(T_1738, T_1712) infer mport T_1741 = idxs[UInt<4>("h09")], clk node T_1742 = eq(T_1741, T_1712) infer mport T_1744 = idxs[UInt<4>("h0a")], clk node T_1745 = eq(T_1744, T_1712) infer mport T_1747 = idxs[UInt<4>("h0b")], clk node T_1748 = eq(T_1747, T_1712) infer mport T_1750 = idxs[UInt<4>("h0c")], clk node T_1751 = eq(T_1750, T_1712) infer mport T_1753 = idxs[UInt<4>("h0d")], clk node T_1754 = eq(T_1753, T_1712) infer mport T_1756 = idxs[UInt<4>("h0e")], clk node T_1757 = eq(T_1756, T_1712) infer mport T_1759 = idxs[UInt<4>("h0f")], clk node T_1760 = eq(T_1759, T_1712) infer mport T_1762 = idxs[UInt<5>("h010")], clk node T_1763 = eq(T_1762, T_1712) infer mport T_1765 = idxs[UInt<5>("h011")], clk node T_1766 = eq(T_1765, T_1712) infer mport T_1768 = idxs[UInt<5>("h012")], clk node T_1769 = eq(T_1768, T_1712) infer mport T_1771 = idxs[UInt<5>("h013")], clk node T_1772 = eq(T_1771, T_1712) infer mport T_1774 = idxs[UInt<5>("h014")], clk node T_1775 = eq(T_1774, T_1712) infer mport T_1777 = idxs[UInt<5>("h015")], clk node T_1778 = eq(T_1777, T_1712) infer mport T_1780 = idxs[UInt<5>("h016")], clk node T_1781 = eq(T_1780, T_1712) infer mport T_1783 = idxs[UInt<5>("h017")], clk node T_1784 = eq(T_1783, T_1712) infer mport T_1786 = idxs[UInt<5>("h018")], clk node T_1787 = eq(T_1786, T_1712) infer mport T_1789 = idxs[UInt<5>("h019")], clk node T_1790 = eq(T_1789, T_1712) infer mport T_1792 = idxs[UInt<5>("h01a")], clk node T_1793 = eq(T_1792, T_1712) infer mport T_1795 = idxs[UInt<5>("h01b")], clk node T_1796 = eq(T_1795, T_1712) infer mport T_1798 = idxs[UInt<5>("h01c")], clk node T_1799 = eq(T_1798, T_1712) infer mport T_1801 = idxs[UInt<5>("h01d")], clk node T_1802 = eq(T_1801, T_1712) infer mport T_1804 = idxs[UInt<5>("h01e")], clk node T_1805 = eq(T_1804, T_1712) infer mport T_1807 = idxs[UInt<5>("h01f")], clk node T_1808 = eq(T_1807, T_1712) infer mport T_1810 = idxs[UInt<6>("h020")], clk node T_1811 = eq(T_1810, T_1712) infer mport T_1813 = idxs[UInt<6>("h021")], clk node T_1814 = eq(T_1813, T_1712) infer mport T_1816 = idxs[UInt<6>("h022")], clk node T_1817 = eq(T_1816, T_1712) infer mport T_1819 = idxs[UInt<6>("h023")], clk node T_1820 = eq(T_1819, T_1712) infer mport T_1822 = idxs[UInt<6>("h024")], clk node T_1823 = eq(T_1822, T_1712) infer mport T_1825 = idxs[UInt<6>("h025")], clk node T_1826 = eq(T_1825, T_1712) infer mport T_1828 = idxs[UInt<6>("h026")], clk node T_1829 = eq(T_1828, T_1712) infer mport T_1831 = idxs[UInt<6>("h027")], clk node T_1832 = eq(T_1831, T_1712) infer mport T_1834 = idxs[UInt<6>("h028")], clk node T_1835 = eq(T_1834, T_1712) infer mport T_1837 = idxs[UInt<6>("h029")], clk node T_1838 = eq(T_1837, T_1712) infer mport T_1840 = idxs[UInt<6>("h02a")], clk node T_1841 = eq(T_1840, T_1712) infer mport T_1843 = idxs[UInt<6>("h02b")], clk node T_1844 = eq(T_1843, T_1712) infer mport T_1846 = idxs[UInt<6>("h02c")], clk node T_1847 = eq(T_1846, T_1712) infer mport T_1849 = idxs[UInt<6>("h02d")], clk node T_1850 = eq(T_1849, T_1712) infer mport T_1852 = idxs[UInt<6>("h02e")], clk node T_1853 = eq(T_1852, T_1712) infer mport T_1855 = idxs[UInt<6>("h02f")], clk node T_1856 = eq(T_1855, T_1712) infer mport T_1858 = idxs[UInt<6>("h030")], clk node T_1859 = eq(T_1858, T_1712) infer mport T_1861 = idxs[UInt<6>("h031")], clk node T_1862 = eq(T_1861, T_1712) infer mport T_1864 = idxs[UInt<6>("h032")], clk node T_1865 = eq(T_1864, T_1712) infer mport T_1867 = idxs[UInt<6>("h033")], clk node T_1868 = eq(T_1867, T_1712) infer mport T_1870 = idxs[UInt<6>("h034")], clk node T_1871 = eq(T_1870, T_1712) infer mport T_1873 = idxs[UInt<6>("h035")], clk node T_1874 = eq(T_1873, T_1712) infer mport T_1876 = idxs[UInt<6>("h036")], clk node T_1877 = eq(T_1876, T_1712) infer mport T_1879 = idxs[UInt<6>("h037")], clk node T_1880 = eq(T_1879, T_1712) infer mport T_1882 = idxs[UInt<6>("h038")], clk node T_1883 = eq(T_1882, T_1712) infer mport T_1885 = idxs[UInt<6>("h039")], clk node T_1886 = eq(T_1885, T_1712) infer mport T_1888 = idxs[UInt<6>("h03a")], clk node T_1889 = eq(T_1888, T_1712) infer mport T_1891 = idxs[UInt<6>("h03b")], clk node T_1892 = eq(T_1891, T_1712) infer mport T_1894 = idxs[UInt<6>("h03c")], clk node T_1895 = eq(T_1894, T_1712) infer mport T_1897 = idxs[UInt<6>("h03d")], clk node T_1898 = eq(T_1897, T_1712) wire T_1900 : UInt<1>[62] T_1900[0] <= T_1715 T_1900[1] <= T_1718 T_1900[2] <= T_1721 T_1900[3] <= T_1724 T_1900[4] <= T_1727 T_1900[5] <= T_1730 T_1900[6] <= T_1733 T_1900[7] <= T_1736 T_1900[8] <= T_1739 T_1900[9] <= T_1742 T_1900[10] <= T_1745 T_1900[11] <= T_1748 T_1900[12] <= T_1751 T_1900[13] <= T_1754 T_1900[14] <= T_1757 T_1900[15] <= T_1760 T_1900[16] <= T_1763 T_1900[17] <= T_1766 T_1900[18] <= T_1769 T_1900[19] <= T_1772 T_1900[20] <= T_1775 T_1900[21] <= T_1778 T_1900[22] <= T_1781 T_1900[23] <= T_1784 T_1900[24] <= T_1787 T_1900[25] <= T_1790 T_1900[26] <= T_1793 T_1900[27] <= T_1796 T_1900[28] <= T_1799 T_1900[29] <= T_1802 T_1900[30] <= T_1805 T_1900[31] <= T_1808 T_1900[32] <= T_1811 T_1900[33] <= T_1814 T_1900[34] <= T_1817 T_1900[35] <= T_1820 T_1900[36] <= T_1823 T_1900[37] <= T_1826 T_1900[38] <= T_1829 T_1900[39] <= T_1832 T_1900[40] <= T_1835 T_1900[41] <= T_1838 T_1900[42] <= T_1841 T_1900[43] <= T_1844 T_1900[44] <= T_1847 T_1900[45] <= T_1850 T_1900[46] <= T_1853 T_1900[47] <= T_1856 T_1900[48] <= T_1859 T_1900[49] <= T_1862 T_1900[50] <= T_1865 T_1900[51] <= T_1868 T_1900[52] <= T_1871 T_1900[53] <= T_1874 T_1900[54] <= T_1877 T_1900[55] <= T_1880 T_1900[56] <= T_1883 T_1900[57] <= T_1886 T_1900[58] <= T_1889 T_1900[59] <= T_1892 T_1900[60] <= T_1895 T_1900[61] <= T_1898 node T_1964 = cat(T_1900[60], T_1900[59]) node T_1965 = cat(T_1900[61], T_1964) node T_1966 = cat(T_1900[58], T_1900[57]) node T_1967 = cat(T_1900[56], T_1900[55]) node T_1968 = cat(T_1966, T_1967) node T_1969 = cat(T_1965, T_1968) node T_1970 = cat(T_1900[54], T_1900[53]) node T_1971 = cat(T_1900[52], T_1900[51]) node T_1972 = cat(T_1970, T_1971) node T_1973 = cat(T_1900[50], T_1900[49]) node T_1974 = cat(T_1900[48], T_1900[47]) node T_1975 = cat(T_1973, T_1974) node T_1976 = cat(T_1972, T_1975) node T_1977 = cat(T_1969, T_1976) node T_1978 = cat(T_1900[46], T_1900[45]) node T_1979 = cat(T_1900[44], T_1900[43]) node T_1980 = cat(T_1978, T_1979) node T_1981 = cat(T_1900[42], T_1900[41]) node T_1982 = cat(T_1900[40], T_1900[39]) node T_1983 = cat(T_1981, T_1982) node T_1984 = cat(T_1980, T_1983) node T_1985 = cat(T_1900[38], T_1900[37]) node T_1986 = cat(T_1900[36], T_1900[35]) node T_1987 = cat(T_1985, T_1986) node T_1988 = cat(T_1900[34], T_1900[33]) node T_1989 = cat(T_1900[32], T_1900[31]) node T_1990 = cat(T_1988, T_1989) node T_1991 = cat(T_1987, T_1990) node T_1992 = cat(T_1984, T_1991) node T_1993 = cat(T_1977, T_1992) node T_1994 = cat(T_1900[29], T_1900[28]) node T_1995 = cat(T_1900[30], T_1994) node T_1996 = cat(T_1900[27], T_1900[26]) node T_1997 = cat(T_1900[25], T_1900[24]) node T_1998 = cat(T_1996, T_1997) node T_1999 = cat(T_1995, T_1998) node T_2000 = cat(T_1900[23], T_1900[22]) node T_2001 = cat(T_1900[21], T_1900[20]) node T_2002 = cat(T_2000, T_2001) node T_2003 = cat(T_1900[19], T_1900[18]) node T_2004 = cat(T_1900[17], T_1900[16]) node T_2005 = cat(T_2003, T_2004) node T_2006 = cat(T_2002, T_2005) node T_2007 = cat(T_1999, T_2006) node T_2008 = cat(T_1900[15], T_1900[14]) node T_2009 = cat(T_1900[13], T_1900[12]) node T_2010 = cat(T_2008, T_2009) node T_2011 = cat(T_1900[11], T_1900[10]) node T_2012 = cat(T_1900[9], T_1900[8]) node T_2013 = cat(T_2011, T_2012) node T_2014 = cat(T_2010, T_2013) node T_2015 = cat(T_1900[7], T_1900[6]) node T_2016 = cat(T_1900[5], T_1900[4]) node T_2017 = cat(T_2015, T_2016) node T_2018 = cat(T_1900[3], T_1900[2]) node T_2019 = cat(T_1900[1], T_1900[0]) node T_2020 = cat(T_2018, T_2019) node T_2021 = cat(T_2017, T_2020) node T_2022 = cat(T_2014, T_2021) node T_2023 = cat(T_2007, T_2022) node T_2024 = cat(T_1993, T_2023) node T_2025 = and(T_593, pageHit) node T_2026 = and(T_598, pageHit) node T_2027 = and(T_603, pageHit) node T_2028 = and(T_608, pageHit) node T_2029 = and(T_613, pageHit) node T_2030 = and(T_618, pageHit) node T_2031 = and(T_623, pageHit) node T_2032 = and(T_628, pageHit) node T_2033 = and(T_633, pageHit) node T_2034 = and(T_638, pageHit) node T_2035 = and(T_643, pageHit) node T_2036 = and(T_648, pageHit) node T_2037 = and(T_653, pageHit) node T_2038 = and(T_658, pageHit) node T_2039 = and(T_663, pageHit) node T_2040 = and(T_668, pageHit) node T_2041 = and(T_673, pageHit) node T_2042 = and(T_678, pageHit) node T_2043 = and(T_683, pageHit) node T_2044 = and(T_688, pageHit) node T_2045 = and(T_693, pageHit) node T_2046 = and(T_698, pageHit) node T_2047 = and(T_703, pageHit) node T_2048 = and(T_708, pageHit) node T_2049 = and(T_713, pageHit) node T_2050 = and(T_718, pageHit) node T_2051 = and(T_723, pageHit) node T_2052 = and(T_728, pageHit) node T_2053 = and(T_733, pageHit) node T_2054 = and(T_738, pageHit) node T_2055 = and(T_743, pageHit) node T_2056 = and(T_748, pageHit) node T_2057 = and(T_753, pageHit) node T_2058 = and(T_758, pageHit) node T_2059 = and(T_763, pageHit) node T_2060 = and(T_768, pageHit) node T_2061 = and(T_773, pageHit) node T_2062 = and(T_778, pageHit) node T_2063 = and(T_783, pageHit) node T_2064 = and(T_788, pageHit) node T_2065 = and(T_793, pageHit) node T_2066 = and(T_798, pageHit) node T_2067 = and(T_803, pageHit) node T_2068 = and(T_808, pageHit) node T_2069 = and(T_813, pageHit) node T_2070 = and(T_818, pageHit) node T_2071 = and(T_823, pageHit) node T_2072 = and(T_828, pageHit) node T_2073 = and(T_833, pageHit) node T_2074 = and(T_838, pageHit) node T_2075 = and(T_843, pageHit) node T_2076 = and(T_848, pageHit) node T_2077 = and(T_853, pageHit) node T_2078 = and(T_858, pageHit) node T_2079 = and(T_863, pageHit) node T_2080 = and(T_868, pageHit) node T_2081 = and(T_873, pageHit) node T_2082 = and(T_878, pageHit) node T_2083 = and(T_883, pageHit) node T_2084 = and(T_888, pageHit) node T_2085 = and(T_893, pageHit) node T_2086 = and(T_898, pageHit) node T_2088 = neq(T_2025, UInt<1>("h00")) node T_2090 = neq(T_2026, UInt<1>("h00")) node T_2092 = neq(T_2027, UInt<1>("h00")) node T_2094 = neq(T_2028, UInt<1>("h00")) node T_2096 = neq(T_2029, UInt<1>("h00")) node T_2098 = neq(T_2030, UInt<1>("h00")) node T_2100 = neq(T_2031, UInt<1>("h00")) node T_2102 = neq(T_2032, UInt<1>("h00")) node T_2104 = neq(T_2033, UInt<1>("h00")) node T_2106 = neq(T_2034, UInt<1>("h00")) node T_2108 = neq(T_2035, UInt<1>("h00")) node T_2110 = neq(T_2036, UInt<1>("h00")) node T_2112 = neq(T_2037, UInt<1>("h00")) node T_2114 = neq(T_2038, UInt<1>("h00")) node T_2116 = neq(T_2039, UInt<1>("h00")) node T_2118 = neq(T_2040, UInt<1>("h00")) node T_2120 = neq(T_2041, UInt<1>("h00")) node T_2122 = neq(T_2042, UInt<1>("h00")) node T_2124 = neq(T_2043, UInt<1>("h00")) node T_2126 = neq(T_2044, UInt<1>("h00")) node T_2128 = neq(T_2045, UInt<1>("h00")) node T_2130 = neq(T_2046, UInt<1>("h00")) node T_2132 = neq(T_2047, UInt<1>("h00")) node T_2134 = neq(T_2048, UInt<1>("h00")) node T_2136 = neq(T_2049, UInt<1>("h00")) node T_2138 = neq(T_2050, UInt<1>("h00")) node T_2140 = neq(T_2051, UInt<1>("h00")) node T_2142 = neq(T_2052, UInt<1>("h00")) node T_2144 = neq(T_2053, UInt<1>("h00")) node T_2146 = neq(T_2054, UInt<1>("h00")) node T_2148 = neq(T_2055, UInt<1>("h00")) node T_2150 = neq(T_2056, UInt<1>("h00")) node T_2152 = neq(T_2057, UInt<1>("h00")) node T_2154 = neq(T_2058, UInt<1>("h00")) node T_2156 = neq(T_2059, UInt<1>("h00")) node T_2158 = neq(T_2060, UInt<1>("h00")) node T_2160 = neq(T_2061, UInt<1>("h00")) node T_2162 = neq(T_2062, UInt<1>("h00")) node T_2164 = neq(T_2063, UInt<1>("h00")) node T_2166 = neq(T_2064, UInt<1>("h00")) node T_2168 = neq(T_2065, UInt<1>("h00")) node T_2170 = neq(T_2066, UInt<1>("h00")) node T_2172 = neq(T_2067, UInt<1>("h00")) node T_2174 = neq(T_2068, UInt<1>("h00")) node T_2176 = neq(T_2069, UInt<1>("h00")) node T_2178 = neq(T_2070, UInt<1>("h00")) node T_2180 = neq(T_2071, UInt<1>("h00")) node T_2182 = neq(T_2072, UInt<1>("h00")) node T_2184 = neq(T_2073, UInt<1>("h00")) node T_2186 = neq(T_2074, UInt<1>("h00")) node T_2188 = neq(T_2075, UInt<1>("h00")) node T_2190 = neq(T_2076, UInt<1>("h00")) node T_2192 = neq(T_2077, UInt<1>("h00")) node T_2194 = neq(T_2078, UInt<1>("h00")) node T_2196 = neq(T_2079, UInt<1>("h00")) node T_2198 = neq(T_2080, UInt<1>("h00")) node T_2200 = neq(T_2081, UInt<1>("h00")) node T_2202 = neq(T_2082, UInt<1>("h00")) node T_2204 = neq(T_2083, UInt<1>("h00")) node T_2206 = neq(T_2084, UInt<1>("h00")) node T_2208 = neq(T_2085, UInt<1>("h00")) node T_2210 = neq(T_2086, UInt<1>("h00")) wire T_2212 : UInt<1>[62] T_2212[0] <= T_2088 T_2212[1] <= T_2090 T_2212[2] <= T_2092 T_2212[3] <= T_2094 T_2212[4] <= T_2096 T_2212[5] <= T_2098 T_2212[6] <= T_2100 T_2212[7] <= T_2102 T_2212[8] <= T_2104 T_2212[9] <= T_2106 T_2212[10] <= T_2108 T_2212[11] <= T_2110 T_2212[12] <= T_2112 T_2212[13] <= T_2114 T_2212[14] <= T_2116 T_2212[15] <= T_2118 T_2212[16] <= T_2120 T_2212[17] <= T_2122 T_2212[18] <= T_2124 T_2212[19] <= T_2126 T_2212[20] <= T_2128 T_2212[21] <= T_2130 T_2212[22] <= T_2132 T_2212[23] <= T_2134 T_2212[24] <= T_2136 T_2212[25] <= T_2138 T_2212[26] <= T_2140 T_2212[27] <= T_2142 T_2212[28] <= T_2144 T_2212[29] <= T_2146 T_2212[30] <= T_2148 T_2212[31] <= T_2150 T_2212[32] <= T_2152 T_2212[33] <= T_2154 T_2212[34] <= T_2156 T_2212[35] <= T_2158 T_2212[36] <= T_2160 T_2212[37] <= T_2162 T_2212[38] <= T_2164 T_2212[39] <= T_2166 T_2212[40] <= T_2168 T_2212[41] <= T_2170 T_2212[42] <= T_2172 T_2212[43] <= T_2174 T_2212[44] <= T_2176 T_2212[45] <= T_2178 T_2212[46] <= T_2180 T_2212[47] <= T_2182 T_2212[48] <= T_2184 T_2212[49] <= T_2186 T_2212[50] <= T_2188 T_2212[51] <= T_2190 T_2212[52] <= T_2192 T_2212[53] <= T_2194 T_2212[54] <= T_2196 T_2212[55] <= T_2198 T_2212[56] <= T_2200 T_2212[57] <= T_2202 T_2212[58] <= T_2204 T_2212[59] <= T_2206 T_2212[60] <= T_2208 T_2212[61] <= T_2210 node T_2276 = cat(T_2212[60], T_2212[59]) node T_2277 = cat(T_2212[61], T_2276) node T_2278 = cat(T_2212[58], T_2212[57]) node T_2279 = cat(T_2212[56], T_2212[55]) node T_2280 = cat(T_2278, T_2279) node T_2281 = cat(T_2277, T_2280) node T_2282 = cat(T_2212[54], T_2212[53]) node T_2283 = cat(T_2212[52], T_2212[51]) node T_2284 = cat(T_2282, T_2283) node T_2285 = cat(T_2212[50], T_2212[49]) node T_2286 = cat(T_2212[48], T_2212[47]) node T_2287 = cat(T_2285, T_2286) node T_2288 = cat(T_2284, T_2287) node T_2289 = cat(T_2281, T_2288) node T_2290 = cat(T_2212[46], T_2212[45]) node T_2291 = cat(T_2212[44], T_2212[43]) node T_2292 = cat(T_2290, T_2291) node T_2293 = cat(T_2212[42], T_2212[41]) node T_2294 = cat(T_2212[40], T_2212[39]) node T_2295 = cat(T_2293, T_2294) node T_2296 = cat(T_2292, T_2295) node T_2297 = cat(T_2212[38], T_2212[37]) node T_2298 = cat(T_2212[36], T_2212[35]) node T_2299 = cat(T_2297, T_2298) node T_2300 = cat(T_2212[34], T_2212[33]) node T_2301 = cat(T_2212[32], T_2212[31]) node T_2302 = cat(T_2300, T_2301) node T_2303 = cat(T_2299, T_2302) node T_2304 = cat(T_2296, T_2303) node T_2305 = cat(T_2289, T_2304) node T_2306 = cat(T_2212[29], T_2212[28]) node T_2307 = cat(T_2212[30], T_2306) node T_2308 = cat(T_2212[27], T_2212[26]) node T_2309 = cat(T_2212[25], T_2212[24]) node T_2310 = cat(T_2308, T_2309) node T_2311 = cat(T_2307, T_2310) node T_2312 = cat(T_2212[23], T_2212[22]) node T_2313 = cat(T_2212[21], T_2212[20]) node T_2314 = cat(T_2312, T_2313) node T_2315 = cat(T_2212[19], T_2212[18]) node T_2316 = cat(T_2212[17], T_2212[16]) node T_2317 = cat(T_2315, T_2316) node T_2318 = cat(T_2314, T_2317) node T_2319 = cat(T_2311, T_2318) node T_2320 = cat(T_2212[15], T_2212[14]) node T_2321 = cat(T_2212[13], T_2212[12]) node T_2322 = cat(T_2320, T_2321) node T_2323 = cat(T_2212[11], T_2212[10]) node T_2324 = cat(T_2212[9], T_2212[8]) node T_2325 = cat(T_2323, T_2324) node T_2326 = cat(T_2322, T_2325) node T_2327 = cat(T_2212[7], T_2212[6]) node T_2328 = cat(T_2212[5], T_2212[4]) node T_2329 = cat(T_2327, T_2328) node T_2330 = cat(T_2212[3], T_2212[2]) node T_2331 = cat(T_2212[1], T_2212[0]) node T_2332 = cat(T_2330, T_2331) node T_2333 = cat(T_2329, T_2332) node T_2334 = cat(T_2326, T_2333) node T_2335 = cat(T_2319, T_2334) node T_2336 = cat(T_2305, T_2335) node T_2337 = and(idxValid, T_2024) node hits = and(T_2337, T_2336) node T_2339 = shr(r_btb_update.bits.pc, 12) infer mport T_2341 = pages[UInt<1>("h00")], clk node T_2342 = eq(T_2341, T_2339) infer mport T_2344 = pages[UInt<1>("h01")], clk node T_2345 = eq(T_2344, T_2339) infer mport T_2347 = pages[UInt<2>("h02")], clk node T_2348 = eq(T_2347, T_2339) infer mport T_2350 = pages[UInt<2>("h03")], clk node T_2351 = eq(T_2350, T_2339) infer mport T_2353 = pages[UInt<3>("h04")], clk node T_2354 = eq(T_2353, T_2339) infer mport T_2356 = pages[UInt<3>("h05")], clk node T_2357 = eq(T_2356, T_2339) wire T_2359 : UInt<1>[6] T_2359[0] <= T_2342 T_2359[1] <= T_2345 T_2359[2] <= T_2348 T_2359[3] <= T_2351 T_2359[4] <= T_2354 T_2359[5] <= T_2357 node T_2367 = cat(T_2359[4], T_2359[3]) node T_2368 = cat(T_2359[5], T_2367) node T_2369 = cat(T_2359[1], T_2359[0]) node T_2370 = cat(T_2359[2], T_2369) node T_2371 = cat(T_2368, T_2370) node updatePageHit = and(T_2371, pageValid) node T_2373 = bits(r_btb_update.bits.pc, 11, 0) infer mport T_2375 = idxs[UInt<1>("h00")], clk node T_2376 = eq(T_2375, T_2373) infer mport T_2378 = idxs[UInt<1>("h01")], clk node T_2379 = eq(T_2378, T_2373) infer mport T_2381 = idxs[UInt<2>("h02")], clk node T_2382 = eq(T_2381, T_2373) infer mport T_2384 = idxs[UInt<2>("h03")], clk node T_2385 = eq(T_2384, T_2373) infer mport T_2387 = idxs[UInt<3>("h04")], clk node T_2388 = eq(T_2387, T_2373) infer mport T_2390 = idxs[UInt<3>("h05")], clk node T_2391 = eq(T_2390, T_2373) infer mport T_2393 = idxs[UInt<3>("h06")], clk node T_2394 = eq(T_2393, T_2373) infer mport T_2396 = idxs[UInt<3>("h07")], clk node T_2397 = eq(T_2396, T_2373) infer mport T_2399 = idxs[UInt<4>("h08")], clk node T_2400 = eq(T_2399, T_2373) infer mport T_2402 = idxs[UInt<4>("h09")], clk node T_2403 = eq(T_2402, T_2373) infer mport T_2405 = idxs[UInt<4>("h0a")], clk node T_2406 = eq(T_2405, T_2373) infer mport T_2408 = idxs[UInt<4>("h0b")], clk node T_2409 = eq(T_2408, T_2373) infer mport T_2411 = idxs[UInt<4>("h0c")], clk node T_2412 = eq(T_2411, T_2373) infer mport T_2414 = idxs[UInt<4>("h0d")], clk node T_2415 = eq(T_2414, T_2373) infer mport T_2417 = idxs[UInt<4>("h0e")], clk node T_2418 = eq(T_2417, T_2373) infer mport T_2420 = idxs[UInt<4>("h0f")], clk node T_2421 = eq(T_2420, T_2373) infer mport T_2423 = idxs[UInt<5>("h010")], clk node T_2424 = eq(T_2423, T_2373) infer mport T_2426 = idxs[UInt<5>("h011")], clk node T_2427 = eq(T_2426, T_2373) infer mport T_2429 = idxs[UInt<5>("h012")], clk node T_2430 = eq(T_2429, T_2373) infer mport T_2432 = idxs[UInt<5>("h013")], clk node T_2433 = eq(T_2432, T_2373) infer mport T_2435 = idxs[UInt<5>("h014")], clk node T_2436 = eq(T_2435, T_2373) infer mport T_2438 = idxs[UInt<5>("h015")], clk node T_2439 = eq(T_2438, T_2373) infer mport T_2441 = idxs[UInt<5>("h016")], clk node T_2442 = eq(T_2441, T_2373) infer mport T_2444 = idxs[UInt<5>("h017")], clk node T_2445 = eq(T_2444, T_2373) infer mport T_2447 = idxs[UInt<5>("h018")], clk node T_2448 = eq(T_2447, T_2373) infer mport T_2450 = idxs[UInt<5>("h019")], clk node T_2451 = eq(T_2450, T_2373) infer mport T_2453 = idxs[UInt<5>("h01a")], clk node T_2454 = eq(T_2453, T_2373) infer mport T_2456 = idxs[UInt<5>("h01b")], clk node T_2457 = eq(T_2456, T_2373) infer mport T_2459 = idxs[UInt<5>("h01c")], clk node T_2460 = eq(T_2459, T_2373) infer mport T_2462 = idxs[UInt<5>("h01d")], clk node T_2463 = eq(T_2462, T_2373) infer mport T_2465 = idxs[UInt<5>("h01e")], clk node T_2466 = eq(T_2465, T_2373) infer mport T_2468 = idxs[UInt<5>("h01f")], clk node T_2469 = eq(T_2468, T_2373) infer mport T_2471 = idxs[UInt<6>("h020")], clk node T_2472 = eq(T_2471, T_2373) infer mport T_2474 = idxs[UInt<6>("h021")], clk node T_2475 = eq(T_2474, T_2373) infer mport T_2477 = idxs[UInt<6>("h022")], clk node T_2478 = eq(T_2477, T_2373) infer mport T_2480 = idxs[UInt<6>("h023")], clk node T_2481 = eq(T_2480, T_2373) infer mport T_2483 = idxs[UInt<6>("h024")], clk node T_2484 = eq(T_2483, T_2373) infer mport T_2486 = idxs[UInt<6>("h025")], clk node T_2487 = eq(T_2486, T_2373) infer mport T_2489 = idxs[UInt<6>("h026")], clk node T_2490 = eq(T_2489, T_2373) infer mport T_2492 = idxs[UInt<6>("h027")], clk node T_2493 = eq(T_2492, T_2373) infer mport T_2495 = idxs[UInt<6>("h028")], clk node T_2496 = eq(T_2495, T_2373) infer mport T_2498 = idxs[UInt<6>("h029")], clk node T_2499 = eq(T_2498, T_2373) infer mport T_2501 = idxs[UInt<6>("h02a")], clk node T_2502 = eq(T_2501, T_2373) infer mport T_2504 = idxs[UInt<6>("h02b")], clk node T_2505 = eq(T_2504, T_2373) infer mport T_2507 = idxs[UInt<6>("h02c")], clk node T_2508 = eq(T_2507, T_2373) infer mport T_2510 = idxs[UInt<6>("h02d")], clk node T_2511 = eq(T_2510, T_2373) infer mport T_2513 = idxs[UInt<6>("h02e")], clk node T_2514 = eq(T_2513, T_2373) infer mport T_2516 = idxs[UInt<6>("h02f")], clk node T_2517 = eq(T_2516, T_2373) infer mport T_2519 = idxs[UInt<6>("h030")], clk node T_2520 = eq(T_2519, T_2373) infer mport T_2522 = idxs[UInt<6>("h031")], clk node T_2523 = eq(T_2522, T_2373) infer mport T_2525 = idxs[UInt<6>("h032")], clk node T_2526 = eq(T_2525, T_2373) infer mport T_2528 = idxs[UInt<6>("h033")], clk node T_2529 = eq(T_2528, T_2373) infer mport T_2531 = idxs[UInt<6>("h034")], clk node T_2532 = eq(T_2531, T_2373) infer mport T_2534 = idxs[UInt<6>("h035")], clk node T_2535 = eq(T_2534, T_2373) infer mport T_2537 = idxs[UInt<6>("h036")], clk node T_2538 = eq(T_2537, T_2373) infer mport T_2540 = idxs[UInt<6>("h037")], clk node T_2541 = eq(T_2540, T_2373) infer mport T_2543 = idxs[UInt<6>("h038")], clk node T_2544 = eq(T_2543, T_2373) infer mport T_2546 = idxs[UInt<6>("h039")], clk node T_2547 = eq(T_2546, T_2373) infer mport T_2549 = idxs[UInt<6>("h03a")], clk node T_2550 = eq(T_2549, T_2373) infer mport T_2552 = idxs[UInt<6>("h03b")], clk node T_2553 = eq(T_2552, T_2373) infer mport T_2555 = idxs[UInt<6>("h03c")], clk node T_2556 = eq(T_2555, T_2373) infer mport T_2558 = idxs[UInt<6>("h03d")], clk node T_2559 = eq(T_2558, T_2373) wire T_2561 : UInt<1>[62] T_2561[0] <= T_2376 T_2561[1] <= T_2379 T_2561[2] <= T_2382 T_2561[3] <= T_2385 T_2561[4] <= T_2388 T_2561[5] <= T_2391 T_2561[6] <= T_2394 T_2561[7] <= T_2397 T_2561[8] <= T_2400 T_2561[9] <= T_2403 T_2561[10] <= T_2406 T_2561[11] <= T_2409 T_2561[12] <= T_2412 T_2561[13] <= T_2415 T_2561[14] <= T_2418 T_2561[15] <= T_2421 T_2561[16] <= T_2424 T_2561[17] <= T_2427 T_2561[18] <= T_2430 T_2561[19] <= T_2433 T_2561[20] <= T_2436 T_2561[21] <= T_2439 T_2561[22] <= T_2442 T_2561[23] <= T_2445 T_2561[24] <= T_2448 T_2561[25] <= T_2451 T_2561[26] <= T_2454 T_2561[27] <= T_2457 T_2561[28] <= T_2460 T_2561[29] <= T_2463 T_2561[30] <= T_2466 T_2561[31] <= T_2469 T_2561[32] <= T_2472 T_2561[33] <= T_2475 T_2561[34] <= T_2478 T_2561[35] <= T_2481 T_2561[36] <= T_2484 T_2561[37] <= T_2487 T_2561[38] <= T_2490 T_2561[39] <= T_2493 T_2561[40] <= T_2496 T_2561[41] <= T_2499 T_2561[42] <= T_2502 T_2561[43] <= T_2505 T_2561[44] <= T_2508 T_2561[45] <= T_2511 T_2561[46] <= T_2514 T_2561[47] <= T_2517 T_2561[48] <= T_2520 T_2561[49] <= T_2523 T_2561[50] <= T_2526 T_2561[51] <= T_2529 T_2561[52] <= T_2532 T_2561[53] <= T_2535 T_2561[54] <= T_2538 T_2561[55] <= T_2541 T_2561[56] <= T_2544 T_2561[57] <= T_2547 T_2561[58] <= T_2550 T_2561[59] <= T_2553 T_2561[60] <= T_2556 T_2561[61] <= T_2559 node T_2625 = cat(T_2561[60], T_2561[59]) node T_2626 = cat(T_2561[61], T_2625) node T_2627 = cat(T_2561[58], T_2561[57]) node T_2628 = cat(T_2561[56], T_2561[55]) node T_2629 = cat(T_2627, T_2628) node T_2630 = cat(T_2626, T_2629) node T_2631 = cat(T_2561[54], T_2561[53]) node T_2632 = cat(T_2561[52], T_2561[51]) node T_2633 = cat(T_2631, T_2632) node T_2634 = cat(T_2561[50], T_2561[49]) node T_2635 = cat(T_2561[48], T_2561[47]) node T_2636 = cat(T_2634, T_2635) node T_2637 = cat(T_2633, T_2636) node T_2638 = cat(T_2630, T_2637) node T_2639 = cat(T_2561[46], T_2561[45]) node T_2640 = cat(T_2561[44], T_2561[43]) node T_2641 = cat(T_2639, T_2640) node T_2642 = cat(T_2561[42], T_2561[41]) node T_2643 = cat(T_2561[40], T_2561[39]) node T_2644 = cat(T_2642, T_2643) node T_2645 = cat(T_2641, T_2644) node T_2646 = cat(T_2561[38], T_2561[37]) node T_2647 = cat(T_2561[36], T_2561[35]) node T_2648 = cat(T_2646, T_2647) node T_2649 = cat(T_2561[34], T_2561[33]) node T_2650 = cat(T_2561[32], T_2561[31]) node T_2651 = cat(T_2649, T_2650) node T_2652 = cat(T_2648, T_2651) node T_2653 = cat(T_2645, T_2652) node T_2654 = cat(T_2638, T_2653) node T_2655 = cat(T_2561[29], T_2561[28]) node T_2656 = cat(T_2561[30], T_2655) node T_2657 = cat(T_2561[27], T_2561[26]) node T_2658 = cat(T_2561[25], T_2561[24]) node T_2659 = cat(T_2657, T_2658) node T_2660 = cat(T_2656, T_2659) node T_2661 = cat(T_2561[23], T_2561[22]) node T_2662 = cat(T_2561[21], T_2561[20]) node T_2663 = cat(T_2661, T_2662) node T_2664 = cat(T_2561[19], T_2561[18]) node T_2665 = cat(T_2561[17], T_2561[16]) node T_2666 = cat(T_2664, T_2665) node T_2667 = cat(T_2663, T_2666) node T_2668 = cat(T_2660, T_2667) node T_2669 = cat(T_2561[15], T_2561[14]) node T_2670 = cat(T_2561[13], T_2561[12]) node T_2671 = cat(T_2669, T_2670) node T_2672 = cat(T_2561[11], T_2561[10]) node T_2673 = cat(T_2561[9], T_2561[8]) node T_2674 = cat(T_2672, T_2673) node T_2675 = cat(T_2671, T_2674) node T_2676 = cat(T_2561[7], T_2561[6]) node T_2677 = cat(T_2561[5], T_2561[4]) node T_2678 = cat(T_2676, T_2677) node T_2679 = cat(T_2561[3], T_2561[2]) node T_2680 = cat(T_2561[1], T_2561[0]) node T_2681 = cat(T_2679, T_2680) node T_2682 = cat(T_2678, T_2681) node T_2683 = cat(T_2675, T_2682) node T_2684 = cat(T_2668, T_2683) node T_2685 = cat(T_2654, T_2684) node T_2686 = and(T_593, updatePageHit) node T_2687 = and(T_598, updatePageHit) node T_2688 = and(T_603, updatePageHit) node T_2689 = and(T_608, updatePageHit) node T_2690 = and(T_613, updatePageHit) node T_2691 = and(T_618, updatePageHit) node T_2692 = and(T_623, updatePageHit) node T_2693 = and(T_628, updatePageHit) node T_2694 = and(T_633, updatePageHit) node T_2695 = and(T_638, updatePageHit) node T_2696 = and(T_643, updatePageHit) node T_2697 = and(T_648, updatePageHit) node T_2698 = and(T_653, updatePageHit) node T_2699 = and(T_658, updatePageHit) node T_2700 = and(T_663, updatePageHit) node T_2701 = and(T_668, updatePageHit) node T_2702 = and(T_673, updatePageHit) node T_2703 = and(T_678, updatePageHit) node T_2704 = and(T_683, updatePageHit) node T_2705 = and(T_688, updatePageHit) node T_2706 = and(T_693, updatePageHit) node T_2707 = and(T_698, updatePageHit) node T_2708 = and(T_703, updatePageHit) node T_2709 = and(T_708, updatePageHit) node T_2710 = and(T_713, updatePageHit) node T_2711 = and(T_718, updatePageHit) node T_2712 = and(T_723, updatePageHit) node T_2713 = and(T_728, updatePageHit) node T_2714 = and(T_733, updatePageHit) node T_2715 = and(T_738, updatePageHit) node T_2716 = and(T_743, updatePageHit) node T_2717 = and(T_748, updatePageHit) node T_2718 = and(T_753, updatePageHit) node T_2719 = and(T_758, updatePageHit) node T_2720 = and(T_763, updatePageHit) node T_2721 = and(T_768, updatePageHit) node T_2722 = and(T_773, updatePageHit) node T_2723 = and(T_778, updatePageHit) node T_2724 = and(T_783, updatePageHit) node T_2725 = and(T_788, updatePageHit) node T_2726 = and(T_793, updatePageHit) node T_2727 = and(T_798, updatePageHit) node T_2728 = and(T_803, updatePageHit) node T_2729 = and(T_808, updatePageHit) node T_2730 = and(T_813, updatePageHit) node T_2731 = and(T_818, updatePageHit) node T_2732 = and(T_823, updatePageHit) node T_2733 = and(T_828, updatePageHit) node T_2734 = and(T_833, updatePageHit) node T_2735 = and(T_838, updatePageHit) node T_2736 = and(T_843, updatePageHit) node T_2737 = and(T_848, updatePageHit) node T_2738 = and(T_853, updatePageHit) node T_2739 = and(T_858, updatePageHit) node T_2740 = and(T_863, updatePageHit) node T_2741 = and(T_868, updatePageHit) node T_2742 = and(T_873, updatePageHit) node T_2743 = and(T_878, updatePageHit) node T_2744 = and(T_883, updatePageHit) node T_2745 = and(T_888, updatePageHit) node T_2746 = and(T_893, updatePageHit) node T_2747 = and(T_898, updatePageHit) node T_2749 = neq(T_2686, UInt<1>("h00")) node T_2751 = neq(T_2687, UInt<1>("h00")) node T_2753 = neq(T_2688, UInt<1>("h00")) node T_2755 = neq(T_2689, UInt<1>("h00")) node T_2757 = neq(T_2690, UInt<1>("h00")) node T_2759 = neq(T_2691, UInt<1>("h00")) node T_2761 = neq(T_2692, UInt<1>("h00")) node T_2763 = neq(T_2693, UInt<1>("h00")) node T_2765 = neq(T_2694, UInt<1>("h00")) node T_2767 = neq(T_2695, UInt<1>("h00")) node T_2769 = neq(T_2696, UInt<1>("h00")) node T_2771 = neq(T_2697, UInt<1>("h00")) node T_2773 = neq(T_2698, UInt<1>("h00")) node T_2775 = neq(T_2699, UInt<1>("h00")) node T_2777 = neq(T_2700, UInt<1>("h00")) node T_2779 = neq(T_2701, UInt<1>("h00")) node T_2781 = neq(T_2702, UInt<1>("h00")) node T_2783 = neq(T_2703, UInt<1>("h00")) node T_2785 = neq(T_2704, UInt<1>("h00")) node T_2787 = neq(T_2705, UInt<1>("h00")) node T_2789 = neq(T_2706, UInt<1>("h00")) node T_2791 = neq(T_2707, UInt<1>("h00")) node T_2793 = neq(T_2708, UInt<1>("h00")) node T_2795 = neq(T_2709, UInt<1>("h00")) node T_2797 = neq(T_2710, UInt<1>("h00")) node T_2799 = neq(T_2711, UInt<1>("h00")) node T_2801 = neq(T_2712, UInt<1>("h00")) node T_2803 = neq(T_2713, UInt<1>("h00")) node T_2805 = neq(T_2714, UInt<1>("h00")) node T_2807 = neq(T_2715, UInt<1>("h00")) node T_2809 = neq(T_2716, UInt<1>("h00")) node T_2811 = neq(T_2717, UInt<1>("h00")) node T_2813 = neq(T_2718, UInt<1>("h00")) node T_2815 = neq(T_2719, UInt<1>("h00")) node T_2817 = neq(T_2720, UInt<1>("h00")) node T_2819 = neq(T_2721, UInt<1>("h00")) node T_2821 = neq(T_2722, UInt<1>("h00")) node T_2823 = neq(T_2723, UInt<1>("h00")) node T_2825 = neq(T_2724, UInt<1>("h00")) node T_2827 = neq(T_2725, UInt<1>("h00")) node T_2829 = neq(T_2726, UInt<1>("h00")) node T_2831 = neq(T_2727, UInt<1>("h00")) node T_2833 = neq(T_2728, UInt<1>("h00")) node T_2835 = neq(T_2729, UInt<1>("h00")) node T_2837 = neq(T_2730, UInt<1>("h00")) node T_2839 = neq(T_2731, UInt<1>("h00")) node T_2841 = neq(T_2732, UInt<1>("h00")) node T_2843 = neq(T_2733, UInt<1>("h00")) node T_2845 = neq(T_2734, UInt<1>("h00")) node T_2847 = neq(T_2735, UInt<1>("h00")) node T_2849 = neq(T_2736, UInt<1>("h00")) node T_2851 = neq(T_2737, UInt<1>("h00")) node T_2853 = neq(T_2738, UInt<1>("h00")) node T_2855 = neq(T_2739, UInt<1>("h00")) node T_2857 = neq(T_2740, UInt<1>("h00")) node T_2859 = neq(T_2741, UInt<1>("h00")) node T_2861 = neq(T_2742, UInt<1>("h00")) node T_2863 = neq(T_2743, UInt<1>("h00")) node T_2865 = neq(T_2744, UInt<1>("h00")) node T_2867 = neq(T_2745, UInt<1>("h00")) node T_2869 = neq(T_2746, UInt<1>("h00")) node T_2871 = neq(T_2747, UInt<1>("h00")) wire T_2873 : UInt<1>[62] T_2873[0] <= T_2749 T_2873[1] <= T_2751 T_2873[2] <= T_2753 T_2873[3] <= T_2755 T_2873[4] <= T_2757 T_2873[5] <= T_2759 T_2873[6] <= T_2761 T_2873[7] <= T_2763 T_2873[8] <= T_2765 T_2873[9] <= T_2767 T_2873[10] <= T_2769 T_2873[11] <= T_2771 T_2873[12] <= T_2773 T_2873[13] <= T_2775 T_2873[14] <= T_2777 T_2873[15] <= T_2779 T_2873[16] <= T_2781 T_2873[17] <= T_2783 T_2873[18] <= T_2785 T_2873[19] <= T_2787 T_2873[20] <= T_2789 T_2873[21] <= T_2791 T_2873[22] <= T_2793 T_2873[23] <= T_2795 T_2873[24] <= T_2797 T_2873[25] <= T_2799 T_2873[26] <= T_2801 T_2873[27] <= T_2803 T_2873[28] <= T_2805 T_2873[29] <= T_2807 T_2873[30] <= T_2809 T_2873[31] <= T_2811 T_2873[32] <= T_2813 T_2873[33] <= T_2815 T_2873[34] <= T_2817 T_2873[35] <= T_2819 T_2873[36] <= T_2821 T_2873[37] <= T_2823 T_2873[38] <= T_2825 T_2873[39] <= T_2827 T_2873[40] <= T_2829 T_2873[41] <= T_2831 T_2873[42] <= T_2833 T_2873[43] <= T_2835 T_2873[44] <= T_2837 T_2873[45] <= T_2839 T_2873[46] <= T_2841 T_2873[47] <= T_2843 T_2873[48] <= T_2845 T_2873[49] <= T_2847 T_2873[50] <= T_2849 T_2873[51] <= T_2851 T_2873[52] <= T_2853 T_2873[53] <= T_2855 T_2873[54] <= T_2857 T_2873[55] <= T_2859 T_2873[56] <= T_2861 T_2873[57] <= T_2863 T_2873[58] <= T_2865 T_2873[59] <= T_2867 T_2873[60] <= T_2869 T_2873[61] <= T_2871 node T_2937 = cat(T_2873[60], T_2873[59]) node T_2938 = cat(T_2873[61], T_2937) node T_2939 = cat(T_2873[58], T_2873[57]) node T_2940 = cat(T_2873[56], T_2873[55]) node T_2941 = cat(T_2939, T_2940) node T_2942 = cat(T_2938, T_2941) node T_2943 = cat(T_2873[54], T_2873[53]) node T_2944 = cat(T_2873[52], T_2873[51]) node T_2945 = cat(T_2943, T_2944) node T_2946 = cat(T_2873[50], T_2873[49]) node T_2947 = cat(T_2873[48], T_2873[47]) node T_2948 = cat(T_2946, T_2947) node T_2949 = cat(T_2945, T_2948) node T_2950 = cat(T_2942, T_2949) node T_2951 = cat(T_2873[46], T_2873[45]) node T_2952 = cat(T_2873[44], T_2873[43]) node T_2953 = cat(T_2951, T_2952) node T_2954 = cat(T_2873[42], T_2873[41]) node T_2955 = cat(T_2873[40], T_2873[39]) node T_2956 = cat(T_2954, T_2955) node T_2957 = cat(T_2953, T_2956) node T_2958 = cat(T_2873[38], T_2873[37]) node T_2959 = cat(T_2873[36], T_2873[35]) node T_2960 = cat(T_2958, T_2959) node T_2961 = cat(T_2873[34], T_2873[33]) node T_2962 = cat(T_2873[32], T_2873[31]) node T_2963 = cat(T_2961, T_2962) node T_2964 = cat(T_2960, T_2963) node T_2965 = cat(T_2957, T_2964) node T_2966 = cat(T_2950, T_2965) node T_2967 = cat(T_2873[29], T_2873[28]) node T_2968 = cat(T_2873[30], T_2967) node T_2969 = cat(T_2873[27], T_2873[26]) node T_2970 = cat(T_2873[25], T_2873[24]) node T_2971 = cat(T_2969, T_2970) node T_2972 = cat(T_2968, T_2971) node T_2973 = cat(T_2873[23], T_2873[22]) node T_2974 = cat(T_2873[21], T_2873[20]) node T_2975 = cat(T_2973, T_2974) node T_2976 = cat(T_2873[19], T_2873[18]) node T_2977 = cat(T_2873[17], T_2873[16]) node T_2978 = cat(T_2976, T_2977) node T_2979 = cat(T_2975, T_2978) node T_2980 = cat(T_2972, T_2979) node T_2981 = cat(T_2873[15], T_2873[14]) node T_2982 = cat(T_2873[13], T_2873[12]) node T_2983 = cat(T_2981, T_2982) node T_2984 = cat(T_2873[11], T_2873[10]) node T_2985 = cat(T_2873[9], T_2873[8]) node T_2986 = cat(T_2984, T_2985) node T_2987 = cat(T_2983, T_2986) node T_2988 = cat(T_2873[7], T_2873[6]) node T_2989 = cat(T_2873[5], T_2873[4]) node T_2990 = cat(T_2988, T_2989) node T_2991 = cat(T_2873[3], T_2873[2]) node T_2992 = cat(T_2873[1], T_2873[0]) node T_2993 = cat(T_2991, T_2992) node T_2994 = cat(T_2990, T_2993) node T_2995 = cat(T_2987, T_2994) node T_2996 = cat(T_2980, T_2995) node T_2997 = cat(T_2966, T_2996) node T_2998 = and(idxValid, T_2685) node updateHits = and(T_2998, T_2997) reg T_3001 : UInt<16>, clk, reset, UInt<16>("h01") when r_btb_update.valid : node T_3002 = bit(T_3001, 0) node T_3003 = bit(T_3001, 2) node T_3004 = xor(T_3002, T_3003) node T_3005 = bit(T_3001, 3) node T_3006 = xor(T_3004, T_3005) node T_3007 = bit(T_3001, 5) node T_3008 = xor(T_3006, T_3007) node T_3009 = bits(T_3001, 15, 1) node T_3010 = cat(T_3008, T_3009) T_3001 <= T_3010 skip node T_3012 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) node T_3013 = and(r_btb_update.valid, T_3012) reg nextRepl : UInt<6>, clk, reset, UInt<6>("h00") when T_3013 : node T_3017 = eq(nextRepl, UInt<6>("h03d")) node T_3019 = and(UInt<1>("h01"), T_3017) node T_3022 = addw(nextRepl, UInt<1>("h01")) node T_3023 = mux(T_3019, UInt<1>("h00"), T_3022) nextRepl <= T_3023 skip node T_3024 = and(T_3013, T_3017) node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) wire idxPageRepl : UInt<6> idxPageRepl <= UInt<1>("h00") node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) node T_3033 = bits(idxPageUpdateOH, 5, 4) node T_3034 = bits(idxPageUpdateOH, 3, 0) node T_3036 = neq(T_3033, UInt<1>("h00")) node T_3037 = or(T_3033, T_3034) node T_3038 = bits(T_3037, 3, 2) node T_3039 = bits(T_3037, 1, 0) node T_3041 = neq(T_3038, UInt<1>("h00")) node T_3042 = or(T_3038, T_3039) node T_3043 = bit(T_3042, 1) node T_3044 = cat(T_3041, T_3043) node idxPageUpdate = cat(T_3036, T_3044) node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) node T_3048 = shr(r_btb_update.bits.pc, 12) node T_3049 = shr(io.req.bits.addr, 12) node samePage = eq(T_3048, T_3049) node T_3051 = not(idxPageReplEn) node T_3052 = and(pageHit, T_3051) node usePageHit = neq(T_3052, UInt<1>("h00")) node T_3056 = eq(samePage, UInt<1>("h00")) node T_3058 = eq(usePageHit, UInt<1>("h00")) node doTgtPageRepl = and(T_3056, T_3058) node T_3060 = bits(idxPageUpdateOH, 4, 0) node T_3061 = shl(T_3060, 1) node T_3062 = bit(idxPageUpdateOH, 5) node T_3063 = or(T_3061, T_3062) node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3063) node T_3065 = mux(usePageHit, pageHit, tgtPageRepl) node T_3066 = bits(T_3065, 5, 4) node T_3067 = bits(T_3065, 3, 0) node T_3069 = neq(T_3066, UInt<1>("h00")) node T_3070 = or(T_3066, T_3067) node T_3071 = bits(T_3070, 3, 2) node T_3072 = bits(T_3070, 1, 0) node T_3074 = neq(T_3071, UInt<1>("h00")) node T_3075 = or(T_3071, T_3072) node T_3076 = bit(T_3075, 1) node T_3077 = cat(T_3074, T_3076) node tgtPageUpdate = cat(T_3069, T_3077) node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) node pageReplEn = or(idxPageReplEn, tgtPageReplEn) node T_3083 = and(r_btb_update.valid, doPageRepl) reg T_3085 : UInt<3>, clk, reset, UInt<3>("h00") when T_3083 : node T_3087 = eq(T_3085, UInt<3>("h05")) node T_3089 = and(UInt<1>("h01"), T_3087) node T_3092 = addw(T_3085, UInt<1>("h01")) node T_3093 = mux(T_3089, UInt<1>("h00"), T_3092) T_3085 <= T_3093 skip node T_3094 = and(T_3083, T_3087) node T_3096 = dshl(UInt<1>("h01"), T_3085) idxPageRepl <= T_3096 when r_btb_update.valid : node T_3097 = eq(io.req.bits.addr, r_btb_update.bits.target) node T_3099 = eq(reset, UInt<1>("h00")) when T_3099 : node T_3101 = eq(T_3097, UInt<1>("h00")) when T_3101 : node T_3103 = eq(reset, UInt<1>("h00")) when T_3103 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): BTB request != I$ target") skip stop(clk, UInt<1>(1), 1) skip skip node T_3104 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) node T_3105 = or(T_593, T_903) node T_3106 = and(pageReplEn, T_3105) node T_3108 = neq(T_3106, UInt<1>("h00")) node T_3109 = or(T_598, T_908) node T_3110 = and(pageReplEn, T_3109) node T_3112 = neq(T_3110, UInt<1>("h00")) node T_3113 = or(T_603, T_913) node T_3114 = and(pageReplEn, T_3113) node T_3116 = neq(T_3114, UInt<1>("h00")) node T_3117 = or(T_608, T_918) node T_3118 = and(pageReplEn, T_3117) node T_3120 = neq(T_3118, UInt<1>("h00")) node T_3121 = or(T_613, T_923) node T_3122 = and(pageReplEn, T_3121) node T_3124 = neq(T_3122, UInt<1>("h00")) node T_3125 = or(T_618, T_928) node T_3126 = and(pageReplEn, T_3125) node T_3128 = neq(T_3126, UInt<1>("h00")) node T_3129 = or(T_623, T_933) node T_3130 = and(pageReplEn, T_3129) node T_3132 = neq(T_3130, UInt<1>("h00")) node T_3133 = or(T_628, T_938) node T_3134 = and(pageReplEn, T_3133) node T_3136 = neq(T_3134, UInt<1>("h00")) node T_3137 = or(T_633, T_943) node T_3138 = and(pageReplEn, T_3137) node T_3140 = neq(T_3138, UInt<1>("h00")) node T_3141 = or(T_638, T_948) node T_3142 = and(pageReplEn, T_3141) node T_3144 = neq(T_3142, UInt<1>("h00")) node T_3145 = or(T_643, T_953) node T_3146 = and(pageReplEn, T_3145) node T_3148 = neq(T_3146, UInt<1>("h00")) node T_3149 = or(T_648, T_958) node T_3150 = and(pageReplEn, T_3149) node T_3152 = neq(T_3150, UInt<1>("h00")) node T_3153 = or(T_653, T_963) node T_3154 = and(pageReplEn, T_3153) node T_3156 = neq(T_3154, UInt<1>("h00")) node T_3157 = or(T_658, T_968) node T_3158 = and(pageReplEn, T_3157) node T_3160 = neq(T_3158, UInt<1>("h00")) node T_3161 = or(T_663, T_973) node T_3162 = and(pageReplEn, T_3161) node T_3164 = neq(T_3162, UInt<1>("h00")) node T_3165 = or(T_668, T_978) node T_3166 = and(pageReplEn, T_3165) node T_3168 = neq(T_3166, UInt<1>("h00")) node T_3169 = or(T_673, T_983) node T_3170 = and(pageReplEn, T_3169) node T_3172 = neq(T_3170, UInt<1>("h00")) node T_3173 = or(T_678, T_988) node T_3174 = and(pageReplEn, T_3173) node T_3176 = neq(T_3174, UInt<1>("h00")) node T_3177 = or(T_683, T_993) node T_3178 = and(pageReplEn, T_3177) node T_3180 = neq(T_3178, UInt<1>("h00")) node T_3181 = or(T_688, T_998) node T_3182 = and(pageReplEn, T_3181) node T_3184 = neq(T_3182, UInt<1>("h00")) node T_3185 = or(T_693, T_1003) node T_3186 = and(pageReplEn, T_3185) node T_3188 = neq(T_3186, UInt<1>("h00")) node T_3189 = or(T_698, T_1008) node T_3190 = and(pageReplEn, T_3189) node T_3192 = neq(T_3190, UInt<1>("h00")) node T_3193 = or(T_703, T_1013) node T_3194 = and(pageReplEn, T_3193) node T_3196 = neq(T_3194, UInt<1>("h00")) node T_3197 = or(T_708, T_1018) node T_3198 = and(pageReplEn, T_3197) node T_3200 = neq(T_3198, UInt<1>("h00")) node T_3201 = or(T_713, T_1023) node T_3202 = and(pageReplEn, T_3201) node T_3204 = neq(T_3202, UInt<1>("h00")) node T_3205 = or(T_718, T_1028) node T_3206 = and(pageReplEn, T_3205) node T_3208 = neq(T_3206, UInt<1>("h00")) node T_3209 = or(T_723, T_1033) node T_3210 = and(pageReplEn, T_3209) node T_3212 = neq(T_3210, UInt<1>("h00")) node T_3213 = or(T_728, T_1038) node T_3214 = and(pageReplEn, T_3213) node T_3216 = neq(T_3214, UInt<1>("h00")) node T_3217 = or(T_733, T_1043) node T_3218 = and(pageReplEn, T_3217) node T_3220 = neq(T_3218, UInt<1>("h00")) node T_3221 = or(T_738, T_1048) node T_3222 = and(pageReplEn, T_3221) node T_3224 = neq(T_3222, UInt<1>("h00")) node T_3225 = or(T_743, T_1053) node T_3226 = and(pageReplEn, T_3225) node T_3228 = neq(T_3226, UInt<1>("h00")) node T_3229 = or(T_748, T_1058) node T_3230 = and(pageReplEn, T_3229) node T_3232 = neq(T_3230, UInt<1>("h00")) node T_3233 = or(T_753, T_1063) node T_3234 = and(pageReplEn, T_3233) node T_3236 = neq(T_3234, UInt<1>("h00")) node T_3237 = or(T_758, T_1068) node T_3238 = and(pageReplEn, T_3237) node T_3240 = neq(T_3238, UInt<1>("h00")) node T_3241 = or(T_763, T_1073) node T_3242 = and(pageReplEn, T_3241) node T_3244 = neq(T_3242, UInt<1>("h00")) node T_3245 = or(T_768, T_1078) node T_3246 = and(pageReplEn, T_3245) node T_3248 = neq(T_3246, UInt<1>("h00")) node T_3249 = or(T_773, T_1083) node T_3250 = and(pageReplEn, T_3249) node T_3252 = neq(T_3250, UInt<1>("h00")) node T_3253 = or(T_778, T_1088) node T_3254 = and(pageReplEn, T_3253) node T_3256 = neq(T_3254, UInt<1>("h00")) node T_3257 = or(T_783, T_1093) node T_3258 = and(pageReplEn, T_3257) node T_3260 = neq(T_3258, UInt<1>("h00")) node T_3261 = or(T_788, T_1098) node T_3262 = and(pageReplEn, T_3261) node T_3264 = neq(T_3262, UInt<1>("h00")) node T_3265 = or(T_793, T_1103) node T_3266 = and(pageReplEn, T_3265) node T_3268 = neq(T_3266, UInt<1>("h00")) node T_3269 = or(T_798, T_1108) node T_3270 = and(pageReplEn, T_3269) node T_3272 = neq(T_3270, UInt<1>("h00")) node T_3273 = or(T_803, T_1113) node T_3274 = and(pageReplEn, T_3273) node T_3276 = neq(T_3274, UInt<1>("h00")) node T_3277 = or(T_808, T_1118) node T_3278 = and(pageReplEn, T_3277) node T_3280 = neq(T_3278, UInt<1>("h00")) node T_3281 = or(T_813, T_1123) node T_3282 = and(pageReplEn, T_3281) node T_3284 = neq(T_3282, UInt<1>("h00")) node T_3285 = or(T_818, T_1128) node T_3286 = and(pageReplEn, T_3285) node T_3288 = neq(T_3286, UInt<1>("h00")) node T_3289 = or(T_823, T_1133) node T_3290 = and(pageReplEn, T_3289) node T_3292 = neq(T_3290, UInt<1>("h00")) node T_3293 = or(T_828, T_1138) node T_3294 = and(pageReplEn, T_3293) node T_3296 = neq(T_3294, UInt<1>("h00")) node T_3297 = or(T_833, T_1143) node T_3298 = and(pageReplEn, T_3297) node T_3300 = neq(T_3298, UInt<1>("h00")) node T_3301 = or(T_838, T_1148) node T_3302 = and(pageReplEn, T_3301) node T_3304 = neq(T_3302, UInt<1>("h00")) node T_3305 = or(T_843, T_1153) node T_3306 = and(pageReplEn, T_3305) node T_3308 = neq(T_3306, UInt<1>("h00")) node T_3309 = or(T_848, T_1158) node T_3310 = and(pageReplEn, T_3309) node T_3312 = neq(T_3310, UInt<1>("h00")) node T_3313 = or(T_853, T_1163) node T_3314 = and(pageReplEn, T_3313) node T_3316 = neq(T_3314, UInt<1>("h00")) node T_3317 = or(T_858, T_1168) node T_3318 = and(pageReplEn, T_3317) node T_3320 = neq(T_3318, UInt<1>("h00")) node T_3321 = or(T_863, T_1173) node T_3322 = and(pageReplEn, T_3321) node T_3324 = neq(T_3322, UInt<1>("h00")) node T_3325 = or(T_868, T_1178) node T_3326 = and(pageReplEn, T_3325) node T_3328 = neq(T_3326, UInt<1>("h00")) node T_3329 = or(T_873, T_1183) node T_3330 = and(pageReplEn, T_3329) node T_3332 = neq(T_3330, UInt<1>("h00")) node T_3333 = or(T_878, T_1188) node T_3334 = and(pageReplEn, T_3333) node T_3336 = neq(T_3334, UInt<1>("h00")) node T_3337 = or(T_883, T_1193) node T_3338 = and(pageReplEn, T_3337) node T_3340 = neq(T_3338, UInt<1>("h00")) node T_3341 = or(T_888, T_1198) node T_3342 = and(pageReplEn, T_3341) node T_3344 = neq(T_3342, UInt<1>("h00")) node T_3345 = or(T_893, T_1203) node T_3346 = and(pageReplEn, T_3345) node T_3348 = neq(T_3346, UInt<1>("h00")) node T_3349 = or(T_898, T_1208) node T_3350 = and(pageReplEn, T_3349) node T_3352 = neq(T_3350, UInt<1>("h00")) wire T_3354 : UInt<1>[62] T_3354[0] <= T_3108 T_3354[1] <= T_3112 T_3354[2] <= T_3116 T_3354[3] <= T_3120 T_3354[4] <= T_3124 T_3354[5] <= T_3128 T_3354[6] <= T_3132 T_3354[7] <= T_3136 T_3354[8] <= T_3140 T_3354[9] <= T_3144 T_3354[10] <= T_3148 T_3354[11] <= T_3152 T_3354[12] <= T_3156 T_3354[13] <= T_3160 T_3354[14] <= T_3164 T_3354[15] <= T_3168 T_3354[16] <= T_3172 T_3354[17] <= T_3176 T_3354[18] <= T_3180 T_3354[19] <= T_3184 T_3354[20] <= T_3188 T_3354[21] <= T_3192 T_3354[22] <= T_3196 T_3354[23] <= T_3200 T_3354[24] <= T_3204 T_3354[25] <= T_3208 T_3354[26] <= T_3212 T_3354[27] <= T_3216 T_3354[28] <= T_3220 T_3354[29] <= T_3224 T_3354[30] <= T_3228 T_3354[31] <= T_3232 T_3354[32] <= T_3236 T_3354[33] <= T_3240 T_3354[34] <= T_3244 T_3354[35] <= T_3248 T_3354[36] <= T_3252 T_3354[37] <= T_3256 T_3354[38] <= T_3260 T_3354[39] <= T_3264 T_3354[40] <= T_3268 T_3354[41] <= T_3272 T_3354[42] <= T_3276 T_3354[43] <= T_3280 T_3354[44] <= T_3284 T_3354[45] <= T_3288 T_3354[46] <= T_3292 T_3354[47] <= T_3296 T_3354[48] <= T_3300 T_3354[49] <= T_3304 T_3354[50] <= T_3308 T_3354[51] <= T_3312 T_3354[52] <= T_3316 T_3354[53] <= T_3320 T_3354[54] <= T_3324 T_3354[55] <= T_3328 T_3354[56] <= T_3332 T_3354[57] <= T_3336 T_3354[58] <= T_3340 T_3354[59] <= T_3344 T_3354[60] <= T_3348 T_3354[61] <= T_3352 node T_3418 = cat(T_3354[60], T_3354[59]) node T_3419 = cat(T_3354[61], T_3418) node T_3420 = cat(T_3354[58], T_3354[57]) node T_3421 = cat(T_3354[56], T_3354[55]) node T_3422 = cat(T_3420, T_3421) node T_3423 = cat(T_3419, T_3422) node T_3424 = cat(T_3354[54], T_3354[53]) node T_3425 = cat(T_3354[52], T_3354[51]) node T_3426 = cat(T_3424, T_3425) node T_3427 = cat(T_3354[50], T_3354[49]) node T_3428 = cat(T_3354[48], T_3354[47]) node T_3429 = cat(T_3427, T_3428) node T_3430 = cat(T_3426, T_3429) node T_3431 = cat(T_3423, T_3430) node T_3432 = cat(T_3354[46], T_3354[45]) node T_3433 = cat(T_3354[44], T_3354[43]) node T_3434 = cat(T_3432, T_3433) node T_3435 = cat(T_3354[42], T_3354[41]) node T_3436 = cat(T_3354[40], T_3354[39]) node T_3437 = cat(T_3435, T_3436) node T_3438 = cat(T_3434, T_3437) node T_3439 = cat(T_3354[38], T_3354[37]) node T_3440 = cat(T_3354[36], T_3354[35]) node T_3441 = cat(T_3439, T_3440) node T_3442 = cat(T_3354[34], T_3354[33]) node T_3443 = cat(T_3354[32], T_3354[31]) node T_3444 = cat(T_3442, T_3443) node T_3445 = cat(T_3441, T_3444) node T_3446 = cat(T_3438, T_3445) node T_3447 = cat(T_3431, T_3446) node T_3448 = cat(T_3354[29], T_3354[28]) node T_3449 = cat(T_3354[30], T_3448) node T_3450 = cat(T_3354[27], T_3354[26]) node T_3451 = cat(T_3354[25], T_3354[24]) node T_3452 = cat(T_3450, T_3451) node T_3453 = cat(T_3449, T_3452) node T_3454 = cat(T_3354[23], T_3354[22]) node T_3455 = cat(T_3354[21], T_3354[20]) node T_3456 = cat(T_3454, T_3455) node T_3457 = cat(T_3354[19], T_3354[18]) node T_3458 = cat(T_3354[17], T_3354[16]) node T_3459 = cat(T_3457, T_3458) node T_3460 = cat(T_3456, T_3459) node T_3461 = cat(T_3453, T_3460) node T_3462 = cat(T_3354[15], T_3354[14]) node T_3463 = cat(T_3354[13], T_3354[12]) node T_3464 = cat(T_3462, T_3463) node T_3465 = cat(T_3354[11], T_3354[10]) node T_3466 = cat(T_3354[9], T_3354[8]) node T_3467 = cat(T_3465, T_3466) node T_3468 = cat(T_3464, T_3467) node T_3469 = cat(T_3354[7], T_3354[6]) node T_3470 = cat(T_3354[5], T_3354[4]) node T_3471 = cat(T_3469, T_3470) node T_3472 = cat(T_3354[3], T_3354[2]) node T_3473 = cat(T_3354[1], T_3354[0]) node T_3474 = cat(T_3472, T_3473) node T_3475 = cat(T_3471, T_3474) node T_3476 = cat(T_3468, T_3475) node T_3477 = cat(T_3461, T_3476) node T_3478 = cat(T_3447, T_3477) node T_3480 = dshl(UInt<1>("h01"), T_3104) node T_3481 = not(T_3478) node T_3482 = and(idxValid, T_3481) node T_3483 = or(T_3482, T_3480) idxValid <= T_3483 infer mport T_3484 = idxs[T_3104], clk T_3484 <= r_btb_update.bits.pc infer mport T_3485 = tgts[T_3104], clk T_3485 <= io.req.bits.addr infer mport T_3486 = idxPages[T_3104], clk T_3486 <= idxPageUpdate infer mport T_3487 = tgtPages[T_3104], clk T_3487 <= tgtPageUpdate useRAS[T_3104] <= r_btb_update.bits.isReturn isJump[T_3104] <= r_btb_update.bits.isJump infer mport T_3490 = brIdx[T_3104], clk T_3490 <= UInt<1>("h00") node T_3493 = cat(UInt<2>("h01"), UInt<2>("h01")) node T_3494 = cat(UInt<2>("h01"), T_3493) node T_3495 = and(idxPageUpdateOH, T_3494) node T_3497 = neq(T_3495, UInt<1>("h00")) node T_3498 = mux(T_3497, doIdxPageRepl, doTgtPageRepl) node T_3499 = shr(r_btb_update.bits.pc, 12) node T_3500 = shr(io.req.bits.addr, 12) node T_3501 = mux(T_3497, T_3499, T_3500) node T_3502 = bit(pageReplEn, 0) node T_3503 = and(T_3498, T_3502) when T_3503 : infer mport T_3505 = pages[UInt<1>("h00")], clk T_3505 <= T_3501 skip node T_3506 = bit(pageReplEn, 2) node T_3507 = and(T_3498, T_3506) when T_3507 : infer mport T_3509 = pages[UInt<2>("h02")], clk T_3509 <= T_3501 skip node T_3510 = bit(pageReplEn, 4) node T_3511 = and(T_3498, T_3510) when T_3511 : infer mport T_3513 = pages[UInt<3>("h04")], clk T_3513 <= T_3501 skip node T_3514 = mux(T_3497, doTgtPageRepl, doIdxPageRepl) node T_3515 = shr(io.req.bits.addr, 12) node T_3516 = shr(r_btb_update.bits.pc, 12) node T_3517 = mux(T_3497, T_3515, T_3516) node T_3518 = bit(pageReplEn, 1) node T_3519 = and(T_3514, T_3518) when T_3519 : infer mport T_3521 = pages[UInt<1>("h01")], clk T_3521 <= T_3517 skip node T_3522 = bit(pageReplEn, 3) node T_3523 = and(T_3514, T_3522) when T_3523 : infer mport T_3525 = pages[UInt<2>("h03")], clk T_3525 <= T_3517 skip node T_3526 = bit(pageReplEn, 5) node T_3527 = and(T_3514, T_3526) when T_3527 : infer mport T_3529 = pages[UInt<3>("h05")], clk T_3529 <= T_3517 skip when doPageRepl : node T_3530 = or(pageValid, pageReplEn) pageValid <= T_3530 skip skip when io.invalidate : idxValid <= UInt<1>("h00") pageValid <= UInt<1>("h00") skip node T_3534 = neq(hits, UInt<1>("h00")) io.resp.valid <= T_3534 io.resp.bits.taken <= io.resp.valid node T_3535 = bit(hits, 0) node T_3536 = bit(hits, 1) node T_3537 = bit(hits, 2) node T_3538 = bit(hits, 3) node T_3539 = bit(hits, 4) node T_3540 = bit(hits, 5) node T_3541 = bit(hits, 6) node T_3542 = bit(hits, 7) node T_3543 = bit(hits, 8) node T_3544 = bit(hits, 9) node T_3545 = bit(hits, 10) node T_3546 = bit(hits, 11) node T_3547 = bit(hits, 12) node T_3548 = bit(hits, 13) node T_3549 = bit(hits, 14) node T_3550 = bit(hits, 15) node T_3551 = bit(hits, 16) node T_3552 = bit(hits, 17) node T_3553 = bit(hits, 18) node T_3554 = bit(hits, 19) node T_3555 = bit(hits, 20) node T_3556 = bit(hits, 21) node T_3557 = bit(hits, 22) node T_3558 = bit(hits, 23) node T_3559 = bit(hits, 24) node T_3560 = bit(hits, 25) node T_3561 = bit(hits, 26) node T_3562 = bit(hits, 27) node T_3563 = bit(hits, 28) node T_3564 = bit(hits, 29) node T_3565 = bit(hits, 30) node T_3566 = bit(hits, 31) node T_3567 = bit(hits, 32) node T_3568 = bit(hits, 33) node T_3569 = bit(hits, 34) node T_3570 = bit(hits, 35) node T_3571 = bit(hits, 36) node T_3572 = bit(hits, 37) node T_3573 = bit(hits, 38) node T_3574 = bit(hits, 39) node T_3575 = bit(hits, 40) node T_3576 = bit(hits, 41) node T_3577 = bit(hits, 42) node T_3578 = bit(hits, 43) node T_3579 = bit(hits, 44) node T_3580 = bit(hits, 45) node T_3581 = bit(hits, 46) node T_3582 = bit(hits, 47) node T_3583 = bit(hits, 48) node T_3584 = bit(hits, 49) node T_3585 = bit(hits, 50) node T_3586 = bit(hits, 51) node T_3587 = bit(hits, 52) node T_3588 = bit(hits, 53) node T_3589 = bit(hits, 54) node T_3590 = bit(hits, 55) node T_3591 = bit(hits, 56) node T_3592 = bit(hits, 57) node T_3593 = bit(hits, 58) node T_3594 = bit(hits, 59) node T_3595 = bit(hits, 60) node T_3596 = bit(hits, 61) node T_3598 = mux(T_3535, T_903, UInt<1>("h00")) node T_3600 = mux(T_3536, T_908, UInt<1>("h00")) node T_3602 = mux(T_3537, T_913, UInt<1>("h00")) node T_3604 = mux(T_3538, T_918, UInt<1>("h00")) node T_3606 = mux(T_3539, T_923, UInt<1>("h00")) node T_3608 = mux(T_3540, T_928, UInt<1>("h00")) node T_3610 = mux(T_3541, T_933, UInt<1>("h00")) node T_3612 = mux(T_3542, T_938, UInt<1>("h00")) node T_3614 = mux(T_3543, T_943, UInt<1>("h00")) node T_3616 = mux(T_3544, T_948, UInt<1>("h00")) node T_3618 = mux(T_3545, T_953, UInt<1>("h00")) node T_3620 = mux(T_3546, T_958, UInt<1>("h00")) node T_3622 = mux(T_3547, T_963, UInt<1>("h00")) node T_3624 = mux(T_3548, T_968, UInt<1>("h00")) node T_3626 = mux(T_3549, T_973, UInt<1>("h00")) node T_3628 = mux(T_3550, T_978, UInt<1>("h00")) node T_3630 = mux(T_3551, T_983, UInt<1>("h00")) node T_3632 = mux(T_3552, T_988, UInt<1>("h00")) node T_3634 = mux(T_3553, T_993, UInt<1>("h00")) node T_3636 = mux(T_3554, T_998, UInt<1>("h00")) node T_3638 = mux(T_3555, T_1003, UInt<1>("h00")) node T_3640 = mux(T_3556, T_1008, UInt<1>("h00")) node T_3642 = mux(T_3557, T_1013, UInt<1>("h00")) node T_3644 = mux(T_3558, T_1018, UInt<1>("h00")) node T_3646 = mux(T_3559, T_1023, UInt<1>("h00")) node T_3648 = mux(T_3560, T_1028, UInt<1>("h00")) node T_3650 = mux(T_3561, T_1033, UInt<1>("h00")) node T_3652 = mux(T_3562, T_1038, UInt<1>("h00")) node T_3654 = mux(T_3563, T_1043, UInt<1>("h00")) node T_3656 = mux(T_3564, T_1048, UInt<1>("h00")) node T_3658 = mux(T_3565, T_1053, UInt<1>("h00")) node T_3660 = mux(T_3566, T_1058, UInt<1>("h00")) node T_3662 = mux(T_3567, T_1063, UInt<1>("h00")) node T_3664 = mux(T_3568, T_1068, UInt<1>("h00")) node T_3666 = mux(T_3569, T_1073, UInt<1>("h00")) node T_3668 = mux(T_3570, T_1078, UInt<1>("h00")) node T_3670 = mux(T_3571, T_1083, UInt<1>("h00")) node T_3672 = mux(T_3572, T_1088, UInt<1>("h00")) node T_3674 = mux(T_3573, T_1093, UInt<1>("h00")) node T_3676 = mux(T_3574, T_1098, UInt<1>("h00")) node T_3678 = mux(T_3575, T_1103, UInt<1>("h00")) node T_3680 = mux(T_3576, T_1108, UInt<1>("h00")) node T_3682 = mux(T_3577, T_1113, UInt<1>("h00")) node T_3684 = mux(T_3578, T_1118, UInt<1>("h00")) node T_3686 = mux(T_3579, T_1123, UInt<1>("h00")) node T_3688 = mux(T_3580, T_1128, UInt<1>("h00")) node T_3690 = mux(T_3581, T_1133, UInt<1>("h00")) node T_3692 = mux(T_3582, T_1138, UInt<1>("h00")) node T_3694 = mux(T_3583, T_1143, UInt<1>("h00")) node T_3696 = mux(T_3584, T_1148, UInt<1>("h00")) node T_3698 = mux(T_3585, T_1153, UInt<1>("h00")) node T_3700 = mux(T_3586, T_1158, UInt<1>("h00")) node T_3702 = mux(T_3587, T_1163, UInt<1>("h00")) node T_3704 = mux(T_3588, T_1168, UInt<1>("h00")) node T_3706 = mux(T_3589, T_1173, UInt<1>("h00")) node T_3708 = mux(T_3590, T_1178, UInt<1>("h00")) node T_3710 = mux(T_3591, T_1183, UInt<1>("h00")) node T_3712 = mux(T_3592, T_1188, UInt<1>("h00")) node T_3714 = mux(T_3593, T_1193, UInt<1>("h00")) node T_3716 = mux(T_3594, T_1198, UInt<1>("h00")) node T_3718 = mux(T_3595, T_1203, UInt<1>("h00")) node T_3720 = mux(T_3596, T_1208, UInt<1>("h00")) node T_3722 = or(T_3598, T_3600) node T_3723 = or(T_3722, T_3602) node T_3724 = or(T_3723, T_3604) node T_3725 = or(T_3724, T_3606) node T_3726 = or(T_3725, T_3608) node T_3727 = or(T_3726, T_3610) node T_3728 = or(T_3727, T_3612) node T_3729 = or(T_3728, T_3614) node T_3730 = or(T_3729, T_3616) node T_3731 = or(T_3730, T_3618) node T_3732 = or(T_3731, T_3620) node T_3733 = or(T_3732, T_3622) node T_3734 = or(T_3733, T_3624) node T_3735 = or(T_3734, T_3626) node T_3736 = or(T_3735, T_3628) node T_3737 = or(T_3736, T_3630) node T_3738 = or(T_3737, T_3632) node T_3739 = or(T_3738, T_3634) node T_3740 = or(T_3739, T_3636) node T_3741 = or(T_3740, T_3638) node T_3742 = or(T_3741, T_3640) node T_3743 = or(T_3742, T_3642) node T_3744 = or(T_3743, T_3644) node T_3745 = or(T_3744, T_3646) node T_3746 = or(T_3745, T_3648) node T_3747 = or(T_3746, T_3650) node T_3748 = or(T_3747, T_3652) node T_3749 = or(T_3748, T_3654) node T_3750 = or(T_3749, T_3656) node T_3751 = or(T_3750, T_3658) node T_3752 = or(T_3751, T_3660) node T_3753 = or(T_3752, T_3662) node T_3754 = or(T_3753, T_3664) node T_3755 = or(T_3754, T_3666) node T_3756 = or(T_3755, T_3668) node T_3757 = or(T_3756, T_3670) node T_3758 = or(T_3757, T_3672) node T_3759 = or(T_3758, T_3674) node T_3760 = or(T_3759, T_3676) node T_3761 = or(T_3760, T_3678) node T_3762 = or(T_3761, T_3680) node T_3763 = or(T_3762, T_3682) node T_3764 = or(T_3763, T_3684) node T_3765 = or(T_3764, T_3686) node T_3766 = or(T_3765, T_3688) node T_3767 = or(T_3766, T_3690) node T_3768 = or(T_3767, T_3692) node T_3769 = or(T_3768, T_3694) node T_3770 = or(T_3769, T_3696) node T_3771 = or(T_3770, T_3698) node T_3772 = or(T_3771, T_3700) node T_3773 = or(T_3772, T_3702) node T_3774 = or(T_3773, T_3704) node T_3775 = or(T_3774, T_3706) node T_3776 = or(T_3775, T_3708) node T_3777 = or(T_3776, T_3710) node T_3778 = or(T_3777, T_3712) node T_3779 = or(T_3778, T_3714) node T_3780 = or(T_3779, T_3716) node T_3781 = or(T_3780, T_3718) node T_3782 = or(T_3781, T_3720) wire T_3783 : UInt<6> T_3783 <= UInt<1>("h00") T_3783 <= T_3782 node T_3785 = bit(T_3783, 0) node T_3786 = bit(T_3783, 1) node T_3787 = bit(T_3783, 2) node T_3788 = bit(T_3783, 3) node T_3789 = bit(T_3783, 4) node T_3790 = bit(T_3783, 5) infer mport T_3792 = pages[UInt<1>("h00")], clk infer mport T_3794 = pages[UInt<1>("h01")], clk infer mport T_3796 = pages[UInt<2>("h02")], clk infer mport T_3798 = pages[UInt<2>("h03")], clk infer mport T_3800 = pages[UInt<3>("h04")], clk infer mport T_3802 = pages[UInt<3>("h05")], clk node T_3804 = mux(T_3785, T_3792, UInt<1>("h00")) node T_3806 = mux(T_3786, T_3794, UInt<1>("h00")) node T_3808 = mux(T_3787, T_3796, UInt<1>("h00")) node T_3810 = mux(T_3788, T_3798, UInt<1>("h00")) node T_3812 = mux(T_3789, T_3800, UInt<1>("h00")) node T_3814 = mux(T_3790, T_3802, UInt<1>("h00")) node T_3816 = or(T_3804, T_3806) node T_3817 = or(T_3816, T_3808) node T_3818 = or(T_3817, T_3810) node T_3819 = or(T_3818, T_3812) node T_3820 = or(T_3819, T_3814) wire T_3821 : UInt<27> T_3821 <= UInt<1>("h00") T_3821 <= T_3820 node T_3823 = bit(hits, 0) node T_3824 = bit(hits, 1) node T_3825 = bit(hits, 2) node T_3826 = bit(hits, 3) node T_3827 = bit(hits, 4) node T_3828 = bit(hits, 5) node T_3829 = bit(hits, 6) node T_3830 = bit(hits, 7) node T_3831 = bit(hits, 8) node T_3832 = bit(hits, 9) node T_3833 = bit(hits, 10) node T_3834 = bit(hits, 11) node T_3835 = bit(hits, 12) node T_3836 = bit(hits, 13) node T_3837 = bit(hits, 14) node T_3838 = bit(hits, 15) node T_3839 = bit(hits, 16) node T_3840 = bit(hits, 17) node T_3841 = bit(hits, 18) node T_3842 = bit(hits, 19) node T_3843 = bit(hits, 20) node T_3844 = bit(hits, 21) node T_3845 = bit(hits, 22) node T_3846 = bit(hits, 23) node T_3847 = bit(hits, 24) node T_3848 = bit(hits, 25) node T_3849 = bit(hits, 26) node T_3850 = bit(hits, 27) node T_3851 = bit(hits, 28) node T_3852 = bit(hits, 29) node T_3853 = bit(hits, 30) node T_3854 = bit(hits, 31) node T_3855 = bit(hits, 32) node T_3856 = bit(hits, 33) node T_3857 = bit(hits, 34) node T_3858 = bit(hits, 35) node T_3859 = bit(hits, 36) node T_3860 = bit(hits, 37) node T_3861 = bit(hits, 38) node T_3862 = bit(hits, 39) node T_3863 = bit(hits, 40) node T_3864 = bit(hits, 41) node T_3865 = bit(hits, 42) node T_3866 = bit(hits, 43) node T_3867 = bit(hits, 44) node T_3868 = bit(hits, 45) node T_3869 = bit(hits, 46) node T_3870 = bit(hits, 47) node T_3871 = bit(hits, 48) node T_3872 = bit(hits, 49) node T_3873 = bit(hits, 50) node T_3874 = bit(hits, 51) node T_3875 = bit(hits, 52) node T_3876 = bit(hits, 53) node T_3877 = bit(hits, 54) node T_3878 = bit(hits, 55) node T_3879 = bit(hits, 56) node T_3880 = bit(hits, 57) node T_3881 = bit(hits, 58) node T_3882 = bit(hits, 59) node T_3883 = bit(hits, 60) node T_3884 = bit(hits, 61) infer mport T_3886 = tgts[UInt<1>("h00")], clk infer mport T_3888 = tgts[UInt<1>("h01")], clk infer mport T_3890 = tgts[UInt<2>("h02")], clk infer mport T_3892 = tgts[UInt<2>("h03")], clk infer mport T_3894 = tgts[UInt<3>("h04")], clk infer mport T_3896 = tgts[UInt<3>("h05")], clk infer mport T_3898 = tgts[UInt<3>("h06")], clk infer mport T_3900 = tgts[UInt<3>("h07")], clk infer mport T_3902 = tgts[UInt<4>("h08")], clk infer mport T_3904 = tgts[UInt<4>("h09")], clk infer mport T_3906 = tgts[UInt<4>("h0a")], clk infer mport T_3908 = tgts[UInt<4>("h0b")], clk infer mport T_3910 = tgts[UInt<4>("h0c")], clk infer mport T_3912 = tgts[UInt<4>("h0d")], clk infer mport T_3914 = tgts[UInt<4>("h0e")], clk infer mport T_3916 = tgts[UInt<4>("h0f")], clk infer mport T_3918 = tgts[UInt<5>("h010")], clk infer mport T_3920 = tgts[UInt<5>("h011")], clk infer mport T_3922 = tgts[UInt<5>("h012")], clk infer mport T_3924 = tgts[UInt<5>("h013")], clk infer mport T_3926 = tgts[UInt<5>("h014")], clk infer mport T_3928 = tgts[UInt<5>("h015")], clk infer mport T_3930 = tgts[UInt<5>("h016")], clk infer mport T_3932 = tgts[UInt<5>("h017")], clk infer mport T_3934 = tgts[UInt<5>("h018")], clk infer mport T_3936 = tgts[UInt<5>("h019")], clk infer mport T_3938 = tgts[UInt<5>("h01a")], clk infer mport T_3940 = tgts[UInt<5>("h01b")], clk infer mport T_3942 = tgts[UInt<5>("h01c")], clk infer mport T_3944 = tgts[UInt<5>("h01d")], clk infer mport T_3946 = tgts[UInt<5>("h01e")], clk infer mport T_3948 = tgts[UInt<5>("h01f")], clk infer mport T_3950 = tgts[UInt<6>("h020")], clk infer mport T_3952 = tgts[UInt<6>("h021")], clk infer mport T_3954 = tgts[UInt<6>("h022")], clk infer mport T_3956 = tgts[UInt<6>("h023")], clk infer mport T_3958 = tgts[UInt<6>("h024")], clk infer mport T_3960 = tgts[UInt<6>("h025")], clk infer mport T_3962 = tgts[UInt<6>("h026")], clk infer mport T_3964 = tgts[UInt<6>("h027")], clk infer mport T_3966 = tgts[UInt<6>("h028")], clk infer mport T_3968 = tgts[UInt<6>("h029")], clk infer mport T_3970 = tgts[UInt<6>("h02a")], clk infer mport T_3972 = tgts[UInt<6>("h02b")], clk infer mport T_3974 = tgts[UInt<6>("h02c")], clk infer mport T_3976 = tgts[UInt<6>("h02d")], clk infer mport T_3978 = tgts[UInt<6>("h02e")], clk infer mport T_3980 = tgts[UInt<6>("h02f")], clk infer mport T_3982 = tgts[UInt<6>("h030")], clk infer mport T_3984 = tgts[UInt<6>("h031")], clk infer mport T_3986 = tgts[UInt<6>("h032")], clk infer mport T_3988 = tgts[UInt<6>("h033")], clk infer mport T_3990 = tgts[UInt<6>("h034")], clk infer mport T_3992 = tgts[UInt<6>("h035")], clk infer mport T_3994 = tgts[UInt<6>("h036")], clk infer mport T_3996 = tgts[UInt<6>("h037")], clk infer mport T_3998 = tgts[UInt<6>("h038")], clk infer mport T_4000 = tgts[UInt<6>("h039")], clk infer mport T_4002 = tgts[UInt<6>("h03a")], clk infer mport T_4004 = tgts[UInt<6>("h03b")], clk infer mport T_4006 = tgts[UInt<6>("h03c")], clk infer mport T_4008 = tgts[UInt<6>("h03d")], clk node T_4010 = mux(T_3823, T_3886, UInt<1>("h00")) node T_4012 = mux(T_3824, T_3888, UInt<1>("h00")) node T_4014 = mux(T_3825, T_3890, UInt<1>("h00")) node T_4016 = mux(T_3826, T_3892, UInt<1>("h00")) node T_4018 = mux(T_3827, T_3894, UInt<1>("h00")) node T_4020 = mux(T_3828, T_3896, UInt<1>("h00")) node T_4022 = mux(T_3829, T_3898, UInt<1>("h00")) node T_4024 = mux(T_3830, T_3900, UInt<1>("h00")) node T_4026 = mux(T_3831, T_3902, UInt<1>("h00")) node T_4028 = mux(T_3832, T_3904, UInt<1>("h00")) node T_4030 = mux(T_3833, T_3906, UInt<1>("h00")) node T_4032 = mux(T_3834, T_3908, UInt<1>("h00")) node T_4034 = mux(T_3835, T_3910, UInt<1>("h00")) node T_4036 = mux(T_3836, T_3912, UInt<1>("h00")) node T_4038 = mux(T_3837, T_3914, UInt<1>("h00")) node T_4040 = mux(T_3838, T_3916, UInt<1>("h00")) node T_4042 = mux(T_3839, T_3918, UInt<1>("h00")) node T_4044 = mux(T_3840, T_3920, UInt<1>("h00")) node T_4046 = mux(T_3841, T_3922, UInt<1>("h00")) node T_4048 = mux(T_3842, T_3924, UInt<1>("h00")) node T_4050 = mux(T_3843, T_3926, UInt<1>("h00")) node T_4052 = mux(T_3844, T_3928, UInt<1>("h00")) node T_4054 = mux(T_3845, T_3930, UInt<1>("h00")) node T_4056 = mux(T_3846, T_3932, UInt<1>("h00")) node T_4058 = mux(T_3847, T_3934, UInt<1>("h00")) node T_4060 = mux(T_3848, T_3936, UInt<1>("h00")) node T_4062 = mux(T_3849, T_3938, UInt<1>("h00")) node T_4064 = mux(T_3850, T_3940, UInt<1>("h00")) node T_4066 = mux(T_3851, T_3942, UInt<1>("h00")) node T_4068 = mux(T_3852, T_3944, UInt<1>("h00")) node T_4070 = mux(T_3853, T_3946, UInt<1>("h00")) node T_4072 = mux(T_3854, T_3948, UInt<1>("h00")) node T_4074 = mux(T_3855, T_3950, UInt<1>("h00")) node T_4076 = mux(T_3856, T_3952, UInt<1>("h00")) node T_4078 = mux(T_3857, T_3954, UInt<1>("h00")) node T_4080 = mux(T_3858, T_3956, UInt<1>("h00")) node T_4082 = mux(T_3859, T_3958, UInt<1>("h00")) node T_4084 = mux(T_3860, T_3960, UInt<1>("h00")) node T_4086 = mux(T_3861, T_3962, UInt<1>("h00")) node T_4088 = mux(T_3862, T_3964, UInt<1>("h00")) node T_4090 = mux(T_3863, T_3966, UInt<1>("h00")) node T_4092 = mux(T_3864, T_3968, UInt<1>("h00")) node T_4094 = mux(T_3865, T_3970, UInt<1>("h00")) node T_4096 = mux(T_3866, T_3972, UInt<1>("h00")) node T_4098 = mux(T_3867, T_3974, UInt<1>("h00")) node T_4100 = mux(T_3868, T_3976, UInt<1>("h00")) node T_4102 = mux(T_3869, T_3978, UInt<1>("h00")) node T_4104 = mux(T_3870, T_3980, UInt<1>("h00")) node T_4106 = mux(T_3871, T_3982, UInt<1>("h00")) node T_4108 = mux(T_3872, T_3984, UInt<1>("h00")) node T_4110 = mux(T_3873, T_3986, UInt<1>("h00")) node T_4112 = mux(T_3874, T_3988, UInt<1>("h00")) node T_4114 = mux(T_3875, T_3990, UInt<1>("h00")) node T_4116 = mux(T_3876, T_3992, UInt<1>("h00")) node T_4118 = mux(T_3877, T_3994, UInt<1>("h00")) node T_4120 = mux(T_3878, T_3996, UInt<1>("h00")) node T_4122 = mux(T_3879, T_3998, UInt<1>("h00")) node T_4124 = mux(T_3880, T_4000, UInt<1>("h00")) node T_4126 = mux(T_3881, T_4002, UInt<1>("h00")) node T_4128 = mux(T_3882, T_4004, UInt<1>("h00")) node T_4130 = mux(T_3883, T_4006, UInt<1>("h00")) node T_4132 = mux(T_3884, T_4008, UInt<1>("h00")) node T_4134 = or(T_4010, T_4012) node T_4135 = or(T_4134, T_4014) node T_4136 = or(T_4135, T_4016) node T_4137 = or(T_4136, T_4018) node T_4138 = or(T_4137, T_4020) node T_4139 = or(T_4138, T_4022) node T_4140 = or(T_4139, T_4024) node T_4141 = or(T_4140, T_4026) node T_4142 = or(T_4141, T_4028) node T_4143 = or(T_4142, T_4030) node T_4144 = or(T_4143, T_4032) node T_4145 = or(T_4144, T_4034) node T_4146 = or(T_4145, T_4036) node T_4147 = or(T_4146, T_4038) node T_4148 = or(T_4147, T_4040) node T_4149 = or(T_4148, T_4042) node T_4150 = or(T_4149, T_4044) node T_4151 = or(T_4150, T_4046) node T_4152 = or(T_4151, T_4048) node T_4153 = or(T_4152, T_4050) node T_4154 = or(T_4153, T_4052) node T_4155 = or(T_4154, T_4054) node T_4156 = or(T_4155, T_4056) node T_4157 = or(T_4156, T_4058) node T_4158 = or(T_4157, T_4060) node T_4159 = or(T_4158, T_4062) node T_4160 = or(T_4159, T_4064) node T_4161 = or(T_4160, T_4066) node T_4162 = or(T_4161, T_4068) node T_4163 = or(T_4162, T_4070) node T_4164 = or(T_4163, T_4072) node T_4165 = or(T_4164, T_4074) node T_4166 = or(T_4165, T_4076) node T_4167 = or(T_4166, T_4078) node T_4168 = or(T_4167, T_4080) node T_4169 = or(T_4168, T_4082) node T_4170 = or(T_4169, T_4084) node T_4171 = or(T_4170, T_4086) node T_4172 = or(T_4171, T_4088) node T_4173 = or(T_4172, T_4090) node T_4174 = or(T_4173, T_4092) node T_4175 = or(T_4174, T_4094) node T_4176 = or(T_4175, T_4096) node T_4177 = or(T_4176, T_4098) node T_4178 = or(T_4177, T_4100) node T_4179 = or(T_4178, T_4102) node T_4180 = or(T_4179, T_4104) node T_4181 = or(T_4180, T_4106) node T_4182 = or(T_4181, T_4108) node T_4183 = or(T_4182, T_4110) node T_4184 = or(T_4183, T_4112) node T_4185 = or(T_4184, T_4114) node T_4186 = or(T_4185, T_4116) node T_4187 = or(T_4186, T_4118) node T_4188 = or(T_4187, T_4120) node T_4189 = or(T_4188, T_4122) node T_4190 = or(T_4189, T_4124) node T_4191 = or(T_4190, T_4126) node T_4192 = or(T_4191, T_4128) node T_4193 = or(T_4192, T_4130) node T_4194 = or(T_4193, T_4132) wire T_4195 : UInt<12> T_4195 <= UInt<1>("h00") T_4195 <= T_4194 node T_4197 = cat(T_3821, T_4195) io.resp.bits.target <= T_4197 node T_4198 = bits(hits, 61, 32) node T_4199 = bits(hits, 31, 0) node T_4201 = neq(T_4198, UInt<1>("h00")) node T_4202 = or(T_4198, T_4199) node T_4203 = bits(T_4202, 31, 16) node T_4204 = bits(T_4202, 15, 0) node T_4206 = neq(T_4203, UInt<1>("h00")) node T_4207 = or(T_4203, T_4204) node T_4208 = bits(T_4207, 15, 8) node T_4209 = bits(T_4207, 7, 0) node T_4211 = neq(T_4208, UInt<1>("h00")) node T_4212 = or(T_4208, T_4209) node T_4213 = bits(T_4212, 7, 4) node T_4214 = bits(T_4212, 3, 0) node T_4216 = neq(T_4213, UInt<1>("h00")) node T_4217 = or(T_4213, T_4214) node T_4218 = bits(T_4217, 3, 2) node T_4219 = bits(T_4217, 1, 0) node T_4221 = neq(T_4218, UInt<1>("h00")) node T_4222 = or(T_4218, T_4219) node T_4223 = bit(T_4222, 1) node T_4224 = cat(T_4221, T_4223) node T_4225 = cat(T_4216, T_4224) node T_4226 = cat(T_4211, T_4225) node T_4227 = cat(T_4206, T_4226) node T_4228 = cat(T_4201, T_4227) io.resp.bits.entry <= T_4228 infer mport T_4229 = brIdx[io.resp.bits.entry], clk io.resp.bits.bridx <= T_4229 io.resp.bits.mask <= UInt<1>("h01") cmem T_4233 : UInt<2>[128] reg T_4235 : UInt<7>, clk, UInt<1>("h00"), T_4235 node T_4236 = bit(hits, 0) node T_4237 = bit(hits, 1) node T_4238 = bit(hits, 2) node T_4239 = bit(hits, 3) node T_4240 = bit(hits, 4) node T_4241 = bit(hits, 5) node T_4242 = bit(hits, 6) node T_4243 = bit(hits, 7) node T_4244 = bit(hits, 8) node T_4245 = bit(hits, 9) node T_4246 = bit(hits, 10) node T_4247 = bit(hits, 11) node T_4248 = bit(hits, 12) node T_4249 = bit(hits, 13) node T_4250 = bit(hits, 14) node T_4251 = bit(hits, 15) node T_4252 = bit(hits, 16) node T_4253 = bit(hits, 17) node T_4254 = bit(hits, 18) node T_4255 = bit(hits, 19) node T_4256 = bit(hits, 20) node T_4257 = bit(hits, 21) node T_4258 = bit(hits, 22) node T_4259 = bit(hits, 23) node T_4260 = bit(hits, 24) node T_4261 = bit(hits, 25) node T_4262 = bit(hits, 26) node T_4263 = bit(hits, 27) node T_4264 = bit(hits, 28) node T_4265 = bit(hits, 29) node T_4266 = bit(hits, 30) node T_4267 = bit(hits, 31) node T_4268 = bit(hits, 32) node T_4269 = bit(hits, 33) node T_4270 = bit(hits, 34) node T_4271 = bit(hits, 35) node T_4272 = bit(hits, 36) node T_4273 = bit(hits, 37) node T_4274 = bit(hits, 38) node T_4275 = bit(hits, 39) node T_4276 = bit(hits, 40) node T_4277 = bit(hits, 41) node T_4278 = bit(hits, 42) node T_4279 = bit(hits, 43) node T_4280 = bit(hits, 44) node T_4281 = bit(hits, 45) node T_4282 = bit(hits, 46) node T_4283 = bit(hits, 47) node T_4284 = bit(hits, 48) node T_4285 = bit(hits, 49) node T_4286 = bit(hits, 50) node T_4287 = bit(hits, 51) node T_4288 = bit(hits, 52) node T_4289 = bit(hits, 53) node T_4290 = bit(hits, 54) node T_4291 = bit(hits, 55) node T_4292 = bit(hits, 56) node T_4293 = bit(hits, 57) node T_4294 = bit(hits, 58) node T_4295 = bit(hits, 59) node T_4296 = bit(hits, 60) node T_4297 = bit(hits, 61) node T_4299 = shl(isJump[0], 0) node T_4300 = mux(T_4236, T_4299, UInt<1>("h00")) node T_4302 = shl(isJump[1], 0) node T_4303 = mux(T_4237, T_4302, UInt<1>("h00")) node T_4305 = shl(isJump[2], 0) node T_4306 = mux(T_4238, T_4305, UInt<1>("h00")) node T_4308 = shl(isJump[3], 0) node T_4309 = mux(T_4239, T_4308, UInt<1>("h00")) node T_4311 = shl(isJump[4], 0) node T_4312 = mux(T_4240, T_4311, UInt<1>("h00")) node T_4314 = shl(isJump[5], 0) node T_4315 = mux(T_4241, T_4314, UInt<1>("h00")) node T_4317 = shl(isJump[6], 0) node T_4318 = mux(T_4242, T_4317, UInt<1>("h00")) node T_4320 = shl(isJump[7], 0) node T_4321 = mux(T_4243, T_4320, UInt<1>("h00")) node T_4323 = shl(isJump[8], 0) node T_4324 = mux(T_4244, T_4323, UInt<1>("h00")) node T_4326 = shl(isJump[9], 0) node T_4327 = mux(T_4245, T_4326, UInt<1>("h00")) node T_4329 = shl(isJump[10], 0) node T_4330 = mux(T_4246, T_4329, UInt<1>("h00")) node T_4332 = shl(isJump[11], 0) node T_4333 = mux(T_4247, T_4332, UInt<1>("h00")) node T_4335 = shl(isJump[12], 0) node T_4336 = mux(T_4248, T_4335, UInt<1>("h00")) node T_4338 = shl(isJump[13], 0) node T_4339 = mux(T_4249, T_4338, UInt<1>("h00")) node T_4341 = shl(isJump[14], 0) node T_4342 = mux(T_4250, T_4341, UInt<1>("h00")) node T_4344 = shl(isJump[15], 0) node T_4345 = mux(T_4251, T_4344, UInt<1>("h00")) node T_4347 = shl(isJump[16], 0) node T_4348 = mux(T_4252, T_4347, UInt<1>("h00")) node T_4350 = shl(isJump[17], 0) node T_4351 = mux(T_4253, T_4350, UInt<1>("h00")) node T_4353 = shl(isJump[18], 0) node T_4354 = mux(T_4254, T_4353, UInt<1>("h00")) node T_4356 = shl(isJump[19], 0) node T_4357 = mux(T_4255, T_4356, UInt<1>("h00")) node T_4359 = shl(isJump[20], 0) node T_4360 = mux(T_4256, T_4359, UInt<1>("h00")) node T_4362 = shl(isJump[21], 0) node T_4363 = mux(T_4257, T_4362, UInt<1>("h00")) node T_4365 = shl(isJump[22], 0) node T_4366 = mux(T_4258, T_4365, UInt<1>("h00")) node T_4368 = shl(isJump[23], 0) node T_4369 = mux(T_4259, T_4368, UInt<1>("h00")) node T_4371 = shl(isJump[24], 0) node T_4372 = mux(T_4260, T_4371, UInt<1>("h00")) node T_4374 = shl(isJump[25], 0) node T_4375 = mux(T_4261, T_4374, UInt<1>("h00")) node T_4377 = shl(isJump[26], 0) node T_4378 = mux(T_4262, T_4377, UInt<1>("h00")) node T_4380 = shl(isJump[27], 0) node T_4381 = mux(T_4263, T_4380, UInt<1>("h00")) node T_4383 = shl(isJump[28], 0) node T_4384 = mux(T_4264, T_4383, UInt<1>("h00")) node T_4386 = shl(isJump[29], 0) node T_4387 = mux(T_4265, T_4386, UInt<1>("h00")) node T_4389 = shl(isJump[30], 0) node T_4390 = mux(T_4266, T_4389, UInt<1>("h00")) node T_4392 = shl(isJump[31], 0) node T_4393 = mux(T_4267, T_4392, UInt<1>("h00")) node T_4395 = shl(isJump[32], 0) node T_4396 = mux(T_4268, T_4395, UInt<1>("h00")) node T_4398 = shl(isJump[33], 0) node T_4399 = mux(T_4269, T_4398, UInt<1>("h00")) node T_4401 = shl(isJump[34], 0) node T_4402 = mux(T_4270, T_4401, UInt<1>("h00")) node T_4404 = shl(isJump[35], 0) node T_4405 = mux(T_4271, T_4404, UInt<1>("h00")) node T_4407 = shl(isJump[36], 0) node T_4408 = mux(T_4272, T_4407, UInt<1>("h00")) node T_4410 = shl(isJump[37], 0) node T_4411 = mux(T_4273, T_4410, UInt<1>("h00")) node T_4413 = shl(isJump[38], 0) node T_4414 = mux(T_4274, T_4413, UInt<1>("h00")) node T_4416 = shl(isJump[39], 0) node T_4417 = mux(T_4275, T_4416, UInt<1>("h00")) node T_4419 = shl(isJump[40], 0) node T_4420 = mux(T_4276, T_4419, UInt<1>("h00")) node T_4422 = shl(isJump[41], 0) node T_4423 = mux(T_4277, T_4422, UInt<1>("h00")) node T_4425 = shl(isJump[42], 0) node T_4426 = mux(T_4278, T_4425, UInt<1>("h00")) node T_4428 = shl(isJump[43], 0) node T_4429 = mux(T_4279, T_4428, UInt<1>("h00")) node T_4431 = shl(isJump[44], 0) node T_4432 = mux(T_4280, T_4431, UInt<1>("h00")) node T_4434 = shl(isJump[45], 0) node T_4435 = mux(T_4281, T_4434, UInt<1>("h00")) node T_4437 = shl(isJump[46], 0) node T_4438 = mux(T_4282, T_4437, UInt<1>("h00")) node T_4440 = shl(isJump[47], 0) node T_4441 = mux(T_4283, T_4440, UInt<1>("h00")) node T_4443 = shl(isJump[48], 0) node T_4444 = mux(T_4284, T_4443, UInt<1>("h00")) node T_4446 = shl(isJump[49], 0) node T_4447 = mux(T_4285, T_4446, UInt<1>("h00")) node T_4449 = shl(isJump[50], 0) node T_4450 = mux(T_4286, T_4449, UInt<1>("h00")) node T_4452 = shl(isJump[51], 0) node T_4453 = mux(T_4287, T_4452, UInt<1>("h00")) node T_4455 = shl(isJump[52], 0) node T_4456 = mux(T_4288, T_4455, UInt<1>("h00")) node T_4458 = shl(isJump[53], 0) node T_4459 = mux(T_4289, T_4458, UInt<1>("h00")) node T_4461 = shl(isJump[54], 0) node T_4462 = mux(T_4290, T_4461, UInt<1>("h00")) node T_4464 = shl(isJump[55], 0) node T_4465 = mux(T_4291, T_4464, UInt<1>("h00")) node T_4467 = shl(isJump[56], 0) node T_4468 = mux(T_4292, T_4467, UInt<1>("h00")) node T_4470 = shl(isJump[57], 0) node T_4471 = mux(T_4293, T_4470, UInt<1>("h00")) node T_4473 = shl(isJump[58], 0) node T_4474 = mux(T_4294, T_4473, UInt<1>("h00")) node T_4476 = shl(isJump[59], 0) node T_4477 = mux(T_4295, T_4476, UInt<1>("h00")) node T_4479 = shl(isJump[60], 0) node T_4480 = mux(T_4296, T_4479, UInt<1>("h00")) node T_4482 = shl(isJump[61], 0) node T_4483 = mux(T_4297, T_4482, UInt<1>("h00")) node T_4485 = or(T_4300, T_4303) node T_4486 = or(T_4485, T_4306) node T_4487 = or(T_4486, T_4309) node T_4488 = or(T_4487, T_4312) node T_4489 = or(T_4488, T_4315) node T_4490 = or(T_4489, T_4318) node T_4491 = or(T_4490, T_4321) node T_4492 = or(T_4491, T_4324) node T_4493 = or(T_4492, T_4327) node T_4494 = or(T_4493, T_4330) node T_4495 = or(T_4494, T_4333) node T_4496 = or(T_4495, T_4336) node T_4497 = or(T_4496, T_4339) node T_4498 = or(T_4497, T_4342) node T_4499 = or(T_4498, T_4345) node T_4500 = or(T_4499, T_4348) node T_4501 = or(T_4500, T_4351) node T_4502 = or(T_4501, T_4354) node T_4503 = or(T_4502, T_4357) node T_4504 = or(T_4503, T_4360) node T_4505 = or(T_4504, T_4363) node T_4506 = or(T_4505, T_4366) node T_4507 = or(T_4506, T_4369) node T_4508 = or(T_4507, T_4372) node T_4509 = or(T_4508, T_4375) node T_4510 = or(T_4509, T_4378) node T_4511 = or(T_4510, T_4381) node T_4512 = or(T_4511, T_4384) node T_4513 = or(T_4512, T_4387) node T_4514 = or(T_4513, T_4390) node T_4515 = or(T_4514, T_4393) node T_4516 = or(T_4515, T_4396) node T_4517 = or(T_4516, T_4399) node T_4518 = or(T_4517, T_4402) node T_4519 = or(T_4518, T_4405) node T_4520 = or(T_4519, T_4408) node T_4521 = or(T_4520, T_4411) node T_4522 = or(T_4521, T_4414) node T_4523 = or(T_4522, T_4417) node T_4524 = or(T_4523, T_4420) node T_4525 = or(T_4524, T_4423) node T_4526 = or(T_4525, T_4426) node T_4527 = or(T_4526, T_4429) node T_4528 = or(T_4527, T_4432) node T_4529 = or(T_4528, T_4435) node T_4530 = or(T_4529, T_4438) node T_4531 = or(T_4530, T_4441) node T_4532 = or(T_4531, T_4444) node T_4533 = or(T_4532, T_4447) node T_4534 = or(T_4533, T_4450) node T_4535 = or(T_4534, T_4453) node T_4536 = or(T_4535, T_4456) node T_4537 = or(T_4536, T_4459) node T_4538 = or(T_4537, T_4462) node T_4539 = or(T_4538, T_4465) node T_4540 = or(T_4539, T_4468) node T_4541 = or(T_4540, T_4471) node T_4542 = or(T_4541, T_4474) node T_4543 = or(T_4542, T_4477) node T_4544 = or(T_4543, T_4480) node T_4545 = or(T_4544, T_4483) wire T_4546 : UInt<1> T_4546 <= UInt<1>("h00") T_4546 <= T_4545 node T_4549 = eq(T_4546, UInt<1>("h00")) node T_4550 = and(io.req.valid, io.resp.valid) node T_4551 = and(T_4550, T_4549) wire T_4555 : {history : UInt<7>, value : UInt<2>} T_4555.value <= UInt<1>("h00") T_4555.history <= UInt<1>("h00") node T_4560 = bits(io.req.bits.addr, 8, 2) node T_4561 = xor(T_4560, T_4235) infer mport T_4562 = T_4233[T_4561], clk T_4555.value <= T_4562 T_4555.history <= T_4235 node T_4563 = bit(T_4555.value, 0) when T_4551 : node T_4564 = bits(T_4235, 6, 1) node T_4565 = cat(T_4563, T_4564) T_4235 <= T_4565 skip node T_4566 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) when T_4566 : node T_4567 = bits(io.bht_update.bits.pc, 8, 2) node T_4568 = xor(T_4567, io.bht_update.bits.prediction.bits.bht.history) infer mport T_4569 = T_4233[T_4568], clk node T_4570 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) node T_4571 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) node T_4572 = and(T_4570, T_4571) node T_4573 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) node T_4574 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) node T_4575 = or(T_4573, T_4574) node T_4576 = and(T_4575, io.bht_update.bits.taken) node T_4577 = or(T_4572, T_4576) node T_4578 = cat(io.bht_update.bits.taken, T_4577) T_4569 <= T_4578 when io.bht_update.bits.mispredict : node T_4579 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) node T_4580 = cat(io.bht_update.bits.taken, T_4579) T_4235 <= T_4580 skip skip node T_4581 = bit(T_4555.value, 0) node T_4583 = eq(T_4581, UInt<1>("h00")) node T_4584 = and(T_4583, T_4549) when T_4584 : io.resp.bits.taken <= UInt<1>("h00") skip io.resp.bits.bht <- T_4555 reg T_4587 : UInt<2>, clk, reset, UInt<2>("h00") reg T_4589 : UInt<1>, clk, reset, UInt<1>("h00") reg T_4598 : UInt[2], clk, UInt<1>("h00"), T_4598 node T_4602 = bit(hits, 0) node T_4603 = bit(hits, 1) node T_4604 = bit(hits, 2) node T_4605 = bit(hits, 3) node T_4606 = bit(hits, 4) node T_4607 = bit(hits, 5) node T_4608 = bit(hits, 6) node T_4609 = bit(hits, 7) node T_4610 = bit(hits, 8) node T_4611 = bit(hits, 9) node T_4612 = bit(hits, 10) node T_4613 = bit(hits, 11) node T_4614 = bit(hits, 12) node T_4615 = bit(hits, 13) node T_4616 = bit(hits, 14) node T_4617 = bit(hits, 15) node T_4618 = bit(hits, 16) node T_4619 = bit(hits, 17) node T_4620 = bit(hits, 18) node T_4621 = bit(hits, 19) node T_4622 = bit(hits, 20) node T_4623 = bit(hits, 21) node T_4624 = bit(hits, 22) node T_4625 = bit(hits, 23) node T_4626 = bit(hits, 24) node T_4627 = bit(hits, 25) node T_4628 = bit(hits, 26) node T_4629 = bit(hits, 27) node T_4630 = bit(hits, 28) node T_4631 = bit(hits, 29) node T_4632 = bit(hits, 30) node T_4633 = bit(hits, 31) node T_4634 = bit(hits, 32) node T_4635 = bit(hits, 33) node T_4636 = bit(hits, 34) node T_4637 = bit(hits, 35) node T_4638 = bit(hits, 36) node T_4639 = bit(hits, 37) node T_4640 = bit(hits, 38) node T_4641 = bit(hits, 39) node T_4642 = bit(hits, 40) node T_4643 = bit(hits, 41) node T_4644 = bit(hits, 42) node T_4645 = bit(hits, 43) node T_4646 = bit(hits, 44) node T_4647 = bit(hits, 45) node T_4648 = bit(hits, 46) node T_4649 = bit(hits, 47) node T_4650 = bit(hits, 48) node T_4651 = bit(hits, 49) node T_4652 = bit(hits, 50) node T_4653 = bit(hits, 51) node T_4654 = bit(hits, 52) node T_4655 = bit(hits, 53) node T_4656 = bit(hits, 54) node T_4657 = bit(hits, 55) node T_4658 = bit(hits, 56) node T_4659 = bit(hits, 57) node T_4660 = bit(hits, 58) node T_4661 = bit(hits, 59) node T_4662 = bit(hits, 60) node T_4663 = bit(hits, 61) node T_4665 = shl(useRAS[0], 0) node T_4666 = mux(T_4602, T_4665, UInt<1>("h00")) node T_4668 = shl(useRAS[1], 0) node T_4669 = mux(T_4603, T_4668, UInt<1>("h00")) node T_4671 = shl(useRAS[2], 0) node T_4672 = mux(T_4604, T_4671, UInt<1>("h00")) node T_4674 = shl(useRAS[3], 0) node T_4675 = mux(T_4605, T_4674, UInt<1>("h00")) node T_4677 = shl(useRAS[4], 0) node T_4678 = mux(T_4606, T_4677, UInt<1>("h00")) node T_4680 = shl(useRAS[5], 0) node T_4681 = mux(T_4607, T_4680, UInt<1>("h00")) node T_4683 = shl(useRAS[6], 0) node T_4684 = mux(T_4608, T_4683, UInt<1>("h00")) node T_4686 = shl(useRAS[7], 0) node T_4687 = mux(T_4609, T_4686, UInt<1>("h00")) node T_4689 = shl(useRAS[8], 0) node T_4690 = mux(T_4610, T_4689, UInt<1>("h00")) node T_4692 = shl(useRAS[9], 0) node T_4693 = mux(T_4611, T_4692, UInt<1>("h00")) node T_4695 = shl(useRAS[10], 0) node T_4696 = mux(T_4612, T_4695, UInt<1>("h00")) node T_4698 = shl(useRAS[11], 0) node T_4699 = mux(T_4613, T_4698, UInt<1>("h00")) node T_4701 = shl(useRAS[12], 0) node T_4702 = mux(T_4614, T_4701, UInt<1>("h00")) node T_4704 = shl(useRAS[13], 0) node T_4705 = mux(T_4615, T_4704, UInt<1>("h00")) node T_4707 = shl(useRAS[14], 0) node T_4708 = mux(T_4616, T_4707, UInt<1>("h00")) node T_4710 = shl(useRAS[15], 0) node T_4711 = mux(T_4617, T_4710, UInt<1>("h00")) node T_4713 = shl(useRAS[16], 0) node T_4714 = mux(T_4618, T_4713, UInt<1>("h00")) node T_4716 = shl(useRAS[17], 0) node T_4717 = mux(T_4619, T_4716, UInt<1>("h00")) node T_4719 = shl(useRAS[18], 0) node T_4720 = mux(T_4620, T_4719, UInt<1>("h00")) node T_4722 = shl(useRAS[19], 0) node T_4723 = mux(T_4621, T_4722, UInt<1>("h00")) node T_4725 = shl(useRAS[20], 0) node T_4726 = mux(T_4622, T_4725, UInt<1>("h00")) node T_4728 = shl(useRAS[21], 0) node T_4729 = mux(T_4623, T_4728, UInt<1>("h00")) node T_4731 = shl(useRAS[22], 0) node T_4732 = mux(T_4624, T_4731, UInt<1>("h00")) node T_4734 = shl(useRAS[23], 0) node T_4735 = mux(T_4625, T_4734, UInt<1>("h00")) node T_4737 = shl(useRAS[24], 0) node T_4738 = mux(T_4626, T_4737, UInt<1>("h00")) node T_4740 = shl(useRAS[25], 0) node T_4741 = mux(T_4627, T_4740, UInt<1>("h00")) node T_4743 = shl(useRAS[26], 0) node T_4744 = mux(T_4628, T_4743, UInt<1>("h00")) node T_4746 = shl(useRAS[27], 0) node T_4747 = mux(T_4629, T_4746, UInt<1>("h00")) node T_4749 = shl(useRAS[28], 0) node T_4750 = mux(T_4630, T_4749, UInt<1>("h00")) node T_4752 = shl(useRAS[29], 0) node T_4753 = mux(T_4631, T_4752, UInt<1>("h00")) node T_4755 = shl(useRAS[30], 0) node T_4756 = mux(T_4632, T_4755, UInt<1>("h00")) node T_4758 = shl(useRAS[31], 0) node T_4759 = mux(T_4633, T_4758, UInt<1>("h00")) node T_4761 = shl(useRAS[32], 0) node T_4762 = mux(T_4634, T_4761, UInt<1>("h00")) node T_4764 = shl(useRAS[33], 0) node T_4765 = mux(T_4635, T_4764, UInt<1>("h00")) node T_4767 = shl(useRAS[34], 0) node T_4768 = mux(T_4636, T_4767, UInt<1>("h00")) node T_4770 = shl(useRAS[35], 0) node T_4771 = mux(T_4637, T_4770, UInt<1>("h00")) node T_4773 = shl(useRAS[36], 0) node T_4774 = mux(T_4638, T_4773, UInt<1>("h00")) node T_4776 = shl(useRAS[37], 0) node T_4777 = mux(T_4639, T_4776, UInt<1>("h00")) node T_4779 = shl(useRAS[38], 0) node T_4780 = mux(T_4640, T_4779, UInt<1>("h00")) node T_4782 = shl(useRAS[39], 0) node T_4783 = mux(T_4641, T_4782, UInt<1>("h00")) node T_4785 = shl(useRAS[40], 0) node T_4786 = mux(T_4642, T_4785, UInt<1>("h00")) node T_4788 = shl(useRAS[41], 0) node T_4789 = mux(T_4643, T_4788, UInt<1>("h00")) node T_4791 = shl(useRAS[42], 0) node T_4792 = mux(T_4644, T_4791, UInt<1>("h00")) node T_4794 = shl(useRAS[43], 0) node T_4795 = mux(T_4645, T_4794, UInt<1>("h00")) node T_4797 = shl(useRAS[44], 0) node T_4798 = mux(T_4646, T_4797, UInt<1>("h00")) node T_4800 = shl(useRAS[45], 0) node T_4801 = mux(T_4647, T_4800, UInt<1>("h00")) node T_4803 = shl(useRAS[46], 0) node T_4804 = mux(T_4648, T_4803, UInt<1>("h00")) node T_4806 = shl(useRAS[47], 0) node T_4807 = mux(T_4649, T_4806, UInt<1>("h00")) node T_4809 = shl(useRAS[48], 0) node T_4810 = mux(T_4650, T_4809, UInt<1>("h00")) node T_4812 = shl(useRAS[49], 0) node T_4813 = mux(T_4651, T_4812, UInt<1>("h00")) node T_4815 = shl(useRAS[50], 0) node T_4816 = mux(T_4652, T_4815, UInt<1>("h00")) node T_4818 = shl(useRAS[51], 0) node T_4819 = mux(T_4653, T_4818, UInt<1>("h00")) node T_4821 = shl(useRAS[52], 0) node T_4822 = mux(T_4654, T_4821, UInt<1>("h00")) node T_4824 = shl(useRAS[53], 0) node T_4825 = mux(T_4655, T_4824, UInt<1>("h00")) node T_4827 = shl(useRAS[54], 0) node T_4828 = mux(T_4656, T_4827, UInt<1>("h00")) node T_4830 = shl(useRAS[55], 0) node T_4831 = mux(T_4657, T_4830, UInt<1>("h00")) node T_4833 = shl(useRAS[56], 0) node T_4834 = mux(T_4658, T_4833, UInt<1>("h00")) node T_4836 = shl(useRAS[57], 0) node T_4837 = mux(T_4659, T_4836, UInt<1>("h00")) node T_4839 = shl(useRAS[58], 0) node T_4840 = mux(T_4660, T_4839, UInt<1>("h00")) node T_4842 = shl(useRAS[59], 0) node T_4843 = mux(T_4661, T_4842, UInt<1>("h00")) node T_4845 = shl(useRAS[60], 0) node T_4846 = mux(T_4662, T_4845, UInt<1>("h00")) node T_4848 = shl(useRAS[61], 0) node T_4849 = mux(T_4663, T_4848, UInt<1>("h00")) node T_4851 = or(T_4666, T_4669) node T_4852 = or(T_4851, T_4672) node T_4853 = or(T_4852, T_4675) node T_4854 = or(T_4853, T_4678) node T_4855 = or(T_4854, T_4681) node T_4856 = or(T_4855, T_4684) node T_4857 = or(T_4856, T_4687) node T_4858 = or(T_4857, T_4690) node T_4859 = or(T_4858, T_4693) node T_4860 = or(T_4859, T_4696) node T_4861 = or(T_4860, T_4699) node T_4862 = or(T_4861, T_4702) node T_4863 = or(T_4862, T_4705) node T_4864 = or(T_4863, T_4708) node T_4865 = or(T_4864, T_4711) node T_4866 = or(T_4865, T_4714) node T_4867 = or(T_4866, T_4717) node T_4868 = or(T_4867, T_4720) node T_4869 = or(T_4868, T_4723) node T_4870 = or(T_4869, T_4726) node T_4871 = or(T_4870, T_4729) node T_4872 = or(T_4871, T_4732) node T_4873 = or(T_4872, T_4735) node T_4874 = or(T_4873, T_4738) node T_4875 = or(T_4874, T_4741) node T_4876 = or(T_4875, T_4744) node T_4877 = or(T_4876, T_4747) node T_4878 = or(T_4877, T_4750) node T_4879 = or(T_4878, T_4753) node T_4880 = or(T_4879, T_4756) node T_4881 = or(T_4880, T_4759) node T_4882 = or(T_4881, T_4762) node T_4883 = or(T_4882, T_4765) node T_4884 = or(T_4883, T_4768) node T_4885 = or(T_4884, T_4771) node T_4886 = or(T_4885, T_4774) node T_4887 = or(T_4886, T_4777) node T_4888 = or(T_4887, T_4780) node T_4889 = or(T_4888, T_4783) node T_4890 = or(T_4889, T_4786) node T_4891 = or(T_4890, T_4789) node T_4892 = or(T_4891, T_4792) node T_4893 = or(T_4892, T_4795) node T_4894 = or(T_4893, T_4798) node T_4895 = or(T_4894, T_4801) node T_4896 = or(T_4895, T_4804) node T_4897 = or(T_4896, T_4807) node T_4898 = or(T_4897, T_4810) node T_4899 = or(T_4898, T_4813) node T_4900 = or(T_4899, T_4816) node T_4901 = or(T_4900, T_4819) node T_4902 = or(T_4901, T_4822) node T_4903 = or(T_4902, T_4825) node T_4904 = or(T_4903, T_4828) node T_4905 = or(T_4904, T_4831) node T_4906 = or(T_4905, T_4834) node T_4907 = or(T_4906, T_4837) node T_4908 = or(T_4907, T_4840) node T_4909 = or(T_4908, T_4843) node T_4910 = or(T_4909, T_4846) node T_4911 = or(T_4910, T_4849) wire T_4912 : UInt<1> T_4912 <= UInt<1>("h00") T_4912 <= T_4911 node T_4915 = eq(T_4587, UInt<1>("h00")) node T_4917 = eq(T_4915, UInt<1>("h00")) node T_4918 = and(T_4917, T_4912) when T_4918 : io.resp.bits.target <= T_4598[T_4589] skip when io.ras_update.valid : when io.ras_update.bits.isCall : node T_4921 = lt(T_4587, UInt<2>("h02")) when T_4921 : node T_4923 = addw(T_4587, UInt<1>("h01")) T_4587 <= T_4923 skip node T_4926 = lt(T_4589, UInt<1>("h01")) node T_4927 = or(UInt<1>("h01"), T_4926) node T_4929 = addw(T_4589, UInt<1>("h01")) node T_4931 = mux(T_4927, T_4929, UInt<1>("h00")) T_4598[T_4931] <= io.ras_update.bits.returnAddr T_4589 <= T_4931 when T_4912 : io.resp.bits.target <= io.ras_update.bits.returnAddr skip skip node T_4933 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) node T_4935 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) node T_4936 = and(T_4935, T_4933) when T_4936 : node T_4938 = eq(T_4587, UInt<1>("h00")) node T_4940 = eq(T_4938, UInt<1>("h00")) when T_4940 : node T_4942 = subw(T_4587, UInt<1>("h01")) T_4587 <= T_4942 node T_4945 = gt(T_4589, UInt<1>("h00")) node T_4946 = or(UInt<1>("h01"), T_4945) node T_4948 = subw(T_4589, UInt<1>("h01")) node T_4950 = mux(T_4946, T_4948, UInt<1>("h01")) T_4589 <= T_4950 skip skip skip when io.invalidate : T_4587 <= UInt<1>("h00") skip module FlowThroughSerializer : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, cnt : UInt<1>, done : UInt<1>} io.done <= UInt<1>("h00") io.cnt <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.g_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.manager_xact_id <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in.ready <= UInt<1>("h00") io.out <- io.in io.cnt <= UInt<1>("h00") io.done <= UInt<1>("h01") module ICache : input clk : Clock input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} io.mem.grant.ready <= UInt<1>("h00") io.mem.acquire.bits.data <= UInt<1>("h00") io.mem.acquire.bits.union <= UInt<1>("h00") io.mem.acquire.bits.a_type <= UInt<1>("h00") io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") io.mem.acquire.bits.addr_beat <= UInt<1>("h00") io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") io.mem.acquire.bits.addr_block <= UInt<1>("h00") io.mem.acquire.valid <= UInt<1>("h00") io.resp.bits.datablock <= UInt<1>("h00") io.resp.bits.data <= UInt<1>("h00") io.resp.valid <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg invalidated : UInt<1>, clk, UInt<1>("h00"), invalidated node stall = eq(io.resp.ready, UInt<1>("h00")) wire rdy : UInt<1> rdy <= UInt<1>("h00") reg refill_addr : UInt<32>, clk, UInt<1>("h00"), refill_addr wire s1_any_tag_hit : UInt<1> s1_any_tag_hit <= UInt<1>("h00") reg s1_valid : UInt<1>, clk, reset, UInt<1>("h00") reg s1_pgoff : UInt<12>, clk, UInt<1>("h00"), s1_pgoff node s1_addr = cat(io.req.bits.ppn, s1_pgoff) node s1_tag = bits(s1_addr, 31, 12) node T_525 = and(s1_valid, stall) node s0_valid = or(io.req.valid, T_525) node T_527 = and(s1_valid, stall) node s0_pgoff = mux(T_527, s1_pgoff, io.req.bits.idx) node T_529 = and(io.req.valid, rdy) node T_530 = and(s1_valid, stall) node T_532 = eq(io.req.bits.kill, UInt<1>("h00")) node T_533 = and(T_530, T_532) node T_534 = or(T_529, T_533) s1_valid <= T_534 node T_535 = and(io.req.valid, rdy) when T_535 : s1_pgoff <= io.req.bits.idx skip node T_537 = eq(io.req.bits.kill, UInt<1>("h00")) node T_538 = and(s1_valid, T_537) node T_539 = eq(state, UInt<1>("h00")) node out_valid = and(T_538, T_539) node s1_idx = bits(s1_addr, 11, 6) node s1_offset = bits(s1_addr, 5, 0) node s1_hit = and(out_valid, s1_any_tag_hit) node T_545 = eq(s1_any_tag_hit, UInt<1>("h00")) node s1_miss = and(out_valid, T_545) node T_547 = eq(state, UInt<1>("h00")) node T_549 = eq(s1_miss, UInt<1>("h00")) node T_550 = and(T_547, T_549) rdy <= T_550 node T_551 = eq(state, UInt<1>("h00")) node T_552 = and(s1_valid, T_551) node T_553 = and(T_552, s1_miss) when T_553 : refill_addr <= s1_addr skip node refill_tag = bits(refill_addr, 31, 12) inst T_555 of FlowThroughSerializer T_555.io.out.ready <= UInt<1>("h00") T_555.io.in.bits.data <= UInt<1>("h00") T_555.io.in.bits.g_type <= UInt<1>("h00") T_555.io.in.bits.is_builtin_type <= UInt<1>("h00") T_555.io.in.bits.manager_xact_id <= UInt<1>("h00") T_555.io.in.bits.client_xact_id <= UInt<1>("h00") T_555.io.in.bits.addr_beat <= UInt<1>("h00") T_555.io.in.valid <= UInt<1>("h00") T_555.clk <= clk T_555.reset <= reset T_555.io.in.valid <= io.mem.grant.valid T_555.io.in.bits <- io.mem.grant.bits io.mem.grant.ready <= T_555.io.in.ready node T_564 = and(T_555.io.out.ready, T_555.io.out.valid) reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") when T_564 : node T_568 = eq(refill_cnt, UInt<2>("h03")) node T_570 = and(UInt<1>("h00"), T_568) node T_573 = addw(refill_cnt, UInt<1>("h01")) node T_574 = mux(T_570, UInt<1>("h00"), T_573) refill_cnt <= T_574 skip node refill_wrap = and(T_564, T_568) node T_576 = eq(state, UInt<2>("h03")) node refill_done = and(T_576, refill_wrap) T_555.io.out.ready <= UInt<1>("h01") reg T_580 : UInt<16>, clk, reset, UInt<16>("h01") when s1_miss : node T_581 = bit(T_580, 0) node T_582 = bit(T_580, 2) node T_583 = xor(T_581, T_582) node T_584 = bit(T_580, 3) node T_585 = xor(T_583, T_584) node T_586 = bit(T_580, 5) node T_587 = xor(T_585, T_586) node T_588 = bits(T_580, 15, 1) node T_589 = cat(T_587, T_588) T_580 <= T_589 skip node repl_way = bits(T_580, 1, 0) smem tag_array : UInt<20>[4][64] node T_608 = bits(s0_pgoff, 11, 6) node T_610 = eq(refill_done, UInt<1>("h00")) node T_611 = and(T_610, s0_valid) poison T_612 : UInt<6> node T_613 = mux(T_611, T_608, T_612) read mport tag_rdata = tag_array[T_613], clk when refill_done : wire T_623 : UInt<20>[4] T_623[0] <= refill_tag T_623[1] <= refill_tag T_623[2] <= refill_tag T_623[3] <= refill_tag node T_630 = eq(repl_way, UInt<1>("h00")) node T_632 = eq(repl_way, UInt<1>("h01")) node T_634 = eq(repl_way, UInt<2>("h02")) node T_636 = eq(repl_way, UInt<2>("h03")) wire T_638 : UInt<1>[4] T_638[0] <= T_630 T_638[1] <= T_632 T_638[2] <= T_634 T_638[3] <= T_636 write mport T_646 = tag_array[s1_idx], clk when T_638[0] : T_646[0] <= T_623[0] skip when T_638[1] : T_646[1] <= T_623[1] skip when T_638[2] : T_646[2] <= T_623[2] skip when T_638[3] : T_646[3] <= T_623[3] skip skip reg vb_array : UInt<256>, clk, reset, UInt<256>("h00") node T_655 = eq(invalidated, UInt<1>("h00")) node T_656 = and(refill_done, T_655) when T_656 : node T_657 = cat(repl_way, s1_idx) node T_660 = dshl(UInt<1>("h01"), T_657) node T_661 = or(vb_array, T_660) node T_662 = not(vb_array) node T_663 = or(T_662, T_660) node T_664 = not(T_663) node T_665 = mux(UInt<1>("h01"), T_661, T_664) vb_array <= T_665 skip when io.invalidate : vb_array <= UInt<1>("h00") invalidated <= UInt<1>("h01") skip wire s1_disparity : UInt<1>[4] s1_disparity[0] <= UInt<1>("h00") s1_disparity[1] <= UInt<1>("h00") s1_disparity[2] <= UInt<1>("h00") s1_disparity[3] <= UInt<1>("h00") node T_688 = and(s1_valid, s1_disparity[0]) when T_688 : node T_690 = cat(UInt<1>("h00"), s1_idx) node T_693 = dshl(UInt<1>("h01"), T_690) node T_694 = or(vb_array, T_693) node T_695 = not(vb_array) node T_696 = or(T_695, T_693) node T_697 = not(T_696) node T_698 = mux(UInt<1>("h00"), T_694, T_697) vb_array <= T_698 skip node T_699 = and(s1_valid, s1_disparity[1]) when T_699 : node T_701 = cat(UInt<1>("h01"), s1_idx) node T_704 = dshl(UInt<1>("h01"), T_701) node T_705 = or(vb_array, T_704) node T_706 = not(vb_array) node T_707 = or(T_706, T_704) node T_708 = not(T_707) node T_709 = mux(UInt<1>("h00"), T_705, T_708) vb_array <= T_709 skip node T_710 = and(s1_valid, s1_disparity[2]) when T_710 : node T_712 = cat(UInt<2>("h02"), s1_idx) node T_715 = dshl(UInt<1>("h01"), T_712) node T_716 = or(vb_array, T_715) node T_717 = not(vb_array) node T_718 = or(T_717, T_715) node T_719 = not(T_718) node T_720 = mux(UInt<1>("h00"), T_716, T_719) vb_array <= T_720 skip node T_721 = and(s1_valid, s1_disparity[3]) when T_721 : node T_723 = cat(UInt<2>("h03"), s1_idx) node T_726 = dshl(UInt<1>("h01"), T_723) node T_727 = or(vb_array, T_726) node T_728 = not(vb_array) node T_729 = or(T_728, T_726) node T_730 = not(T_729) node T_731 = mux(UInt<1>("h00"), T_727, T_730) vb_array <= T_731 skip wire s1_tag_match : UInt<1>[4] s1_tag_match[0] <= UInt<1>("h00") s1_tag_match[1] <= UInt<1>("h00") s1_tag_match[2] <= UInt<1>("h00") s1_tag_match[3] <= UInt<1>("h00") wire s1_tag_hit : UInt<1>[4] s1_tag_hit[0] <= UInt<1>("h00") s1_tag_hit[1] <= UInt<1>("h00") s1_tag_hit[2] <= UInt<1>("h00") s1_tag_hit[3] <= UInt<1>("h00") wire s1_dout : UInt<128>[4] s1_dout[0] <= UInt<1>("h00") s1_dout[1] <= UInt<1>("h00") s1_dout[2] <= UInt<1>("h00") s1_dout[3] <= UInt<1>("h00") node T_793 = eq(io.invalidate, UInt<1>("h00")) node T_795 = bits(s1_pgoff, 11, 6) node T_796 = cat(UInt<1>("h00"), T_795) node T_797 = dshr(vb_array, T_796) node T_798 = bit(T_797, 0) node T_799 = bit(T_798, 0) node T_800 = and(T_793, T_799) node T_803 = or(UInt<1>("h00"), UInt<1>("h00")) node T_804 = and(s1_valid, rdy) node T_806 = eq(stall, UInt<1>("h00")) node T_807 = and(T_804, T_806) when T_807 : skip node T_808 = bits(tag_rdata[0], 19, 0) node T_809 = eq(T_808, s1_tag) s1_tag_match[0] <= T_809 node T_810 = and(T_800, s1_tag_match[0]) s1_tag_hit[0] <= T_810 node T_813 = or(UInt<1>("h00"), UInt<1>("h00")) node T_814 = or(T_803, T_813) node T_815 = and(T_800, T_814) s1_disparity[0] <= T_815 node T_817 = eq(io.invalidate, UInt<1>("h00")) node T_819 = bits(s1_pgoff, 11, 6) node T_820 = cat(UInt<1>("h01"), T_819) node T_821 = dshr(vb_array, T_820) node T_822 = bit(T_821, 0) node T_823 = bit(T_822, 0) node T_824 = and(T_817, T_823) node T_827 = or(UInt<1>("h00"), UInt<1>("h00")) node T_828 = and(s1_valid, rdy) node T_830 = eq(stall, UInt<1>("h00")) node T_831 = and(T_828, T_830) when T_831 : skip node T_832 = bits(tag_rdata[1], 19, 0) node T_833 = eq(T_832, s1_tag) s1_tag_match[1] <= T_833 node T_834 = and(T_824, s1_tag_match[1]) s1_tag_hit[1] <= T_834 node T_837 = or(UInt<1>("h00"), UInt<1>("h00")) node T_838 = or(T_827, T_837) node T_839 = and(T_824, T_838) s1_disparity[1] <= T_839 node T_841 = eq(io.invalidate, UInt<1>("h00")) node T_843 = bits(s1_pgoff, 11, 6) node T_844 = cat(UInt<2>("h02"), T_843) node T_845 = dshr(vb_array, T_844) node T_846 = bit(T_845, 0) node T_847 = bit(T_846, 0) node T_848 = and(T_841, T_847) node T_851 = or(UInt<1>("h00"), UInt<1>("h00")) node T_852 = and(s1_valid, rdy) node T_854 = eq(stall, UInt<1>("h00")) node T_855 = and(T_852, T_854) when T_855 : skip node T_856 = bits(tag_rdata[2], 19, 0) node T_857 = eq(T_856, s1_tag) s1_tag_match[2] <= T_857 node T_858 = and(T_848, s1_tag_match[2]) s1_tag_hit[2] <= T_858 node T_861 = or(UInt<1>("h00"), UInt<1>("h00")) node T_862 = or(T_851, T_861) node T_863 = and(T_848, T_862) s1_disparity[2] <= T_863 node T_865 = eq(io.invalidate, UInt<1>("h00")) node T_867 = bits(s1_pgoff, 11, 6) node T_868 = cat(UInt<2>("h03"), T_867) node T_869 = dshr(vb_array, T_868) node T_870 = bit(T_869, 0) node T_871 = bit(T_870, 0) node T_872 = and(T_865, T_871) node T_875 = or(UInt<1>("h00"), UInt<1>("h00")) node T_876 = and(s1_valid, rdy) node T_878 = eq(stall, UInt<1>("h00")) node T_879 = and(T_876, T_878) when T_879 : skip node T_880 = bits(tag_rdata[3], 19, 0) node T_881 = eq(T_880, s1_tag) s1_tag_match[3] <= T_881 node T_882 = and(T_872, s1_tag_match[3]) s1_tag_hit[3] <= T_882 node T_885 = or(UInt<1>("h00"), UInt<1>("h00")) node T_886 = or(T_875, T_885) node T_887 = and(T_872, T_886) s1_disparity[3] <= T_887 node T_888 = or(s1_tag_hit[0], s1_tag_hit[1]) node T_889 = or(T_888, s1_tag_hit[2]) node T_890 = or(T_889, s1_tag_hit[3]) node T_891 = or(s1_disparity[0], s1_disparity[1]) node T_892 = or(T_891, s1_disparity[2]) node T_893 = or(T_892, s1_disparity[3]) node T_895 = eq(T_893, UInt<1>("h00")) node T_896 = and(T_890, T_895) s1_any_tag_hit <= T_896 smem T_899 : UInt<128>[256] node T_901 = eq(repl_way, UInt<1>("h00")) node T_902 = and(T_555.io.out.valid, T_901) when T_902 : node T_903 = cat(s1_idx, refill_cnt) write mport T_904 = T_899[T_903], clk T_904 <= T_555.io.out.bits.data skip node T_905 = bits(s0_pgoff, 11, 4) node T_907 = eq(T_902, UInt<1>("h00")) node T_908 = and(T_907, s0_valid) poison T_909 : UInt<8> node T_910 = mux(T_908, T_905, T_909) read mport T_911 = T_899[T_910], clk s1_dout[0] <= UInt<1>("h00") node T_913 = and(s1_valid, rdy) node T_915 = eq(stall, UInt<1>("h00")) node T_916 = and(T_913, T_915) node T_918 = or(UInt<1>("h00"), s1_tag_match[0]) node T_919 = and(T_916, T_918) when T_919 : s1_dout[0] <= T_911 skip smem T_922 : UInt<128>[256] node T_924 = eq(repl_way, UInt<1>("h01")) node T_925 = and(T_555.io.out.valid, T_924) when T_925 : node T_926 = cat(s1_idx, refill_cnt) write mport T_927 = T_922[T_926], clk T_927 <= T_555.io.out.bits.data skip node T_928 = bits(s0_pgoff, 11, 4) node T_930 = eq(T_925, UInt<1>("h00")) node T_931 = and(T_930, s0_valid) poison T_932 : UInt<8> node T_933 = mux(T_931, T_928, T_932) read mport T_934 = T_922[T_933], clk s1_dout[1] <= UInt<1>("h00") node T_936 = and(s1_valid, rdy) node T_938 = eq(stall, UInt<1>("h00")) node T_939 = and(T_936, T_938) node T_941 = or(UInt<1>("h00"), s1_tag_match[1]) node T_942 = and(T_939, T_941) when T_942 : s1_dout[1] <= T_934 skip smem T_945 : UInt<128>[256] node T_947 = eq(repl_way, UInt<2>("h02")) node T_948 = and(T_555.io.out.valid, T_947) when T_948 : node T_949 = cat(s1_idx, refill_cnt) write mport T_950 = T_945[T_949], clk T_950 <= T_555.io.out.bits.data skip node T_951 = bits(s0_pgoff, 11, 4) node T_953 = eq(T_948, UInt<1>("h00")) node T_954 = and(T_953, s0_valid) poison T_955 : UInt<8> node T_956 = mux(T_954, T_951, T_955) read mport T_957 = T_945[T_956], clk s1_dout[2] <= UInt<1>("h00") node T_959 = and(s1_valid, rdy) node T_961 = eq(stall, UInt<1>("h00")) node T_962 = and(T_959, T_961) node T_964 = or(UInt<1>("h00"), s1_tag_match[2]) node T_965 = and(T_962, T_964) when T_965 : s1_dout[2] <= T_957 skip smem T_968 : UInt<128>[256] node T_970 = eq(repl_way, UInt<2>("h03")) node T_971 = and(T_555.io.out.valid, T_970) when T_971 : node T_972 = cat(s1_idx, refill_cnt) write mport T_973 = T_968[T_972], clk T_973 <= T_555.io.out.bits.data skip node T_974 = bits(s0_pgoff, 11, 4) node T_976 = eq(T_971, UInt<1>("h00")) node T_977 = and(T_976, s0_valid) poison T_978 : UInt<8> node T_979 = mux(T_977, T_974, T_978) read mport T_980 = T_968[T_979], clk s1_dout[3] <= UInt<1>("h00") node T_982 = and(s1_valid, rdy) node T_984 = eq(stall, UInt<1>("h00")) node T_985 = and(T_982, T_984) node T_987 = or(UInt<1>("h00"), s1_tag_match[3]) node T_988 = and(T_985, T_987) when T_988 : s1_dout[3] <= T_980 skip node T_990 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h00")) node T_992 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h00")) node T_994 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h00")) node T_996 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h00")) node T_998 = or(T_990, T_992) node T_999 = or(T_998, T_994) node T_1000 = or(T_999, T_996) wire T_1001 : UInt<128> T_1001 <= UInt<1>("h00") T_1001 <= T_1000 io.resp.bits.datablock <= T_1001 io.resp.valid <= s1_hit node T_1003 = eq(state, UInt<1>("h01")) io.mem.acquire.valid <= T_1003 node T_1004 = shr(refill_addr, 6) node T_1015 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1016 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1017 = cat(T_1015, T_1016) node T_1019 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1020 = cat(UInt<3>("h07"), T_1019) node T_1022 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1024 = cat(UInt<1>("h00"), UInt<1>("h01")) node T_1026 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1027 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1028 = cat(T_1026, T_1027) node T_1030 = cat(UInt<5>("h00"), UInt<1>("h01")) node T_1032 = cat(UInt<5>("h01"), UInt<1>("h01")) node T_1033 = eq(UInt<3>("h06"), UInt<3>("h01")) node T_1034 = mux(T_1033, T_1032, UInt<1>("h00")) node T_1035 = eq(UInt<3>("h05"), UInt<3>("h01")) node T_1036 = mux(T_1035, T_1030, T_1034) node T_1037 = eq(UInt<3>("h04"), UInt<3>("h01")) node T_1038 = mux(T_1037, T_1028, T_1036) node T_1039 = eq(UInt<3>("h03"), UInt<3>("h01")) node T_1040 = mux(T_1039, T_1024, T_1038) node T_1041 = eq(UInt<3>("h02"), UInt<3>("h01")) node T_1042 = mux(T_1041, T_1022, T_1040) node T_1043 = eq(UInt<3>("h01"), UInt<3>("h01")) node T_1044 = mux(T_1043, T_1020, T_1042) node T_1045 = eq(UInt<3>("h00"), UInt<3>("h01")) node T_1046 = mux(T_1045, T_1017, T_1044) wire T_1078 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1078.data <= UInt<1>("h00") T_1078.union <= UInt<1>("h00") T_1078.a_type <= UInt<1>("h00") T_1078.is_builtin_type <= UInt<1>("h00") T_1078.addr_beat <= UInt<1>("h00") T_1078.client_xact_id <= UInt<1>("h00") T_1078.addr_block <= UInt<1>("h00") T_1078.is_builtin_type <= UInt<1>("h01") T_1078.a_type <= UInt<3>("h01") T_1078.client_xact_id <= UInt<1>("h00") T_1078.addr_block <= T_1004 T_1078.addr_beat <= UInt<1>("h00") T_1078.data <= UInt<1>("h00") T_1078.union <= T_1046 io.mem.acquire.bits <- T_1078 node T_1116 = eq(UInt<1>("h00"), state) when T_1116 : when s1_miss : state <= UInt<1>("h01") skip invalidated <= UInt<1>("h00") skip node T_1118 = eq(UInt<1>("h01"), state) when T_1118 : when io.mem.acquire.ready : state <= UInt<2>("h02") skip skip node T_1119 = eq(UInt<2>("h02"), state) when T_1119 : when io.mem.grant.valid : state <= UInt<2>("h03") skip skip node T_1120 = eq(UInt<2>("h03"), state) when T_1120 : when refill_done : state <= UInt<1>("h00") skip skip module RocketCAM : input clk : Clock input reset : UInt<1> output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>} io.valid_bits <= UInt<1>("h00") io.hits <= UInt<1>("h00") io.hit <= UInt<1>("h00") cmem cam_tags : UInt<34>[8] reg vb_array : UInt<8>, clk, reset, UInt<8>("h00") when io.write : node T_21 = dshl(UInt<1>("h01"), io.write_addr) node T_22 = or(vb_array, T_21) node T_23 = not(vb_array) node T_24 = or(T_23, T_21) node T_25 = not(T_24) node T_26 = mux(UInt<1>("h01"), T_22, T_25) vb_array <= T_26 infer mport T_27 = cam_tags[io.write_addr], clk T_27 <= io.write_tag skip when io.clear : node T_28 = not(io.clear_mask) node T_29 = and(vb_array, T_28) vb_array <= T_29 skip node T_30 = bit(vb_array, 0) infer mport T_32 = cam_tags[UInt<1>("h00")], clk node T_33 = eq(T_32, io.tag) node T_34 = and(T_30, T_33) node T_35 = bit(vb_array, 1) infer mport T_37 = cam_tags[UInt<1>("h01")], clk node T_38 = eq(T_37, io.tag) node T_39 = and(T_35, T_38) node T_40 = bit(vb_array, 2) infer mport T_42 = cam_tags[UInt<2>("h02")], clk node T_43 = eq(T_42, io.tag) node T_44 = and(T_40, T_43) node T_45 = bit(vb_array, 3) infer mport T_47 = cam_tags[UInt<2>("h03")], clk node T_48 = eq(T_47, io.tag) node T_49 = and(T_45, T_48) node T_50 = bit(vb_array, 4) infer mport T_52 = cam_tags[UInt<3>("h04")], clk node T_53 = eq(T_52, io.tag) node T_54 = and(T_50, T_53) node T_55 = bit(vb_array, 5) infer mport T_57 = cam_tags[UInt<3>("h05")], clk node T_58 = eq(T_57, io.tag) node T_59 = and(T_55, T_58) node T_60 = bit(vb_array, 6) infer mport T_62 = cam_tags[UInt<3>("h06")], clk node T_63 = eq(T_62, io.tag) node T_64 = and(T_60, T_63) node T_65 = bit(vb_array, 7) infer mport T_67 = cam_tags[UInt<3>("h07")], clk node T_68 = eq(T_67, io.tag) node T_69 = and(T_65, T_68) io.valid_bits <= vb_array wire T_71 : UInt<1>[8] T_71[0] <= T_34 T_71[1] <= T_39 T_71[2] <= T_44 T_71[3] <= T_49 T_71[4] <= T_54 T_71[5] <= T_59 T_71[6] <= T_64 T_71[7] <= T_69 node T_81 = cat(T_71[7], T_71[6]) node T_82 = cat(T_71[5], T_71[4]) node T_83 = cat(T_81, T_82) node T_84 = cat(T_71[3], T_71[2]) node T_85 = cat(T_71[1], T_71[0]) node T_86 = cat(T_84, T_85) node T_87 = cat(T_83, T_86) io.hits <= T_87 node T_89 = neq(io.hits, UInt<1>("h00")) io.hit <= T_89 module TLB : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} io.ptw.req.bits.fetch <= UInt<1>("h00") io.ptw.req.bits.store <= UInt<1>("h00") io.ptw.req.bits.prv <= UInt<1>("h00") io.ptw.req.bits.addr <= UInt<1>("h00") io.ptw.req.valid <= UInt<1>("h00") io.resp.hit_idx <= UInt<1>("h00") io.resp.xcpt_if <= UInt<1>("h00") io.resp.xcpt_st <= UInt<1>("h00") io.resp.xcpt_ld <= UInt<1>("h00") io.resp.ppn <= UInt<1>("h00") io.resp.miss <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg r_refill_tag : UInt, clk, UInt<1>("h00"), r_refill_tag reg r_refill_waddr : UInt, clk, UInt<1>("h00"), r_refill_waddr reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk, UInt<1>("h00"), r_req inst tag_cam of RocketCAM tag_cam.io.write_addr <= UInt<1>("h00") tag_cam.io.write_tag <= UInt<1>("h00") tag_cam.io.write <= UInt<1>("h00") tag_cam.io.tag <= UInt<1>("h00") tag_cam.io.clear_mask <= UInt<1>("h00") tag_cam.io.clear <= UInt<1>("h00") tag_cam.clk <= clk tag_cam.reset <= reset cmem tag_ram : UInt<20>[8] node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) tag_cam.io.tag <= lookup_tag node T_182 = eq(state, UInt<2>("h02")) node T_183 = and(T_182, io.ptw.resp.valid) tag_cam.io.write <= T_183 tag_cam.io.write_tag <= r_refill_tag tag_cam.io.write_addr <= r_refill_waddr node T_184 = bits(tag_cam.io.hits, 7, 4) node T_185 = bits(tag_cam.io.hits, 3, 0) node T_187 = neq(T_184, UInt<1>("h00")) node T_188 = or(T_184, T_185) node T_189 = bits(T_188, 3, 2) node T_190 = bits(T_188, 1, 0) node T_192 = neq(T_189, UInt<1>("h00")) node T_193 = or(T_189, T_190) node T_194 = bit(T_193, 1) node T_195 = cat(T_192, T_194) node tag_hit_addr = cat(T_187, T_195) reg valid_array : UInt<1>[8], clk, UInt<1>("h00"), valid_array reg ur_array : UInt<1>[8], clk, UInt<1>("h00"), ur_array reg uw_array : UInt<1>[8], clk, UInt<1>("h00"), uw_array reg ux_array : UInt<1>[8], clk, UInt<1>("h00"), ux_array reg sr_array : UInt<1>[8], clk, UInt<1>("h00"), sr_array reg sw_array : UInt<1>[8], clk, UInt<1>("h00"), sw_array reg sx_array : UInt<1>[8], clk, UInt<1>("h00"), sx_array reg dirty_array : UInt<1>[8], clk, UInt<1>("h00"), dirty_array when io.ptw.resp.valid : infer mport T_389 = tag_ram[r_refill_waddr], clk T_389 <= io.ptw.resp.bits.pte.ppn node T_392 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) valid_array[r_refill_waddr] <= T_392 node T_395 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_396 = and(io.ptw.resp.bits.pte.v, T_395) node T_398 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_399 = and(T_396, T_398) node T_401 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_402 = and(T_399, T_401) ur_array[r_refill_waddr] <= T_402 node T_405 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_406 = and(io.ptw.resp.bits.pte.v, T_405) node T_408 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_409 = and(T_406, T_408) node T_410 = bit(io.ptw.resp.bits.pte.typ, 0) node T_411 = and(T_409, T_410) node T_413 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_414 = and(T_411, T_413) uw_array[r_refill_waddr] <= T_414 node T_417 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_418 = and(io.ptw.resp.bits.pte.v, T_417) node T_420 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) node T_421 = and(T_418, T_420) node T_422 = bit(io.ptw.resp.bits.pte.typ, 1) node T_423 = and(T_421, T_422) node T_425 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_426 = and(T_423, T_425) ux_array[r_refill_waddr] <= T_426 node T_429 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_430 = and(io.ptw.resp.bits.pte.v, T_429) node T_432 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_433 = and(T_430, T_432) sr_array[r_refill_waddr] <= T_433 node T_436 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) node T_437 = and(io.ptw.resp.bits.pte.v, T_436) node T_438 = bit(io.ptw.resp.bits.pte.typ, 0) node T_439 = and(T_437, T_438) node T_441 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_442 = and(T_439, T_441) sw_array[r_refill_waddr] <= T_442 node T_445 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) node T_446 = and(io.ptw.resp.bits.pte.v, T_445) node T_447 = bit(io.ptw.resp.bits.pte.typ, 1) node T_448 = and(T_446, T_447) node T_450 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) node T_451 = and(T_448, T_450) sx_array[r_refill_waddr] <= T_451 dirty_array[r_refill_waddr] <= io.ptw.resp.bits.pte.d skip node T_453 = not(tag_cam.io.valid_bits) node T_455 = eq(T_453, UInt<1>("h00")) node has_invalid_entry = eq(T_455, UInt<1>("h00")) node T_458 = not(tag_cam.io.valid_bits) node T_459 = bit(T_458, 0) node T_460 = bit(T_458, 1) node T_461 = bit(T_458, 2) node T_462 = bit(T_458, 3) node T_463 = bit(T_458, 4) node T_464 = bit(T_458, 5) node T_465 = bit(T_458, 6) node T_466 = bit(T_458, 7) wire T_468 : UInt<1>[8] T_468[0] <= T_459 T_468[1] <= T_460 T_468[2] <= T_461 T_468[3] <= T_462 T_468[4] <= T_463 T_468[5] <= T_464 T_468[6] <= T_465 T_468[7] <= T_466 node T_486 = mux(T_468[6], UInt<3>("h06"), UInt<3>("h07")) node T_487 = mux(T_468[5], UInt<3>("h05"), T_486) node T_488 = mux(T_468[4], UInt<3>("h04"), T_487) node T_489 = mux(T_468[3], UInt<2>("h03"), T_488) node T_490 = mux(T_468[2], UInt<2>("h02"), T_489) node T_491 = mux(T_468[1], UInt<1>("h01"), T_490) node invalid_entry = mux(T_468[0], UInt<1>("h00"), T_491) reg T_494 : UInt<8>, clk, UInt<1>("h00"), T_494 node T_496 = dshr(T_494, UInt<1>("h01")) node T_497 = bit(T_496, 0) node T_498 = cat(UInt<1>("h01"), T_497) node T_499 = dshr(T_494, T_498) node T_500 = bit(T_499, 0) node T_501 = cat(T_498, T_500) node T_502 = dshr(T_494, T_501) node T_503 = bit(T_502, 0) node T_504 = cat(T_501, T_503) node T_505 = bits(T_504, 2, 0) node repl_waddr = mux(has_invalid_entry, invalid_entry, T_505) node T_508 = eq(io.req.bits.instruction, UInt<1>("h00")) node T_509 = and(io.ptw.status.mprv, T_508) node priv = mux(T_509, io.ptw.status.prv1, io.ptw.status.prv) node priv_s = eq(priv, UInt<1>("h01")) node priv_uses_vm = leq(priv, UInt<1>("h01")) node T_516 = eq(r_req.store, UInt<1>("h00")) node T_517 = or(r_req.instruction, r_req.store) node T_519 = eq(T_517, UInt<1>("h00")) node T_520 = cat(r_req.store, T_519) node req_xwr = cat(T_516, T_520) node T_522 = cat(sr_array[7], sr_array[6]) node T_523 = cat(sr_array[5], sr_array[4]) node T_524 = cat(T_522, T_523) node T_525 = cat(sr_array[3], sr_array[2]) node T_526 = cat(sr_array[1], sr_array[0]) node T_527 = cat(T_525, T_526) node T_528 = cat(T_524, T_527) node T_529 = cat(ur_array[7], ur_array[6]) node T_530 = cat(ur_array[5], ur_array[4]) node T_531 = cat(T_529, T_530) node T_532 = cat(ur_array[3], ur_array[2]) node T_533 = cat(ur_array[1], ur_array[0]) node T_534 = cat(T_532, T_533) node T_535 = cat(T_531, T_534) node r_array = mux(priv_s, T_528, T_535) node T_537 = cat(sw_array[7], sw_array[6]) node T_538 = cat(sw_array[5], sw_array[4]) node T_539 = cat(T_537, T_538) node T_540 = cat(sw_array[3], sw_array[2]) node T_541 = cat(sw_array[1], sw_array[0]) node T_542 = cat(T_540, T_541) node T_543 = cat(T_539, T_542) node T_544 = cat(uw_array[7], uw_array[6]) node T_545 = cat(uw_array[5], uw_array[4]) node T_546 = cat(T_544, T_545) node T_547 = cat(uw_array[3], uw_array[2]) node T_548 = cat(uw_array[1], uw_array[0]) node T_549 = cat(T_547, T_548) node T_550 = cat(T_546, T_549) node w_array = mux(priv_s, T_543, T_550) node T_552 = cat(sx_array[7], sx_array[6]) node T_553 = cat(sx_array[5], sx_array[4]) node T_554 = cat(T_552, T_553) node T_555 = cat(sx_array[3], sx_array[2]) node T_556 = cat(sx_array[1], sx_array[0]) node T_557 = cat(T_555, T_556) node T_558 = cat(T_554, T_557) node T_559 = cat(ux_array[7], ux_array[6]) node T_560 = cat(ux_array[5], ux_array[4]) node T_561 = cat(T_559, T_560) node T_562 = cat(ux_array[3], ux_array[2]) node T_563 = cat(ux_array[1], ux_array[0]) node T_564 = cat(T_562, T_563) node T_565 = cat(T_561, T_564) node x_array = mux(priv_s, T_558, T_565) node T_567 = bit(io.ptw.status.vm, 3) node T_568 = and(T_567, priv_uses_vm) node T_570 = eq(io.req.bits.passthrough, UInt<1>("h00")) node vm_enabled = and(T_568, T_570) node T_572 = bit(io.req.bits.vpn, 27) node T_573 = bit(io.req.bits.vpn, 26) node bad_va = neq(T_572, T_573) node T_575 = cat(dirty_array[7], dirty_array[6]) node T_576 = cat(dirty_array[5], dirty_array[4]) node T_577 = cat(T_575, T_576) node T_578 = cat(dirty_array[3], dirty_array[2]) node T_579 = cat(dirty_array[1], dirty_array[0]) node T_580 = cat(T_578, T_579) node T_581 = cat(T_577, T_580) node T_583 = mux(io.req.bits.store, w_array, UInt<1>("h00")) node T_584 = not(T_583) node T_585 = or(T_581, T_584) node tag_hits = and(tag_cam.io.hits, T_585) node tag_hit = neq(tag_hits, UInt<1>("h00")) node tlb_hit = and(vm_enabled, tag_hit) node T_591 = eq(tag_hit, UInt<1>("h00")) node T_592 = and(vm_enabled, T_591) node T_594 = eq(bad_va, UInt<1>("h00")) node tlb_miss = and(T_592, T_594) node T_596 = and(io.req.valid, tlb_hit) when T_596 : node T_597 = bits(tag_cam.io.hits, 7, 4) node T_598 = bits(tag_cam.io.hits, 3, 0) node T_600 = neq(T_597, UInt<1>("h00")) node T_601 = or(T_597, T_598) node T_602 = bits(T_601, 3, 2) node T_603 = bits(T_601, 1, 0) node T_605 = neq(T_602, UInt<1>("h00")) node T_606 = or(T_602, T_603) node T_607 = bit(T_606, 1) node T_608 = cat(T_605, T_607) node T_609 = cat(T_600, T_608) node T_611 = bit(T_609, 2) node T_613 = dshl(UInt<8>("h01"), UInt<1>("h01")) node T_614 = bits(T_613, 7, 0) node T_615 = not(T_614) node T_616 = and(T_494, T_615) node T_618 = mux(T_611, UInt<1>("h00"), T_614) node T_619 = or(T_616, T_618) node T_620 = cat(UInt<1>("h01"), T_611) node T_621 = bit(T_609, 1) node T_623 = dshl(UInt<8>("h01"), T_620) node T_624 = bits(T_623, 7, 0) node T_625 = not(T_624) node T_626 = and(T_619, T_625) node T_628 = mux(T_621, UInt<1>("h00"), T_624) node T_629 = or(T_626, T_628) node T_630 = cat(T_620, T_621) node T_631 = bit(T_609, 0) node T_633 = dshl(UInt<8>("h01"), T_630) node T_634 = bits(T_633, 7, 0) node T_635 = not(T_634) node T_636 = and(T_629, T_635) node T_638 = mux(T_631, UInt<1>("h00"), T_634) node T_639 = or(T_636, T_638) node T_640 = cat(T_630, T_631) T_494 <= T_639 skip node paddr = cat(io.resp.ppn, UInt<12>("h00")) node T_644 = geq(paddr, UInt<1>("h00")) node T_646 = lt(paddr, UInt<31>("h040000000")) node T_647 = and(T_644, T_646) node T_649 = geq(paddr, UInt<31>("h040000000")) node T_651 = lt(paddr, UInt<31>("h040008000")) node T_652 = and(T_649, T_651) node T_654 = geq(paddr, UInt<31>("h040008000")) node T_656 = lt(paddr, UInt<31>("h040010000")) node T_657 = and(T_654, T_656) node T_659 = geq(paddr, UInt<31>("h040010000")) node T_661 = lt(paddr, UInt<31>("h040010200")) node T_662 = and(T_659, T_661) node T_664 = geq(paddr, UInt<32>("h080000000")) node T_666 = lt(paddr, UInt<33>("h0100000000")) node T_667 = and(T_664, T_666) node T_668 = or(T_647, T_652) node T_669 = or(T_668, T_657) node T_670 = or(T_669, T_662) node addr_ok = or(T_670, T_667) node T_673 = geq(paddr, UInt<1>("h00")) node T_675 = lt(paddr, UInt<31>("h040000000")) node T_676 = and(T_673, T_675) wire T_686 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} T_686.r <= UInt<1>("h00") T_686.w <= UInt<1>("h00") T_686.x <= UInt<1>("h00") T_686.r <= UInt<1>("h01") T_686.w <= UInt<1>("h01") T_686.x <= UInt<1>("h01") node T_697 = geq(paddr, UInt<31>("h040000000")) node T_699 = lt(paddr, UInt<31>("h040008000")) node T_700 = and(T_697, T_699) wire T_710 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} T_710.r <= UInt<1>("h00") T_710.w <= UInt<1>("h00") T_710.x <= UInt<1>("h00") T_710.r <= UInt<1>("h01") T_710.w <= UInt<1>("h00") T_710.x <= UInt<1>("h00") node T_721 = geq(paddr, UInt<31>("h040008000")) node T_723 = lt(paddr, UInt<31>("h040010000")) node T_724 = and(T_721, T_723) wire T_734 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} T_734.r <= UInt<1>("h00") T_734.w <= UInt<1>("h00") T_734.x <= UInt<1>("h00") T_734.r <= UInt<1>("h01") T_734.w <= UInt<1>("h01") T_734.x <= UInt<1>("h00") node T_745 = geq(paddr, UInt<31>("h040010000")) node T_747 = lt(paddr, UInt<31>("h040010200")) node T_748 = and(T_745, T_747) wire T_758 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} T_758.r <= UInt<1>("h00") T_758.w <= UInt<1>("h00") T_758.x <= UInt<1>("h00") T_758.r <= UInt<1>("h01") T_758.w <= UInt<1>("h01") T_758.x <= UInt<1>("h00") node T_769 = geq(paddr, UInt<32>("h080000000")) node T_771 = lt(paddr, UInt<33>("h0100000000")) node T_772 = and(T_769, T_771) wire T_782 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} T_782.r <= UInt<1>("h00") T_782.w <= UInt<1>("h00") T_782.x <= UInt<1>("h00") T_782.r <= UInt<1>("h01") T_782.w <= UInt<1>("h01") T_782.x <= UInt<1>("h00") node T_792 = cat(T_686.w, T_686.r) node T_793 = cat(T_686.x, T_792) node T_795 = mux(T_676, T_793, UInt<1>("h00")) node T_796 = cat(T_710.w, T_710.r) node T_797 = cat(T_710.x, T_796) node T_799 = mux(T_700, T_797, UInt<1>("h00")) node T_800 = cat(T_734.w, T_734.r) node T_801 = cat(T_734.x, T_800) node T_803 = mux(T_724, T_801, UInt<1>("h00")) node T_804 = cat(T_758.w, T_758.r) node T_805 = cat(T_758.x, T_804) node T_807 = mux(T_748, T_805, UInt<1>("h00")) node T_808 = cat(T_782.w, T_782.r) node T_809 = cat(T_782.x, T_808) node T_811 = mux(T_772, T_809, UInt<1>("h00")) node T_816 = or(T_795, T_799) node T_817 = or(T_816, T_803) node T_818 = or(T_817, T_807) node T_819 = or(T_818, T_811) wire addr_prot : {x : UInt<1>, w : UInt<1>, r : UInt<1>} addr_prot.r <= UInt<1>("h00") addr_prot.w <= UInt<1>("h00") addr_prot.x <= UInt<1>("h00") node T_831 = bits(T_819, 0, 0) addr_prot.r <= T_831 node T_832 = bits(T_819, 1, 1) addr_prot.w <= T_832 node T_833 = bits(T_819, 2, 2) addr_prot.x <= T_833 node T_834 = eq(state, UInt<1>("h00")) io.req.ready <= T_834 node T_836 = eq(addr_ok, UInt<1>("h00")) node T_838 = eq(addr_prot.r, UInt<1>("h00")) node T_839 = or(T_836, T_838) node T_840 = or(T_839, bad_va) node T_841 = and(r_array, tag_cam.io.hits) node T_843 = neq(T_841, UInt<1>("h00")) node T_845 = eq(T_843, UInt<1>("h00")) node T_846 = and(tlb_hit, T_845) node T_847 = or(T_840, T_846) io.resp.xcpt_ld <= T_847 node T_849 = eq(addr_ok, UInt<1>("h00")) node T_851 = eq(addr_prot.w, UInt<1>("h00")) node T_852 = or(T_849, T_851) node T_853 = or(T_852, bad_va) node T_854 = and(w_array, tag_cam.io.hits) node T_856 = neq(T_854, UInt<1>("h00")) node T_858 = eq(T_856, UInt<1>("h00")) node T_859 = and(tlb_hit, T_858) node T_860 = or(T_853, T_859) io.resp.xcpt_st <= T_860 node T_862 = eq(addr_ok, UInt<1>("h00")) node T_864 = eq(addr_prot.x, UInt<1>("h00")) node T_865 = or(T_862, T_864) node T_866 = or(T_865, bad_va) node T_867 = and(x_array, tag_cam.io.hits) node T_869 = neq(T_867, UInt<1>("h00")) node T_871 = eq(T_869, UInt<1>("h00")) node T_872 = and(tlb_hit, T_871) node T_873 = or(T_866, T_872) io.resp.xcpt_if <= T_873 io.resp.miss <= tlb_miss node T_874 = bit(tag_cam.io.hits, 0) node T_875 = bit(tag_cam.io.hits, 1) node T_876 = bit(tag_cam.io.hits, 2) node T_877 = bit(tag_cam.io.hits, 3) node T_878 = bit(tag_cam.io.hits, 4) node T_879 = bit(tag_cam.io.hits, 5) node T_880 = bit(tag_cam.io.hits, 6) node T_881 = bit(tag_cam.io.hits, 7) infer mport T_883 = tag_ram[UInt<1>("h00")], clk infer mport T_885 = tag_ram[UInt<1>("h01")], clk infer mport T_887 = tag_ram[UInt<2>("h02")], clk infer mport T_889 = tag_ram[UInt<2>("h03")], clk infer mport T_891 = tag_ram[UInt<3>("h04")], clk infer mport T_893 = tag_ram[UInt<3>("h05")], clk infer mport T_895 = tag_ram[UInt<3>("h06")], clk infer mport T_897 = tag_ram[UInt<3>("h07")], clk node T_899 = mux(T_874, T_883, UInt<1>("h00")) node T_901 = mux(T_875, T_885, UInt<1>("h00")) node T_903 = mux(T_876, T_887, UInt<1>("h00")) node T_905 = mux(T_877, T_889, UInt<1>("h00")) node T_907 = mux(T_878, T_891, UInt<1>("h00")) node T_909 = mux(T_879, T_893, UInt<1>("h00")) node T_911 = mux(T_880, T_895, UInt<1>("h00")) node T_913 = mux(T_881, T_897, UInt<1>("h00")) node T_915 = or(T_899, T_901) node T_916 = or(T_915, T_903) node T_917 = or(T_916, T_905) node T_918 = or(T_917, T_907) node T_919 = or(T_918, T_909) node T_920 = or(T_919, T_911) node T_921 = or(T_920, T_913) wire T_922 : UInt<20> T_922 <= UInt<1>("h00") T_922 <= T_921 node T_924 = bits(io.req.bits.vpn, 19, 0) node T_925 = mux(vm_enabled, T_922, T_924) io.resp.ppn <= T_925 io.resp.hit_idx <= tag_cam.io.hits node T_926 = and(io.req.ready, io.req.valid) node T_927 = or(io.ptw.invalidate, T_926) tag_cam.io.clear <= T_927 node T_928 = cat(valid_array[7], valid_array[6]) node T_929 = cat(valid_array[5], valid_array[4]) node T_930 = cat(T_928, T_929) node T_931 = cat(valid_array[3], valid_array[2]) node T_932 = cat(valid_array[1], valid_array[0]) node T_933 = cat(T_931, T_932) node T_934 = cat(T_930, T_933) node T_935 = not(T_934) node T_936 = not(tag_hits) node T_937 = and(tag_cam.io.hits, T_936) node T_938 = or(T_935, T_937) tag_cam.io.clear_mask <= T_938 when io.ptw.invalidate : node T_940 = not(UInt<8>("h00")) tag_cam.io.clear_mask <= T_940 skip node T_941 = eq(state, UInt<1>("h01")) io.ptw.req.valid <= T_941 io.ptw.req.bits.addr <= r_refill_tag io.ptw.req.bits.prv <= io.ptw.status.prv io.ptw.req.bits.store <= r_req.store io.ptw.req.bits.fetch <= r_req.instruction node T_942 = and(io.req.ready, io.req.valid) node T_943 = and(T_942, tlb_miss) when T_943 : state <= UInt<1>("h01") r_refill_tag <= lookup_tag r_refill_waddr <= repl_waddr r_req <- io.req.bits skip node T_944 = eq(state, UInt<1>("h01")) when T_944 : when io.ptw.invalidate : state <= UInt<1>("h00") skip when io.ptw.req.ready : state <= UInt<2>("h02") when io.ptw.invalidate : state <= UInt<2>("h03") skip skip skip node T_945 = eq(state, UInt<2>("h02")) node T_946 = and(T_945, io.ptw.invalidate) when T_946 : state <= UInt<2>("h03") skip when io.ptw.resp.valid : state <= UInt<1>("h00") skip module Queue_92 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, count : UInt<1>} io.count <= UInt<1>("h00") io.deq.bits.datablock <= UInt<1>("h00") io.deq.bits.data <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {data : UInt<32>, datablock : UInt<128>}[1] reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_463 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_463) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_469 = and(io.enq.ready, io.enq.valid) node T_471 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_469, T_471) node T_473 = and(io.deq.ready, io.deq.valid) node T_475 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_473, T_475) when do_enq : infer mport T_477 = ram[UInt<1>("h00")], clk T_477 <- io.enq.bits skip when do_deq : skip node T_528 = neq(do_enq, do_deq) when T_528 : maybe_full <= do_enq skip node T_530 = eq(empty, UInt<1>("h00")) node T_532 = and(UInt<1>("h00"), io.enq.valid) node T_533 = or(T_530, T_532) io.deq.valid <= T_533 node T_535 = eq(full, UInt<1>("h00")) node T_537 = and(UInt<1>("h01"), io.deq.ready) node T_538 = or(T_535, T_537) io.enq.ready <= T_538 infer mport T_539 = ram[UInt<1>("h00")], clk wire T_637 : {data : UInt<32>, datablock : UInt<128>} T_637 <- T_539 when maybe_flow : T_637 <- io.enq.bits skip io.deq.bits <- T_637 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_687 = and(maybe_full, ptr_match) node T_688 = cat(T_687, ptr_diff) io.count <= T_688 module Frontend : input clk : Clock input reset : UInt<1> output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} io.mem.grant.ready <= UInt<1>("h00") io.mem.acquire.bits.data <= UInt<1>("h00") io.mem.acquire.bits.union <= UInt<1>("h00") io.mem.acquire.bits.a_type <= UInt<1>("h00") io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") io.mem.acquire.bits.addr_beat <= UInt<1>("h00") io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") io.mem.acquire.bits.addr_block <= UInt<1>("h00") io.mem.acquire.valid <= UInt<1>("h00") io.ptw.req.bits.fetch <= UInt<1>("h00") io.ptw.req.bits.store <= UInt<1>("h00") io.ptw.req.bits.prv <= UInt<1>("h00") io.ptw.req.bits.addr <= UInt<1>("h00") io.ptw.req.valid <= UInt<1>("h00") io.cpu.npc <= UInt<1>("h00") io.cpu.btb_resp.bits.bht.value <= UInt<1>("h00") io.cpu.btb_resp.bits.bht.history <= UInt<1>("h00") io.cpu.btb_resp.bits.entry <= UInt<1>("h00") io.cpu.btb_resp.bits.target <= UInt<1>("h00") io.cpu.btb_resp.bits.bridx <= UInt<1>("h00") io.cpu.btb_resp.bits.mask <= UInt<1>("h00") io.cpu.btb_resp.bits.taken <= UInt<1>("h00") io.cpu.btb_resp.valid <= UInt<1>("h00") io.cpu.resp.bits.xcpt_if <= UInt<1>("h00") io.cpu.resp.bits.mask <= UInt<1>("h00") io.cpu.resp.bits.data[0] <= UInt<1>("h00") io.cpu.resp.bits.pc <= UInt<1>("h00") io.cpu.resp.valid <= UInt<1>("h00") inst btb of BTB btb.io.invalidate <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.target <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") btb.io.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") btb.io.ras_update.bits.prediction.valid <= UInt<1>("h00") btb.io.ras_update.bits.returnAddr <= UInt<1>("h00") btb.io.ras_update.bits.isReturn <= UInt<1>("h00") btb.io.ras_update.bits.isCall <= UInt<1>("h00") btb.io.ras_update.valid <= UInt<1>("h00") btb.io.bht_update.bits.mispredict <= UInt<1>("h00") btb.io.bht_update.bits.taken <= UInt<1>("h00") btb.io.bht_update.bits.pc <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.target <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") btb.io.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") btb.io.bht_update.bits.prediction.valid <= UInt<1>("h00") btb.io.bht_update.valid <= UInt<1>("h00") btb.io.btb_update.bits.br_pc <= UInt<1>("h00") btb.io.btb_update.bits.isReturn <= UInt<1>("h00") btb.io.btb_update.bits.isJump <= UInt<1>("h00") btb.io.btb_update.bits.taken <= UInt<1>("h00") btb.io.btb_update.bits.target <= UInt<1>("h00") btb.io.btb_update.bits.pc <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.target <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") btb.io.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") btb.io.btb_update.bits.prediction.valid <= UInt<1>("h00") btb.io.btb_update.valid <= UInt<1>("h00") btb.io.req.bits.addr <= UInt<1>("h00") btb.io.req.valid <= UInt<1>("h00") btb.clk <= clk btb.reset <= reset inst icache of ICache icache.io.mem.grant.bits.data <= UInt<1>("h00") icache.io.mem.grant.bits.g_type <= UInt<1>("h00") icache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") icache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") icache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") icache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") icache.io.mem.grant.valid <= UInt<1>("h00") icache.io.mem.acquire.ready <= UInt<1>("h00") icache.io.invalidate <= UInt<1>("h00") icache.io.resp.ready <= UInt<1>("h00") icache.io.req.bits.kill <= UInt<1>("h00") icache.io.req.bits.ppn <= UInt<1>("h00") icache.io.req.bits.idx <= UInt<1>("h00") icache.io.req.valid <= UInt<1>("h00") icache.clk <= clk icache.reset <= reset inst tlb of TLB tlb.io.ptw.invalidate <= UInt<1>("h00") tlb.io.ptw.status.ie <= UInt<1>("h00") tlb.io.ptw.status.prv <= UInt<1>("h00") tlb.io.ptw.status.ie1 <= UInt<1>("h00") tlb.io.ptw.status.prv1 <= UInt<1>("h00") tlb.io.ptw.status.ie2 <= UInt<1>("h00") tlb.io.ptw.status.prv2 <= UInt<1>("h00") tlb.io.ptw.status.ie3 <= UInt<1>("h00") tlb.io.ptw.status.prv3 <= UInt<1>("h00") tlb.io.ptw.status.fs <= UInt<1>("h00") tlb.io.ptw.status.xs <= UInt<1>("h00") tlb.io.ptw.status.mprv <= UInt<1>("h00") tlb.io.ptw.status.vm <= UInt<1>("h00") tlb.io.ptw.status.zero1 <= UInt<1>("h00") tlb.io.ptw.status.sd_rv32 <= UInt<1>("h00") tlb.io.ptw.status.zero2 <= UInt<1>("h00") tlb.io.ptw.status.sd <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.v <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.r <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.d <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") tlb.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") tlb.io.ptw.resp.bits.error <= UInt<1>("h00") tlb.io.ptw.resp.valid <= UInt<1>("h00") tlb.io.ptw.req.ready <= UInt<1>("h00") tlb.io.req.bits.store <= UInt<1>("h00") tlb.io.req.bits.instruction <= UInt<1>("h00") tlb.io.req.bits.passthrough <= UInt<1>("h00") tlb.io.req.bits.vpn <= UInt<1>("h00") tlb.io.req.bits.asid <= UInt<1>("h00") tlb.io.req.valid <= UInt<1>("h00") tlb.clk <= clk tlb.reset <= reset reg s1_pc_ : UInt, clk, UInt<1>("h00"), s1_pc_ node T_1368 = not(s1_pc_) node T_1370 = or(T_1368, UInt<2>("h03")) node s1_pc = not(T_1370) reg s1_same_block : UInt<1>, clk, UInt<1>("h00"), s1_same_block reg s2_valid : UInt<1>, clk, reset, UInt<1>("h01") reg s2_pc : UInt, clk, reset, UInt<10>("h0200") reg s2_btb_resp_valid : UInt<1>, clk, reset, UInt<1>("h00") reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), s2_btb_resp_bits reg s2_xcpt_if : UInt<1>, clk, reset, UInt<1>("h00") wire s2_resp_valid : UInt<1> s2_resp_valid <= UInt<1>("h00") wire s2_resp_data : UInt<128> s2_resp_data <= UInt<1>("h00") node T_1396 = bit(btb.io.resp.bits.target, 38) node btbTarget = cat(T_1396, btb.io.resp.bits.target) node ntpc_0 = addw(s1_pc, UInt<3>("h04")) node T_1400 = bit(s1_pc, 38) node T_1401 = bit(ntpc_0, 38) node T_1402 = and(T_1400, T_1401) node T_1403 = bits(ntpc_0, 38, 2) node T_1405 = cat(T_1403, UInt<2>("h00")) node ntpc = cat(T_1402, T_1405) node T_1408 = eq(s2_resp_valid, UInt<1>("h00")) node icmiss = and(s2_valid, T_1408) node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc) node npc = mux(icmiss, s2_pc, predicted_npc) node T_1413 = eq(icmiss, UInt<1>("h00")) node T_1415 = eq(io.cpu.req.valid, UInt<1>("h00")) node T_1416 = and(T_1413, T_1415) node T_1418 = eq(btb.io.resp.bits.taken, UInt<1>("h00")) node T_1419 = and(T_1416, T_1418) node T_1421 = and(ntpc, UInt<5>("h010")) node T_1423 = and(s1_pc, UInt<5>("h010")) node T_1424 = eq(T_1421, T_1423) node s0_same_block = and(T_1419, T_1424) node T_1427 = eq(io.cpu.resp.ready, UInt<1>("h00")) node stall = and(io.cpu.resp.valid, T_1427) node T_1430 = eq(stall, UInt<1>("h00")) when T_1430 : node T_1432 = eq(tlb.io.resp.miss, UInt<1>("h00")) node T_1433 = and(s0_same_block, T_1432) s1_same_block <= T_1433 s1_pc_ <= npc node T_1435 = eq(icmiss, UInt<1>("h00")) s2_valid <= T_1435 node T_1437 = eq(icmiss, UInt<1>("h00")) when T_1437 : s2_pc <= s1_pc s2_btb_resp_valid <= btb.io.resp.valid when btb.io.resp.valid : s2_btb_resp_bits <- btb.io.resp.bits skip s2_xcpt_if <= tlb.io.resp.xcpt_if skip skip when io.cpu.req.valid : s1_same_block <= UInt<1>("h00") s1_pc_ <= io.cpu.req.bits.pc s2_valid <= UInt<1>("h00") skip node T_1441 = eq(stall, UInt<1>("h00")) node T_1443 = eq(icmiss, UInt<1>("h00")) node T_1444 = and(T_1441, T_1443) btb.io.req.valid <= T_1444 btb.io.req.bits.addr <= s1_pc btb.io.btb_update <- io.cpu.btb_update btb.io.bht_update <- io.cpu.bht_update btb.io.ras_update <- io.cpu.ras_update node T_1445 = or(io.cpu.invalidate, io.ptw.invalidate) btb.io.invalidate <= T_1445 io.ptw <- tlb.io.ptw node T_1447 = eq(stall, UInt<1>("h00")) node T_1449 = eq(icmiss, UInt<1>("h00")) node T_1450 = and(T_1447, T_1449) tlb.io.req.valid <= T_1450 node T_1451 = shr(s1_pc, 12) tlb.io.req.bits.vpn <= T_1451 tlb.io.req.bits.asid <= UInt<1>("h00") tlb.io.req.bits.passthrough <= UInt<1>("h00") tlb.io.req.bits.instruction <= UInt<1>("h01") tlb.io.req.bits.store <= UInt<1>("h00") io.mem <- icache.io.mem node T_1457 = eq(stall, UInt<1>("h00")) node T_1459 = eq(s0_same_block, UInt<1>("h00")) node T_1460 = and(T_1457, T_1459) icache.io.req.valid <= T_1460 icache.io.req.bits.idx <= io.cpu.npc icache.io.invalidate <= io.cpu.invalidate icache.io.req.bits.ppn <= tlb.io.resp.ppn node T_1461 = or(io.cpu.req.valid, tlb.io.resp.miss) node T_1462 = or(T_1461, tlb.io.resp.xcpt_if) node T_1463 = or(T_1462, icmiss) node T_1464 = or(T_1463, io.ptw.invalidate) icache.io.req.bits.kill <= T_1464 node T_1465 = or(s2_xcpt_if, s2_resp_valid) node T_1466 = and(s2_valid, T_1465) io.cpu.resp.valid <= T_1466 io.cpu.resp.bits.pc <= s2_pc node T_1467 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) io.cpu.npc <= T_1467 inst T_1517 of Queue_92 T_1517.io.deq.ready <= UInt<1>("h00") T_1517.io.enq.bits.datablock <= UInt<1>("h00") T_1517.io.enq.bits.data <= UInt<1>("h00") T_1517.io.enq.valid <= UInt<1>("h00") T_1517.clk <= clk T_1517.reset <= reset T_1517.io.enq <- icache.io.resp node T_1523 = eq(stall, UInt<1>("h00")) node T_1525 = eq(s1_same_block, UInt<1>("h00")) node T_1526 = and(T_1523, T_1525) T_1517.io.deq.ready <= T_1526 s2_resp_valid <= T_1517.io.deq.valid s2_resp_data <= T_1517.io.deq.bits.datablock node T_1527 = bits(s2_pc, 3, 2) node T_1528 = shl(T_1527, 5) node fetch_data = dshr(s2_resp_data, T_1528) node T_1530 = bits(fetch_data, 31, 0) io.cpu.resp.bits.data[0] <= T_1530 node T_1532 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) node T_1533 = mux(s2_btb_resp_valid, T_1532, UInt<2>("h03")) io.cpu.resp.bits.mask <= T_1533 io.cpu.resp.bits.xcpt_if <= s2_xcpt_if io.cpu.btb_resp.valid <= s2_btb_resp_valid io.cpu.btb_resp.bits <- s2_btb_resp_bits module WritebackUnit : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} io.release.bits.data <= UInt<1>("h00") io.release.bits.r_type <= UInt<1>("h00") io.release.bits.voluntary <= UInt<1>("h00") io.release.bits.client_xact_id <= UInt<1>("h00") io.release.bits.addr_block <= UInt<1>("h00") io.release.bits.addr_beat <= UInt<1>("h00") io.release.valid <= UInt<1>("h00") io.data_req.bits.addr <= UInt<1>("h00") io.data_req.bits.way_en <= UInt<1>("h00") io.data_req.valid <= UInt<1>("h00") io.meta_read.bits.tag <= UInt<1>("h00") io.meta_read.bits.idx <= UInt<1>("h00") io.meta_read.valid <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") reg active : UInt<1>, clk, reset, UInt<1>("h00") reg r1_data_req_fired : UInt<1>, clk, reset, UInt<1>("h00") reg r2_data_req_fired : UInt<1>, clk, reset, UInt<1>("h00") reg data_req_cnt : UInt<3>, clk, reset, UInt<3>("h00") node T_476 = not(UInt<1>("h01")) node beat_done = eq(T_476, UInt<1>("h00")) node T_479 = and(io.release.ready, io.release.valid) reg beat_cnt : UInt<2>, clk, reset, UInt<2>("h00") when T_479 : node T_483 = eq(beat_cnt, UInt<2>("h03")) node T_485 = and(UInt<1>("h00"), T_483) node T_488 = addw(beat_cnt, UInt<1>("h01")) node T_489 = mux(T_485, UInt<1>("h00"), T_488) beat_cnt <= T_489 skip node all_beats_done = and(T_479, T_483) reg req : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk, UInt<1>("h00"), req io.release.valid <= UInt<1>("h00") when active : r1_data_req_fired <= UInt<1>("h00") r2_data_req_fired <= r1_data_req_fired node T_555 = and(io.data_req.ready, io.data_req.valid) node T_556 = and(io.meta_read.ready, io.meta_read.valid) node T_557 = and(T_555, T_556) when T_557 : r1_data_req_fired <= UInt<1>("h01") node T_560 = addw(data_req_cnt, UInt<1>("h01")) data_req_cnt <= T_560 skip when r2_data_req_fired : io.release.valid <= beat_done when beat_done : node T_562 = eq(io.release.ready, UInt<1>("h00")) when T_562 : r1_data_req_fired <= UInt<1>("h00") r2_data_req_fired <= UInt<1>("h00") node T_566 = and(UInt<1>("h01"), r1_data_req_fired) node T_569 = mux(T_566, UInt<2>("h02"), UInt<1>("h01")) node T_570 = subw(data_req_cnt, T_569) data_req_cnt <= T_570 skip node T_572 = eq(T_562, UInt<1>("h00")) when T_572 : skip skip node T_574 = eq(r1_data_req_fired, UInt<1>("h00")) when T_574 : node T_576 = lt(data_req_cnt, UInt<3>("h04")) node T_578 = eq(io.release.ready, UInt<1>("h00")) node T_579 = or(T_576, T_578) active <= T_579 skip skip skip node T_580 = and(io.req.ready, io.req.valid) when T_580 : active <= UInt<1>("h01") data_req_cnt <= UInt<1>("h00") req <- io.req.bits skip node T_584 = eq(active, UInt<1>("h00")) io.req.ready <= T_584 node req_idx = bits(req.addr_block, 5, 0) node T_587 = lt(data_req_cnt, UInt<3>("h04")) node fire = and(active, T_587) io.meta_read.valid <= fire io.meta_read.bits.idx <= req_idx node T_589 = shr(req.addr_block, 6) io.meta_read.bits.tag <= T_589 io.data_req.valid <= fire io.data_req.bits.way_en <= req.way_en node T_590 = bits(data_req_cnt, 1, 0) node T_591 = cat(req_idx, T_590) node T_592 = shl(T_591, 4) io.data_req.bits.addr <= T_592 io.release.bits <- req io.release.bits.addr_beat <= beat_cnt io.release.bits.data <= io.data_resp module ProbeUnit : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}} io.wb_req.bits.way_en <= UInt<1>("h00") io.wb_req.bits.data <= UInt<1>("h00") io.wb_req.bits.r_type <= UInt<1>("h00") io.wb_req.bits.voluntary <= UInt<1>("h00") io.wb_req.bits.client_xact_id <= UInt<1>("h00") io.wb_req.bits.addr_block <= UInt<1>("h00") io.wb_req.bits.addr_beat <= UInt<1>("h00") io.wb_req.valid <= UInt<1>("h00") io.meta_write.bits.data.coh.state <= UInt<1>("h00") io.meta_write.bits.data.tag <= UInt<1>("h00") io.meta_write.bits.way_en <= UInt<1>("h00") io.meta_write.bits.idx <= UInt<1>("h00") io.meta_write.valid <= UInt<1>("h00") io.meta_read.bits.tag <= UInt<1>("h00") io.meta_read.bits.idx <= UInt<1>("h00") io.meta_read.valid <= UInt<1>("h00") io.rep.bits.data <= UInt<1>("h00") io.rep.bits.r_type <= UInt<1>("h00") io.rep.bits.voluntary <= UInt<1>("h00") io.rep.bits.client_xact_id <= UInt<1>("h00") io.rep.bits.addr_block <= UInt<1>("h00") io.rep.bits.addr_beat <= UInt<1>("h00") io.rep.valid <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg old_coh : {state : UInt<2>}, clk, UInt<1>("h00"), old_coh reg way_en : UInt, clk, UInt<1>("h00"), way_en reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk, UInt<1>("h00"), req node tag_matches = neq(way_en, UInt<1>("h00")) wire miss_coh : {state : UInt<2>} miss_coh.state <= UInt<1>("h00") miss_coh.state <= UInt<1>("h00") wire reply_coh : {state : UInt<2>} reply_coh <- miss_coh when tag_matches : reply_coh <- old_coh skip wire T_973 : UInt<2>[1] T_973[0] <= UInt<2>("h03") node T_976 = eq(T_973[0], reply_coh.state) node T_978 = or(UInt<1>("h00"), T_976) node T_979 = mux(T_978, UInt<1>("h00"), UInt<2>("h03")) node T_980 = mux(T_978, UInt<1>("h01"), UInt<3>("h04")) node T_981 = mux(T_978, UInt<2>("h02"), UInt<3>("h05")) node T_982 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_983 = mux(T_982, T_981, UInt<3>("h05")) node T_984 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_985 = mux(T_984, T_980, T_983) node T_986 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_987 = mux(T_986, T_979, T_985) wire T_989 : UInt<2>[1] T_989[0] <= UInt<2>("h03") node T_992 = eq(T_989[0], reply_coh.state) node T_994 = or(UInt<1>("h00"), T_992) node T_995 = mux(T_994, UInt<1>("h00"), UInt<2>("h03")) node T_996 = mux(T_994, UInt<1>("h01"), UInt<3>("h04")) node T_997 = mux(T_994, UInt<2>("h02"), UInt<3>("h05")) node T_998 = eq(UInt<5>("h013"), UInt<5>("h011")) node T_999 = mux(T_998, T_997, UInt<3>("h05")) node T_1000 = eq(UInt<5>("h011"), UInt<5>("h011")) node T_1001 = mux(T_1000, T_996, T_999) node T_1002 = eq(UInt<5>("h010"), UInt<5>("h011")) node T_1003 = mux(T_1002, T_995, T_1001) wire T_1005 : UInt<2>[1] T_1005[0] <= UInt<2>("h03") node T_1008 = eq(T_1005[0], reply_coh.state) node T_1010 = or(UInt<1>("h00"), T_1008) node T_1011 = mux(T_1010, UInt<1>("h00"), UInt<2>("h03")) node T_1012 = mux(T_1010, UInt<1>("h01"), UInt<3>("h04")) node T_1013 = mux(T_1010, UInt<2>("h02"), UInt<3>("h05")) node T_1014 = eq(UInt<5>("h013"), UInt<5>("h013")) node T_1015 = mux(T_1014, T_1013, UInt<3>("h05")) node T_1016 = eq(UInt<5>("h011"), UInt<5>("h013")) node T_1017 = mux(T_1016, T_1012, T_1015) node T_1018 = eq(UInt<5>("h010"), UInt<5>("h013")) node T_1019 = mux(T_1018, T_1011, T_1017) node T_1020 = eq(UInt<2>("h02"), req.p_type) node T_1021 = mux(T_1020, T_1019, UInt<2>("h03")) node T_1022 = eq(UInt<1>("h01"), req.p_type) node T_1023 = mux(T_1022, T_1003, T_1021) node T_1024 = eq(UInt<1>("h00"), req.p_type) node T_1025 = mux(T_1024, T_987, T_1023) wire reply : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} reply.data <= UInt<1>("h00") reply.r_type <= UInt<1>("h00") reply.voluntary <= UInt<1>("h00") reply.client_xact_id <= UInt<1>("h00") reply.addr_block <= UInt<1>("h00") reply.addr_beat <= UInt<1>("h00") reply.r_type <= T_1025 reply.client_xact_id <= UInt<1>("h00") reply.addr_block <= req.addr_block reply.addr_beat <= UInt<1>("h00") reply.data <= UInt<1>("h00") reply.voluntary <= UInt<1>("h00") node T_1093 = eq(state, UInt<1>("h00")) io.req.ready <= T_1093 node T_1094 = eq(state, UInt<3>("h05")) io.rep.valid <= T_1094 io.rep.bits <- reply node T_1096 = eq(io.rep.valid, UInt<1>("h00")) wire T_1098 : UInt<2>[3] T_1098[0] <= UInt<1>("h00") T_1098[1] <= UInt<1>("h01") T_1098[2] <= UInt<2>("h02") node T_1103 = eq(T_1098[0], io.rep.bits.r_type) node T_1104 = eq(T_1098[1], io.rep.bits.r_type) node T_1105 = eq(T_1098[2], io.rep.bits.r_type) node T_1107 = or(UInt<1>("h00"), T_1103) node T_1108 = or(T_1107, T_1104) node T_1109 = or(T_1108, T_1105) node T_1111 = eq(T_1109, UInt<1>("h00")) node T_1112 = or(T_1096, T_1111) node T_1114 = eq(reset, UInt<1>("h00")) when T_1114 : node T_1116 = eq(T_1112, UInt<1>("h00")) when T_1116 : node T_1118 = eq(reset, UInt<1>("h00")) when T_1118 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data") skip stop(clk, UInt<1>(1), 1) skip skip node T_1119 = eq(state, UInt<1>("h01")) io.meta_read.valid <= T_1119 io.meta_read.bits.idx <= req.addr_block node T_1120 = shr(req.addr_block, 6) io.meta_read.bits.tag <= T_1120 node T_1121 = eq(state, UInt<4>("h08")) io.meta_write.valid <= T_1121 io.meta_write.bits.way_en <= way_en io.meta_write.bits.idx <= req.addr_block node T_1122 = shr(req.addr_block, 6) io.meta_write.bits.data.tag <= T_1122 node T_1123 = eq(UInt<2>("h02"), req.p_type) node T_1124 = mux(T_1123, old_coh.state, old_coh.state) node T_1125 = eq(UInt<1>("h01"), req.p_type) node T_1126 = mux(T_1125, UInt<1>("h01"), T_1124) node T_1127 = eq(UInt<1>("h00"), req.p_type) node T_1128 = mux(T_1127, UInt<1>("h00"), T_1126) wire T_1154 : {state : UInt<2>} T_1154.state <= UInt<1>("h00") T_1154.state <= T_1128 io.meta_write.bits.data.coh <- T_1154 node T_1180 = eq(state, UInt<3>("h06")) io.wb_req.valid <= T_1180 io.wb_req.bits <- reply io.wb_req.bits.way_en <= way_en node T_1181 = and(io.req.ready, io.req.valid) when T_1181 : state <= UInt<1>("h01") req <- io.req.bits skip node T_1182 = and(io.meta_read.ready, io.meta_read.valid) when T_1182 : state <= UInt<2>("h02") skip node T_1183 = eq(state, UInt<2>("h02")) when T_1183 : state <= UInt<2>("h03") skip node T_1184 = eq(state, UInt<2>("h03")) when T_1184 : state <= UInt<3>("h04") old_coh <- io.block_state way_en <= io.way_en node T_1186 = eq(io.mshr_rdy, UInt<1>("h00")) when T_1186 : state <= UInt<1>("h01") skip skip node T_1187 = eq(state, UInt<3>("h04")) when T_1187 : wire T_1189 : UInt<2>[1] T_1189[0] <= UInt<2>("h03") node T_1192 = eq(T_1189[0], old_coh.state) node T_1194 = or(UInt<1>("h00"), T_1192) node T_1195 = and(tag_matches, T_1194) node T_1196 = mux(T_1195, UInt<3>("h06"), UInt<3>("h05")) state <= T_1196 skip node T_1197 = eq(state, UInt<3>("h05")) node T_1198 = and(T_1197, io.rep.ready) when T_1198 : node T_1199 = mux(tag_matches, UInt<4>("h08"), UInt<1>("h00")) state <= T_1199 skip node T_1200 = and(io.wb_req.ready, io.wb_req.valid) when T_1200 : state <= UInt<3>("h07") skip node T_1201 = eq(state, UInt<3>("h07")) node T_1202 = and(T_1201, io.wb_req.ready) when T_1202 : state <= UInt<4>("h08") skip node T_1203 = and(io.meta_write.ready, io.meta_write.valid) when T_1203 : state <= UInt<1>("h00") skip module Arbiter_93 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.tag <= UInt<1>("h00") io.out.bits.idx <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_108 : UInt<1> T_108 <= UInt<1>("h00") io.out.valid <= io.in[T_108].valid io.out.bits <- io.in[T_108].bits io.chosen <= T_108 io.in[T_108].ready <= UInt<1>("h00") node T_140 = or(UInt<1>("h00"), io.in[0].valid) node T_142 = eq(T_140, UInt<1>("h00")) node T_144 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_145 = mux(UInt<1>("h00"), T_144, UInt<1>("h01")) node T_146 = and(T_145, io.out.ready) io.in[0].ready <= T_146 node T_148 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_149 = mux(UInt<1>("h00"), T_148, T_142) node T_150 = and(T_149, io.out.ready) io.in[1].ready <= T_150 node T_153 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_154 = mux(UInt<1>("h00"), UInt<1>("h01"), T_153) T_108 <= T_154 module Arbiter_94 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data.coh.state <= UInt<1>("h00") io.out.bits.data.tag <= UInt<1>("h00") io.out.bits.way_en <= UInt<1>("h00") io.out.bits.idx <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_1714 : UInt<1> T_1714 <= UInt<1>("h00") io.out.valid <= io.in[T_1714].valid io.out.bits <- io.in[T_1714].bits io.chosen <= T_1714 io.in[T_1714].ready <= UInt<1>("h00") node T_2184 = or(UInt<1>("h00"), io.in[0].valid) node T_2186 = eq(T_2184, UInt<1>("h00")) node T_2188 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2189 = mux(UInt<1>("h00"), T_2188, UInt<1>("h01")) node T_2190 = and(T_2189, io.out.ready) io.in[0].ready <= T_2190 node T_2192 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_2193 = mux(UInt<1>("h00"), T_2192, T_2186) node T_2194 = and(T_2193, io.out.ready) io.in[1].ready <= T_2194 node T_2197 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_2198 = mux(UInt<1>("h00"), UInt<1>("h01"), T_2197) T_1714 <= T_2198 module LockingArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.union <= UInt<1>("h00") io.out.bits.a_type <= UInt<1>("h00") io.out.bits.is_builtin_type <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") reg T_852 : UInt<1>, clk, reset, UInt<1>("h00") reg T_854 : UInt, clk, reset, UInt<2>("h02") wire T_856 : UInt<2> T_856 <= UInt<1>("h00") io.out.valid <= io.in[T_856].valid io.out.bits <- io.in[T_856].bits io.chosen <= T_856 io.in[T_856].ready <= UInt<1>("h00") node T_1056 = or(UInt<1>("h00"), io.in[0].valid) node T_1058 = eq(T_1056, UInt<1>("h00")) node T_1060 = or(UInt<1>("h00"), io.in[0].valid) node T_1061 = or(T_1060, io.in[1].valid) node T_1063 = eq(T_1061, UInt<1>("h00")) node T_1065 = eq(T_854, UInt<1>("h00")) node T_1066 = mux(T_852, T_1065, UInt<1>("h01")) node T_1067 = and(T_1066, io.out.ready) io.in[0].ready <= T_1067 node T_1069 = eq(T_854, UInt<1>("h01")) node T_1070 = mux(T_852, T_1069, T_1058) node T_1071 = and(T_1070, io.out.ready) io.in[1].ready <= T_1071 node T_1073 = eq(T_854, UInt<2>("h02")) node T_1074 = mux(T_852, T_1073, T_1063) node T_1075 = and(T_1074, io.out.ready) io.in[2].ready <= T_1075 reg T_1077 : UInt<2>, clk, reset, UInt<2>("h00") node T_1079 = addw(T_1077, UInt<1>("h01")) node T_1080 = and(io.out.ready, io.out.valid) when T_1080 : node T_1082 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) wire T_1085 : UInt<3>[1] T_1085[0] <= UInt<3>("h03") node T_1088 = eq(T_1085[0], io.out.bits.a_type) node T_1090 = or(UInt<1>("h00"), T_1088) node T_1091 = and(T_1082, T_1090) when T_1091 : T_1077 <= T_1079 node T_1093 = eq(T_852, UInt<1>("h00")) when T_1093 : T_852 <= UInt<1>("h01") node T_1095 = and(io.in[0].ready, io.in[0].valid) node T_1096 = and(io.in[1].ready, io.in[1].valid) node T_1097 = and(io.in[2].ready, io.in[2].valid) wire T_1099 : UInt<1>[3] T_1099[0] <= T_1095 T_1099[1] <= T_1096 T_1099[2] <= T_1097 node T_1107 = mux(T_1099[1], UInt<1>("h01"), UInt<2>("h02")) node T_1108 = mux(T_1099[0], UInt<1>("h00"), T_1107) T_854 <= T_1108 skip skip node T_1110 = eq(T_1079, UInt<1>("h00")) when T_1110 : T_852 <= UInt<1>("h00") skip skip node T_1114 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) node choose = mux(io.in[0].valid, UInt<1>("h00"), T_1114) node T_1117 = mux(T_852, T_854, choose) T_856 <= T_1117 module Arbiter_95 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.way_en <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.r_type <= UInt<1>("h00") io.out.bits.voluntary <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_724 : UInt<1> T_724 <= UInt<1>("h00") io.out.valid <= io.in[T_724].valid io.out.bits <- io.in[T_724].bits io.chosen <= T_724 io.in[T_724].ready <= UInt<1>("h00") node T_924 = or(UInt<1>("h00"), io.in[0].valid) node T_926 = eq(T_924, UInt<1>("h00")) node T_928 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_929 = mux(UInt<1>("h00"), T_928, UInt<1>("h01")) node T_930 = and(T_929, io.out.ready) io.in[0].ready <= T_930 node T_932 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_933 = mux(UInt<1>("h00"), T_932, T_926) node T_934 = and(T_933, io.out.ready) io.in[1].ready <= T_934 node T_937 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_938 = mux(UInt<1>("h00"), UInt<1>("h01"), T_937) T_724 <= T_938 module Arbiter_96 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.sdq_id <= UInt<1>("h00") io.out.bits.phys <= UInt<1>("h00") io.out.bits.kill <= UInt<1>("h00") io.out.bits.typ <= UInt<1>("h00") io.out.bits.cmd <= UInt<1>("h00") io.out.bits.tag <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_1230 : UInt<1> T_1230 <= UInt<1>("h00") io.out.valid <= io.in[T_1230].valid io.out.bits <- io.in[T_1230].bits io.chosen <= T_1230 io.in[T_1230].ready <= UInt<1>("h00") node T_1568 = or(UInt<1>("h00"), io.in[0].valid) node T_1570 = eq(T_1568, UInt<1>("h00")) node T_1572 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1573 = mux(UInt<1>("h00"), T_1572, UInt<1>("h01")) node T_1574 = and(T_1573, io.out.ready) io.in[0].ready <= T_1574 node T_1576 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_1577 = mux(UInt<1>("h00"), T_1576, T_1570) node T_1578 = and(T_1577, io.out.ready) io.in[1].ready <= T_1578 node T_1581 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_1582 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1581) T_1230 <= T_1582 module Arbiter_97 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_64 : UInt<1> T_64 <= UInt<1>("h00") io.out.valid <= io.in[T_64].valid io.out.bits <= io.in[T_64].bits io.chosen <= T_64 io.in[T_64].ready <= UInt<1>("h00") node T_84 = or(UInt<1>("h00"), io.in[0].valid) node T_86 = eq(T_84, UInt<1>("h00")) node T_88 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_89 = mux(UInt<1>("h00"), T_88, UInt<1>("h01")) node T_90 = and(T_89, io.out.ready) io.in[0].ready <= T_90 node T_92 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_93 = mux(UInt<1>("h00"), T_92, T_86) node T_94 = and(T_93, io.out.ready) io.in[1].ready <= T_94 node T_97 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_98 = mux(UInt<1>("h00"), UInt<1>("h01"), T_97) T_64 <= T_98 module Queue_98 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>} io.count <= UInt<1>("h00") io.deq.bits.sdq_id <= UInt<1>("h00") io.deq.bits.phys <= UInt<1>("h00") io.deq.bits.kill <= UInt<1>("h00") io.deq.bits.typ <= UInt<1>("h00") io.deq.bits.cmd <= UInt<1>("h00") io.deq.bits.tag <= UInt<1>("h00") io.deq.bits.addr <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16] reg T_503 : UInt<4>, clk, reset, UInt<4>("h00") reg T_505 : UInt<4>, clk, reset, UInt<4>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_503, T_505) node T_510 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_510) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_516 = and(io.enq.ready, io.enq.valid) node T_518 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_516, T_518) node T_520 = and(io.deq.ready, io.deq.valid) node T_522 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_520, T_522) when do_enq : infer mport T_524 = ram[T_503], clk T_524 <- io.enq.bits node T_579 = eq(T_503, UInt<4>("h0f")) node T_581 = and(UInt<1>("h00"), T_579) node T_584 = addw(T_503, UInt<1>("h01")) node T_585 = mux(T_581, UInt<1>("h00"), T_584) T_503 <= T_585 skip when do_deq : node T_587 = eq(T_505, UInt<4>("h0f")) node T_589 = and(UInt<1>("h00"), T_587) node T_592 = addw(T_505, UInt<1>("h01")) node T_593 = mux(T_589, UInt<1>("h00"), T_592) T_505 <= T_593 skip node T_594 = neq(do_enq, do_deq) when T_594 : maybe_full <= do_enq skip node T_596 = eq(empty, UInt<1>("h00")) node T_598 = and(UInt<1>("h00"), io.enq.valid) node T_599 = or(T_596, T_598) io.deq.valid <= T_599 node T_601 = eq(full, UInt<1>("h00")) node T_603 = and(UInt<1>("h00"), io.deq.ready) node T_604 = or(T_601, T_603) io.enq.ready <= T_604 infer mport T_605 = ram[T_505], clk wire T_713 : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} T_713 <- T_605 when maybe_flow : T_713 <- io.enq.bits skip io.deq.bits <- T_713 node ptr_diff = subw(T_503, T_505) node T_768 = and(maybe_full, ptr_match) node T_769 = cat(T_768, ptr_diff) io.count <= T_769 module MSHR : input clk : Clock input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} io.probe_rdy <= UInt<1>("h00") io.wb_req.bits.way_en <= UInt<1>("h00") io.wb_req.bits.data <= UInt<1>("h00") io.wb_req.bits.r_type <= UInt<1>("h00") io.wb_req.bits.voluntary <= UInt<1>("h00") io.wb_req.bits.client_xact_id <= UInt<1>("h00") io.wb_req.bits.addr_block <= UInt<1>("h00") io.wb_req.bits.addr_beat <= UInt<1>("h00") io.wb_req.valid <= UInt<1>("h00") io.replay.bits.sdq_id <= UInt<1>("h00") io.replay.bits.phys <= UInt<1>("h00") io.replay.bits.kill <= UInt<1>("h00") io.replay.bits.typ <= UInt<1>("h00") io.replay.bits.cmd <= UInt<1>("h00") io.replay.bits.tag <= UInt<1>("h00") io.replay.bits.addr <= UInt<1>("h00") io.replay.valid <= UInt<1>("h00") io.meta_write.bits.data.coh.state <= UInt<1>("h00") io.meta_write.bits.data.tag <= UInt<1>("h00") io.meta_write.bits.way_en <= UInt<1>("h00") io.meta_write.bits.idx <= UInt<1>("h00") io.meta_write.valid <= UInt<1>("h00") io.meta_read.bits.tag <= UInt<1>("h00") io.meta_read.bits.idx <= UInt<1>("h00") io.meta_read.valid <= UInt<1>("h00") io.refill.addr <= UInt<1>("h00") io.refill.way_en <= UInt<1>("h00") io.mem_req.bits.data <= UInt<1>("h00") io.mem_req.bits.union <= UInt<1>("h00") io.mem_req.bits.a_type <= UInt<1>("h00") io.mem_req.bits.is_builtin_type <= UInt<1>("h00") io.mem_req.bits.addr_beat <= UInt<1>("h00") io.mem_req.bits.client_xact_id <= UInt<1>("h00") io.mem_req.bits.addr_block <= UInt<1>("h00") io.mem_req.valid <= UInt<1>("h00") io.tag <= UInt<1>("h00") io.idx_match <= UInt<1>("h00") io.req_sec_rdy <= UInt<1>("h00") io.req_pri_rdy <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") wire T_1277 : {state : UInt<2>} T_1277.state <= UInt<1>("h00") T_1277.state <= UInt<1>("h00") reg new_coh_state : {state : UInt<2>}, clk, reset, T_1277 reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk, UInt<1>("h00"), req node req_idx = bits(req.addr, 11, 6) node T_1587 = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, T_1587) node T_1589 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1590 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1591 = or(T_1589, T_1590) node T_1592 = bit(io.req_bits.cmd, 3) node T_1593 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1594 = or(T_1592, T_1593) node T_1595 = or(T_1591, T_1594) node T_1596 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1597 = or(T_1595, T_1596) node T_1598 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1599 = or(T_1597, T_1598) node T_1600 = eq(req.cmd, UInt<5>("h01")) node T_1601 = eq(req.cmd, UInt<5>("h07")) node T_1602 = or(T_1600, T_1601) node T_1603 = bit(req.cmd, 3) node T_1604 = eq(req.cmd, UInt<5>("h04")) node T_1605 = or(T_1603, T_1604) node T_1606 = or(T_1602, T_1605) node T_1607 = eq(req.cmd, UInt<5>("h03")) node T_1608 = or(T_1606, T_1607) node T_1609 = eq(req.cmd, UInt<5>("h06")) node T_1610 = or(T_1608, T_1609) node T_1612 = eq(T_1610, UInt<1>("h00")) node cmd_requires_second_acquire = and(T_1599, T_1612) wire states_before_refill : UInt<2>[3] states_before_refill[0] <= UInt<1>("h01") states_before_refill[1] <= UInt<2>("h02") states_before_refill[2] <= UInt<2>("h03") node T_1620 = eq(states_before_refill[0], state) node T_1621 = eq(states_before_refill[1], state) node T_1622 = eq(states_before_refill[2], state) node T_1624 = or(UInt<1>("h00"), T_1620) node T_1625 = or(T_1624, T_1621) node T_1626 = or(T_1625, T_1622) wire T_1628 : UInt<3>[2] T_1628[0] <= UInt<3>("h04") T_1628[1] <= UInt<3>("h05") node T_1632 = eq(T_1628[0], state) node T_1633 = eq(T_1628[1], state) node T_1635 = or(UInt<1>("h00"), T_1632) node T_1636 = or(T_1635, T_1633) node T_1638 = eq(cmd_requires_second_acquire, UInt<1>("h00")) node T_1639 = and(T_1636, T_1638) node T_1640 = or(T_1626, T_1639) node sec_rdy = and(idx_match, T_1640) wire T_1645 : UInt<3>[1] T_1645[0] <= UInt<3>("h05") node T_1648 = eq(T_1645[0], io.mem_grant.bits.g_type) node T_1650 = or(UInt<1>("h00"), T_1648) wire T_1652 : UInt<1>[2] T_1652[0] <= UInt<1>("h00") T_1652[1] <= UInt<1>("h01") node T_1656 = eq(T_1652[0], io.mem_grant.bits.g_type) node T_1657 = eq(T_1652[1], io.mem_grant.bits.g_type) node T_1659 = or(UInt<1>("h00"), T_1656) node T_1660 = or(T_1659, T_1657) node T_1661 = mux(io.mem_grant.bits.is_builtin_type, T_1650, T_1660) node gnt_multi_data = and(UInt<1>("h01"), T_1661) node T_1663 = and(io.mem_grant.valid, gnt_multi_data) reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") when T_1663 : node T_1667 = eq(refill_cnt, UInt<2>("h03")) node T_1669 = and(UInt<1>("h00"), T_1667) node T_1672 = addw(refill_cnt, UInt<1>("h01")) node T_1673 = mux(T_1669, UInt<1>("h00"), T_1672) refill_cnt <= T_1673 skip node refill_count_done = and(T_1663, T_1667) node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) node T_1677 = or(T_1676, refill_count_done) node refill_done = and(io.mem_grant.valid, T_1677) inst rpq of Queue_98 rpq.io.deq.ready <= UInt<1>("h00") rpq.io.enq.bits.sdq_id <= UInt<1>("h00") rpq.io.enq.bits.phys <= UInt<1>("h00") rpq.io.enq.bits.kill <= UInt<1>("h00") rpq.io.enq.bits.typ <= UInt<1>("h00") rpq.io.enq.bits.cmd <= UInt<1>("h00") rpq.io.enq.bits.tag <= UInt<1>("h00") rpq.io.enq.bits.addr <= UInt<1>("h00") rpq.io.enq.valid <= UInt<1>("h00") rpq.clk <= clk rpq.reset <= reset node T_1743 = and(io.req_pri_val, io.req_pri_rdy) node T_1744 = and(io.req_sec_val, sec_rdy) node T_1745 = or(T_1743, T_1744) node T_1746 = eq(io.req_bits.cmd, UInt<5>("h02")) node T_1747 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1748 = or(T_1746, T_1747) node T_1750 = eq(T_1748, UInt<1>("h00")) node T_1751 = and(T_1745, T_1750) rpq.io.enq.valid <= T_1751 rpq.io.enq.bits <- io.req_bits node T_1752 = eq(state, UInt<4>("h08")) node T_1753 = and(io.replay.ready, T_1752) node T_1754 = eq(state, UInt<1>("h00")) node T_1755 = or(T_1753, T_1754) rpq.io.deq.ready <= T_1755 node T_1756 = eq(req.cmd, UInt<5>("h01")) node T_1757 = eq(req.cmd, UInt<5>("h07")) node T_1758 = or(T_1756, T_1757) node T_1759 = bit(req.cmd, 3) node T_1760 = eq(req.cmd, UInt<5>("h04")) node T_1761 = or(T_1759, T_1760) node T_1762 = or(T_1758, T_1761) node T_1763 = mux(T_1762, UInt<2>("h03"), UInt<2>("h02")) node T_1764 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) node T_1765 = mux(T_1764, UInt<2>("h03"), UInt<1>("h00")) node T_1766 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) node T_1767 = mux(T_1766, T_1763, T_1765) node T_1768 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) node T_1769 = mux(T_1768, UInt<1>("h01"), T_1767) node T_1770 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1769) wire coh_on_grant : {state : UInt<2>} coh_on_grant.state <= UInt<1>("h00") coh_on_grant.state <= T_1770 node T_1822 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1823 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1824 = or(T_1822, T_1823) node T_1825 = bit(io.req_bits.cmd, 3) node T_1826 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1827 = or(T_1825, T_1826) node T_1828 = or(T_1824, T_1827) node T_1829 = mux(T_1828, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} coh_on_hit.state <= UInt<1>("h00") coh_on_hit.state <= T_1829 node T_1881 = eq(state, UInt<4>("h08")) node T_1883 = eq(rpq.io.deq.valid, UInt<1>("h00")) node T_1884 = and(T_1881, T_1883) when T_1884 : state <= UInt<1>("h00") skip node T_1885 = eq(state, UInt<3>("h07")) when T_1885 : state <= UInt<4>("h08") skip node T_1886 = eq(state, UInt<3>("h06")) node T_1887 = and(T_1886, io.meta_write.ready) when T_1887 : state <= UInt<3>("h07") skip node T_1888 = eq(state, UInt<3>("h05")) when T_1888 : when io.mem_grant.valid : new_coh_state <- coh_on_grant skip when refill_done : state <= UInt<3>("h06") skip skip node T_1889 = and(io.mem_req.ready, io.mem_req.valid) when T_1889 : state <= UInt<3>("h05") skip node T_1890 = eq(state, UInt<2>("h03")) node T_1891 = and(T_1890, io.meta_write.ready) when T_1891 : state <= UInt<3>("h04") skip node T_1892 = eq(state, UInt<2>("h02")) node T_1893 = and(T_1892, io.mem_grant.valid) when T_1893 : state <= UInt<2>("h03") skip node T_1894 = and(io.wb_req.ready, io.wb_req.valid) when T_1894 : node T_1897 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1898 = mux(T_1897, UInt<2>("h02"), UInt<2>("h03")) state <= T_1898 skip node T_1899 = and(io.req_sec_val, io.req_sec_rdy) when T_1899 : when cmd_requires_second_acquire : req.cmd <= io.req_bits.cmd skip skip node T_1900 = and(io.req_pri_val, io.req_pri_rdy) when T_1900 : req <- io.req_bits when io.req_bits.tag_match : node T_1901 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1902 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1903 = or(T_1901, T_1902) node T_1904 = bit(io.req_bits.cmd, 3) node T_1905 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1906 = or(T_1904, T_1905) node T_1907 = or(T_1903, T_1906) node T_1908 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1909 = or(T_1907, T_1908) node T_1910 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1911 = or(T_1909, T_1910) wire T_1913 : UInt<2>[2] T_1913[0] <= UInt<2>("h02") T_1913[1] <= UInt<2>("h03") node T_1917 = eq(T_1913[0], io.req_bits.old_meta.coh.state) node T_1918 = eq(T_1913[1], io.req_bits.old_meta.coh.state) node T_1920 = or(UInt<1>("h00"), T_1917) node T_1921 = or(T_1920, T_1918) wire T_1923 : UInt<2>[3] T_1923[0] <= UInt<1>("h01") T_1923[1] <= UInt<2>("h02") T_1923[2] <= UInt<2>("h03") node T_1928 = eq(T_1923[0], io.req_bits.old_meta.coh.state) node T_1929 = eq(T_1923[1], io.req_bits.old_meta.coh.state) node T_1930 = eq(T_1923[2], io.req_bits.old_meta.coh.state) node T_1932 = or(UInt<1>("h00"), T_1928) node T_1933 = or(T_1932, T_1929) node T_1934 = or(T_1933, T_1930) node T_1935 = mux(T_1911, T_1921, T_1934) when T_1935 : state <= UInt<3>("h06") new_coh_state <- coh_on_hit skip node T_1937 = eq(T_1935, UInt<1>("h00")) when T_1937 : state <= UInt<3>("h04") skip skip node T_1939 = eq(io.req_bits.tag_match, UInt<1>("h00")) when T_1939 : wire T_1941 : UInt<2>[1] T_1941[0] <= UInt<2>("h03") node T_1944 = eq(T_1941[0], io.req_bits.old_meta.coh.state) node T_1946 = or(UInt<1>("h00"), T_1944) node T_1947 = mux(T_1946, UInt<1>("h01"), UInt<2>("h03")) state <= T_1947 skip skip node T_1948 = neq(state, UInt<1>("h00")) node T_1949 = and(T_1948, idx_match) io.idx_match <= T_1949 io.refill.way_en <= req.way_en node T_1950 = cat(req_idx, refill_cnt) node T_1951 = shl(T_1950, 4) io.refill.addr <= T_1951 node T_1952 = shr(req.addr, 12) io.tag <= T_1952 node T_1953 = eq(state, UInt<1>("h00")) io.req_pri_rdy <= T_1953 node T_1954 = and(sec_rdy, rpq.io.enq.ready) io.req_sec_rdy <= T_1954 reg meta_hazard : UInt<2>, clk, reset, UInt<2>("h00") node T_1958 = neq(meta_hazard, UInt<1>("h00")) when T_1958 : node T_1960 = addw(meta_hazard, UInt<1>("h01")) meta_hazard <= T_1960 skip node T_1961 = and(io.meta_write.ready, io.meta_write.valid) when T_1961 : meta_hazard <= UInt<1>("h01") skip node T_1964 = eq(idx_match, UInt<1>("h00")) node T_1965 = eq(states_before_refill[0], state) node T_1966 = eq(states_before_refill[1], state) node T_1967 = eq(states_before_refill[2], state) node T_1969 = or(UInt<1>("h00"), T_1965) node T_1970 = or(T_1969, T_1966) node T_1971 = or(T_1970, T_1967) node T_1973 = eq(T_1971, UInt<1>("h00")) node T_1975 = eq(meta_hazard, UInt<1>("h00")) node T_1976 = and(T_1973, T_1975) node T_1977 = or(T_1964, T_1976) io.probe_rdy <= T_1977 node T_1978 = eq(state, UInt<3>("h06")) node T_1979 = eq(state, UInt<2>("h03")) node T_1980 = or(T_1978, T_1979) io.meta_write.valid <= T_1980 io.meta_write.bits.idx <= req_idx node T_1981 = eq(state, UInt<2>("h03")) wire T_1983 : UInt<2>[2] T_1983[0] <= UInt<2>("h02") T_1983[1] <= UInt<2>("h03") node T_1987 = eq(T_1983[0], req.old_meta.coh.state) node T_1988 = eq(T_1983[1], req.old_meta.coh.state) node T_1990 = or(UInt<1>("h00"), T_1987) node T_1991 = or(T_1990, T_1988) node T_1992 = mux(T_1991, UInt<1>("h01"), req.old_meta.coh.state) node T_1993 = eq(req.old_meta.coh.state, UInt<2>("h03")) node T_1994 = mux(T_1993, UInt<2>("h02"), req.old_meta.coh.state) node T_1995 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1996 = mux(T_1995, T_1994, req.old_meta.coh.state) node T_1997 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1998 = mux(T_1997, T_1992, T_1996) node T_1999 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_2000 = mux(T_1999, UInt<1>("h00"), T_1998) wire T_2026 : {state : UInt<2>} T_2026.state <= UInt<1>("h00") T_2026.state <= T_2000 wire T_2077 : {state : UInt<2>} T_2077 <- new_coh_state when T_1981 : T_2077 <- T_2026 skip io.meta_write.bits.data.coh <- T_2077 io.meta_write.bits.data.tag <= io.tag io.meta_write.bits.way_en <= req.way_en node T_2102 = eq(state, UInt<1>("h01")) io.wb_req.valid <= T_2102 node T_2104 = cat(req.old_meta.tag, req_idx) wire T_2109 : UInt<2>[1] T_2109[0] <= UInt<2>("h03") node T_2112 = eq(T_2109[0], req.old_meta.coh.state) node T_2114 = or(UInt<1>("h00"), T_2112) node T_2115 = mux(T_2114, UInt<1>("h00"), UInt<2>("h03")) node T_2116 = mux(T_2114, UInt<1>("h01"), UInt<3>("h04")) node T_2117 = mux(T_2114, UInt<2>("h02"), UInt<3>("h05")) node T_2118 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_2119 = mux(T_2118, T_2117, UInt<3>("h05")) node T_2120 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_2121 = mux(T_2120, T_2116, T_2119) node T_2122 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_2123 = mux(T_2122, T_2115, T_2121) wire T_2154 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} T_2154.data <= UInt<1>("h00") T_2154.r_type <= UInt<1>("h00") T_2154.voluntary <= UInt<1>("h00") T_2154.client_xact_id <= UInt<1>("h00") T_2154.addr_block <= UInt<1>("h00") T_2154.addr_beat <= UInt<1>("h00") T_2154.r_type <= T_2123 T_2154.client_xact_id <= UInt<1>("h00") T_2154.addr_block <= T_2104 T_2154.addr_beat <= UInt<1>("h00") T_2154.data <= UInt<1>("h00") T_2154.voluntary <= UInt<1>("h01") io.wb_req.bits <- T_2154 io.wb_req.bits.way_en <= req.way_en node T_2190 = eq(state, UInt<3>("h04")) io.mem_req.valid <= T_2190 node T_2191 = cat(io.tag, req_idx) node T_2194 = eq(req.cmd, UInt<5>("h01")) node T_2195 = eq(req.cmd, UInt<5>("h07")) node T_2196 = or(T_2194, T_2195) node T_2197 = bit(req.cmd, 3) node T_2198 = eq(req.cmd, UInt<5>("h04")) node T_2199 = or(T_2197, T_2198) node T_2200 = or(T_2196, T_2199) node T_2201 = eq(req.cmd, UInt<5>("h03")) node T_2202 = or(T_2200, T_2201) node T_2203 = eq(req.cmd, UInt<5>("h06")) node T_2204 = or(T_2202, T_2203) node T_2205 = mux(T_2204, UInt<1>("h01"), UInt<1>("h00")) node T_2207 = cat(req.cmd, UInt<1>("h01")) wire T_2241 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_2241.data <= UInt<1>("h00") T_2241.union <= UInt<1>("h00") T_2241.a_type <= UInt<1>("h00") T_2241.is_builtin_type <= UInt<1>("h00") T_2241.addr_beat <= UInt<1>("h00") T_2241.client_xact_id <= UInt<1>("h00") T_2241.addr_block <= UInt<1>("h00") T_2241.is_builtin_type <= UInt<1>("h00") T_2241.a_type <= T_2205 T_2241.client_xact_id <= UInt<1>("h00") T_2241.addr_block <= T_2191 T_2241.addr_beat <= UInt<1>("h00") T_2241.data <= UInt<1>("h00") T_2241.union <= T_2207 io.mem_req.bits <- T_2241 node T_2279 = eq(state, UInt<4>("h08")) io.meta_read.valid <= T_2279 io.meta_read.bits.idx <= req_idx io.meta_read.bits.tag <= io.tag node T_2280 = eq(state, UInt<4>("h08")) node T_2281 = and(T_2280, rpq.io.deq.valid) io.replay.valid <= T_2281 io.replay.bits <- rpq.io.deq.bits io.replay.bits.phys <= UInt<1>("h01") node T_2283 = bits(rpq.io.deq.bits.addr, 5, 0) node T_2284 = cat(req_idx, T_2283) node T_2285 = cat(io.tag, T_2284) io.replay.bits.addr <= T_2285 node T_2287 = eq(io.meta_read.ready, UInt<1>("h00")) when T_2287 : rpq.io.deq.ready <= UInt<1>("h00") io.replay.bits.cmd <= UInt<5>("h05") skip module MSHR_99 : input clk : Clock input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} io.probe_rdy <= UInt<1>("h00") io.wb_req.bits.way_en <= UInt<1>("h00") io.wb_req.bits.data <= UInt<1>("h00") io.wb_req.bits.r_type <= UInt<1>("h00") io.wb_req.bits.voluntary <= UInt<1>("h00") io.wb_req.bits.client_xact_id <= UInt<1>("h00") io.wb_req.bits.addr_block <= UInt<1>("h00") io.wb_req.bits.addr_beat <= UInt<1>("h00") io.wb_req.valid <= UInt<1>("h00") io.replay.bits.sdq_id <= UInt<1>("h00") io.replay.bits.phys <= UInt<1>("h00") io.replay.bits.kill <= UInt<1>("h00") io.replay.bits.typ <= UInt<1>("h00") io.replay.bits.cmd <= UInt<1>("h00") io.replay.bits.tag <= UInt<1>("h00") io.replay.bits.addr <= UInt<1>("h00") io.replay.valid <= UInt<1>("h00") io.meta_write.bits.data.coh.state <= UInt<1>("h00") io.meta_write.bits.data.tag <= UInt<1>("h00") io.meta_write.bits.way_en <= UInt<1>("h00") io.meta_write.bits.idx <= UInt<1>("h00") io.meta_write.valid <= UInt<1>("h00") io.meta_read.bits.tag <= UInt<1>("h00") io.meta_read.bits.idx <= UInt<1>("h00") io.meta_read.valid <= UInt<1>("h00") io.refill.addr <= UInt<1>("h00") io.refill.way_en <= UInt<1>("h00") io.mem_req.bits.data <= UInt<1>("h00") io.mem_req.bits.union <= UInt<1>("h00") io.mem_req.bits.a_type <= UInt<1>("h00") io.mem_req.bits.is_builtin_type <= UInt<1>("h00") io.mem_req.bits.addr_beat <= UInt<1>("h00") io.mem_req.bits.client_xact_id <= UInt<1>("h00") io.mem_req.bits.addr_block <= UInt<1>("h00") io.mem_req.valid <= UInt<1>("h00") io.tag <= UInt<1>("h00") io.idx_match <= UInt<1>("h00") io.req_sec_rdy <= UInt<1>("h00") io.req_pri_rdy <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") wire T_1277 : {state : UInt<2>} T_1277.state <= UInt<1>("h00") T_1277.state <= UInt<1>("h00") reg new_coh_state : {state : UInt<2>}, clk, reset, T_1277 reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk, UInt<1>("h00"), req node req_idx = bits(req.addr, 11, 6) node T_1587 = bits(io.req_bits.addr, 11, 6) node idx_match = eq(req_idx, T_1587) node T_1589 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1590 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1591 = or(T_1589, T_1590) node T_1592 = bit(io.req_bits.cmd, 3) node T_1593 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1594 = or(T_1592, T_1593) node T_1595 = or(T_1591, T_1594) node T_1596 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1597 = or(T_1595, T_1596) node T_1598 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1599 = or(T_1597, T_1598) node T_1600 = eq(req.cmd, UInt<5>("h01")) node T_1601 = eq(req.cmd, UInt<5>("h07")) node T_1602 = or(T_1600, T_1601) node T_1603 = bit(req.cmd, 3) node T_1604 = eq(req.cmd, UInt<5>("h04")) node T_1605 = or(T_1603, T_1604) node T_1606 = or(T_1602, T_1605) node T_1607 = eq(req.cmd, UInt<5>("h03")) node T_1608 = or(T_1606, T_1607) node T_1609 = eq(req.cmd, UInt<5>("h06")) node T_1610 = or(T_1608, T_1609) node T_1612 = eq(T_1610, UInt<1>("h00")) node cmd_requires_second_acquire = and(T_1599, T_1612) wire states_before_refill : UInt<2>[3] states_before_refill[0] <= UInt<1>("h01") states_before_refill[1] <= UInt<2>("h02") states_before_refill[2] <= UInt<2>("h03") node T_1620 = eq(states_before_refill[0], state) node T_1621 = eq(states_before_refill[1], state) node T_1622 = eq(states_before_refill[2], state) node T_1624 = or(UInt<1>("h00"), T_1620) node T_1625 = or(T_1624, T_1621) node T_1626 = or(T_1625, T_1622) wire T_1628 : UInt<3>[2] T_1628[0] <= UInt<3>("h04") T_1628[1] <= UInt<3>("h05") node T_1632 = eq(T_1628[0], state) node T_1633 = eq(T_1628[1], state) node T_1635 = or(UInt<1>("h00"), T_1632) node T_1636 = or(T_1635, T_1633) node T_1638 = eq(cmd_requires_second_acquire, UInt<1>("h00")) node T_1639 = and(T_1636, T_1638) node T_1640 = or(T_1626, T_1639) node sec_rdy = and(idx_match, T_1640) wire T_1645 : UInt<3>[1] T_1645[0] <= UInt<3>("h05") node T_1648 = eq(T_1645[0], io.mem_grant.bits.g_type) node T_1650 = or(UInt<1>("h00"), T_1648) wire T_1652 : UInt<1>[2] T_1652[0] <= UInt<1>("h00") T_1652[1] <= UInt<1>("h01") node T_1656 = eq(T_1652[0], io.mem_grant.bits.g_type) node T_1657 = eq(T_1652[1], io.mem_grant.bits.g_type) node T_1659 = or(UInt<1>("h00"), T_1656) node T_1660 = or(T_1659, T_1657) node T_1661 = mux(io.mem_grant.bits.is_builtin_type, T_1650, T_1660) node gnt_multi_data = and(UInt<1>("h01"), T_1661) node T_1663 = and(io.mem_grant.valid, gnt_multi_data) reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") when T_1663 : node T_1667 = eq(refill_cnt, UInt<2>("h03")) node T_1669 = and(UInt<1>("h00"), T_1667) node T_1672 = addw(refill_cnt, UInt<1>("h01")) node T_1673 = mux(T_1669, UInt<1>("h00"), T_1672) refill_cnt <= T_1673 skip node refill_count_done = and(T_1663, T_1667) node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) node T_1677 = or(T_1676, refill_count_done) node refill_done = and(io.mem_grant.valid, T_1677) inst rpq of Queue_98 rpq.io.deq.ready <= UInt<1>("h00") rpq.io.enq.bits.sdq_id <= UInt<1>("h00") rpq.io.enq.bits.phys <= UInt<1>("h00") rpq.io.enq.bits.kill <= UInt<1>("h00") rpq.io.enq.bits.typ <= UInt<1>("h00") rpq.io.enq.bits.cmd <= UInt<1>("h00") rpq.io.enq.bits.tag <= UInt<1>("h00") rpq.io.enq.bits.addr <= UInt<1>("h00") rpq.io.enq.valid <= UInt<1>("h00") rpq.clk <= clk rpq.reset <= reset node T_1743 = and(io.req_pri_val, io.req_pri_rdy) node T_1744 = and(io.req_sec_val, sec_rdy) node T_1745 = or(T_1743, T_1744) node T_1746 = eq(io.req_bits.cmd, UInt<5>("h02")) node T_1747 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1748 = or(T_1746, T_1747) node T_1750 = eq(T_1748, UInt<1>("h00")) node T_1751 = and(T_1745, T_1750) rpq.io.enq.valid <= T_1751 rpq.io.enq.bits <- io.req_bits node T_1752 = eq(state, UInt<4>("h08")) node T_1753 = and(io.replay.ready, T_1752) node T_1754 = eq(state, UInt<1>("h00")) node T_1755 = or(T_1753, T_1754) rpq.io.deq.ready <= T_1755 node T_1756 = eq(req.cmd, UInt<5>("h01")) node T_1757 = eq(req.cmd, UInt<5>("h07")) node T_1758 = or(T_1756, T_1757) node T_1759 = bit(req.cmd, 3) node T_1760 = eq(req.cmd, UInt<5>("h04")) node T_1761 = or(T_1759, T_1760) node T_1762 = or(T_1758, T_1761) node T_1763 = mux(T_1762, UInt<2>("h03"), UInt<2>("h02")) node T_1764 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) node T_1765 = mux(T_1764, UInt<2>("h03"), UInt<1>("h00")) node T_1766 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) node T_1767 = mux(T_1766, T_1763, T_1765) node T_1768 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) node T_1769 = mux(T_1768, UInt<1>("h01"), T_1767) node T_1770 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1769) wire coh_on_grant : {state : UInt<2>} coh_on_grant.state <= UInt<1>("h00") coh_on_grant.state <= T_1770 node T_1822 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1823 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1824 = or(T_1822, T_1823) node T_1825 = bit(io.req_bits.cmd, 3) node T_1826 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1827 = or(T_1825, T_1826) node T_1828 = or(T_1824, T_1827) node T_1829 = mux(T_1828, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} coh_on_hit.state <= UInt<1>("h00") coh_on_hit.state <= T_1829 node T_1881 = eq(state, UInt<4>("h08")) node T_1883 = eq(rpq.io.deq.valid, UInt<1>("h00")) node T_1884 = and(T_1881, T_1883) when T_1884 : state <= UInt<1>("h00") skip node T_1885 = eq(state, UInt<3>("h07")) when T_1885 : state <= UInt<4>("h08") skip node T_1886 = eq(state, UInt<3>("h06")) node T_1887 = and(T_1886, io.meta_write.ready) when T_1887 : state <= UInt<3>("h07") skip node T_1888 = eq(state, UInt<3>("h05")) when T_1888 : when io.mem_grant.valid : new_coh_state <- coh_on_grant skip when refill_done : state <= UInt<3>("h06") skip skip node T_1889 = and(io.mem_req.ready, io.mem_req.valid) when T_1889 : state <= UInt<3>("h05") skip node T_1890 = eq(state, UInt<2>("h03")) node T_1891 = and(T_1890, io.meta_write.ready) when T_1891 : state <= UInt<3>("h04") skip node T_1892 = eq(state, UInt<2>("h02")) node T_1893 = and(T_1892, io.mem_grant.valid) when T_1893 : state <= UInt<2>("h03") skip node T_1894 = and(io.wb_req.ready, io.wb_req.valid) when T_1894 : node T_1897 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1898 = mux(T_1897, UInt<2>("h02"), UInt<2>("h03")) state <= T_1898 skip node T_1899 = and(io.req_sec_val, io.req_sec_rdy) when T_1899 : when cmd_requires_second_acquire : req.cmd <= io.req_bits.cmd skip skip node T_1900 = and(io.req_pri_val, io.req_pri_rdy) when T_1900 : req <- io.req_bits when io.req_bits.tag_match : node T_1901 = eq(io.req_bits.cmd, UInt<5>("h01")) node T_1902 = eq(io.req_bits.cmd, UInt<5>("h07")) node T_1903 = or(T_1901, T_1902) node T_1904 = bit(io.req_bits.cmd, 3) node T_1905 = eq(io.req_bits.cmd, UInt<5>("h04")) node T_1906 = or(T_1904, T_1905) node T_1907 = or(T_1903, T_1906) node T_1908 = eq(io.req_bits.cmd, UInt<5>("h03")) node T_1909 = or(T_1907, T_1908) node T_1910 = eq(io.req_bits.cmd, UInt<5>("h06")) node T_1911 = or(T_1909, T_1910) wire T_1913 : UInt<2>[2] T_1913[0] <= UInt<2>("h02") T_1913[1] <= UInt<2>("h03") node T_1917 = eq(T_1913[0], io.req_bits.old_meta.coh.state) node T_1918 = eq(T_1913[1], io.req_bits.old_meta.coh.state) node T_1920 = or(UInt<1>("h00"), T_1917) node T_1921 = or(T_1920, T_1918) wire T_1923 : UInt<2>[3] T_1923[0] <= UInt<1>("h01") T_1923[1] <= UInt<2>("h02") T_1923[2] <= UInt<2>("h03") node T_1928 = eq(T_1923[0], io.req_bits.old_meta.coh.state) node T_1929 = eq(T_1923[1], io.req_bits.old_meta.coh.state) node T_1930 = eq(T_1923[2], io.req_bits.old_meta.coh.state) node T_1932 = or(UInt<1>("h00"), T_1928) node T_1933 = or(T_1932, T_1929) node T_1934 = or(T_1933, T_1930) node T_1935 = mux(T_1911, T_1921, T_1934) when T_1935 : state <= UInt<3>("h06") new_coh_state <- coh_on_hit skip node T_1937 = eq(T_1935, UInt<1>("h00")) when T_1937 : state <= UInt<3>("h04") skip skip node T_1939 = eq(io.req_bits.tag_match, UInt<1>("h00")) when T_1939 : wire T_1941 : UInt<2>[1] T_1941[0] <= UInt<2>("h03") node T_1944 = eq(T_1941[0], io.req_bits.old_meta.coh.state) node T_1946 = or(UInt<1>("h00"), T_1944) node T_1947 = mux(T_1946, UInt<1>("h01"), UInt<2>("h03")) state <= T_1947 skip skip node T_1948 = neq(state, UInt<1>("h00")) node T_1949 = and(T_1948, idx_match) io.idx_match <= T_1949 io.refill.way_en <= req.way_en node T_1950 = cat(req_idx, refill_cnt) node T_1951 = shl(T_1950, 4) io.refill.addr <= T_1951 node T_1952 = shr(req.addr, 12) io.tag <= T_1952 node T_1953 = eq(state, UInt<1>("h00")) io.req_pri_rdy <= T_1953 node T_1954 = and(sec_rdy, rpq.io.enq.ready) io.req_sec_rdy <= T_1954 reg meta_hazard : UInt<2>, clk, reset, UInt<2>("h00") node T_1958 = neq(meta_hazard, UInt<1>("h00")) when T_1958 : node T_1960 = addw(meta_hazard, UInt<1>("h01")) meta_hazard <= T_1960 skip node T_1961 = and(io.meta_write.ready, io.meta_write.valid) when T_1961 : meta_hazard <= UInt<1>("h01") skip node T_1964 = eq(idx_match, UInt<1>("h00")) node T_1965 = eq(states_before_refill[0], state) node T_1966 = eq(states_before_refill[1], state) node T_1967 = eq(states_before_refill[2], state) node T_1969 = or(UInt<1>("h00"), T_1965) node T_1970 = or(T_1969, T_1966) node T_1971 = or(T_1970, T_1967) node T_1973 = eq(T_1971, UInt<1>("h00")) node T_1975 = eq(meta_hazard, UInt<1>("h00")) node T_1976 = and(T_1973, T_1975) node T_1977 = or(T_1964, T_1976) io.probe_rdy <= T_1977 node T_1978 = eq(state, UInt<3>("h06")) node T_1979 = eq(state, UInt<2>("h03")) node T_1980 = or(T_1978, T_1979) io.meta_write.valid <= T_1980 io.meta_write.bits.idx <= req_idx node T_1981 = eq(state, UInt<2>("h03")) wire T_1983 : UInt<2>[2] T_1983[0] <= UInt<2>("h02") T_1983[1] <= UInt<2>("h03") node T_1987 = eq(T_1983[0], req.old_meta.coh.state) node T_1988 = eq(T_1983[1], req.old_meta.coh.state) node T_1990 = or(UInt<1>("h00"), T_1987) node T_1991 = or(T_1990, T_1988) node T_1992 = mux(T_1991, UInt<1>("h01"), req.old_meta.coh.state) node T_1993 = eq(req.old_meta.coh.state, UInt<2>("h03")) node T_1994 = mux(T_1993, UInt<2>("h02"), req.old_meta.coh.state) node T_1995 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_1996 = mux(T_1995, T_1994, req.old_meta.coh.state) node T_1997 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_1998 = mux(T_1997, T_1992, T_1996) node T_1999 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_2000 = mux(T_1999, UInt<1>("h00"), T_1998) wire T_2026 : {state : UInt<2>} T_2026.state <= UInt<1>("h00") T_2026.state <= T_2000 wire T_2077 : {state : UInt<2>} T_2077 <- new_coh_state when T_1981 : T_2077 <- T_2026 skip io.meta_write.bits.data.coh <- T_2077 io.meta_write.bits.data.tag <= io.tag io.meta_write.bits.way_en <= req.way_en node T_2102 = eq(state, UInt<1>("h01")) io.wb_req.valid <= T_2102 node T_2104 = cat(req.old_meta.tag, req_idx) wire T_2109 : UInt<2>[1] T_2109[0] <= UInt<2>("h03") node T_2112 = eq(T_2109[0], req.old_meta.coh.state) node T_2114 = or(UInt<1>("h00"), T_2112) node T_2115 = mux(T_2114, UInt<1>("h00"), UInt<2>("h03")) node T_2116 = mux(T_2114, UInt<1>("h01"), UInt<3>("h04")) node T_2117 = mux(T_2114, UInt<2>("h02"), UInt<3>("h05")) node T_2118 = eq(UInt<5>("h013"), UInt<5>("h010")) node T_2119 = mux(T_2118, T_2117, UInt<3>("h05")) node T_2120 = eq(UInt<5>("h011"), UInt<5>("h010")) node T_2121 = mux(T_2120, T_2116, T_2119) node T_2122 = eq(UInt<5>("h010"), UInt<5>("h010")) node T_2123 = mux(T_2122, T_2115, T_2121) wire T_2154 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} T_2154.data <= UInt<1>("h00") T_2154.r_type <= UInt<1>("h00") T_2154.voluntary <= UInt<1>("h00") T_2154.client_xact_id <= UInt<1>("h00") T_2154.addr_block <= UInt<1>("h00") T_2154.addr_beat <= UInt<1>("h00") T_2154.r_type <= T_2123 T_2154.client_xact_id <= UInt<1>("h01") T_2154.addr_block <= T_2104 T_2154.addr_beat <= UInt<1>("h00") T_2154.data <= UInt<1>("h00") T_2154.voluntary <= UInt<1>("h01") io.wb_req.bits <- T_2154 io.wb_req.bits.way_en <= req.way_en node T_2190 = eq(state, UInt<3>("h04")) io.mem_req.valid <= T_2190 node T_2191 = cat(io.tag, req_idx) node T_2194 = eq(req.cmd, UInt<5>("h01")) node T_2195 = eq(req.cmd, UInt<5>("h07")) node T_2196 = or(T_2194, T_2195) node T_2197 = bit(req.cmd, 3) node T_2198 = eq(req.cmd, UInt<5>("h04")) node T_2199 = or(T_2197, T_2198) node T_2200 = or(T_2196, T_2199) node T_2201 = eq(req.cmd, UInt<5>("h03")) node T_2202 = or(T_2200, T_2201) node T_2203 = eq(req.cmd, UInt<5>("h06")) node T_2204 = or(T_2202, T_2203) node T_2205 = mux(T_2204, UInt<1>("h01"), UInt<1>("h00")) node T_2207 = cat(req.cmd, UInt<1>("h01")) wire T_2241 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_2241.data <= UInt<1>("h00") T_2241.union <= UInt<1>("h00") T_2241.a_type <= UInt<1>("h00") T_2241.is_builtin_type <= UInt<1>("h00") T_2241.addr_beat <= UInt<1>("h00") T_2241.client_xact_id <= UInt<1>("h00") T_2241.addr_block <= UInt<1>("h00") T_2241.is_builtin_type <= UInt<1>("h00") T_2241.a_type <= T_2205 T_2241.client_xact_id <= UInt<1>("h01") T_2241.addr_block <= T_2191 T_2241.addr_beat <= UInt<1>("h00") T_2241.data <= UInt<1>("h00") T_2241.union <= T_2207 io.mem_req.bits <- T_2241 node T_2279 = eq(state, UInt<4>("h08")) io.meta_read.valid <= T_2279 io.meta_read.bits.idx <= req_idx io.meta_read.bits.tag <= io.tag node T_2280 = eq(state, UInt<4>("h08")) node T_2281 = and(T_2280, rpq.io.deq.valid) io.replay.valid <= T_2281 io.replay.bits <- rpq.io.deq.bits io.replay.bits.phys <= UInt<1>("h01") node T_2283 = bits(rpq.io.deq.bits.addr, 5, 0) node T_2284 = cat(req_idx, T_2283) node T_2285 = cat(io.tag, T_2284) io.replay.bits.addr <= T_2285 node T_2287 = eq(io.meta_read.ready, UInt<1>("h00")) when T_2287 : rpq.io.deq.ready <= UInt<1>("h00") io.replay.bits.cmd <= UInt<5>("h05") skip module Arbiter_101 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") wire T_54 : UInt<1> T_54 <= UInt<1>("h00") io.out.valid <= io.in[T_54].valid io.out.bits <= io.in[T_54].bits io.chosen <= T_54 io.in[T_54].ready <= UInt<1>("h00") node T_74 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_75 = mux(UInt<1>("h00"), T_74, UInt<1>("h01")) node T_76 = and(T_75, io.out.ready) io.in[0].ready <= T_76 node T_78 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) T_54 <= T_78 module Arbiter_102 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.store_data <= UInt<1>("h00") io.out.bits.data_word_bypass <= UInt<1>("h00") io.out.bits.has_data <= UInt<1>("h00") io.out.bits.replay <= UInt<1>("h00") io.out.bits.nack <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.typ <= UInt<1>("h00") io.out.bits.cmd <= UInt<1>("h00") io.out.bits.tag <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") wire T_1062 : UInt<1> T_1062 <= UInt<1>("h00") io.out.valid <= io.in[T_1062].valid io.out.bits <- io.in[T_1062].bits io.chosen <= T_1062 io.in[T_1062].ready <= UInt<1>("h00") node T_1418 = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1419 = mux(UInt<1>("h00"), T_1418, UInt<1>("h01")) node T_1420 = and(T_1419, io.out.ready) io.in[0].ready <= T_1420 node T_1422 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) T_1062 <= T_1422 module IOMSHR : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}} io.resp.bits.store_data <= UInt<1>("h00") io.resp.bits.data_word_bypass <= UInt<1>("h00") io.resp.bits.has_data <= UInt<1>("h00") io.resp.bits.replay <= UInt<1>("h00") io.resp.bits.nack <= UInt<1>("h00") io.resp.bits.data <= UInt<1>("h00") io.resp.bits.typ <= UInt<1>("h00") io.resp.bits.cmd <= UInt<1>("h00") io.resp.bits.tag <= UInt<1>("h00") io.resp.bits.addr <= UInt<1>("h00") io.resp.valid <= UInt<1>("h00") io.acquire.bits.data <= UInt<1>("h00") io.acquire.bits.union <= UInt<1>("h00") io.acquire.bits.a_type <= UInt<1>("h00") io.acquire.bits.is_builtin_type <= UInt<1>("h00") io.acquire.bits.addr_beat <= UInt<1>("h00") io.acquire.bits.client_xact_id <= UInt<1>("h00") io.acquire.bits.addr_block <= UInt<1>("h00") io.acquire.valid <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), req node req_cmd_sc = eq(req.cmd, UInt<5>("h07")) reg grant_word : UInt<64>, clk, UInt<1>("h00"), grant_word node T_861 = bits(req.typ, 1, 0) node T_862 = bits(req.typ, 1, 0) node T_863 = asSInt(req.typ) node T_865 = geq(T_863, asSInt(UInt<1>("h00"))) node beat_offset = bits(req.addr, 3, 3) node T_868 = bit(req.addr, 0) node T_870 = mux(T_868, UInt<1>("h01"), UInt<1>("h00")) node T_872 = geq(T_861, UInt<1>("h01")) node T_875 = mux(T_872, UInt<1>("h01"), UInt<1>("h00")) node T_876 = or(T_870, T_875) node T_877 = bit(req.addr, 0) node T_879 = mux(T_877, UInt<1>("h00"), UInt<1>("h01")) node T_880 = cat(T_876, T_879) node T_881 = bit(req.addr, 1) node T_883 = mux(T_881, T_880, UInt<1>("h00")) node T_885 = geq(T_861, UInt<2>("h02")) node T_888 = mux(T_885, UInt<2>("h03"), UInt<1>("h00")) node T_889 = or(T_883, T_888) node T_890 = bit(req.addr, 1) node T_892 = mux(T_890, UInt<1>("h00"), T_880) node T_893 = cat(T_889, T_892) node T_894 = bit(req.addr, 2) node T_896 = mux(T_894, T_893, UInt<1>("h00")) node T_898 = geq(T_861, UInt<2>("h03")) node T_901 = mux(T_898, UInt<4>("h0f"), UInt<1>("h00")) node T_902 = or(T_896, T_901) node T_903 = bit(req.addr, 2) node T_905 = mux(T_903, UInt<1>("h00"), T_893) node T_906 = cat(T_902, T_905) node T_908 = cat(beat_offset, UInt<3>("h00")) node beat_mask = dshl(T_906, T_908) node T_911 = eq(T_861, UInt<1>("h00")) node T_912 = bits(req.data, 7, 0) node T_913 = cat(T_912, T_912) node T_914 = cat(T_913, T_913) node T_915 = cat(T_914, T_914) node T_917 = eq(T_861, UInt<1>("h01")) node T_918 = bits(req.data, 15, 0) node T_919 = cat(T_918, T_918) node T_920 = cat(T_919, T_919) node T_922 = eq(T_861, UInt<2>("h02")) node T_923 = bits(req.data, 31, 0) node T_924 = cat(T_923, T_923) node T_925 = mux(T_922, T_924, req.data) node T_926 = mux(T_917, T_920, T_925) node T_927 = mux(T_911, T_915, T_926) node beat_data = cat(T_927, T_927) reg state : UInt, clk, reset, UInt<1>("h00") node T_935 = eq(state, UInt<1>("h00")) io.req.ready <= T_935 node addr_block = bits(req.addr, 31, 6) node addr_beat = bits(req.addr, 5, 4) node addr_byte = bits(req.addr, 3, 0) node T_947 = cat(addr_byte, req.typ) node T_948 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_949 = cat(T_947, T_948) node T_951 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_952 = cat(req.typ, T_951) node T_954 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_956 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_958 = cat(addr_byte, req.typ) node T_959 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_960 = cat(T_958, T_959) node T_962 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_964 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_965 = eq(UInt<3>("h06"), UInt<3>("h00")) node T_966 = mux(T_965, T_964, UInt<1>("h00")) node T_967 = eq(UInt<3>("h05"), UInt<3>("h00")) node T_968 = mux(T_967, T_962, T_966) node T_969 = eq(UInt<3>("h04"), UInt<3>("h00")) node T_970 = mux(T_969, T_960, T_968) node T_971 = eq(UInt<3>("h03"), UInt<3>("h00")) node T_972 = mux(T_971, T_956, T_970) node T_973 = eq(UInt<3>("h02"), UInt<3>("h00")) node T_974 = mux(T_973, T_954, T_972) node T_975 = eq(UInt<3>("h01"), UInt<3>("h00")) node T_976 = mux(T_975, T_952, T_974) node T_977 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_978 = mux(T_977, T_949, T_976) wire get_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} get_acquire.data <= UInt<1>("h00") get_acquire.union <= UInt<1>("h00") get_acquire.a_type <= UInt<1>("h00") get_acquire.is_builtin_type <= UInt<1>("h00") get_acquire.addr_beat <= UInt<1>("h00") get_acquire.client_xact_id <= UInt<1>("h00") get_acquire.addr_block <= UInt<1>("h00") get_acquire.is_builtin_type <= UInt<1>("h01") get_acquire.a_type <= UInt<3>("h00") get_acquire.client_xact_id <= UInt<2>("h02") get_acquire.addr_block <= addr_block get_acquire.addr_beat <= addr_beat get_acquire.data <= UInt<1>("h00") get_acquire.union <= T_978 node T_1056 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1057 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_1058 = cat(T_1056, T_1057) node T_1060 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_1061 = cat(UInt<3>("h07"), T_1060) node T_1063 = cat(beat_mask, UInt<1>("h00")) node T_1065 = cat(beat_mask, UInt<1>("h00")) node T_1067 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_1068 = cat(UInt<1>("h00"), UInt<1>("h00")) node T_1069 = cat(T_1067, T_1068) node T_1071 = cat(UInt<5>("h00"), UInt<1>("h00")) node T_1073 = cat(UInt<5>("h01"), UInt<1>("h00")) node T_1074 = eq(UInt<3>("h06"), UInt<3>("h02")) node T_1075 = mux(T_1074, T_1073, UInt<1>("h00")) node T_1076 = eq(UInt<3>("h05"), UInt<3>("h02")) node T_1077 = mux(T_1076, T_1071, T_1075) node T_1078 = eq(UInt<3>("h04"), UInt<3>("h02")) node T_1079 = mux(T_1078, T_1069, T_1077) node T_1080 = eq(UInt<3>("h03"), UInt<3>("h02")) node T_1081 = mux(T_1080, T_1065, T_1079) node T_1082 = eq(UInt<3>("h02"), UInt<3>("h02")) node T_1083 = mux(T_1082, T_1063, T_1081) node T_1084 = eq(UInt<3>("h01"), UInt<3>("h02")) node T_1085 = mux(T_1084, T_1061, T_1083) node T_1086 = eq(UInt<3>("h00"), UInt<3>("h02")) node T_1087 = mux(T_1086, T_1058, T_1085) wire put_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} put_acquire.data <= UInt<1>("h00") put_acquire.union <= UInt<1>("h00") put_acquire.a_type <= UInt<1>("h00") put_acquire.is_builtin_type <= UInt<1>("h00") put_acquire.addr_beat <= UInt<1>("h00") put_acquire.client_xact_id <= UInt<1>("h00") put_acquire.addr_block <= UInt<1>("h00") put_acquire.is_builtin_type <= UInt<1>("h01") put_acquire.a_type <= UInt<3>("h02") put_acquire.client_xact_id <= UInt<2>("h02") put_acquire.addr_block <= addr_block put_acquire.addr_beat <= addr_beat put_acquire.data <= beat_data put_acquire.union <= T_1087 node T_1157 = eq(state, UInt<1>("h01")) io.acquire.valid <= T_1157 node T_1158 = eq(req.cmd, UInt<5>("h00")) node T_1159 = eq(req.cmd, UInt<5>("h06")) node T_1160 = or(T_1158, T_1159) node T_1161 = eq(req.cmd, UInt<5>("h07")) node T_1162 = or(T_1160, T_1161) node T_1163 = bit(req.cmd, 3) node T_1164 = eq(req.cmd, UInt<5>("h04")) node T_1165 = or(T_1163, T_1164) node T_1166 = or(T_1162, T_1165) wire T_1198 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} T_1198 <- put_acquire when T_1166 : T_1198 <- get_acquire skip io.acquire.bits <- T_1198 node T_1229 = eq(state, UInt<2>("h03")) io.resp.valid <= T_1229 io.resp.bits <- req node T_1230 = eq(req.cmd, UInt<5>("h00")) node T_1231 = eq(req.cmd, UInt<5>("h06")) node T_1232 = or(T_1230, T_1231) node T_1233 = eq(req.cmd, UInt<5>("h07")) node T_1234 = or(T_1232, T_1233) node T_1235 = bit(req.cmd, 3) node T_1236 = eq(req.cmd, UInt<5>("h04")) node T_1237 = or(T_1235, T_1236) node T_1238 = or(T_1234, T_1237) io.resp.bits.has_data <= T_1238 node T_1239 = bit(req.addr, 2) node T_1240 = bits(grant_word, 63, 32) node T_1241 = bits(grant_word, 31, 0) node T_1242 = mux(T_1239, T_1240, T_1241) node T_1244 = and(UInt<1>("h00"), req_cmd_sc) node T_1246 = mux(T_1244, UInt<1>("h00"), T_1242) node T_1248 = eq(T_862, UInt<2>("h02")) node T_1249 = or(T_1248, T_1244) node T_1250 = bit(T_1246, 31) node T_1251 = and(T_865, T_1250) node T_1253 = subw(UInt<32>("h00"), T_1251) node T_1254 = bits(grant_word, 63, 32) node T_1255 = mux(T_1249, T_1253, T_1254) node T_1256 = cat(T_1255, T_1246) node T_1257 = bit(req.addr, 1) node T_1258 = bits(T_1256, 31, 16) node T_1259 = bits(T_1256, 15, 0) node T_1260 = mux(T_1257, T_1258, T_1259) node T_1262 = and(UInt<1>("h00"), req_cmd_sc) node T_1264 = mux(T_1262, UInt<1>("h00"), T_1260) node T_1266 = eq(T_862, UInt<1>("h01")) node T_1267 = or(T_1266, T_1262) node T_1268 = bit(T_1264, 15) node T_1269 = and(T_865, T_1268) node T_1271 = subw(UInt<48>("h00"), T_1269) node T_1272 = bits(T_1256, 63, 16) node T_1273 = mux(T_1267, T_1271, T_1272) node T_1274 = cat(T_1273, T_1264) node T_1275 = bit(req.addr, 0) node T_1276 = bits(T_1274, 15, 8) node T_1277 = bits(T_1274, 7, 0) node T_1278 = mux(T_1275, T_1276, T_1277) node T_1280 = and(UInt<1>("h01"), req_cmd_sc) node T_1282 = mux(T_1280, UInt<1>("h00"), T_1278) node T_1284 = eq(T_862, UInt<1>("h00")) node T_1285 = or(T_1284, T_1280) node T_1286 = bit(T_1282, 7) node T_1287 = and(T_865, T_1286) node T_1289 = subw(UInt<56>("h00"), T_1287) node T_1290 = bits(T_1274, 63, 8) node T_1291 = mux(T_1285, T_1289, T_1290) node T_1292 = cat(T_1291, T_1282) node T_1293 = or(T_1292, req_cmd_sc) io.resp.bits.data <= T_1293 io.resp.bits.store_data <= req.data io.resp.bits.nack <= UInt<1>("h00") io.resp.bits.replay <= io.resp.valid node T_1295 = and(io.req.ready, io.req.valid) when T_1295 : req <- io.req.bits state <= UInt<1>("h01") skip node T_1296 = and(io.acquire.ready, io.acquire.valid) when T_1296 : state <= UInt<2>("h02") skip node T_1297 = eq(state, UInt<2>("h02")) node T_1298 = and(T_1297, io.grant.valid) when T_1298 : node T_1299 = eq(req.cmd, UInt<5>("h00")) node T_1300 = eq(req.cmd, UInt<5>("h06")) node T_1301 = or(T_1299, T_1300) node T_1302 = eq(req.cmd, UInt<5>("h07")) node T_1303 = or(T_1301, T_1302) node T_1304 = bit(req.cmd, 3) node T_1305 = eq(req.cmd, UInt<5>("h04")) node T_1306 = or(T_1304, T_1305) node T_1307 = or(T_1303, T_1306) when T_1307 : node T_1308 = bits(req.addr, 3, 3) node T_1310 = cat(T_1308, UInt<6>("h00")) node T_1311 = dshr(io.grant.bits.data, T_1310) node T_1312 = bits(T_1311, 63, 0) grant_word <= T_1312 state <= UInt<2>("h03") skip node T_1314 = eq(T_1307, UInt<1>("h00")) when T_1314 : state <= UInt<1>("h00") skip skip node T_1315 = and(io.resp.ready, io.resp.valid) when T_1315 : state <= UInt<1>("h00") skip module MSHRFile : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>} io.fence_rdy <= UInt<1>("h00") io.probe_rdy <= UInt<1>("h00") io.wb_req.bits.way_en <= UInt<1>("h00") io.wb_req.bits.data <= UInt<1>("h00") io.wb_req.bits.r_type <= UInt<1>("h00") io.wb_req.bits.voluntary <= UInt<1>("h00") io.wb_req.bits.client_xact_id <= UInt<1>("h00") io.wb_req.bits.addr_block <= UInt<1>("h00") io.wb_req.bits.addr_beat <= UInt<1>("h00") io.wb_req.valid <= UInt<1>("h00") io.replay.bits.data <= UInt<1>("h00") io.replay.bits.phys <= UInt<1>("h00") io.replay.bits.kill <= UInt<1>("h00") io.replay.bits.typ <= UInt<1>("h00") io.replay.bits.cmd <= UInt<1>("h00") io.replay.bits.tag <= UInt<1>("h00") io.replay.bits.addr <= UInt<1>("h00") io.replay.valid <= UInt<1>("h00") io.meta_write.bits.data.coh.state <= UInt<1>("h00") io.meta_write.bits.data.tag <= UInt<1>("h00") io.meta_write.bits.way_en <= UInt<1>("h00") io.meta_write.bits.idx <= UInt<1>("h00") io.meta_write.valid <= UInt<1>("h00") io.meta_read.bits.tag <= UInt<1>("h00") io.meta_read.bits.idx <= UInt<1>("h00") io.meta_read.valid <= UInt<1>("h00") io.refill.addr <= UInt<1>("h00") io.refill.way_en <= UInt<1>("h00") io.mem_req.bits.data <= UInt<1>("h00") io.mem_req.bits.union <= UInt<1>("h00") io.mem_req.bits.a_type <= UInt<1>("h00") io.mem_req.bits.is_builtin_type <= UInt<1>("h00") io.mem_req.bits.addr_beat <= UInt<1>("h00") io.mem_req.bits.client_xact_id <= UInt<1>("h00") io.mem_req.bits.addr_block <= UInt<1>("h00") io.mem_req.valid <= UInt<1>("h00") io.secondary_miss <= UInt<1>("h00") io.resp.bits.store_data <= UInt<1>("h00") io.resp.bits.data_word_bypass <= UInt<1>("h00") io.resp.bits.has_data <= UInt<1>("h00") io.resp.bits.replay <= UInt<1>("h00") io.resp.bits.nack <= UInt<1>("h00") io.resp.bits.data <= UInt<1>("h00") io.resp.bits.typ <= UInt<1>("h00") io.resp.bits.cmd <= UInt<1>("h00") io.resp.bits.tag <= UInt<1>("h00") io.resp.bits.addr <= UInt<1>("h00") io.resp.valid <= UInt<1>("h00") io.req.ready <= UInt<1>("h00") node cacheable = lt(io.req.bits.addr, UInt<31>("h040000000")) reg sdq_val : UInt<17>, clk, reset, UInt<17>("h00") node T_1807 = bits(sdq_val, 16, 0) node T_1808 = not(T_1807) node T_1809 = bit(T_1808, 0) node T_1810 = bit(T_1808, 1) node T_1811 = bit(T_1808, 2) node T_1812 = bit(T_1808, 3) node T_1813 = bit(T_1808, 4) node T_1814 = bit(T_1808, 5) node T_1815 = bit(T_1808, 6) node T_1816 = bit(T_1808, 7) node T_1817 = bit(T_1808, 8) node T_1818 = bit(T_1808, 9) node T_1819 = bit(T_1808, 10) node T_1820 = bit(T_1808, 11) node T_1821 = bit(T_1808, 12) node T_1822 = bit(T_1808, 13) node T_1823 = bit(T_1808, 14) node T_1824 = bit(T_1808, 15) node T_1825 = bit(T_1808, 16) wire T_1827 : UInt<1>[17] T_1827[0] <= T_1809 T_1827[1] <= T_1810 T_1827[2] <= T_1811 T_1827[3] <= T_1812 T_1827[4] <= T_1813 T_1827[5] <= T_1814 T_1827[6] <= T_1815 T_1827[7] <= T_1816 T_1827[8] <= T_1817 T_1827[9] <= T_1818 T_1827[10] <= T_1819 T_1827[11] <= T_1820 T_1827[12] <= T_1821 T_1827[13] <= T_1822 T_1827[14] <= T_1823 T_1827[15] <= T_1824 T_1827[16] <= T_1825 node T_1863 = mux(T_1827[15], UInt<4>("h0f"), UInt<5>("h010")) node T_1864 = mux(T_1827[14], UInt<4>("h0e"), T_1863) node T_1865 = mux(T_1827[13], UInt<4>("h0d"), T_1864) node T_1866 = mux(T_1827[12], UInt<4>("h0c"), T_1865) node T_1867 = mux(T_1827[11], UInt<4>("h0b"), T_1866) node T_1868 = mux(T_1827[10], UInt<4>("h0a"), T_1867) node T_1869 = mux(T_1827[9], UInt<4>("h09"), T_1868) node T_1870 = mux(T_1827[8], UInt<4>("h08"), T_1869) node T_1871 = mux(T_1827[7], UInt<3>("h07"), T_1870) node T_1872 = mux(T_1827[6], UInt<3>("h06"), T_1871) node T_1873 = mux(T_1827[5], UInt<3>("h05"), T_1872) node T_1874 = mux(T_1827[4], UInt<3>("h04"), T_1873) node T_1875 = mux(T_1827[3], UInt<2>("h03"), T_1874) node T_1876 = mux(T_1827[2], UInt<2>("h02"), T_1875) node T_1877 = mux(T_1827[1], UInt<1>("h01"), T_1876) node sdq_alloc_id = mux(T_1827[0], UInt<1>("h00"), T_1877) node T_1879 = not(sdq_val) node T_1881 = eq(T_1879, UInt<1>("h00")) node sdq_rdy = eq(T_1881, UInt<1>("h00")) node T_1884 = and(io.req.valid, io.req.ready) node T_1885 = and(T_1884, cacheable) node T_1886 = eq(io.req.bits.cmd, UInt<5>("h01")) node T_1887 = eq(io.req.bits.cmd, UInt<5>("h07")) node T_1888 = or(T_1886, T_1887) node T_1889 = bit(io.req.bits.cmd, 3) node T_1890 = eq(io.req.bits.cmd, UInt<5>("h04")) node T_1891 = or(T_1889, T_1890) node T_1892 = or(T_1888, T_1891) node sdq_enq = and(T_1885, T_1892) cmem sdq : UInt<64>[17] when sdq_enq : infer mport T_1896 = sdq[sdq_alloc_id], clk T_1896 <= io.req.bits.data skip wire idxMatch : UInt<1>[2] idxMatch[0] <= UInt<1>("h00") idxMatch[1] <= UInt<1>("h00") wire tagList : UInt<20>[2] tagList[0] <= UInt<1>("h00") tagList[1] <= UInt<1>("h00") node T_1926 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) node T_1928 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) node T_1930 = or(T_1926, T_1928) wire T_1931 : UInt<20> T_1931 <= UInt<1>("h00") T_1931 <= T_1930 node T_1933 = shr(io.req.bits.addr, 12) node tag_match = eq(T_1931, T_1933) wire wbTagList : UInt[2] wbTagList[0] <= UInt<1>("h00") wbTagList[1] <= UInt<1>("h00") wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] refillMux[0].addr <= UInt<1>("h00") refillMux[0].way_en <= UInt<1>("h00") refillMux[1].addr <= UInt<1>("h00") refillMux[1].way_en <= UInt<1>("h00") inst meta_read_arb of Arbiter_93 meta_read_arb.io.out.ready <= UInt<1>("h00") meta_read_arb.io.in[0].bits.tag <= UInt<1>("h00") meta_read_arb.io.in[0].bits.idx <= UInt<1>("h00") meta_read_arb.io.in[0].valid <= UInt<1>("h00") meta_read_arb.io.in[1].bits.tag <= UInt<1>("h00") meta_read_arb.io.in[1].bits.idx <= UInt<1>("h00") meta_read_arb.io.in[1].valid <= UInt<1>("h00") meta_read_arb.clk <= clk meta_read_arb.reset <= reset inst meta_write_arb of Arbiter_94 meta_write_arb.io.out.ready <= UInt<1>("h00") meta_write_arb.io.in[0].bits.data.coh.state <= UInt<1>("h00") meta_write_arb.io.in[0].bits.data.tag <= UInt<1>("h00") meta_write_arb.io.in[0].bits.way_en <= UInt<1>("h00") meta_write_arb.io.in[0].bits.idx <= UInt<1>("h00") meta_write_arb.io.in[0].valid <= UInt<1>("h00") meta_write_arb.io.in[1].bits.data.coh.state <= UInt<1>("h00") meta_write_arb.io.in[1].bits.data.tag <= UInt<1>("h00") meta_write_arb.io.in[1].bits.way_en <= UInt<1>("h00") meta_write_arb.io.in[1].bits.idx <= UInt<1>("h00") meta_write_arb.io.in[1].valid <= UInt<1>("h00") meta_write_arb.clk <= clk meta_write_arb.reset <= reset inst mem_req_arb of LockingArbiter mem_req_arb.io.out.ready <= UInt<1>("h00") mem_req_arb.io.in[0].bits.data <= UInt<1>("h00") mem_req_arb.io.in[0].bits.union <= UInt<1>("h00") mem_req_arb.io.in[0].bits.a_type <= UInt<1>("h00") mem_req_arb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") mem_req_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") mem_req_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") mem_req_arb.io.in[0].bits.addr_block <= UInt<1>("h00") mem_req_arb.io.in[0].valid <= UInt<1>("h00") mem_req_arb.io.in[1].bits.data <= UInt<1>("h00") mem_req_arb.io.in[1].bits.union <= UInt<1>("h00") mem_req_arb.io.in[1].bits.a_type <= UInt<1>("h00") mem_req_arb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") mem_req_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") mem_req_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") mem_req_arb.io.in[1].bits.addr_block <= UInt<1>("h00") mem_req_arb.io.in[1].valid <= UInt<1>("h00") mem_req_arb.io.in[2].bits.data <= UInt<1>("h00") mem_req_arb.io.in[2].bits.union <= UInt<1>("h00") mem_req_arb.io.in[2].bits.a_type <= UInt<1>("h00") mem_req_arb.io.in[2].bits.is_builtin_type <= UInt<1>("h00") mem_req_arb.io.in[2].bits.addr_beat <= UInt<1>("h00") mem_req_arb.io.in[2].bits.client_xact_id <= UInt<1>("h00") mem_req_arb.io.in[2].bits.addr_block <= UInt<1>("h00") mem_req_arb.io.in[2].valid <= UInt<1>("h00") mem_req_arb.clk <= clk mem_req_arb.reset <= reset inst wb_req_arb of Arbiter_95 wb_req_arb.io.out.ready <= UInt<1>("h00") wb_req_arb.io.in[0].bits.way_en <= UInt<1>("h00") wb_req_arb.io.in[0].bits.data <= UInt<1>("h00") wb_req_arb.io.in[0].bits.r_type <= UInt<1>("h00") wb_req_arb.io.in[0].bits.voluntary <= UInt<1>("h00") wb_req_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") wb_req_arb.io.in[0].bits.addr_block <= UInt<1>("h00") wb_req_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") wb_req_arb.io.in[0].valid <= UInt<1>("h00") wb_req_arb.io.in[1].bits.way_en <= UInt<1>("h00") wb_req_arb.io.in[1].bits.data <= UInt<1>("h00") wb_req_arb.io.in[1].bits.r_type <= UInt<1>("h00") wb_req_arb.io.in[1].bits.voluntary <= UInt<1>("h00") wb_req_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") wb_req_arb.io.in[1].bits.addr_block <= UInt<1>("h00") wb_req_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") wb_req_arb.io.in[1].valid <= UInt<1>("h00") wb_req_arb.clk <= clk wb_req_arb.reset <= reset inst replay_arb of Arbiter_96 replay_arb.io.out.ready <= UInt<1>("h00") replay_arb.io.in[0].bits.sdq_id <= UInt<1>("h00") replay_arb.io.in[0].bits.phys <= UInt<1>("h00") replay_arb.io.in[0].bits.kill <= UInt<1>("h00") replay_arb.io.in[0].bits.typ <= UInt<1>("h00") replay_arb.io.in[0].bits.cmd <= UInt<1>("h00") replay_arb.io.in[0].bits.tag <= UInt<1>("h00") replay_arb.io.in[0].bits.addr <= UInt<1>("h00") replay_arb.io.in[0].valid <= UInt<1>("h00") replay_arb.io.in[1].bits.sdq_id <= UInt<1>("h00") replay_arb.io.in[1].bits.phys <= UInt<1>("h00") replay_arb.io.in[1].bits.kill <= UInt<1>("h00") replay_arb.io.in[1].bits.typ <= UInt<1>("h00") replay_arb.io.in[1].bits.cmd <= UInt<1>("h00") replay_arb.io.in[1].bits.tag <= UInt<1>("h00") replay_arb.io.in[1].bits.addr <= UInt<1>("h00") replay_arb.io.in[1].valid <= UInt<1>("h00") replay_arb.clk <= clk replay_arb.reset <= reset inst alloc_arb of Arbiter_97 alloc_arb.io.out.ready <= UInt<1>("h00") alloc_arb.io.in[0].bits <= UInt<1>("h00") alloc_arb.io.in[0].valid <= UInt<1>("h00") alloc_arb.io.in[1].bits <= UInt<1>("h00") alloc_arb.io.in[1].valid <= UInt<1>("h00") alloc_arb.clk <= clk alloc_arb.reset <= reset io.fence_rdy <= UInt<1>("h01") io.probe_rdy <= UInt<1>("h01") inst T_2807 of MSHR T_2807.io.wb_req.ready <= UInt<1>("h00") T_2807.io.mem_grant.bits.data <= UInt<1>("h00") T_2807.io.mem_grant.bits.g_type <= UInt<1>("h00") T_2807.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") T_2807.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") T_2807.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") T_2807.io.mem_grant.bits.addr_beat <= UInt<1>("h00") T_2807.io.mem_grant.valid <= UInt<1>("h00") T_2807.io.replay.ready <= UInt<1>("h00") T_2807.io.meta_write.ready <= UInt<1>("h00") T_2807.io.meta_read.ready <= UInt<1>("h00") T_2807.io.mem_req.ready <= UInt<1>("h00") T_2807.io.req_bits.way_en <= UInt<1>("h00") T_2807.io.req_bits.old_meta.coh.state <= UInt<1>("h00") T_2807.io.req_bits.old_meta.tag <= UInt<1>("h00") T_2807.io.req_bits.tag_match <= UInt<1>("h00") T_2807.io.req_bits.sdq_id <= UInt<1>("h00") T_2807.io.req_bits.phys <= UInt<1>("h00") T_2807.io.req_bits.kill <= UInt<1>("h00") T_2807.io.req_bits.typ <= UInt<1>("h00") T_2807.io.req_bits.cmd <= UInt<1>("h00") T_2807.io.req_bits.tag <= UInt<1>("h00") T_2807.io.req_bits.addr <= UInt<1>("h00") T_2807.io.req_sec_val <= UInt<1>("h00") T_2807.io.req_pri_val <= UInt<1>("h00") T_2807.clk <= clk T_2807.reset <= reset idxMatch[0] <= T_2807.io.idx_match tagList[0] <= T_2807.io.tag node T_2833 = shr(T_2807.io.wb_req.bits.addr_block, 6) wbTagList[0] <= T_2833 alloc_arb.io.in[0].valid <= T_2807.io.req_pri_rdy T_2807.io.req_pri_val <= alloc_arb.io.in[0].ready node T_2834 = and(io.req.valid, sdq_rdy) node T_2835 = and(T_2834, tag_match) T_2807.io.req_sec_val <= T_2835 T_2807.io.req_bits <- io.req.bits T_2807.io.req_bits.sdq_id <= sdq_alloc_id meta_read_arb.io.in[0] <- T_2807.io.meta_read meta_write_arb.io.in[0] <- T_2807.io.meta_write mem_req_arb.io.in[0] <- T_2807.io.mem_req wb_req_arb.io.in[0] <- T_2807.io.wb_req replay_arb.io.in[0] <- T_2807.io.replay node T_2837 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00")) node T_2838 = and(io.mem_grant.valid, T_2837) T_2807.io.mem_grant.valid <= T_2838 T_2807.io.mem_grant.bits <- io.mem_grant.bits refillMux[0] <- T_2807.io.refill node T_2839 = or(UInt<1>("h00"), T_2807.io.req_pri_rdy) node T_2840 = or(UInt<1>("h00"), T_2807.io.req_sec_rdy) node T_2841 = or(UInt<1>("h00"), T_2807.io.idx_match) node T_2843 = eq(T_2807.io.req_pri_rdy, UInt<1>("h00")) when T_2843 : io.fence_rdy <= UInt<1>("h00") skip node T_2846 = eq(T_2807.io.probe_rdy, UInt<1>("h00")) when T_2846 : io.probe_rdy <= UInt<1>("h00") skip inst T_2848 of MSHR_99 T_2848.io.wb_req.ready <= UInt<1>("h00") T_2848.io.mem_grant.bits.data <= UInt<1>("h00") T_2848.io.mem_grant.bits.g_type <= UInt<1>("h00") T_2848.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") T_2848.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") T_2848.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") T_2848.io.mem_grant.bits.addr_beat <= UInt<1>("h00") T_2848.io.mem_grant.valid <= UInt<1>("h00") T_2848.io.replay.ready <= UInt<1>("h00") T_2848.io.meta_write.ready <= UInt<1>("h00") T_2848.io.meta_read.ready <= UInt<1>("h00") T_2848.io.mem_req.ready <= UInt<1>("h00") T_2848.io.req_bits.way_en <= UInt<1>("h00") T_2848.io.req_bits.old_meta.coh.state <= UInt<1>("h00") T_2848.io.req_bits.old_meta.tag <= UInt<1>("h00") T_2848.io.req_bits.tag_match <= UInt<1>("h00") T_2848.io.req_bits.sdq_id <= UInt<1>("h00") T_2848.io.req_bits.phys <= UInt<1>("h00") T_2848.io.req_bits.kill <= UInt<1>("h00") T_2848.io.req_bits.typ <= UInt<1>("h00") T_2848.io.req_bits.cmd <= UInt<1>("h00") T_2848.io.req_bits.tag <= UInt<1>("h00") T_2848.io.req_bits.addr <= UInt<1>("h00") T_2848.io.req_sec_val <= UInt<1>("h00") T_2848.io.req_pri_val <= UInt<1>("h00") T_2848.clk <= clk T_2848.reset <= reset idxMatch[1] <= T_2848.io.idx_match tagList[1] <= T_2848.io.tag node T_2874 = shr(T_2848.io.wb_req.bits.addr_block, 6) wbTagList[1] <= T_2874 alloc_arb.io.in[1].valid <= T_2848.io.req_pri_rdy T_2848.io.req_pri_val <= alloc_arb.io.in[1].ready node T_2875 = and(io.req.valid, sdq_rdy) node T_2876 = and(T_2875, tag_match) T_2848.io.req_sec_val <= T_2876 T_2848.io.req_bits <- io.req.bits T_2848.io.req_bits.sdq_id <= sdq_alloc_id meta_read_arb.io.in[1] <- T_2848.io.meta_read meta_write_arb.io.in[1] <- T_2848.io.meta_write mem_req_arb.io.in[1] <- T_2848.io.mem_req wb_req_arb.io.in[1] <- T_2848.io.wb_req replay_arb.io.in[1] <- T_2848.io.replay node T_2878 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01")) node T_2879 = and(io.mem_grant.valid, T_2878) T_2848.io.mem_grant.valid <= T_2879 T_2848.io.mem_grant.bits <- io.mem_grant.bits refillMux[1] <- T_2848.io.refill node pri_rdy = or(T_2839, T_2848.io.req_pri_rdy) node sec_rdy = or(T_2840, T_2848.io.req_sec_rdy) node idx_match = or(T_2841, T_2848.io.idx_match) node T_2884 = eq(T_2848.io.req_pri_rdy, UInt<1>("h00")) when T_2884 : io.fence_rdy <= UInt<1>("h00") skip node T_2887 = eq(T_2848.io.probe_rdy, UInt<1>("h00")) when T_2887 : io.probe_rdy <= UInt<1>("h00") skip node T_2889 = and(io.req.valid, sdq_rdy) node T_2890 = and(T_2889, cacheable) node T_2892 = eq(idx_match, UInt<1>("h00")) node T_2893 = and(T_2890, T_2892) alloc_arb.io.out.ready <= T_2893 io.meta_read <- meta_read_arb.io.out io.meta_write <- meta_write_arb.io.out io.mem_req <- mem_req_arb.io.out io.wb_req <- wb_req_arb.io.out inst mmio_alloc_arb of Arbiter_101 mmio_alloc_arb.io.out.ready <= UInt<1>("h00") mmio_alloc_arb.io.in[0].bits <= UInt<1>("h00") mmio_alloc_arb.io.in[0].valid <= UInt<1>("h00") mmio_alloc_arb.clk <= clk mmio_alloc_arb.reset <= reset inst resp_arb of Arbiter_102 resp_arb.io.out.ready <= UInt<1>("h00") resp_arb.io.in[0].bits.store_data <= UInt<1>("h00") resp_arb.io.in[0].bits.data_word_bypass <= UInt<1>("h00") resp_arb.io.in[0].bits.has_data <= UInt<1>("h00") resp_arb.io.in[0].bits.replay <= UInt<1>("h00") resp_arb.io.in[0].bits.nack <= UInt<1>("h00") resp_arb.io.in[0].bits.data <= UInt<1>("h00") resp_arb.io.in[0].bits.typ <= UInt<1>("h00") resp_arb.io.in[0].bits.cmd <= UInt<1>("h00") resp_arb.io.in[0].bits.tag <= UInt<1>("h00") resp_arb.io.in[0].bits.addr <= UInt<1>("h00") resp_arb.io.in[0].valid <= UInt<1>("h00") resp_arb.clk <= clk resp_arb.reset <= reset inst T_2970 of IOMSHR T_2970.io.resp.ready <= UInt<1>("h00") T_2970.io.grant.bits.data <= UInt<1>("h00") T_2970.io.grant.bits.g_type <= UInt<1>("h00") T_2970.io.grant.bits.is_builtin_type <= UInt<1>("h00") T_2970.io.grant.bits.manager_xact_id <= UInt<1>("h00") T_2970.io.grant.bits.client_xact_id <= UInt<1>("h00") T_2970.io.grant.bits.addr_beat <= UInt<1>("h00") T_2970.io.grant.valid <= UInt<1>("h00") T_2970.io.acquire.ready <= UInt<1>("h00") T_2970.io.req.bits.data <= UInt<1>("h00") T_2970.io.req.bits.phys <= UInt<1>("h00") T_2970.io.req.bits.kill <= UInt<1>("h00") T_2970.io.req.bits.typ <= UInt<1>("h00") T_2970.io.req.bits.cmd <= UInt<1>("h00") T_2970.io.req.bits.tag <= UInt<1>("h00") T_2970.io.req.bits.addr <= UInt<1>("h00") T_2970.io.req.valid <= UInt<1>("h00") T_2970.clk <= clk T_2970.reset <= reset mmio_alloc_arb.io.in[0].valid <= T_2970.io.req.ready T_2970.io.req.valid <= mmio_alloc_arb.io.in[0].ready T_2970.io.req.bits <- io.req.bits node mmio_rdy = or(UInt<1>("h00"), T_2970.io.req.ready) mem_req_arb.io.in[2] <- T_2970.io.acquire T_2970.io.grant.bits <- io.mem_grant.bits node T_2990 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02")) node T_2991 = and(io.mem_grant.valid, T_2990) T_2970.io.grant.valid <= T_2991 resp_arb.io.in[0] <- T_2970.io.resp node T_2993 = eq(T_2970.io.req.ready, UInt<1>("h00")) when T_2993 : io.fence_rdy <= UInt<1>("h00") skip node T_2996 = eq(cacheable, UInt<1>("h00")) node T_2997 = and(io.req.valid, T_2996) mmio_alloc_arb.io.out.ready <= T_2997 io.resp <- resp_arb.io.out node T_2999 = eq(cacheable, UInt<1>("h00")) node T_3000 = and(tag_match, sec_rdy) node T_3001 = mux(idx_match, T_3000, pri_rdy) node T_3002 = and(T_3001, sdq_rdy) node T_3003 = mux(T_2999, mmio_rdy, T_3002) io.req.ready <= T_3003 io.secondary_miss <= idx_match io.refill <- refillMux[io.mem_grant.bits.client_xact_id] node T_3053 = and(io.replay.ready, io.replay.valid) node T_3054 = eq(io.replay.bits.cmd, UInt<5>("h01")) node T_3055 = eq(io.replay.bits.cmd, UInt<5>("h07")) node T_3056 = or(T_3054, T_3055) node T_3057 = bit(io.replay.bits.cmd, 3) node T_3058 = eq(io.replay.bits.cmd, UInt<5>("h04")) node T_3059 = or(T_3057, T_3058) node T_3060 = or(T_3056, T_3059) node free_sdq = and(T_3053, T_3060) reg T_3062 : UInt<5>, clk, UInt<1>("h00"), T_3062 when free_sdq : T_3062 <= replay_arb.io.out.bits.sdq_id skip infer mport T_3063 = sdq[T_3062], clk io.replay.bits.data <= T_3063 io.replay <- replay_arb.io.out node T_3064 = or(io.replay.valid, sdq_enq) when T_3064 : node T_3066 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id) node T_3068 = subw(UInt<17>("h00"), free_sdq) node T_3069 = and(T_3066, T_3068) node T_3070 = not(T_3069) node T_3071 = and(sdq_val, T_3070) node T_3072 = bits(sdq_val, 16, 0) node T_3073 = not(T_3072) node T_3074 = bit(T_3073, 0) node T_3075 = bit(T_3073, 1) node T_3076 = bit(T_3073, 2) node T_3077 = bit(T_3073, 3) node T_3078 = bit(T_3073, 4) node T_3079 = bit(T_3073, 5) node T_3080 = bit(T_3073, 6) node T_3081 = bit(T_3073, 7) node T_3082 = bit(T_3073, 8) node T_3083 = bit(T_3073, 9) node T_3084 = bit(T_3073, 10) node T_3085 = bit(T_3073, 11) node T_3086 = bit(T_3073, 12) node T_3087 = bit(T_3073, 13) node T_3088 = bit(T_3073, 14) node T_3089 = bit(T_3073, 15) node T_3090 = bit(T_3073, 16) wire T_3109 : UInt<17>[17] T_3109[0] <= UInt<17>("h01") T_3109[1] <= UInt<17>("h02") T_3109[2] <= UInt<17>("h04") T_3109[3] <= UInt<17>("h08") T_3109[4] <= UInt<17>("h010") T_3109[5] <= UInt<17>("h020") T_3109[6] <= UInt<17>("h040") T_3109[7] <= UInt<17>("h080") T_3109[8] <= UInt<17>("h0100") T_3109[9] <= UInt<17>("h0200") T_3109[10] <= UInt<17>("h0400") T_3109[11] <= UInt<17>("h0800") T_3109[12] <= UInt<17>("h01000") T_3109[13] <= UInt<17>("h02000") T_3109[14] <= UInt<17>("h04000") T_3109[15] <= UInt<17>("h08000") T_3109[16] <= UInt<17>("h010000") node T_3130 = mux(T_3090, T_3109[16], UInt<17>("h00")) node T_3131 = mux(T_3089, T_3109[15], T_3130) node T_3132 = mux(T_3088, T_3109[14], T_3131) node T_3133 = mux(T_3087, T_3109[13], T_3132) node T_3134 = mux(T_3086, T_3109[12], T_3133) node T_3135 = mux(T_3085, T_3109[11], T_3134) node T_3136 = mux(T_3084, T_3109[10], T_3135) node T_3137 = mux(T_3083, T_3109[9], T_3136) node T_3138 = mux(T_3082, T_3109[8], T_3137) node T_3139 = mux(T_3081, T_3109[7], T_3138) node T_3140 = mux(T_3080, T_3109[6], T_3139) node T_3141 = mux(T_3079, T_3109[5], T_3140) node T_3142 = mux(T_3078, T_3109[4], T_3141) node T_3143 = mux(T_3077, T_3109[3], T_3142) node T_3144 = mux(T_3076, T_3109[2], T_3143) node T_3145 = mux(T_3075, T_3109[1], T_3144) node T_3146 = mux(T_3074, T_3109[0], T_3145) node T_3148 = subw(UInt<17>("h00"), sdq_enq) node T_3149 = and(T_3146, T_3148) node T_3150 = or(T_3071, T_3149) sdq_val <= T_3150 skip module MetadataArray : input clk : Clock input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]} io.resp[0].coh.state <= UInt<1>("h00") io.resp[0].tag <= UInt<1>("h00") io.resp[1].coh.state <= UInt<1>("h00") io.resp[1].tag <= UInt<1>("h00") io.resp[2].coh.state <= UInt<1>("h00") io.resp[2].tag <= UInt<1>("h00") io.resp[3].coh.state <= UInt<1>("h00") io.resp[3].tag <= UInt<1>("h00") io.write.ready <= UInt<1>("h00") io.read.ready <= UInt<1>("h00") wire T_30 : {state : UInt<2>} T_30.state <= UInt<1>("h00") T_30.state <= UInt<1>("h00") wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} rstVal.coh.state <= UInt<1>("h00") rstVal.tag <= UInt<1>("h00") rstVal.tag <= UInt<1>("h00") rstVal.coh <- T_30 reg rst_cnt : UInt<7>, clk, reset, UInt<7>("h00") node rst = lt(rst_cnt, UInt<7>("h040")) node waddr = mux(rst, rst_cnt, io.write.bits.idx) wire T_1709 : {tag : UInt<20>, coh : {state : UInt<2>}} T_1709 <- io.write.bits.data when rst : T_1709 <- rstVal skip node wdata = cat(T_1709.tag, T_1709.coh.state) node T_1784 = asSInt(io.write.bits.way_en) node T_1785 = mux(rst, asSInt(UInt<1>("h01")), T_1784) node T_1786 = bit(T_1785, 0) node T_1787 = bit(T_1785, 1) node T_1788 = bit(T_1785, 2) node T_1789 = bit(T_1785, 3) wire wmask : UInt<1>[4] wmask[0] <= T_1786 wmask[1] <= T_1787 wmask[2] <= T_1788 wmask[3] <= T_1789 when rst : node T_1798 = addw(rst_cnt, UInt<1>("h01")) rst_cnt <= T_1798 skip smem tag_arr : UInt<22>[4][64] node T_1816 = or(rst, io.write.valid) when T_1816 : wire T_1818 : UInt<22>[4] T_1818[0] <= wdata T_1818[1] <= wdata T_1818[2] <= wdata T_1818[3] <= wdata write mport T_1826 = tag_arr[waddr], clk when wmask[0] : T_1826[0] <= T_1818[0] skip when wmask[1] : T_1826[1] <= T_1818[1] skip when wmask[2] : T_1826[2] <= T_1818[2] skip when wmask[3] : T_1826[3] <= T_1818[3] skip skip poison T_1832 : UInt<6> node T_1833 = mux(io.read.valid, io.read.bits.idx, T_1832) read mport T_1836 = tag_arr[T_1833], clk node T_1842 = cat(T_1836[3], T_1836[2]) node T_1843 = cat(T_1836[1], T_1836[0]) node tags = cat(T_1842, T_1843) wire T_2503 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] T_2503[0].coh.state <= UInt<1>("h00") T_2503[0].tag <= UInt<1>("h00") T_2503[1].coh.state <= UInt<1>("h00") T_2503[1].tag <= UInt<1>("h00") T_2503[2].coh.state <= UInt<1>("h00") T_2503[2].tag <= UInt<1>("h00") T_2503[3].coh.state <= UInt<1>("h00") T_2503[3].tag <= UInt<1>("h00") node T_2877 = bits(tags, 1, 0) T_2503[0].coh.state <= T_2877 node T_2878 = bits(tags, 21, 2) T_2503[0].tag <= T_2878 node T_2879 = bits(tags, 23, 22) T_2503[1].coh.state <= T_2879 node T_2880 = bits(tags, 43, 24) T_2503[1].tag <= T_2880 node T_2881 = bits(tags, 45, 44) T_2503[2].coh.state <= T_2881 node T_2882 = bits(tags, 65, 46) T_2503[2].tag <= T_2882 node T_2883 = bits(tags, 67, 66) T_2503[3].coh.state <= T_2883 node T_2884 = bits(tags, 87, 68) T_2503[3].tag <= T_2884 io.resp <= T_2503 node T_2886 = eq(rst, UInt<1>("h00")) node T_2888 = eq(io.write.valid, UInt<1>("h00")) node T_2889 = and(T_2886, T_2888) io.read.ready <= T_2889 node T_2891 = eq(rst, UInt<1>("h00")) io.write.ready <= T_2891 module Arbiter_105 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, chosen : UInt<3>} io.chosen <= UInt<1>("h00") io.out.bits.idx <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") io.in[4].ready <= UInt<1>("h00") wire T_128 : UInt<3> T_128 <= UInt<1>("h00") io.out.valid <= io.in[T_128].valid io.out.bits <- io.in[T_128].bits io.chosen <= T_128 io.in[T_128].ready <= UInt<1>("h00") node T_154 = or(UInt<1>("h00"), io.in[0].valid) node T_156 = eq(T_154, UInt<1>("h00")) node T_158 = or(UInt<1>("h00"), io.in[0].valid) node T_159 = or(T_158, io.in[1].valid) node T_161 = eq(T_159, UInt<1>("h00")) node T_163 = or(UInt<1>("h00"), io.in[0].valid) node T_164 = or(T_163, io.in[1].valid) node T_165 = or(T_164, io.in[2].valid) node T_167 = eq(T_165, UInt<1>("h00")) node T_169 = or(UInt<1>("h00"), io.in[0].valid) node T_170 = or(T_169, io.in[1].valid) node T_171 = or(T_170, io.in[2].valid) node T_172 = or(T_171, io.in[3].valid) node T_174 = eq(T_172, UInt<1>("h00")) node T_176 = eq(UInt<3>("h04"), UInt<1>("h00")) node T_177 = mux(UInt<1>("h00"), T_176, UInt<1>("h01")) node T_178 = and(T_177, io.out.ready) io.in[0].ready <= T_178 node T_180 = eq(UInt<3>("h04"), UInt<1>("h01")) node T_181 = mux(UInt<1>("h00"), T_180, T_156) node T_182 = and(T_181, io.out.ready) io.in[1].ready <= T_182 node T_184 = eq(UInt<3>("h04"), UInt<2>("h02")) node T_185 = mux(UInt<1>("h00"), T_184, T_161) node T_186 = and(T_185, io.out.ready) io.in[2].ready <= T_186 node T_188 = eq(UInt<3>("h04"), UInt<2>("h03")) node T_189 = mux(UInt<1>("h00"), T_188, T_167) node T_190 = and(T_189, io.out.ready) io.in[3].ready <= T_190 node T_192 = eq(UInt<3>("h04"), UInt<3>("h04")) node T_193 = mux(UInt<1>("h00"), T_192, T_174) node T_194 = and(T_193, io.out.ready) io.in[4].ready <= T_194 node T_197 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) node T_199 = mux(io.in[2].valid, UInt<2>("h02"), T_197) node T_201 = mux(io.in[1].valid, UInt<1>("h01"), T_199) node T_203 = mux(io.in[0].valid, UInt<1>("h00"), T_201) node T_204 = mux(UInt<1>("h00"), UInt<3>("h04"), T_203) T_128 <= T_204 module DataArray : input clk : Clock input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]} io.resp[0] <= UInt<1>("h00") io.resp[1] <= UInt<1>("h00") io.resp[2] <= UInt<1>("h00") io.resp[3] <= UInt<1>("h00") io.write.ready <= UInt<1>("h00") io.read.ready <= UInt<1>("h00") node waddr = shr(io.write.bits.addr, 4) node raddr = shr(io.read.bits.addr, 4) node T_572 = bits(io.write.bits.way_en, 1, 0) node T_573 = bits(io.read.bits.way_en, 1, 0) wire T_582 : UInt<128>[2] T_582[0] <= UInt<1>("h00") T_582[1] <= UInt<1>("h00") reg T_588 : UInt<12>, clk, UInt<1>("h00"), T_588 when io.read.valid : T_588 <= io.read.bits.addr skip smem T_601 : UInt<64>[2][256] node T_603 = neq(T_572, UInt<1>("h00")) node T_604 = and(T_603, io.write.valid) node T_605 = bit(io.write.bits.wmask, 0) node T_606 = and(T_604, T_605) when T_606 : node T_607 = bits(io.write.bits.data, 63, 0) node T_608 = bits(io.write.bits.data, 63, 0) wire T_610 : UInt<64>[2] T_610[0] <= T_607 T_610[1] <= T_608 node T_614 = bit(T_572, 0) node T_615 = bit(T_572, 1) wire T_617 : UInt<1>[2] T_617[0] <= T_614 T_617[1] <= T_615 write mport T_623 = T_601[waddr], clk when T_617[0] : T_623[0] <= T_610[0] skip when T_617[1] : T_623[1] <= T_610[1] skip skip node T_628 = neq(T_573, UInt<1>("h00")) node T_629 = and(T_628, io.read.valid) poison T_630 : UInt<8> node T_631 = mux(T_629, raddr, T_630) read mport T_634 = T_601[T_631], clk node T_638 = cat(T_634[1], T_634[0]) T_582[0] <= T_638 smem T_651 : UInt<64>[2][256] node T_653 = neq(T_572, UInt<1>("h00")) node T_654 = and(T_653, io.write.valid) node T_655 = bit(io.write.bits.wmask, 1) node T_656 = and(T_654, T_655) when T_656 : node T_657 = bits(io.write.bits.data, 127, 64) node T_658 = bits(io.write.bits.data, 127, 64) wire T_660 : UInt<64>[2] T_660[0] <= T_657 T_660[1] <= T_658 node T_664 = bit(T_572, 0) node T_665 = bit(T_572, 1) wire T_667 : UInt<1>[2] T_667[0] <= T_664 T_667[1] <= T_665 write mport T_673 = T_651[waddr], clk when T_667[0] : T_673[0] <= T_660[0] skip when T_667[1] : T_673[1] <= T_660[1] skip skip node T_678 = neq(T_573, UInt<1>("h00")) node T_679 = and(T_678, io.read.valid) poison T_680 : UInt<8> node T_681 = mux(T_679, raddr, T_680) read mport T_684 = T_651[T_681], clk node T_688 = cat(T_684[1], T_684[0]) T_582[1] <= T_688 node T_689 = bits(T_582[0], 63, 0) node T_690 = bits(T_582[1], 63, 0) wire T_692 : UInt<64>[2] T_692[0] <= T_689 T_692[1] <= T_690 node T_696 = bits(T_588, 3, 3) wire T_699 : UInt<64>[2] T_699[0] <= T_692[T_696] T_699[1] <= T_692[1] node T_703 = cat(T_699[1], T_699[0]) io.resp[0] <= T_703 node T_704 = bits(T_582[0], 127, 64) node T_705 = bits(T_582[1], 127, 64) wire T_707 : UInt<64>[2] T_707[0] <= T_704 T_707[1] <= T_705 node T_711 = bits(T_588, 3, 3) wire T_714 : UInt<64>[2] T_714[0] <= T_707[T_711] T_714[1] <= T_707[1] node T_718 = cat(T_714[1], T_714[0]) io.resp[1] <= T_718 node T_719 = bits(io.write.bits.way_en, 3, 2) node T_720 = bits(io.read.bits.way_en, 3, 2) wire T_729 : UInt<128>[2] T_729[0] <= UInt<1>("h00") T_729[1] <= UInt<1>("h00") reg T_735 : UInt<12>, clk, UInt<1>("h00"), T_735 when io.read.valid : T_735 <= io.read.bits.addr skip smem T_748 : UInt<64>[2][256] node T_750 = neq(T_719, UInt<1>("h00")) node T_751 = and(T_750, io.write.valid) node T_752 = bit(io.write.bits.wmask, 0) node T_753 = and(T_751, T_752) when T_753 : node T_754 = bits(io.write.bits.data, 63, 0) node T_755 = bits(io.write.bits.data, 63, 0) wire T_757 : UInt<64>[2] T_757[0] <= T_754 T_757[1] <= T_755 node T_761 = bit(T_719, 0) node T_762 = bit(T_719, 1) wire T_764 : UInt<1>[2] T_764[0] <= T_761 T_764[1] <= T_762 write mport T_770 = T_748[waddr], clk when T_764[0] : T_770[0] <= T_757[0] skip when T_764[1] : T_770[1] <= T_757[1] skip skip node T_775 = neq(T_720, UInt<1>("h00")) node T_776 = and(T_775, io.read.valid) poison T_777 : UInt<8> node T_778 = mux(T_776, raddr, T_777) read mport T_781 = T_748[T_778], clk node T_785 = cat(T_781[1], T_781[0]) T_729[0] <= T_785 smem T_798 : UInt<64>[2][256] node T_800 = neq(T_719, UInt<1>("h00")) node T_801 = and(T_800, io.write.valid) node T_802 = bit(io.write.bits.wmask, 1) node T_803 = and(T_801, T_802) when T_803 : node T_804 = bits(io.write.bits.data, 127, 64) node T_805 = bits(io.write.bits.data, 127, 64) wire T_807 : UInt<64>[2] T_807[0] <= T_804 T_807[1] <= T_805 node T_811 = bit(T_719, 0) node T_812 = bit(T_719, 1) wire T_814 : UInt<1>[2] T_814[0] <= T_811 T_814[1] <= T_812 write mport T_820 = T_798[waddr], clk when T_814[0] : T_820[0] <= T_807[0] skip when T_814[1] : T_820[1] <= T_807[1] skip skip node T_825 = neq(T_720, UInt<1>("h00")) node T_826 = and(T_825, io.read.valid) poison T_827 : UInt<8> node T_828 = mux(T_826, raddr, T_827) read mport T_831 = T_798[T_828], clk node T_835 = cat(T_831[1], T_831[0]) T_729[1] <= T_835 node T_836 = bits(T_729[0], 63, 0) node T_837 = bits(T_729[1], 63, 0) wire T_839 : UInt<64>[2] T_839[0] <= T_836 T_839[1] <= T_837 node T_843 = bits(T_735, 3, 3) wire T_846 : UInt<64>[2] T_846[0] <= T_839[T_843] T_846[1] <= T_839[1] node T_850 = cat(T_846[1], T_846[0]) io.resp[2] <= T_850 node T_851 = bits(T_729[0], 127, 64) node T_852 = bits(T_729[1], 127, 64) wire T_854 : UInt<64>[2] T_854[0] <= T_851 T_854[1] <= T_852 node T_858 = bits(T_735, 3, 3) wire T_861 : UInt<64>[2] T_861[0] <= T_854[T_858] T_861[1] <= T_854[1] node T_865 = cat(T_861[1], T_861[0]) io.resp[3] <= T_865 io.read.ready <= UInt<1>("h01") io.write.ready <= UInt<1>("h01") module Arbiter_107 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>} io.chosen <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.bits.way_en <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") io.in[2].ready <= UInt<1>("h00") io.in[3].ready <= UInt<1>("h00") wire T_1524 : UInt<2> T_1524 <= UInt<1>("h00") io.out.valid <= io.in[T_1524].valid io.out.bits <- io.in[T_1524].bits io.chosen <= T_1524 io.in[T_1524].ready <= UInt<1>("h00") node T_1832 = or(UInt<1>("h00"), io.in[0].valid) node T_1834 = eq(T_1832, UInt<1>("h00")) node T_1836 = or(UInt<1>("h00"), io.in[0].valid) node T_1837 = or(T_1836, io.in[1].valid) node T_1839 = eq(T_1837, UInt<1>("h00")) node T_1841 = or(UInt<1>("h00"), io.in[0].valid) node T_1842 = or(T_1841, io.in[1].valid) node T_1843 = or(T_1842, io.in[2].valid) node T_1845 = eq(T_1843, UInt<1>("h00")) node T_1847 = eq(UInt<2>("h03"), UInt<1>("h00")) node T_1848 = mux(UInt<1>("h00"), T_1847, UInt<1>("h01")) node T_1849 = and(T_1848, io.out.ready) io.in[0].ready <= T_1849 node T_1851 = eq(UInt<2>("h03"), UInt<1>("h01")) node T_1852 = mux(UInt<1>("h00"), T_1851, T_1834) node T_1853 = and(T_1852, io.out.ready) io.in[1].ready <= T_1853 node T_1855 = eq(UInt<2>("h03"), UInt<2>("h02")) node T_1856 = mux(UInt<1>("h00"), T_1855, T_1839) node T_1857 = and(T_1856, io.out.ready) io.in[2].ready <= T_1857 node T_1859 = eq(UInt<2>("h03"), UInt<2>("h03")) node T_1860 = mux(UInt<1>("h00"), T_1859, T_1845) node T_1861 = and(T_1860, io.out.ready) io.in[3].ready <= T_1861 node T_1864 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) node T_1866 = mux(io.in[1].valid, UInt<1>("h01"), T_1864) node T_1868 = mux(io.in[0].valid, UInt<1>("h00"), T_1866) node T_1869 = mux(UInt<1>("h00"), UInt<2>("h03"), T_1868) T_1524 <= T_1869 module Arbiter_108 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.wmask <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.bits.way_en <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_1164 : UInt<1> T_1164 <= UInt<1>("h00") io.out.valid <= io.in[T_1164].valid io.out.bits <- io.in[T_1164].bits io.chosen <= T_1164 io.in[T_1164].ready <= UInt<1>("h00") node T_1484 = or(UInt<1>("h00"), io.in[0].valid) node T_1486 = eq(T_1484, UInt<1>("h00")) node T_1488 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_1489 = mux(UInt<1>("h00"), T_1488, UInt<1>("h01")) node T_1490 = and(T_1489, io.out.ready) io.in[0].ready <= T_1490 node T_1492 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_1493 = mux(UInt<1>("h00"), T_1492, T_1486) node T_1494 = and(T_1493, io.out.ready) io.in[1].ready <= T_1494 node T_1497 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_1498 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1497) T_1164 <= T_1498 module AMOALU : input clk : Clock input reset : UInt<1> output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} io.out <= UInt<1>("h00") node T_10 = bits(io.typ, 1, 0) node T_12 = eq(T_10, UInt<2>("h02")) node T_13 = bits(io.rhs, 31, 0) node T_14 = cat(T_13, T_13) node rhs = mux(T_12, T_14, io.rhs) node T_16 = eq(io.cmd, UInt<5>("h0c")) node T_17 = eq(io.cmd, UInt<5>("h0d")) node sgned = or(T_16, T_17) node T_19 = eq(io.cmd, UInt<5>("h0d")) node T_20 = eq(io.cmd, UInt<5>("h0f")) node max = or(T_19, T_20) node T_22 = eq(io.cmd, UInt<5>("h0c")) node T_23 = eq(io.cmd, UInt<5>("h0e")) node min = or(T_22, T_23) node T_25 = eq(io.typ, UInt<3>("h02")) node T_26 = eq(io.typ, UInt<3>("h06")) node T_27 = or(T_25, T_26) node T_28 = eq(io.typ, UInt<3>("h00")) node T_29 = or(T_27, T_28) node T_30 = eq(io.typ, UInt<3>("h04")) node word = or(T_29, T_30) node T_33 = not(UInt<64>("h00")) node T_34 = bit(io.addr, 2) node T_35 = shl(T_34, 31) node mask = xor(T_33, T_35) node T_37 = and(io.lhs, mask) node T_38 = and(rhs, mask) node adder_out = addw(T_37, T_38) node T_40 = bit(io.addr, 2) node T_42 = eq(T_40, UInt<1>("h00")) node T_43 = and(word, T_42) node T_44 = bit(io.lhs, 31) node T_45 = bit(io.lhs, 63) node cmp_lhs = mux(T_43, T_44, T_45) node T_47 = bit(io.addr, 2) node T_49 = eq(T_47, UInt<1>("h00")) node T_50 = and(word, T_49) node T_51 = bit(rhs, 31) node T_52 = bit(rhs, 63) node cmp_rhs = mux(T_50, T_51, T_52) node T_54 = bits(io.lhs, 31, 0) node T_55 = bits(rhs, 31, 0) node lt_lo = lt(T_54, T_55) node T_57 = bits(io.lhs, 63, 32) node T_58 = bits(rhs, 63, 32) node lt_hi = lt(T_57, T_58) node T_60 = bits(io.lhs, 63, 32) node T_61 = bits(rhs, 63, 32) node eq_hi = eq(T_60, T_61) node T_63 = bit(io.addr, 2) node T_64 = mux(T_63, lt_hi, lt_lo) node T_65 = and(eq_hi, lt_lo) node T_66 = or(lt_hi, T_65) node lt = mux(word, T_64, T_66) node T_68 = eq(cmp_lhs, cmp_rhs) node T_69 = mux(sgned, cmp_lhs, cmp_rhs) node less = mux(T_68, lt, T_69) node T_71 = eq(io.cmd, UInt<5>("h08")) node T_72 = eq(io.cmd, UInt<5>("h0b")) node T_73 = and(io.lhs, rhs) node T_74 = eq(io.cmd, UInt<5>("h0a")) node T_75 = or(io.lhs, rhs) node T_76 = eq(io.cmd, UInt<5>("h09")) node T_77 = xor(io.lhs, rhs) node T_78 = mux(less, min, max) node T_80 = eq(T_10, UInt<1>("h00")) node T_81 = bits(io.rhs, 7, 0) node T_82 = cat(T_81, T_81) node T_83 = cat(T_82, T_82) node T_84 = cat(T_83, T_83) node T_86 = eq(T_10, UInt<1>("h01")) node T_87 = bits(io.rhs, 15, 0) node T_88 = cat(T_87, T_87) node T_89 = cat(T_88, T_88) node T_91 = eq(T_10, UInt<2>("h02")) node T_92 = bits(io.rhs, 31, 0) node T_93 = cat(T_92, T_92) node T_94 = mux(T_91, T_93, io.rhs) node T_95 = mux(T_86, T_89, T_94) node T_96 = mux(T_80, T_84, T_95) node T_97 = mux(T_78, io.lhs, T_96) node T_98 = mux(T_76, T_77, T_97) node T_99 = mux(T_74, T_75, T_98) node T_100 = mux(T_72, T_73, T_99) node out = mux(T_71, adder_out, T_100) node T_103 = bit(io.addr, 0) node T_105 = mux(T_103, UInt<1>("h01"), UInt<1>("h00")) node T_107 = geq(T_10, UInt<1>("h01")) node T_110 = mux(T_107, UInt<1>("h01"), UInt<1>("h00")) node T_111 = or(T_105, T_110) node T_112 = bit(io.addr, 0) node T_114 = mux(T_112, UInt<1>("h00"), UInt<1>("h01")) node T_115 = cat(T_111, T_114) node T_116 = bit(io.addr, 1) node T_118 = mux(T_116, T_115, UInt<1>("h00")) node T_120 = geq(T_10, UInt<2>("h02")) node T_123 = mux(T_120, UInt<2>("h03"), UInt<1>("h00")) node T_124 = or(T_118, T_123) node T_125 = bit(io.addr, 1) node T_127 = mux(T_125, UInt<1>("h00"), T_115) node T_128 = cat(T_124, T_127) node T_129 = bit(io.addr, 2) node T_131 = mux(T_129, T_128, UInt<1>("h00")) node T_133 = geq(T_10, UInt<2>("h03")) node T_136 = mux(T_133, UInt<4>("h0f"), UInt<1>("h00")) node T_137 = or(T_131, T_136) node T_138 = bit(io.addr, 2) node T_140 = mux(T_138, UInt<1>("h00"), T_128) node T_141 = cat(T_137, T_140) node T_142 = bit(T_141, 0) node T_143 = bit(T_141, 1) node T_144 = bit(T_141, 2) node T_145 = bit(T_141, 3) node T_146 = bit(T_141, 4) node T_147 = bit(T_141, 5) node T_148 = bit(T_141, 6) node T_149 = bit(T_141, 7) wire T_151 : UInt<1>[8] T_151[0] <= T_142 T_151[1] <= T_143 T_151[2] <= T_144 T_151[3] <= T_145 T_151[4] <= T_146 T_151[5] <= T_147 T_151[6] <= T_148 T_151[7] <= T_149 node T_162 = subw(UInt<8>("h00"), T_151[0]) node T_164 = subw(UInt<8>("h00"), T_151[1]) node T_166 = subw(UInt<8>("h00"), T_151[2]) node T_168 = subw(UInt<8>("h00"), T_151[3]) node T_170 = subw(UInt<8>("h00"), T_151[4]) node T_172 = subw(UInt<8>("h00"), T_151[5]) node T_174 = subw(UInt<8>("h00"), T_151[6]) node T_176 = subw(UInt<8>("h00"), T_151[7]) wire T_178 : UInt<8>[8] T_178[0] <= T_162 T_178[1] <= T_164 T_178[2] <= T_166 T_178[3] <= T_168 T_178[4] <= T_170 T_178[5] <= T_172 T_178[6] <= T_174 T_178[7] <= T_176 node T_188 = cat(T_178[7], T_178[6]) node T_189 = cat(T_178[5], T_178[4]) node T_190 = cat(T_188, T_189) node T_191 = cat(T_178[3], T_178[2]) node T_192 = cat(T_178[1], T_178[0]) node T_193 = cat(T_191, T_192) node wmask = cat(T_190, T_193) node T_195 = and(wmask, out) node T_196 = not(wmask) node T_197 = and(T_196, io.lhs) node T_198 = or(T_195, T_197) io.out <= T_198 module LockingArbiter_109 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.bits.r_type <= UInt<1>("h00") io.out.bits.voluntary <= UInt<1>("h00") io.out.bits.client_xact_id <= UInt<1>("h00") io.out.bits.addr_block <= UInt<1>("h00") io.out.bits.addr_beat <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") reg T_700 : UInt<1>, clk, reset, UInt<1>("h00") reg T_702 : UInt, clk, reset, UInt<1>("h01") wire T_704 : UInt<1> T_704 <= UInt<1>("h00") io.out.valid <= io.in[T_704].valid io.out.bits <- io.in[T_704].bits io.chosen <= T_704 io.in[T_704].ready <= UInt<1>("h00") node T_898 = or(UInt<1>("h00"), io.in[0].valid) node T_900 = eq(T_898, UInt<1>("h00")) node T_902 = eq(T_702, UInt<1>("h00")) node T_903 = mux(T_700, T_902, UInt<1>("h01")) node T_904 = and(T_903, io.out.ready) io.in[0].ready <= T_904 node T_906 = eq(T_702, UInt<1>("h01")) node T_907 = mux(T_700, T_906, T_900) node T_908 = and(T_907, io.out.ready) io.in[1].ready <= T_908 reg T_910 : UInt<2>, clk, reset, UInt<2>("h00") node T_912 = addw(T_910, UInt<1>("h01")) node T_913 = and(io.out.ready, io.out.valid) when T_913 : wire T_916 : UInt<2>[3] T_916[0] <= UInt<1>("h00") T_916[1] <= UInt<1>("h01") T_916[2] <= UInt<2>("h02") node T_921 = eq(T_916[0], io.out.bits.r_type) node T_922 = eq(T_916[1], io.out.bits.r_type) node T_923 = eq(T_916[2], io.out.bits.r_type) node T_925 = or(UInt<1>("h00"), T_921) node T_926 = or(T_925, T_922) node T_927 = or(T_926, T_923) node T_928 = and(UInt<1>("h01"), T_927) when T_928 : T_910 <= T_912 node T_930 = eq(T_700, UInt<1>("h00")) when T_930 : T_700 <= UInt<1>("h01") node T_932 = and(io.in[0].ready, io.in[0].valid) node T_933 = and(io.in[1].ready, io.in[1].valid) wire T_935 : UInt<1>[2] T_935[0] <= T_932 T_935[1] <= T_933 node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01")) T_702 <= T_941 skip skip node T_943 = eq(T_912, UInt<1>("h00")) when T_943 : T_700 <= UInt<1>("h00") skip skip node choose = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_948 = mux(T_700, T_702, choose) T_704 <= T_948 module HellaCache : input clk : Clock input reset : UInt<1> output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} io.mem.release.bits.data <= UInt<1>("h00") io.mem.release.bits.r_type <= UInt<1>("h00") io.mem.release.bits.voluntary <= UInt<1>("h00") io.mem.release.bits.client_xact_id <= UInt<1>("h00") io.mem.release.bits.addr_block <= UInt<1>("h00") io.mem.release.bits.addr_beat <= UInt<1>("h00") io.mem.release.valid <= UInt<1>("h00") io.mem.probe.ready <= UInt<1>("h00") io.mem.grant.ready <= UInt<1>("h00") io.mem.acquire.bits.data <= UInt<1>("h00") io.mem.acquire.bits.union <= UInt<1>("h00") io.mem.acquire.bits.a_type <= UInt<1>("h00") io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") io.mem.acquire.bits.addr_beat <= UInt<1>("h00") io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") io.mem.acquire.bits.addr_block <= UInt<1>("h00") io.mem.acquire.valid <= UInt<1>("h00") io.ptw.req.bits.fetch <= UInt<1>("h00") io.ptw.req.bits.store <= UInt<1>("h00") io.ptw.req.bits.prv <= UInt<1>("h00") io.ptw.req.bits.addr <= UInt<1>("h00") io.ptw.req.valid <= UInt<1>("h00") io.cpu.ordered <= UInt<1>("h00") io.cpu.xcpt.pf.st <= UInt<1>("h00") io.cpu.xcpt.pf.ld <= UInt<1>("h00") io.cpu.xcpt.ma.st <= UInt<1>("h00") io.cpu.xcpt.ma.ld <= UInt<1>("h00") io.cpu.replay_next.bits <= UInt<1>("h00") io.cpu.replay_next.valid <= UInt<1>("h00") io.cpu.resp.bits.store_data <= UInt<1>("h00") io.cpu.resp.bits.data_word_bypass <= UInt<1>("h00") io.cpu.resp.bits.has_data <= UInt<1>("h00") io.cpu.resp.bits.replay <= UInt<1>("h00") io.cpu.resp.bits.nack <= UInt<1>("h00") io.cpu.resp.bits.data <= UInt<1>("h00") io.cpu.resp.bits.typ <= UInt<1>("h00") io.cpu.resp.bits.cmd <= UInt<1>("h00") io.cpu.resp.bits.tag <= UInt<1>("h00") io.cpu.resp.bits.addr <= UInt<1>("h00") io.cpu.resp.valid <= UInt<1>("h00") io.cpu.req.ready <= UInt<1>("h00") inst wb of WritebackUnit wb.io.release.ready <= UInt<1>("h00") wb.io.data_resp <= UInt<1>("h00") wb.io.data_req.ready <= UInt<1>("h00") wb.io.meta_read.ready <= UInt<1>("h00") wb.io.req.bits.way_en <= UInt<1>("h00") wb.io.req.bits.data <= UInt<1>("h00") wb.io.req.bits.r_type <= UInt<1>("h00") wb.io.req.bits.voluntary <= UInt<1>("h00") wb.io.req.bits.client_xact_id <= UInt<1>("h00") wb.io.req.bits.addr_block <= UInt<1>("h00") wb.io.req.bits.addr_beat <= UInt<1>("h00") wb.io.req.valid <= UInt<1>("h00") wb.clk <= clk wb.reset <= reset inst prober of ProbeUnit prober.io.block_state.state <= UInt<1>("h00") prober.io.mshr_rdy <= UInt<1>("h00") prober.io.way_en <= UInt<1>("h00") prober.io.wb_req.ready <= UInt<1>("h00") prober.io.meta_write.ready <= UInt<1>("h00") prober.io.meta_read.ready <= UInt<1>("h00") prober.io.rep.ready <= UInt<1>("h00") prober.io.req.bits.client_xact_id <= UInt<1>("h00") prober.io.req.bits.p_type <= UInt<1>("h00") prober.io.req.bits.addr_block <= UInt<1>("h00") prober.io.req.valid <= UInt<1>("h00") prober.clk <= clk prober.reset <= reset inst mshrs of MSHRFile mshrs.io.wb_req.ready <= UInt<1>("h00") mshrs.io.mem_grant.bits.data <= UInt<1>("h00") mshrs.io.mem_grant.bits.g_type <= UInt<1>("h00") mshrs.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") mshrs.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") mshrs.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") mshrs.io.mem_grant.bits.addr_beat <= UInt<1>("h00") mshrs.io.mem_grant.valid <= UInt<1>("h00") mshrs.io.replay.ready <= UInt<1>("h00") mshrs.io.meta_write.ready <= UInt<1>("h00") mshrs.io.meta_read.ready <= UInt<1>("h00") mshrs.io.mem_req.ready <= UInt<1>("h00") mshrs.io.resp.ready <= UInt<1>("h00") mshrs.io.req.bits.way_en <= UInt<1>("h00") mshrs.io.req.bits.old_meta.coh.state <= UInt<1>("h00") mshrs.io.req.bits.old_meta.tag <= UInt<1>("h00") mshrs.io.req.bits.tag_match <= UInt<1>("h00") mshrs.io.req.bits.data <= UInt<1>("h00") mshrs.io.req.bits.phys <= UInt<1>("h00") mshrs.io.req.bits.kill <= UInt<1>("h00") mshrs.io.req.bits.typ <= UInt<1>("h00") mshrs.io.req.bits.cmd <= UInt<1>("h00") mshrs.io.req.bits.tag <= UInt<1>("h00") mshrs.io.req.bits.addr <= UInt<1>("h00") mshrs.io.req.valid <= UInt<1>("h00") mshrs.clk <= clk mshrs.reset <= reset io.cpu.req.ready <= UInt<1>("h01") node T_1670 = and(io.cpu.req.ready, io.cpu.req.valid) reg s1_valid : UInt<1>, clk, reset, UInt<1>("h00") s1_valid <= T_1670 reg s1_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s1_req node T_1728 = eq(io.cpu.req.bits.kill, UInt<1>("h00")) node s1_valid_masked = and(s1_valid, T_1728) reg s1_replay : UInt<1>, clk, reset, UInt<1>("h00") reg s1_clk_en : UInt<1>, clk, UInt<1>("h00"), s1_clk_en reg s2_valid : UInt<1>, clk, reset, UInt<1>("h00") s2_valid <= s1_valid_masked node T_1736 = and(s1_valid, io.cpu.req.bits.kill) reg s2_killed : UInt<1>, clk, UInt<1>("h00"), s2_killed s2_killed <= T_1736 reg s2_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s2_req reg T_1793 : UInt<1>, clk, reset, UInt<1>("h00") T_1793 <= s1_replay node T_1794 = neq(s2_req.cmd, UInt<5>("h05")) node s2_replay = and(T_1793, T_1794) wire s2_recycle : UInt<1> s2_recycle <= UInt<1>("h00") wire s2_valid_masked : UInt<1> s2_valid_masked <= UInt<1>("h00") reg s3_valid : UInt<1>, clk, reset, UInt<1>("h00") reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s3_req reg s3_way : UInt, clk, UInt<1>("h00"), s3_way reg s1_recycled : UInt<1>, clk, reset, UInt<1>("h00") when s1_clk_en : s1_recycled <= s2_recycle skip node T_1862 = eq(s1_req.cmd, UInt<5>("h00")) node T_1863 = eq(s1_req.cmd, UInt<5>("h06")) node T_1864 = or(T_1862, T_1863) node T_1865 = eq(s1_req.cmd, UInt<5>("h07")) node T_1866 = or(T_1864, T_1865) node T_1867 = bit(s1_req.cmd, 3) node T_1868 = eq(s1_req.cmd, UInt<5>("h04")) node T_1869 = or(T_1867, T_1868) node s1_read = or(T_1866, T_1869) node T_1871 = eq(s1_req.cmd, UInt<5>("h01")) node T_1872 = eq(s1_req.cmd, UInt<5>("h07")) node T_1873 = or(T_1871, T_1872) node T_1874 = bit(s1_req.cmd, 3) node T_1875 = eq(s1_req.cmd, UInt<5>("h04")) node T_1876 = or(T_1874, T_1875) node s1_write = or(T_1873, T_1876) node T_1878 = or(s1_read, s1_write) node T_1879 = eq(s1_req.cmd, UInt<5>("h02")) node T_1880 = eq(s1_req.cmd, UInt<5>("h03")) node T_1881 = or(T_1879, T_1880) node s1_readwrite = or(T_1878, T_1881) inst dtlb of TLB dtlb.io.ptw.invalidate <= UInt<1>("h00") dtlb.io.ptw.status.ie <= UInt<1>("h00") dtlb.io.ptw.status.prv <= UInt<1>("h00") dtlb.io.ptw.status.ie1 <= UInt<1>("h00") dtlb.io.ptw.status.prv1 <= UInt<1>("h00") dtlb.io.ptw.status.ie2 <= UInt<1>("h00") dtlb.io.ptw.status.prv2 <= UInt<1>("h00") dtlb.io.ptw.status.ie3 <= UInt<1>("h00") dtlb.io.ptw.status.prv3 <= UInt<1>("h00") dtlb.io.ptw.status.fs <= UInt<1>("h00") dtlb.io.ptw.status.xs <= UInt<1>("h00") dtlb.io.ptw.status.mprv <= UInt<1>("h00") dtlb.io.ptw.status.vm <= UInt<1>("h00") dtlb.io.ptw.status.zero1 <= UInt<1>("h00") dtlb.io.ptw.status.sd_rv32 <= UInt<1>("h00") dtlb.io.ptw.status.zero2 <= UInt<1>("h00") dtlb.io.ptw.status.sd <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.v <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.r <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.d <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") dtlb.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") dtlb.io.ptw.resp.bits.error <= UInt<1>("h00") dtlb.io.ptw.resp.valid <= UInt<1>("h00") dtlb.io.ptw.req.ready <= UInt<1>("h00") dtlb.io.req.bits.store <= UInt<1>("h00") dtlb.io.req.bits.instruction <= UInt<1>("h00") dtlb.io.req.bits.passthrough <= UInt<1>("h00") dtlb.io.req.bits.vpn <= UInt<1>("h00") dtlb.io.req.bits.asid <= UInt<1>("h00") dtlb.io.req.valid <= UInt<1>("h00") dtlb.clk <= clk dtlb.reset <= reset io.ptw <- dtlb.io.ptw node T_1916 = and(s1_valid_masked, s1_readwrite) node T_1918 = eq(s1_req.phys, UInt<1>("h00")) node T_1919 = and(T_1916, T_1918) dtlb.io.req.valid <= T_1919 dtlb.io.req.bits.passthrough <= s1_req.phys dtlb.io.req.bits.asid <= UInt<1>("h00") node T_1921 = shr(s1_req.addr, 12) dtlb.io.req.bits.vpn <= T_1921 dtlb.io.req.bits.instruction <= UInt<1>("h00") dtlb.io.req.bits.store <= s1_write node T_1924 = eq(dtlb.io.req.ready, UInt<1>("h00")) node T_1926 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) node T_1927 = and(T_1924, T_1926) when T_1927 : io.cpu.req.ready <= UInt<1>("h00") skip when io.cpu.req.valid : s1_req <- io.cpu.req.bits skip when wb.io.meta_read.valid : node T_1929 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) node T_1930 = shl(T_1929, 6) s1_req.addr <= T_1930 s1_req.phys <= UInt<1>("h01") skip when prober.io.meta_read.valid : node T_1932 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) node T_1933 = shl(T_1932, 6) s1_req.addr <= T_1933 s1_req.phys <= UInt<1>("h01") skip when mshrs.io.replay.valid : s1_req <- mshrs.io.replay.bits skip when s2_recycle : s1_req <- s2_req skip node T_1935 = bits(s1_req.addr, 11, 0) node s1_addr = cat(dtlb.io.resp.ppn, T_1935) when s1_clk_en : s2_req.kill <= s1_req.kill s2_req.typ <= s1_req.typ s2_req.phys <= s1_req.phys s2_req.addr <= s1_addr when s1_write : node T_1937 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) s2_req.data <= T_1937 skip when s1_recycled : s2_req.data <= s1_req.data skip s2_req.tag <= s1_req.tag s2_req.cmd <= s1_req.cmd skip node T_1939 = bits(s1_req.typ, 1, 0) node T_1941 = dshl(UInt<1>("h01"), T_1939) node T_1943 = subw(T_1941, UInt<1>("h01")) node T_1944 = bits(T_1943, 2, 0) node T_1945 = and(s1_req.addr, T_1944) node misaligned = neq(T_1945, UInt<1>("h00")) node T_1948 = and(s1_read, misaligned) io.cpu.xcpt.ma.ld <= T_1948 node T_1949 = and(s1_write, misaligned) io.cpu.xcpt.ma.st <= T_1949 node T_1950 = and(s1_read, dtlb.io.resp.xcpt_ld) io.cpu.xcpt.pf.ld <= T_1950 node T_1951 = and(s1_write, dtlb.io.resp.xcpt_st) io.cpu.xcpt.pf.st <= T_1951 node T_1952 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) node T_1953 = or(T_1952, io.cpu.xcpt.pf.ld) node T_1954 = or(T_1953, io.cpu.xcpt.pf.st) reg T_1955 : UInt<1>, clk, UInt<1>("h00"), T_1955 T_1955 <= T_1954 node T_1956 = and(T_1955, io.cpu.resp.valid) node T_1958 = eq(T_1956, UInt<1>("h00")) node T_1960 = eq(reset, UInt<1>("h00")) when T_1960 : node T_1962 = eq(T_1958, UInt<1>("h00")) when T_1962 : node T_1964 = eq(reset, UInt<1>("h00")) when T_1964 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.") skip stop(clk, UInt<1>(1), 1) skip skip inst meta of MetadataArray meta.io.write.bits.data.coh.state <= UInt<1>("h00") meta.io.write.bits.data.tag <= UInt<1>("h00") meta.io.write.bits.way_en <= UInt<1>("h00") meta.io.write.bits.idx <= UInt<1>("h00") meta.io.write.valid <= UInt<1>("h00") meta.io.read.bits.idx <= UInt<1>("h00") meta.io.read.valid <= UInt<1>("h00") meta.clk <= clk meta.reset <= reset inst metaReadArb of Arbiter_105 metaReadArb.io.out.ready <= UInt<1>("h00") metaReadArb.io.in[0].bits.idx <= UInt<1>("h00") metaReadArb.io.in[0].valid <= UInt<1>("h00") metaReadArb.io.in[1].bits.idx <= UInt<1>("h00") metaReadArb.io.in[1].valid <= UInt<1>("h00") metaReadArb.io.in[2].bits.idx <= UInt<1>("h00") metaReadArb.io.in[2].valid <= UInt<1>("h00") metaReadArb.io.in[3].bits.idx <= UInt<1>("h00") metaReadArb.io.in[3].valid <= UInt<1>("h00") metaReadArb.io.in[4].bits.idx <= UInt<1>("h00") metaReadArb.io.in[4].valid <= UInt<1>("h00") metaReadArb.clk <= clk metaReadArb.reset <= reset inst metaWriteArb of Arbiter_94 metaWriteArb.io.out.ready <= UInt<1>("h00") metaWriteArb.io.in[0].bits.data.coh.state <= UInt<1>("h00") metaWriteArb.io.in[0].bits.data.tag <= UInt<1>("h00") metaWriteArb.io.in[0].bits.way_en <= UInt<1>("h00") metaWriteArb.io.in[0].bits.idx <= UInt<1>("h00") metaWriteArb.io.in[0].valid <= UInt<1>("h00") metaWriteArb.io.in[1].bits.data.coh.state <= UInt<1>("h00") metaWriteArb.io.in[1].bits.data.tag <= UInt<1>("h00") metaWriteArb.io.in[1].bits.way_en <= UInt<1>("h00") metaWriteArb.io.in[1].bits.idx <= UInt<1>("h00") metaWriteArb.io.in[1].valid <= UInt<1>("h00") metaWriteArb.clk <= clk metaWriteArb.reset <= reset meta.io.read <- metaReadArb.io.out meta.io.write <- metaWriteArb.io.out inst data of DataArray data.io.write.bits.data <= UInt<1>("h00") data.io.write.bits.wmask <= UInt<1>("h00") data.io.write.bits.addr <= UInt<1>("h00") data.io.write.bits.way_en <= UInt<1>("h00") data.io.write.valid <= UInt<1>("h00") data.io.read.bits.addr <= UInt<1>("h00") data.io.read.bits.way_en <= UInt<1>("h00") data.io.read.valid <= UInt<1>("h00") data.clk <= clk data.reset <= reset inst readArb of Arbiter_107 readArb.io.out.ready <= UInt<1>("h00") readArb.io.in[0].bits.addr <= UInt<1>("h00") readArb.io.in[0].bits.way_en <= UInt<1>("h00") readArb.io.in[0].valid <= UInt<1>("h00") readArb.io.in[1].bits.addr <= UInt<1>("h00") readArb.io.in[1].bits.way_en <= UInt<1>("h00") readArb.io.in[1].valid <= UInt<1>("h00") readArb.io.in[2].bits.addr <= UInt<1>("h00") readArb.io.in[2].bits.way_en <= UInt<1>("h00") readArb.io.in[2].valid <= UInt<1>("h00") readArb.io.in[3].bits.addr <= UInt<1>("h00") readArb.io.in[3].bits.way_en <= UInt<1>("h00") readArb.io.in[3].valid <= UInt<1>("h00") readArb.clk <= clk readArb.reset <= reset inst writeArb of Arbiter_108 writeArb.io.out.ready <= UInt<1>("h00") writeArb.io.in[0].bits.data <= UInt<1>("h00") writeArb.io.in[0].bits.wmask <= UInt<1>("h00") writeArb.io.in[0].bits.addr <= UInt<1>("h00") writeArb.io.in[0].bits.way_en <= UInt<1>("h00") writeArb.io.in[0].valid <= UInt<1>("h00") writeArb.io.in[1].bits.data <= UInt<1>("h00") writeArb.io.in[1].bits.wmask <= UInt<1>("h00") writeArb.io.in[1].bits.addr <= UInt<1>("h00") writeArb.io.in[1].bits.way_en <= UInt<1>("h00") writeArb.io.in[1].valid <= UInt<1>("h00") writeArb.clk <= clk writeArb.reset <= reset data.io.write.valid <= writeArb.io.out.valid writeArb.io.out.ready <= data.io.write.ready data.io.write.bits <- writeArb.io.out.bits node T_2283 = bits(writeArb.io.out.bits.data, 63, 0) node T_2284 = bits(writeArb.io.out.bits.data, 127, 64) wire T_2286 : UInt<64>[2] T_2286[0] <= T_2283 T_2286[1] <= T_2284 node T_2290 = cat(T_2286[1], T_2286[0]) data.io.write.bits.data <= T_2290 metaReadArb.io.in[4].valid <= io.cpu.req.valid node T_2291 = shr(io.cpu.req.bits.addr, 6) metaReadArb.io.in[4].bits.idx <= T_2291 node T_2293 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00")) when T_2293 : io.cpu.req.ready <= UInt<1>("h00") skip readArb.io.in[3].valid <= io.cpu.req.valid readArb.io.in[3].bits.addr <= io.cpu.req.bits.addr node T_2296 = not(UInt<4>("h00")) readArb.io.in[3].bits.way_en <= T_2296 node T_2298 = eq(readArb.io.in[3].ready, UInt<1>("h00")) when T_2298 : io.cpu.req.ready <= UInt<1>("h00") skip metaReadArb.io.in[0].valid <= s2_recycle node T_2300 = shr(s2_req.addr, 6) metaReadArb.io.in[0].bits.idx <= T_2300 readArb.io.in[0].valid <= s2_recycle readArb.io.in[0].bits.addr <= s2_req.addr node T_2302 = not(UInt<4>("h00")) readArb.io.in[0].bits.way_en <= T_2302 node T_2303 = shr(s1_addr, 12) node T_2304 = eq(meta.io.resp[0].tag, T_2303) node T_2305 = shr(s1_addr, 12) node T_2306 = eq(meta.io.resp[1].tag, T_2305) node T_2307 = shr(s1_addr, 12) node T_2308 = eq(meta.io.resp[2].tag, T_2307) node T_2309 = shr(s1_addr, 12) node T_2310 = eq(meta.io.resp[3].tag, T_2309) wire T_2312 : UInt<1>[4] T_2312[0] <= T_2304 T_2312[1] <= T_2306 T_2312[2] <= T_2308 T_2312[3] <= T_2310 node T_2318 = cat(T_2312[3], T_2312[2]) node T_2319 = cat(T_2312[1], T_2312[0]) node s1_tag_eq_way = cat(T_2318, T_2319) node T_2321 = bit(s1_tag_eq_way, 0) node T_2322 = neq(meta.io.resp[0].coh.state, UInt<1>("h00")) node T_2323 = and(T_2321, T_2322) node T_2324 = bit(s1_tag_eq_way, 1) node T_2325 = neq(meta.io.resp[1].coh.state, UInt<1>("h00")) node T_2326 = and(T_2324, T_2325) node T_2327 = bit(s1_tag_eq_way, 2) node T_2328 = neq(meta.io.resp[2].coh.state, UInt<1>("h00")) node T_2329 = and(T_2327, T_2328) node T_2330 = bit(s1_tag_eq_way, 3) node T_2331 = neq(meta.io.resp[3].coh.state, UInt<1>("h00")) node T_2332 = and(T_2330, T_2331) wire T_2334 : UInt<1>[4] T_2334[0] <= T_2323 T_2334[1] <= T_2326 T_2334[2] <= T_2329 T_2334[3] <= T_2332 node T_2340 = cat(T_2334[3], T_2334[2]) node T_2341 = cat(T_2334[1], T_2334[0]) node s1_tag_match_way = cat(T_2340, T_2341) s1_clk_en <= metaReadArb.io.out.valid node T_2344 = eq(s1_valid, UInt<1>("h00")) node T_2345 = and(s1_clk_en, T_2344) node T_2347 = eq(s1_replay, UInt<1>("h00")) node s1_writeback = and(T_2345, T_2347) reg s2_tag_match_way : UInt<4>, clk, UInt<1>("h00"), s2_tag_match_way when s1_clk_en : s2_tag_match_way <= s1_tag_match_way skip node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) reg T_2352 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2352 when s1_clk_en : T_2352 <- meta.io.resp[0].coh skip reg T_2377 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2377 when s1_clk_en : T_2377 <- meta.io.resp[1].coh skip reg T_2402 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2402 when s1_clk_en : T_2402 <- meta.io.resp[2].coh skip reg T_2427 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2427 when s1_clk_en : T_2427 <- meta.io.resp[3].coh skip wire T_2477 : {state : UInt<2>}[4] T_2477[0] <- T_2352 T_2477[1] <- T_2377 T_2477[2] <- T_2402 T_2477[3] <- T_2427 node T_2603 = bit(s2_tag_match_way, 0) node T_2604 = bit(s2_tag_match_way, 1) node T_2605 = bit(s2_tag_match_way, 2) node T_2606 = bit(s2_tag_match_way, 3) node T_2608 = mux(T_2603, T_2477[0].state, UInt<1>("h00")) node T_2610 = mux(T_2604, T_2477[1].state, UInt<1>("h00")) node T_2612 = mux(T_2605, T_2477[2].state, UInt<1>("h00")) node T_2614 = mux(T_2606, T_2477[3].state, UInt<1>("h00")) node T_2640 = or(T_2608, T_2610) node T_2641 = or(T_2640, T_2612) node T_2642 = or(T_2641, T_2614) wire s2_hit_state : {state : UInt<2>} s2_hit_state.state <= UInt<1>("h00") node T_2694 = bits(T_2642, 1, 0) s2_hit_state.state <= T_2694 node T_2695 = eq(s2_req.cmd, UInt<5>("h01")) node T_2696 = eq(s2_req.cmd, UInt<5>("h07")) node T_2697 = or(T_2695, T_2696) node T_2698 = bit(s2_req.cmd, 3) node T_2699 = eq(s2_req.cmd, UInt<5>("h04")) node T_2700 = or(T_2698, T_2699) node T_2701 = or(T_2697, T_2700) node T_2702 = eq(s2_req.cmd, UInt<5>("h03")) node T_2703 = or(T_2701, T_2702) node T_2704 = eq(s2_req.cmd, UInt<5>("h06")) node T_2705 = or(T_2703, T_2704) wire T_2707 : UInt<2>[2] T_2707[0] <= UInt<2>("h02") T_2707[1] <= UInt<2>("h03") node T_2711 = eq(T_2707[0], s2_hit_state.state) node T_2712 = eq(T_2707[1], s2_hit_state.state) node T_2714 = or(UInt<1>("h00"), T_2711) node T_2715 = or(T_2714, T_2712) wire T_2717 : UInt<2>[3] T_2717[0] <= UInt<1>("h01") T_2717[1] <= UInt<2>("h02") T_2717[2] <= UInt<2>("h03") node T_2722 = eq(T_2717[0], s2_hit_state.state) node T_2723 = eq(T_2717[1], s2_hit_state.state) node T_2724 = eq(T_2717[2], s2_hit_state.state) node T_2726 = or(UInt<1>("h00"), T_2722) node T_2727 = or(T_2726, T_2723) node T_2728 = or(T_2727, T_2724) node T_2729 = mux(T_2705, T_2715, T_2728) node T_2730 = and(s2_tag_match, T_2729) node T_2731 = eq(s2_req.cmd, UInt<5>("h01")) node T_2732 = eq(s2_req.cmd, UInt<5>("h07")) node T_2733 = or(T_2731, T_2732) node T_2734 = bit(s2_req.cmd, 3) node T_2735 = eq(s2_req.cmd, UInt<5>("h04")) node T_2736 = or(T_2734, T_2735) node T_2737 = or(T_2733, T_2736) node T_2738 = mux(T_2737, UInt<2>("h03"), s2_hit_state.state) wire T_2764 : {state : UInt<2>} T_2764.state <= UInt<1>("h00") T_2764.state <= T_2738 node T_2790 = eq(s2_hit_state.state, T_2764.state) node s2_hit = and(T_2730, T_2790) reg lrsc_count : UInt, clk, reset, UInt<1>("h00") node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) reg lrsc_addr : UInt, clk, UInt<1>("h00"), lrsc_addr node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) node T_2800 = shr(s2_req.addr, 6) node T_2801 = eq(lrsc_addr, T_2800) node s2_lrsc_addr_match = and(lrsc_valid, T_2801) node T_2804 = eq(s2_lrsc_addr_match, UInt<1>("h00")) node s2_sc_fail = and(s2_sc, T_2804) when lrsc_valid : node T_2807 = subw(lrsc_count, UInt<1>("h01")) lrsc_count <= T_2807 skip node T_2808 = and(s2_valid_masked, s2_hit) node T_2809 = or(T_2808, s2_replay) when T_2809 : when s2_lr : node T_2811 = eq(lrsc_valid, UInt<1>("h00")) when T_2811 : lrsc_count <= UInt<5>("h01f") skip node T_2813 = shr(s2_req.addr, 6) lrsc_addr <= T_2813 skip when s2_sc : lrsc_count <= UInt<1>("h00") skip skip when io.cpu.invalidate_lr : lrsc_count <= UInt<1>("h00") skip wire s2_data : UInt<128>[4] s2_data[0] <= UInt<1>("h00") s2_data[1] <= UInt<1>("h00") s2_data[2] <= UInt<1>("h00") s2_data[3] <= UInt<1>("h00") reg T_2844 : UInt<64>[2], clk, UInt<1>("h00"), T_2844 node T_2848 = bit(s1_tag_eq_way, 0) node T_2849 = and(s1_clk_en, T_2848) node T_2853 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2854 = or(UInt<1>("h01"), T_2853) node T_2855 = or(T_2854, s1_writeback) node T_2856 = and(T_2849, T_2855) when T_2856 : node T_2857 = shr(data.io.resp[0], 0) T_2844[0] <= T_2857 skip node T_2861 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2862 = or(UInt<1>("h00"), T_2861) node T_2863 = or(T_2862, s1_writeback) node T_2864 = and(T_2849, T_2863) when T_2864 : node T_2865 = shr(data.io.resp[0], 64) T_2844[1] <= T_2865 skip node T_2866 = cat(T_2844[1], T_2844[0]) s2_data[0] <= T_2866 reg T_2875 : UInt<64>[2], clk, UInt<1>("h00"), T_2875 node T_2879 = bit(s1_tag_eq_way, 1) node T_2880 = and(s1_clk_en, T_2879) node T_2884 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2885 = or(UInt<1>("h01"), T_2884) node T_2886 = or(T_2885, s1_writeback) node T_2887 = and(T_2880, T_2886) when T_2887 : node T_2888 = shr(data.io.resp[1], 0) T_2875[0] <= T_2888 skip node T_2892 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2893 = or(UInt<1>("h00"), T_2892) node T_2894 = or(T_2893, s1_writeback) node T_2895 = and(T_2880, T_2894) when T_2895 : node T_2896 = shr(data.io.resp[1], 64) T_2875[1] <= T_2896 skip node T_2897 = cat(T_2875[1], T_2875[0]) s2_data[1] <= T_2897 reg T_2906 : UInt<64>[2], clk, UInt<1>("h00"), T_2906 node T_2910 = bit(s1_tag_eq_way, 2) node T_2911 = and(s1_clk_en, T_2910) node T_2915 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2916 = or(UInt<1>("h01"), T_2915) node T_2917 = or(T_2916, s1_writeback) node T_2918 = and(T_2911, T_2917) when T_2918 : node T_2919 = shr(data.io.resp[2], 0) T_2906[0] <= T_2919 skip node T_2923 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2924 = or(UInt<1>("h00"), T_2923) node T_2925 = or(T_2924, s1_writeback) node T_2926 = and(T_2911, T_2925) when T_2926 : node T_2927 = shr(data.io.resp[2], 64) T_2906[1] <= T_2927 skip node T_2928 = cat(T_2906[1], T_2906[0]) s2_data[2] <= T_2928 reg T_2937 : UInt<64>[2], clk, UInt<1>("h00"), T_2937 node T_2941 = bit(s1_tag_eq_way, 3) node T_2942 = and(s1_clk_en, T_2941) node T_2946 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2947 = or(UInt<1>("h01"), T_2946) node T_2948 = or(T_2947, s1_writeback) node T_2949 = and(T_2942, T_2948) when T_2949 : node T_2950 = shr(data.io.resp[3], 0) T_2937[0] <= T_2950 skip node T_2954 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_2955 = or(UInt<1>("h00"), T_2954) node T_2956 = or(T_2955, s1_writeback) node T_2957 = and(T_2942, T_2956) when T_2957 : node T_2958 = shr(data.io.resp[3], 64) T_2937[1] <= T_2958 skip node T_2959 = cat(T_2937[1], T_2937[0]) s2_data[3] <= T_2959 node T_2960 = bit(s2_tag_match_way, 0) node T_2961 = bit(s2_tag_match_way, 1) node T_2962 = bit(s2_tag_match_way, 2) node T_2963 = bit(s2_tag_match_way, 3) node T_2965 = mux(T_2960, s2_data[0], UInt<1>("h00")) node T_2967 = mux(T_2961, s2_data[1], UInt<1>("h00")) node T_2969 = mux(T_2962, s2_data[2], UInt<1>("h00")) node T_2971 = mux(T_2963, s2_data[3], UInt<1>("h00")) node T_2973 = or(T_2965, T_2967) node T_2974 = or(T_2973, T_2969) node T_2975 = or(T_2974, T_2971) wire s2_data_muxed : UInt<128> s2_data_muxed <= UInt<1>("h00") s2_data_muxed <= T_2975 node T_2978 = bits(s2_data_muxed, 63, 0) node T_2979 = bits(s2_data_muxed, 127, 64) wire T_2981 : UInt<64>[2] T_2981[0] <= T_2978 T_2981[1] <= T_2979 node s2_data_corrected = cat(T_2981[1], T_2981[0]) wire T_2987 : UInt<64>[2] T_2987[0] <= T_2978 T_2987[1] <= T_2979 node s2_data_uncorrected = cat(T_2987[1], T_2987[0]) wire T_2996 : UInt<1>[2] T_2996[0] <= UInt<1>("h00") T_2996[1] <= UInt<1>("h00") node T_3000 = cat(T_2996[1], T_2996[0]) node T_3001 = dshr(T_3000, UInt<1>("h00")) node s2_data_correctable = bit(T_3001, 0) node T_3003 = and(s2_valid_masked, s2_hit) node T_3004 = or(T_3003, s2_replay) node T_3006 = eq(s2_sc_fail, UInt<1>("h00")) node T_3007 = and(T_3004, T_3006) node T_3008 = eq(s2_req.cmd, UInt<5>("h01")) node T_3009 = eq(s2_req.cmd, UInt<5>("h07")) node T_3010 = or(T_3008, T_3009) node T_3011 = bit(s2_req.cmd, 3) node T_3012 = eq(s2_req.cmd, UInt<5>("h04")) node T_3013 = or(T_3011, T_3012) node T_3014 = or(T_3010, T_3013) node T_3015 = and(T_3007, T_3014) s3_valid <= T_3015 inst amoalu of AMOALU amoalu.io.rhs <= UInt<1>("h00") amoalu.io.lhs <= UInt<1>("h00") amoalu.io.typ <= UInt<1>("h00") amoalu.io.cmd <= UInt<1>("h00") amoalu.io.addr <= UInt<1>("h00") amoalu.clk <= clk amoalu.reset <= reset node T_3022 = or(s2_valid, s2_replay) node T_3023 = eq(s2_req.cmd, UInt<5>("h01")) node T_3024 = eq(s2_req.cmd, UInt<5>("h07")) node T_3025 = or(T_3023, T_3024) node T_3026 = bit(s2_req.cmd, 3) node T_3027 = eq(s2_req.cmd, UInt<5>("h04")) node T_3028 = or(T_3026, T_3027) node T_3029 = or(T_3025, T_3028) node T_3030 = or(T_3029, s2_data_correctable) node T_3031 = and(T_3022, T_3030) when T_3031 : s3_req <- s2_req node T_3032 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) s3_req.data <= T_3032 s3_way <= s2_tag_match_way skip writeArb.io.in[0].bits.addr <= s3_req.addr node rowIdx = bits(s3_req.addr, 3, 3) node rowWMask = dshl(UInt<1>("h01"), rowIdx) writeArb.io.in[0].bits.wmask <= rowWMask node T_3036 = cat(s3_req.data, s3_req.data) writeArb.io.in[0].bits.data <= T_3036 writeArb.io.in[0].valid <= s3_valid writeArb.io.in[0].bits.way_en <= s3_way wire T_3038 : UInt<1> T_3038 <= UInt<1>("h00") T_3038 <= UInt<1>("h00") reg T_3042 : UInt<16>, clk, reset, UInt<16>("h01") when T_3038 : node T_3043 = bit(T_3042, 0) node T_3044 = bit(T_3042, 2) node T_3045 = xor(T_3043, T_3044) node T_3046 = bit(T_3042, 3) node T_3047 = xor(T_3045, T_3046) node T_3048 = bit(T_3042, 5) node T_3049 = xor(T_3047, T_3048) node T_3050 = bits(T_3042, 15, 1) node T_3051 = cat(T_3049, T_3050) T_3042 <= T_3051 skip node T_3052 = bits(T_3042, 1, 0) node s1_replaced_way_en = dshl(UInt<1>("h01"), T_3052) node T_3055 = bits(T_3042, 1, 0) reg T_3056 : UInt<2>, clk, UInt<1>("h00"), T_3056 when s1_clk_en : T_3056 <= T_3055 skip node s2_replaced_way_en = dshl(UInt<1>("h01"), T_3056) node T_3059 = bit(s1_replaced_way_en, 0) node T_3060 = and(s1_clk_en, T_3059) reg T_3061 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3061 when T_3060 : T_3061 <- meta.io.resp[0] skip node T_3134 = bit(s1_replaced_way_en, 1) node T_3135 = and(s1_clk_en, T_3134) reg T_3136 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3136 when T_3135 : T_3136 <- meta.io.resp[1] skip node T_3209 = bit(s1_replaced_way_en, 2) node T_3210 = and(s1_clk_en, T_3209) reg T_3211 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3211 when T_3210 : T_3211 <- meta.io.resp[2] skip node T_3284 = bit(s1_replaced_way_en, 3) node T_3285 = and(s1_clk_en, T_3284) reg T_3286 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3286 when T_3285 : T_3286 <- meta.io.resp[3] skip wire T_3432 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] T_3432[0] <- T_3061 T_3432[1] <- T_3136 T_3432[2] <- T_3211 T_3432[3] <- T_3286 node T_3798 = bit(s2_replaced_way_en, 0) node T_3799 = bit(s2_replaced_way_en, 1) node T_3800 = bit(s2_replaced_way_en, 2) node T_3801 = bit(s2_replaced_way_en, 3) node T_3802 = cat(T_3432[0].tag, T_3432[0].coh.state) node T_3804 = mux(T_3798, T_3802, UInt<1>("h00")) node T_3805 = cat(T_3432[1].tag, T_3432[1].coh.state) node T_3807 = mux(T_3799, T_3805, UInt<1>("h00")) node T_3808 = cat(T_3432[2].tag, T_3432[2].coh.state) node T_3810 = mux(T_3800, T_3808, UInt<1>("h00")) node T_3811 = cat(T_3432[3].tag, T_3432[3].coh.state) node T_3813 = mux(T_3801, T_3811, UInt<1>("h00")) node T_3887 = or(T_3804, T_3807) node T_3888 = or(T_3887, T_3810) node T_3889 = or(T_3888, T_3813) wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} s2_repl_meta.coh.state <= UInt<1>("h00") s2_repl_meta.tag <= UInt<1>("h00") node T_4038 = bits(T_3889, 1, 0) s2_repl_meta.coh.state <= T_4038 node T_4039 = bits(T_3889, 21, 2) s2_repl_meta.tag <= T_4039 node T_4041 = eq(s2_hit, UInt<1>("h00")) node T_4042 = and(s2_valid_masked, T_4041) node T_4043 = eq(s2_req.cmd, UInt<5>("h02")) node T_4044 = eq(s2_req.cmd, UInt<5>("h03")) node T_4045 = or(T_4043, T_4044) node T_4046 = eq(s2_req.cmd, UInt<5>("h00")) node T_4047 = eq(s2_req.cmd, UInt<5>("h06")) node T_4048 = or(T_4046, T_4047) node T_4049 = eq(s2_req.cmd, UInt<5>("h07")) node T_4050 = or(T_4048, T_4049) node T_4051 = bit(s2_req.cmd, 3) node T_4052 = eq(s2_req.cmd, UInt<5>("h04")) node T_4053 = or(T_4051, T_4052) node T_4054 = or(T_4050, T_4053) node T_4055 = or(T_4045, T_4054) node T_4056 = eq(s2_req.cmd, UInt<5>("h01")) node T_4057 = eq(s2_req.cmd, UInt<5>("h07")) node T_4058 = or(T_4056, T_4057) node T_4059 = bit(s2_req.cmd, 3) node T_4060 = eq(s2_req.cmd, UInt<5>("h04")) node T_4061 = or(T_4059, T_4060) node T_4062 = or(T_4058, T_4061) node T_4063 = or(T_4055, T_4062) node T_4064 = and(T_4042, T_4063) mshrs.io.req.valid <= T_4064 mshrs.io.req.bits <- s2_req mshrs.io.req.bits.tag_match <= s2_tag_match wire T_4138 : {tag : UInt<20>, coh : {state : UInt<2>}} T_4138.coh.state <= UInt<1>("h00") T_4138.tag <= UInt<1>("h00") T_4138.tag <= s2_repl_meta.tag T_4138.coh <- s2_hit_state wire T_4286 : {tag : UInt<20>, coh : {state : UInt<2>}} T_4286 <- s2_repl_meta when s2_tag_match : T_4286 <- T_4138 skip mshrs.io.req.bits.old_meta <- T_4286 node T_4359 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) mshrs.io.req.bits.way_en <= T_4359 mshrs.io.req.bits.data <= s2_req.data node T_4360 = and(mshrs.io.req.ready, mshrs.io.req.valid) when T_4360 : T_3038 <= UInt<1>("h01") skip io.mem.acquire <- mshrs.io.mem_req readArb.io.in[1].valid <= mshrs.io.replay.valid readArb.io.in[1].bits <- mshrs.io.replay.bits node T_4363 = not(UInt<4>("h00")) readArb.io.in[1].bits.way_en <= T_4363 mshrs.io.replay.ready <= readArb.io.in[1].ready node T_4364 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) s1_replay <= T_4364 metaReadArb.io.in[1] <- mshrs.io.meta_read metaWriteArb.io.in[0] <- mshrs.io.meta_write inst releaseArb of LockingArbiter_109 releaseArb.io.out.ready <= UInt<1>("h00") releaseArb.io.in[0].bits.data <= UInt<1>("h00") releaseArb.io.in[0].bits.r_type <= UInt<1>("h00") releaseArb.io.in[0].bits.voluntary <= UInt<1>("h00") releaseArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") releaseArb.io.in[0].bits.addr_block <= UInt<1>("h00") releaseArb.io.in[0].bits.addr_beat <= UInt<1>("h00") releaseArb.io.in[0].valid <= UInt<1>("h00") releaseArb.io.in[1].bits.data <= UInt<1>("h00") releaseArb.io.in[1].bits.r_type <= UInt<1>("h00") releaseArb.io.in[1].bits.voluntary <= UInt<1>("h00") releaseArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") releaseArb.io.in[1].bits.addr_block <= UInt<1>("h00") releaseArb.io.in[1].bits.addr_beat <= UInt<1>("h00") releaseArb.io.in[1].valid <= UInt<1>("h00") releaseArb.clk <= clk releaseArb.reset <= reset io.mem.release <- releaseArb.io.out node T_4412 = eq(lrsc_valid, UInt<1>("h00")) node T_4413 = and(io.mem.probe.valid, T_4412) prober.io.req.valid <= T_4413 node T_4415 = eq(lrsc_valid, UInt<1>("h00")) node T_4416 = and(prober.io.req.ready, T_4415) io.mem.probe.ready <= T_4416 prober.io.req.bits <- io.mem.probe.bits releaseArb.io.in[1] <- prober.io.rep prober.io.way_en <= s2_tag_match_way prober.io.block_state <- s2_hit_state metaReadArb.io.in[2] <- prober.io.meta_read metaWriteArb.io.in[1] <- prober.io.meta_write prober.io.mshr_rdy <= mshrs.io.probe_rdy inst T_4417 of FlowThroughSerializer T_4417.io.out.ready <= UInt<1>("h00") T_4417.io.in.bits.data <= UInt<1>("h00") T_4417.io.in.bits.g_type <= UInt<1>("h00") T_4417.io.in.bits.is_builtin_type <= UInt<1>("h00") T_4417.io.in.bits.manager_xact_id <= UInt<1>("h00") T_4417.io.in.bits.client_xact_id <= UInt<1>("h00") T_4417.io.in.bits.addr_beat <= UInt<1>("h00") T_4417.io.in.valid <= UInt<1>("h00") T_4417.clk <= clk T_4417.reset <= reset T_4417.io.in.valid <= io.mem.grant.valid T_4417.io.in.bits <- io.mem.grant.bits io.mem.grant.ready <= T_4417.io.in.ready node T_4426 = and(T_4417.io.out.ready, T_4417.io.out.valid) mshrs.io.mem_grant.valid <= T_4426 mshrs.io.mem_grant.bits <- T_4417.io.out.bits wire T_4430 : UInt<3>[2] T_4430[0] <= UInt<3>("h05") T_4430[1] <= UInt<3>("h04") node T_4434 = eq(T_4430[0], T_4417.io.out.bits.g_type) node T_4435 = eq(T_4430[1], T_4417.io.out.bits.g_type) node T_4437 = or(UInt<1>("h00"), T_4434) node T_4438 = or(T_4437, T_4435) wire T_4440 : UInt<1>[2] T_4440[0] <= UInt<1>("h00") T_4440[1] <= UInt<1>("h01") node T_4444 = eq(T_4440[0], T_4417.io.out.bits.g_type) node T_4445 = eq(T_4440[1], T_4417.io.out.bits.g_type) node T_4447 = or(UInt<1>("h00"), T_4444) node T_4448 = or(T_4447, T_4445) node T_4449 = mux(T_4417.io.out.bits.is_builtin_type, T_4438, T_4448) node T_4451 = eq(T_4449, UInt<1>("h00")) node T_4452 = or(writeArb.io.in[1].ready, T_4451) T_4417.io.out.ready <= T_4452 wire T_4456 : UInt<3>[2] T_4456[0] <= UInt<3>("h05") T_4456[1] <= UInt<3>("h04") node T_4460 = eq(T_4456[0], T_4417.io.out.bits.g_type) node T_4461 = eq(T_4456[1], T_4417.io.out.bits.g_type) node T_4463 = or(UInt<1>("h00"), T_4460) node T_4464 = or(T_4463, T_4461) wire T_4466 : UInt<1>[2] T_4466[0] <= UInt<1>("h00") T_4466[1] <= UInt<1>("h01") node T_4470 = eq(T_4466[0], T_4417.io.out.bits.g_type) node T_4471 = eq(T_4466[1], T_4417.io.out.bits.g_type) node T_4473 = or(UInt<1>("h00"), T_4470) node T_4474 = or(T_4473, T_4471) node T_4475 = mux(T_4417.io.out.bits.is_builtin_type, T_4464, T_4474) node T_4476 = and(T_4417.io.out.valid, T_4475) node T_4478 = lt(T_4417.io.out.bits.client_xact_id, UInt<2>("h02")) node T_4479 = and(T_4476, T_4478) writeArb.io.in[1].valid <= T_4479 writeArb.io.in[1].bits.addr <= mshrs.io.refill.addr writeArb.io.in[1].bits.way_en <= mshrs.io.refill.way_en node T_4481 = not(UInt<2>("h00")) writeArb.io.in[1].bits.wmask <= T_4481 node T_4482 = bits(T_4417.io.out.bits.data, 127, 0) writeArb.io.in[1].bits.data <= T_4482 data.io.read <- readArb.io.out node T_4484 = eq(T_4417.io.out.valid, UInt<1>("h00")) node T_4485 = or(T_4484, T_4417.io.out.ready) readArb.io.out.ready <= T_4485 inst wbArb of Arbiter_95 wbArb.io.out.ready <= UInt<1>("h00") wbArb.io.in[0].bits.way_en <= UInt<1>("h00") wbArb.io.in[0].bits.data <= UInt<1>("h00") wbArb.io.in[0].bits.r_type <= UInt<1>("h00") wbArb.io.in[0].bits.voluntary <= UInt<1>("h00") wbArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") wbArb.io.in[0].bits.addr_block <= UInt<1>("h00") wbArb.io.in[0].bits.addr_beat <= UInt<1>("h00") wbArb.io.in[0].valid <= UInt<1>("h00") wbArb.io.in[1].bits.way_en <= UInt<1>("h00") wbArb.io.in[1].bits.data <= UInt<1>("h00") wbArb.io.in[1].bits.r_type <= UInt<1>("h00") wbArb.io.in[1].bits.voluntary <= UInt<1>("h00") wbArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") wbArb.io.in[1].bits.addr_block <= UInt<1>("h00") wbArb.io.in[1].bits.addr_beat <= UInt<1>("h00") wbArb.io.in[1].valid <= UInt<1>("h00") wbArb.clk <= clk wbArb.reset <= reset wbArb.io.in[0] <- prober.io.wb_req wbArb.io.in[1] <- mshrs.io.wb_req wb.io.req <- wbArb.io.out metaReadArb.io.in[3] <- wb.io.meta_read readArb.io.in[2] <- wb.io.data_req wb.io.data_resp <= s2_data_corrected releaseArb.io.in[0] <- wb.io.release reg s4_valid : UInt<1>, clk, reset, UInt<1>("h00") s4_valid <= s3_valid node T_4537 = and(s3_valid, metaReadArb.io.out.valid) reg s4_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s4_req when T_4537 : s4_req <- s3_req skip node T_4592 = or(s2_valid_masked, s2_replay) node T_4594 = eq(s2_sc_fail, UInt<1>("h00")) node T_4595 = and(T_4592, T_4594) node T_4596 = shr(s1_addr, 3) node T_4597 = shr(s2_req.addr, 3) node T_4598 = eq(T_4596, T_4597) node T_4599 = and(T_4595, T_4598) node T_4600 = eq(s2_req.cmd, UInt<5>("h01")) node T_4601 = eq(s2_req.cmd, UInt<5>("h07")) node T_4602 = or(T_4600, T_4601) node T_4603 = bit(s2_req.cmd, 3) node T_4604 = eq(s2_req.cmd, UInt<5>("h04")) node T_4605 = or(T_4603, T_4604) node T_4606 = or(T_4602, T_4605) node T_4607 = and(T_4599, T_4606) node T_4608 = shr(s1_addr, 3) node T_4609 = shr(s3_req.addr, 3) node T_4610 = eq(T_4608, T_4609) node T_4611 = and(s3_valid, T_4610) node T_4612 = eq(s3_req.cmd, UInt<5>("h01")) node T_4613 = eq(s3_req.cmd, UInt<5>("h07")) node T_4614 = or(T_4612, T_4613) node T_4615 = bit(s3_req.cmd, 3) node T_4616 = eq(s3_req.cmd, UInt<5>("h04")) node T_4617 = or(T_4615, T_4616) node T_4618 = or(T_4614, T_4617) node T_4619 = and(T_4611, T_4618) node T_4620 = shr(s1_addr, 3) node T_4621 = shr(s4_req.addr, 3) node T_4622 = eq(T_4620, T_4621) node T_4623 = and(s4_valid, T_4622) node T_4624 = eq(s4_req.cmd, UInt<5>("h01")) node T_4625 = eq(s4_req.cmd, UInt<5>("h07")) node T_4626 = or(T_4624, T_4625) node T_4627 = bit(s4_req.cmd, 3) node T_4628 = eq(s4_req.cmd, UInt<5>("h04")) node T_4629 = or(T_4627, T_4628) node T_4630 = or(T_4626, T_4629) node T_4631 = and(T_4623, T_4630) reg s2_store_bypass_data : UInt<64>, clk, UInt<1>("h00"), s2_store_bypass_data reg s2_store_bypass : UInt<1>, clk, UInt<1>("h00"), s2_store_bypass when s1_clk_en : s2_store_bypass <= UInt<1>("h00") node T_4637 = or(T_4607, T_4619) node T_4638 = or(T_4637, T_4631) when T_4638 : node T_4639 = mux(T_4619, s3_req.data, s4_req.data) node T_4640 = mux(T_4607, amoalu.io.out, T_4639) s2_store_bypass_data <= T_4640 s2_store_bypass <= UInt<1>("h01") skip skip node T_4643 = cat(UInt<1>("h00"), UInt<6>("h00")) node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4643) node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) node T_4646 = bits(s2_req.typ, 1, 0) node T_4647 = asSInt(s2_req.typ) node T_4649 = geq(T_4647, asSInt(UInt<1>("h00"))) amoalu.io.addr <= s2_req.addr amoalu.io.cmd <= s2_req.cmd amoalu.io.typ <= s2_req.typ amoalu.io.lhs <= s2_data_word amoalu.io.rhs <= s2_req.data node T_4650 = and(dtlb.io.req.valid, dtlb.io.resp.miss) node T_4651 = bits(s1_req.addr, 11, 6) node T_4652 = eq(T_4651, prober.io.meta_write.bits.idx) node T_4654 = eq(prober.io.req.ready, UInt<1>("h00")) node T_4655 = and(T_4652, T_4654) node s1_nack = or(T_4650, T_4655) node T_4657 = or(s1_valid, s1_replay) reg s2_nack_hit : UInt<1>, clk, UInt<1>("h00"), s2_nack_hit when T_4657 : s2_nack_hit <= s1_nack skip when s2_nack_hit : mshrs.io.req.valid <= UInt<1>("h00") skip node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss) node T_4662 = eq(s2_hit, UInt<1>("h00")) node T_4664 = eq(mshrs.io.req.ready, UInt<1>("h00")) node s2_nack_miss = and(T_4662, T_4664) node T_4666 = or(s2_nack_hit, s2_nack_victim) node s2_nack = or(T_4666, s2_nack_miss) node T_4669 = eq(s2_nack, UInt<1>("h00")) node T_4670 = and(s2_valid, T_4669) s2_valid_masked <= T_4670 node T_4671 = or(s2_valid, s2_replay) node T_4672 = and(T_4671, s2_hit) node s2_recycle_ecc = and(T_4672, s2_data_correctable) reg s2_recycle_next : UInt<1>, clk, reset, UInt<1>("h00") node T_4676 = or(s1_valid, s1_replay) when T_4676 : s2_recycle_next <= s2_recycle_ecc skip node T_4677 = or(s2_recycle_ecc, s2_recycle_next) s2_recycle <= T_4677 reg block_miss : UInt<1>, clk, reset, UInt<1>("h00") node T_4680 = or(s2_valid, block_miss) node T_4681 = and(T_4680, s2_nack_miss) block_miss <= T_4681 when block_miss : io.cpu.req.ready <= UInt<1>("h00") skip wire cache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} cache_resp.bits.store_data <= UInt<1>("h00") cache_resp.bits.data_word_bypass <= UInt<1>("h00") cache_resp.bits.has_data <= UInt<1>("h00") cache_resp.bits.replay <= UInt<1>("h00") cache_resp.bits.nack <= UInt<1>("h00") cache_resp.bits.data <= UInt<1>("h00") cache_resp.bits.typ <= UInt<1>("h00") cache_resp.bits.cmd <= UInt<1>("h00") cache_resp.bits.tag <= UInt<1>("h00") cache_resp.bits.addr <= UInt<1>("h00") cache_resp.valid <= UInt<1>("h00") node T_4983 = and(s2_valid_masked, s2_hit) node T_4984 = or(s2_replay, T_4983) node T_4986 = eq(s2_data_correctable, UInt<1>("h00")) node T_4987 = and(T_4984, T_4986) cache_resp.valid <= T_4987 cache_resp.bits <- s2_req node T_4988 = eq(s2_req.cmd, UInt<5>("h00")) node T_4989 = eq(s2_req.cmd, UInt<5>("h06")) node T_4990 = or(T_4988, T_4989) node T_4991 = eq(s2_req.cmd, UInt<5>("h07")) node T_4992 = or(T_4990, T_4991) node T_4993 = bit(s2_req.cmd, 3) node T_4994 = eq(s2_req.cmd, UInt<5>("h04")) node T_4995 = or(T_4993, T_4994) node T_4996 = or(T_4992, T_4995) cache_resp.bits.has_data <= T_4996 node T_4997 = bit(s2_req.addr, 2) node T_4998 = bits(s2_data_word, 63, 32) node T_4999 = bits(s2_data_word, 31, 0) node T_5000 = mux(T_4997, T_4998, T_4999) node T_5002 = and(UInt<1>("h00"), s2_sc) node T_5004 = mux(T_5002, UInt<1>("h00"), T_5000) node T_5006 = eq(T_4646, UInt<2>("h02")) node T_5007 = or(T_5006, T_5002) node T_5008 = bit(T_5004, 31) node T_5009 = and(T_4649, T_5008) node T_5011 = subw(UInt<32>("h00"), T_5009) node T_5012 = bits(s2_data_word, 63, 32) node T_5013 = mux(T_5007, T_5011, T_5012) node T_5014 = cat(T_5013, T_5004) node T_5015 = bit(s2_req.addr, 1) node T_5016 = bits(T_5014, 31, 16) node T_5017 = bits(T_5014, 15, 0) node T_5018 = mux(T_5015, T_5016, T_5017) node T_5020 = and(UInt<1>("h00"), s2_sc) node T_5022 = mux(T_5020, UInt<1>("h00"), T_5018) node T_5024 = eq(T_4646, UInt<1>("h01")) node T_5025 = or(T_5024, T_5020) node T_5026 = bit(T_5022, 15) node T_5027 = and(T_4649, T_5026) node T_5029 = subw(UInt<48>("h00"), T_5027) node T_5030 = bits(T_5014, 63, 16) node T_5031 = mux(T_5025, T_5029, T_5030) node T_5032 = cat(T_5031, T_5022) node T_5033 = bit(s2_req.addr, 0) node T_5034 = bits(T_5032, 15, 8) node T_5035 = bits(T_5032, 7, 0) node T_5036 = mux(T_5033, T_5034, T_5035) node T_5038 = and(UInt<1>("h01"), s2_sc) node T_5040 = mux(T_5038, UInt<1>("h00"), T_5036) node T_5042 = eq(T_4646, UInt<1>("h00")) node T_5043 = or(T_5042, T_5038) node T_5044 = bit(T_5040, 7) node T_5045 = and(T_4649, T_5044) node T_5047 = subw(UInt<56>("h00"), T_5045) node T_5048 = bits(T_5032, 63, 8) node T_5049 = mux(T_5043, T_5047, T_5048) node T_5050 = cat(T_5049, T_5040) node T_5051 = or(T_5050, s2_sc_fail) cache_resp.bits.data <= T_5051 cache_resp.bits.store_data <= s2_req.data node T_5052 = and(s2_valid, s2_nack) cache_resp.bits.nack <= T_5052 cache_resp.bits.replay <= s2_replay wire uncache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} uncache_resp.bits.store_data <= UInt<1>("h00") uncache_resp.bits.data_word_bypass <= UInt<1>("h00") uncache_resp.bits.has_data <= UInt<1>("h00") uncache_resp.bits.replay <= UInt<1>("h00") uncache_resp.bits.nack <= UInt<1>("h00") uncache_resp.bits.data <= UInt<1>("h00") uncache_resp.bits.typ <= UInt<1>("h00") uncache_resp.bits.cmd <= UInt<1>("h00") uncache_resp.bits.tag <= UInt<1>("h00") uncache_resp.bits.addr <= UInt<1>("h00") uncache_resp.valid <= UInt<1>("h00") uncache_resp.bits <- mshrs.io.resp.bits uncache_resp.valid <= mshrs.io.resp.valid node T_5353 = or(s2_valid, s2_killed) node cache_pass = or(T_5353, s2_replay) node T_5356 = eq(cache_pass, UInt<1>("h00")) mshrs.io.resp.ready <= T_5356 wire T_5473 : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} T_5473 <- uncache_resp when cache_pass : T_5473 <- cache_resp skip io.cpu.resp <- T_5473 node T_5589 = bit(s2_req.addr, 2) node T_5590 = bits(s2_data_word, 63, 32) node T_5591 = bits(s2_data_word, 31, 0) node T_5592 = mux(T_5589, T_5590, T_5591) node T_5594 = and(UInt<1>("h00"), s2_sc) node T_5596 = mux(T_5594, UInt<1>("h00"), T_5592) node T_5598 = eq(T_4646, UInt<2>("h02")) node T_5599 = or(T_5598, T_5594) node T_5600 = bit(T_5596, 31) node T_5601 = and(T_4649, T_5600) node T_5603 = subw(UInt<32>("h00"), T_5601) node T_5604 = bits(s2_data_word, 63, 32) node T_5605 = mux(T_5599, T_5603, T_5604) node T_5606 = cat(T_5605, T_5596) io.cpu.resp.bits.data_word_bypass <= T_5606 node T_5608 = eq(s1_valid, UInt<1>("h00")) node T_5609 = and(mshrs.io.fence_rdy, T_5608) node T_5611 = eq(s2_valid, UInt<1>("h00")) node T_5612 = and(T_5609, T_5611) io.cpu.ordered <= T_5612 node T_5613 = and(s1_replay, s1_read) io.cpu.replay_next.valid <= T_5613 io.cpu.replay_next.bits <= s1_req.tag module RRArbiter_112 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} io.chosen <= UInt<1>("h00") io.out.bits.fetch <= UInt<1>("h00") io.out.bits.store <= UInt<1>("h00") io.out.bits.prv <= UInt<1>("h00") io.out.bits.addr <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.in[0].ready <= UInt<1>("h00") io.in[1].ready <= UInt<1>("h00") wire T_152 : UInt<1> T_152 <= UInt<1>("h00") io.out.valid <= io.in[T_152].valid io.out.bits <- io.in[T_152].bits io.chosen <= T_152 io.in[T_152].ready <= UInt<1>("h00") reg T_196 : UInt<1>, clk, reset, UInt<1>("h00") node T_197 = gt(UInt<1>("h00"), T_196) node T_198 = and(io.in[0].valid, T_197) node T_200 = gt(UInt<1>("h01"), T_196) node T_201 = and(io.in[1].valid, T_200) node T_204 = or(UInt<1>("h00"), T_198) node T_206 = eq(T_204, UInt<1>("h00")) node T_208 = or(UInt<1>("h00"), T_198) node T_209 = or(T_208, T_201) node T_211 = eq(T_209, UInt<1>("h00")) node T_213 = or(UInt<1>("h00"), T_198) node T_214 = or(T_213, T_201) node T_215 = or(T_214, io.in[0].valid) node T_217 = eq(T_215, UInt<1>("h00")) node T_219 = gt(UInt<1>("h00"), T_196) node T_220 = and(UInt<1>("h01"), T_219) node T_221 = or(T_220, T_211) node T_223 = gt(UInt<1>("h01"), T_196) node T_224 = and(T_206, T_223) node T_225 = or(T_224, T_217) node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) node T_228 = mux(UInt<1>("h00"), T_227, T_221) node T_229 = and(T_228, io.out.ready) io.in[0].ready <= T_229 node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) node T_232 = mux(UInt<1>("h00"), T_231, T_225) node T_233 = and(T_232, io.out.ready) io.in[1].ready <= T_233 node T_236 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) node T_238 = gt(UInt<1>("h01"), T_196) node T_239 = and(io.in[1].valid, T_238) node T_241 = mux(T_239, UInt<1>("h01"), T_236) node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) T_152 <= T_242 node T_243 = and(io.out.ready, io.out.valid) when T_243 : T_196 <= T_152 skip module PTW : input clk : Clock input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}} io.mem.invalidate_lr <= UInt<1>("h00") io.mem.req.bits.data <= UInt<1>("h00") io.mem.req.bits.phys <= UInt<1>("h00") io.mem.req.bits.kill <= UInt<1>("h00") io.mem.req.bits.typ <= UInt<1>("h00") io.mem.req.bits.cmd <= UInt<1>("h00") io.mem.req.bits.tag <= UInt<1>("h00") io.mem.req.bits.addr <= UInt<1>("h00") io.mem.req.valid <= UInt<1>("h00") io.requestor[0].invalidate <= UInt<1>("h00") io.requestor[0].status.ie <= UInt<1>("h00") io.requestor[0].status.prv <= UInt<1>("h00") io.requestor[0].status.ie1 <= UInt<1>("h00") io.requestor[0].status.prv1 <= UInt<1>("h00") io.requestor[0].status.ie2 <= UInt<1>("h00") io.requestor[0].status.prv2 <= UInt<1>("h00") io.requestor[0].status.ie3 <= UInt<1>("h00") io.requestor[0].status.prv3 <= UInt<1>("h00") io.requestor[0].status.fs <= UInt<1>("h00") io.requestor[0].status.xs <= UInt<1>("h00") io.requestor[0].status.mprv <= UInt<1>("h00") io.requestor[0].status.vm <= UInt<1>("h00") io.requestor[0].status.zero1 <= UInt<1>("h00") io.requestor[0].status.sd_rv32 <= UInt<1>("h00") io.requestor[0].status.zero2 <= UInt<1>("h00") io.requestor[0].status.sd <= UInt<1>("h00") io.requestor[0].resp.bits.pte.v <= UInt<1>("h00") io.requestor[0].resp.bits.pte.typ <= UInt<1>("h00") io.requestor[0].resp.bits.pte.r <= UInt<1>("h00") io.requestor[0].resp.bits.pte.d <= UInt<1>("h00") io.requestor[0].resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.requestor[0].resp.bits.pte.ppn <= UInt<1>("h00") io.requestor[0].resp.bits.error <= UInt<1>("h00") io.requestor[0].resp.valid <= UInt<1>("h00") io.requestor[0].req.ready <= UInt<1>("h00") io.requestor[1].invalidate <= UInt<1>("h00") io.requestor[1].status.ie <= UInt<1>("h00") io.requestor[1].status.prv <= UInt<1>("h00") io.requestor[1].status.ie1 <= UInt<1>("h00") io.requestor[1].status.prv1 <= UInt<1>("h00") io.requestor[1].status.ie2 <= UInt<1>("h00") io.requestor[1].status.prv2 <= UInt<1>("h00") io.requestor[1].status.ie3 <= UInt<1>("h00") io.requestor[1].status.prv3 <= UInt<1>("h00") io.requestor[1].status.fs <= UInt<1>("h00") io.requestor[1].status.xs <= UInt<1>("h00") io.requestor[1].status.mprv <= UInt<1>("h00") io.requestor[1].status.vm <= UInt<1>("h00") io.requestor[1].status.zero1 <= UInt<1>("h00") io.requestor[1].status.sd_rv32 <= UInt<1>("h00") io.requestor[1].status.zero2 <= UInt<1>("h00") io.requestor[1].status.sd <= UInt<1>("h00") io.requestor[1].resp.bits.pte.v <= UInt<1>("h00") io.requestor[1].resp.bits.pte.typ <= UInt<1>("h00") io.requestor[1].resp.bits.pte.r <= UInt<1>("h00") io.requestor[1].resp.bits.pte.d <= UInt<1>("h00") io.requestor[1].resp.bits.pte.reserved_for_software <= UInt<1>("h00") io.requestor[1].resp.bits.pte.ppn <= UInt<1>("h00") io.requestor[1].resp.bits.error <= UInt<1>("h00") io.requestor[1].resp.valid <= UInt<1>("h00") io.requestor[1].req.ready <= UInt<1>("h00") reg state : UInt, clk, reset, UInt<1>("h00") reg count : UInt<2>, clk, UInt<1>("h00"), count reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk, UInt<1>("h00"), r_req reg r_req_dest : UInt, clk, UInt<1>("h00"), r_req_dest reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk, UInt<1>("h00"), r_pte node T_1590 = shr(r_req.addr, 18) node T_1591 = bits(T_1590, 8, 0) node T_1592 = shr(r_req.addr, 9) node T_1593 = bits(T_1592, 8, 0) node T_1594 = shr(r_req.addr, 0) node T_1595 = bits(T_1594, 8, 0) wire T_1597 : UInt<9>[3] T_1597[0] <= T_1591 T_1597[1] <= T_1593 T_1597[2] <= T_1595 inst arb of RRArbiter_112 arb.io.out.ready <= UInt<1>("h00") arb.io.in[0].bits.fetch <= UInt<1>("h00") arb.io.in[0].bits.store <= UInt<1>("h00") arb.io.in[0].bits.prv <= UInt<1>("h00") arb.io.in[0].bits.addr <= UInt<1>("h00") arb.io.in[0].valid <= UInt<1>("h00") arb.io.in[1].bits.fetch <= UInt<1>("h00") arb.io.in[1].bits.store <= UInt<1>("h00") arb.io.in[1].bits.prv <= UInt<1>("h00") arb.io.in[1].bits.addr <= UInt<1>("h00") arb.io.in[1].valid <= UInt<1>("h00") arb.clk <= clk arb.reset <= reset arb.io.in[0] <- io.requestor[0].req arb.io.in[1] <- io.requestor[1].req node T_1620 = eq(state, UInt<1>("h00")) arb.io.out.ready <= T_1620 wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} pte.v <= UInt<1>("h00") pte.typ <= UInt<1>("h00") pte.r <= UInt<1>("h00") pte.d <= UInt<1>("h00") pte.reserved_for_software <= UInt<1>("h00") pte.ppn <= UInt<1>("h00") node T_1648 = bits(io.mem.resp.bits.data, 0, 0) pte.v <= T_1648 node T_1649 = bits(io.mem.resp.bits.data, 4, 1) pte.typ <= T_1649 node T_1650 = bits(io.mem.resp.bits.data, 5, 5) pte.r <= T_1650 node T_1651 = bits(io.mem.resp.bits.data, 6, 6) pte.d <= T_1651 node T_1652 = bits(io.mem.resp.bits.data, 9, 7) pte.reserved_for_software <= T_1652 node T_1653 = bits(io.mem.resp.bits.data, 29, 10) pte.ppn <= T_1653 node T_1654 = cat(r_pte.ppn, T_1597[count]) node pte_addr = shl(T_1654, 3) node T_1656 = and(arb.io.out.ready, arb.io.out.valid) when T_1656 : r_req <- arb.io.out.bits r_req_dest <= arb.io.chosen node T_1657 = bits(io.dpath.ptbr, 31, 12) r_pte.ppn <= T_1657 skip reg T_1659 : UInt<3>, clk, UInt<1>("h00"), T_1659 reg T_1669 : UInt<1>[3], clk, UInt<1>("h00"), T_1669 node T_1674 = cat(T_1669[1], T_1669[0]) node T_1675 = cat(T_1669[2], T_1674) cmem T_1678 : UInt<32>[3] cmem T_1681 : UInt<20>[3] infer mport T_1683 = T_1678[UInt<1>("h00")], clk node T_1684 = eq(T_1683, pte_addr) infer mport T_1686 = T_1678[UInt<1>("h01")], clk node T_1687 = eq(T_1686, pte_addr) infer mport T_1689 = T_1678[UInt<2>("h02")], clk node T_1690 = eq(T_1689, pte_addr) wire T_1692 : UInt<1>[3] T_1692[0] <= T_1684 T_1692[1] <= T_1687 T_1692[2] <= T_1690 node T_1697 = cat(T_1692[1], T_1692[0]) node T_1698 = cat(T_1692[2], T_1697) node T_1699 = and(T_1698, T_1675) node pte_cache_hit = neq(T_1699, UInt<1>("h00")) node T_1703 = lt(pte.typ, UInt<2>("h02")) node T_1704 = and(pte.v, T_1703) node T_1705 = and(io.mem.resp.valid, T_1704) node T_1707 = eq(pte_cache_hit, UInt<1>("h00")) node T_1708 = and(T_1705, T_1707) when T_1708 : node T_1709 = not(T_1675) node T_1711 = eq(T_1709, UInt<1>("h00")) node T_1713 = dshr(T_1659, UInt<1>("h01")) node T_1714 = bit(T_1713, 0) node T_1715 = cat(UInt<1>("h01"), T_1714) node T_1716 = dshr(T_1659, T_1715) node T_1717 = bit(T_1716, 0) node T_1718 = cat(T_1715, T_1717) node T_1719 = bits(T_1718, 1, 0) node T_1720 = not(T_1675) node T_1721 = bit(T_1720, 0) node T_1722 = bit(T_1720, 1) node T_1723 = bit(T_1720, 2) wire T_1725 : UInt<1>[3] T_1725[0] <= T_1721 T_1725[1] <= T_1722 T_1725[2] <= T_1723 node T_1733 = mux(T_1725[1], UInt<1>("h01"), UInt<2>("h02")) node T_1734 = mux(T_1725[0], UInt<1>("h00"), T_1733) node T_1735 = mux(T_1711, T_1719, T_1734) T_1669[T_1735] <= UInt<1>("h01") infer mport T_1738 = T_1678[T_1735], clk T_1738 <= pte_addr infer mport T_1739 = T_1681[T_1735], clk T_1739 <= pte.ppn skip node T_1740 = eq(state, UInt<1>("h01")) node T_1741 = and(pte_cache_hit, T_1740) when T_1741 : node T_1742 = bits(T_1699, 2, 2) node T_1743 = bits(T_1699, 1, 0) node T_1745 = neq(T_1742, UInt<1>("h00")) node T_1746 = or(T_1742, T_1743) node T_1747 = bit(T_1746, 1) node T_1748 = cat(T_1745, T_1747) node T_1750 = bit(T_1748, 1) node T_1752 = dshl(UInt<3>("h01"), UInt<1>("h01")) node T_1753 = bits(T_1752, 2, 0) node T_1754 = not(T_1753) node T_1755 = and(T_1659, T_1754) node T_1757 = mux(T_1750, UInt<1>("h00"), T_1753) node T_1758 = or(T_1755, T_1757) node T_1759 = cat(UInt<1>("h01"), T_1750) node T_1760 = bit(T_1748, 0) node T_1762 = dshl(UInt<3>("h01"), T_1759) node T_1763 = bits(T_1762, 2, 0) node T_1764 = not(T_1763) node T_1765 = and(T_1758, T_1764) node T_1767 = mux(T_1760, UInt<1>("h00"), T_1763) node T_1768 = or(T_1765, T_1767) node T_1769 = cat(T_1759, T_1760) T_1659 <= T_1768 skip node T_1770 = or(reset, io.dpath.invalidate) when T_1770 : T_1669[0] <= UInt<1>("h00") T_1669[1] <= UInt<1>("h00") T_1669[2] <= UInt<1>("h00") skip node T_1774 = bit(T_1699, 0) node T_1775 = bit(T_1699, 1) node T_1776 = bit(T_1699, 2) infer mport T_1778 = T_1681[UInt<1>("h00")], clk infer mport T_1780 = T_1681[UInt<1>("h01")], clk infer mport T_1782 = T_1681[UInt<2>("h02")], clk node T_1784 = mux(T_1774, T_1778, UInt<1>("h00")) node T_1786 = mux(T_1775, T_1780, UInt<1>("h00")) node T_1788 = mux(T_1776, T_1782, UInt<1>("h00")) node T_1790 = or(T_1784, T_1786) node T_1791 = or(T_1790, T_1788) wire pte_cache_data : UInt<20> pte_cache_data <= UInt<1>("h00") pte_cache_data <= T_1791 node T_1794 = bit(r_req.prv, 0) node T_1796 = geq(pte.typ, UInt<3>("h04")) node T_1797 = and(pte.v, T_1796) node T_1798 = bit(pte.typ, 1) node T_1799 = and(T_1797, T_1798) node T_1801 = geq(pte.typ, UInt<2>("h02")) node T_1802 = and(pte.v, T_1801) node T_1803 = bit(pte.typ, 0) node T_1804 = and(T_1802, T_1803) node T_1806 = geq(pte.typ, UInt<2>("h02")) node T_1807 = and(pte.v, T_1806) node T_1808 = mux(r_req.store, T_1804, T_1807) node T_1809 = mux(r_req.fetch, T_1799, T_1808) node T_1811 = geq(pte.typ, UInt<2>("h02")) node T_1812 = and(pte.v, T_1811) node T_1814 = lt(pte.typ, UInt<4>("h08")) node T_1815 = and(T_1812, T_1814) node T_1816 = bit(pte.typ, 1) node T_1817 = and(T_1815, T_1816) node T_1819 = geq(pte.typ, UInt<2>("h02")) node T_1820 = and(pte.v, T_1819) node T_1822 = lt(pte.typ, UInt<4>("h08")) node T_1823 = and(T_1820, T_1822) node T_1824 = bit(pte.typ, 0) node T_1825 = and(T_1823, T_1824) node T_1827 = geq(pte.typ, UInt<2>("h02")) node T_1828 = and(pte.v, T_1827) node T_1830 = lt(pte.typ, UInt<4>("h08")) node T_1831 = and(T_1828, T_1830) node T_1832 = mux(r_req.store, T_1825, T_1831) node T_1833 = mux(r_req.fetch, T_1817, T_1832) node perm_ok = mux(T_1794, T_1809, T_1833) node T_1836 = eq(pte.r, UInt<1>("h00")) node T_1838 = eq(pte.d, UInt<1>("h00")) node T_1839 = and(r_req.store, T_1838) node T_1840 = or(T_1836, T_1839) node set_dirty_bit = and(perm_ok, T_1840) node T_1842 = eq(state, UInt<2>("h02")) node T_1843 = and(io.mem.resp.valid, T_1842) node T_1845 = eq(set_dirty_bit, UInt<1>("h00")) node T_1846 = and(T_1843, T_1845) when T_1846 : r_pte <- pte skip wire T_1862 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} T_1862.v <= UInt<1>("h00") T_1862.typ <= UInt<1>("h00") T_1862.r <= UInt<1>("h00") T_1862.d <= UInt<1>("h00") T_1862.reserved_for_software <= UInt<1>("h00") T_1862.ppn <= UInt<1>("h00") T_1862.v <= UInt<1>("h00") T_1862.typ <= UInt<4>("h00") T_1862.r <= UInt<1>("h00") T_1862.d <= UInt<1>("h00") T_1862.reserved_for_software <= UInt<3>("h00") T_1862.ppn <= UInt<20>("h00") wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} pte_wdata <- T_1862 pte_wdata.r <= UInt<1>("h01") pte_wdata.d <= r_req.store node T_1889 = eq(state, UInt<1>("h01")) node T_1890 = eq(state, UInt<2>("h03")) node T_1891 = or(T_1889, T_1890) io.mem.req.valid <= T_1891 io.mem.req.bits.phys <= UInt<1>("h01") node T_1893 = eq(state, UInt<2>("h03")) node T_1894 = mux(T_1893, UInt<5>("h0a"), UInt<5>("h00")) io.mem.req.bits.cmd <= T_1894 io.mem.req.bits.typ <= UInt<3>("h03") io.mem.req.bits.addr <= pte_addr io.mem.req.bits.kill <= UInt<1>("h00") node T_1896 = cat(pte_wdata.reserved_for_software, pte_wdata.d) node T_1897 = cat(pte_wdata.ppn, T_1896) node T_1898 = cat(pte_wdata.typ, pte_wdata.v) node T_1899 = cat(pte_wdata.r, T_1898) node T_1900 = cat(T_1897, T_1899) io.mem.req.bits.data <= T_1900 node resp_err = eq(state, UInt<3>("h06")) node T_1902 = eq(state, UInt<3>("h05")) node resp_val = or(T_1902, resp_err) node r_resp_ppn = shr(io.mem.req.bits.addr, 12) node T_1905 = shr(r_resp_ppn, 18) node T_1906 = bits(r_req.addr, 17, 0) node T_1907 = cat(T_1905, T_1906) node T_1908 = shr(r_resp_ppn, 9) node T_1909 = bits(r_req.addr, 8, 0) node T_1910 = cat(T_1908, T_1909) wire T_1912 : UInt<28>[3] T_1912[0] <= T_1907 T_1912[1] <= T_1910 T_1912[2] <= r_resp_ppn node T_1919 = eq(r_req_dest, UInt<1>("h00")) node T_1920 = and(resp_val, T_1919) io.requestor[0].resp.valid <= T_1920 io.requestor[0].resp.bits.error <= resp_err io.requestor[0].resp.bits.pte <- r_pte io.requestor[0].resp.bits.pte.ppn <= T_1912[count] io.requestor[0].invalidate <= io.dpath.invalidate io.requestor[0].status <- io.dpath.status node T_1922 = eq(r_req_dest, UInt<1>("h01")) node T_1923 = and(resp_val, T_1922) io.requestor[1].resp.valid <= T_1923 io.requestor[1].resp.bits.error <= resp_err io.requestor[1].resp.bits.pte <- r_pte io.requestor[1].resp.bits.pte.ppn <= T_1912[count] io.requestor[1].invalidate <= io.dpath.invalidate io.requestor[1].status <- io.dpath.status node T_1924 = eq(UInt<1>("h00"), state) when T_1924 : when arb.io.out.valid : state <= UInt<1>("h01") skip count <= UInt<1>("h00") skip node T_1926 = eq(UInt<1>("h01"), state) when T_1926 : node T_1928 = lt(count, UInt<2>("h02")) node T_1929 = and(pte_cache_hit, T_1928) when T_1929 : io.mem.req.valid <= UInt<1>("h00") state <= UInt<1>("h01") node T_1932 = addw(count, UInt<1>("h01")) count <= T_1932 r_pte.ppn <= pte_cache_data skip node T_1934 = eq(T_1929, UInt<1>("h00")) node T_1935 = and(T_1934, io.mem.req.ready) when T_1935 : state <= UInt<2>("h02") skip skip node T_1936 = eq(UInt<2>("h02"), state) when T_1936 : when io.mem.resp.bits.nack : state <= UInt<1>("h01") skip when io.mem.resp.valid : state <= UInt<3>("h06") node T_1938 = lt(pte.typ, UInt<2>("h02")) node T_1939 = and(pte.v, T_1938) node T_1941 = lt(count, UInt<2>("h02")) node T_1942 = and(T_1939, T_1941) when T_1942 : state <= UInt<1>("h01") node T_1944 = addw(count, UInt<1>("h01")) count <= T_1944 skip node T_1946 = geq(pte.typ, UInt<2>("h02")) node T_1947 = and(pte.v, T_1946) when T_1947 : node T_1948 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) state <= T_1948 skip skip skip node T_1949 = eq(UInt<2>("h03"), state) when T_1949 : when io.mem.req.ready : state <= UInt<3>("h04") skip skip node T_1950 = eq(UInt<3>("h04"), state) when T_1950 : when io.mem.resp.bits.nack : state <= UInt<2>("h03") skip when io.mem.resp.valid : state <= UInt<1>("h01") skip skip node T_1951 = eq(UInt<3>("h05"), state) when T_1951 : state <= UInt<1>("h00") skip node T_1952 = eq(UInt<3>("h06"), state) when T_1952 : state <= UInt<1>("h00") skip module HellaCacheArbiter : input clk : Clock input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} io.mem.invalidate_lr <= UInt<1>("h00") io.mem.req.bits.data <= UInt<1>("h00") io.mem.req.bits.phys <= UInt<1>("h00") io.mem.req.bits.kill <= UInt<1>("h00") io.mem.req.bits.typ <= UInt<1>("h00") io.mem.req.bits.cmd <= UInt<1>("h00") io.mem.req.bits.tag <= UInt<1>("h00") io.mem.req.bits.addr <= UInt<1>("h00") io.mem.req.valid <= UInt<1>("h00") io.requestor[0].ordered <= UInt<1>("h00") io.requestor[0].xcpt.pf.st <= UInt<1>("h00") io.requestor[0].xcpt.pf.ld <= UInt<1>("h00") io.requestor[0].xcpt.ma.st <= UInt<1>("h00") io.requestor[0].xcpt.ma.ld <= UInt<1>("h00") io.requestor[0].replay_next.bits <= UInt<1>("h00") io.requestor[0].replay_next.valid <= UInt<1>("h00") io.requestor[0].resp.bits.store_data <= UInt<1>("h00") io.requestor[0].resp.bits.data_word_bypass <= UInt<1>("h00") io.requestor[0].resp.bits.has_data <= UInt<1>("h00") io.requestor[0].resp.bits.replay <= UInt<1>("h00") io.requestor[0].resp.bits.nack <= UInt<1>("h00") io.requestor[0].resp.bits.data <= UInt<1>("h00") io.requestor[0].resp.bits.typ <= UInt<1>("h00") io.requestor[0].resp.bits.cmd <= UInt<1>("h00") io.requestor[0].resp.bits.tag <= UInt<1>("h00") io.requestor[0].resp.bits.addr <= UInt<1>("h00") io.requestor[0].resp.valid <= UInt<1>("h00") io.requestor[0].req.ready <= UInt<1>("h00") io.requestor[1].ordered <= UInt<1>("h00") io.requestor[1].xcpt.pf.st <= UInt<1>("h00") io.requestor[1].xcpt.pf.ld <= UInt<1>("h00") io.requestor[1].xcpt.ma.st <= UInt<1>("h00") io.requestor[1].xcpt.ma.ld <= UInt<1>("h00") io.requestor[1].replay_next.bits <= UInt<1>("h00") io.requestor[1].replay_next.valid <= UInt<1>("h00") io.requestor[1].resp.bits.store_data <= UInt<1>("h00") io.requestor[1].resp.bits.data_word_bypass <= UInt<1>("h00") io.requestor[1].resp.bits.has_data <= UInt<1>("h00") io.requestor[1].resp.bits.replay <= UInt<1>("h00") io.requestor[1].resp.bits.nack <= UInt<1>("h00") io.requestor[1].resp.bits.data <= UInt<1>("h00") io.requestor[1].resp.bits.typ <= UInt<1>("h00") io.requestor[1].resp.bits.cmd <= UInt<1>("h00") io.requestor[1].resp.bits.tag <= UInt<1>("h00") io.requestor[1].resp.bits.addr <= UInt<1>("h00") io.requestor[1].resp.valid <= UInt<1>("h00") io.requestor[1].req.ready <= UInt<1>("h00") reg T_5286 : UInt<1>, clk, UInt<1>("h00"), T_5286 T_5286 <= io.requestor[0].req.valid reg T_5287 : UInt<1>, clk, UInt<1>("h00"), T_5287 T_5287 <= io.requestor[1].req.valid node T_5288 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) io.mem.req.valid <= T_5288 io.requestor[0].req.ready <= io.mem.req.ready node T_5290 = eq(io.requestor[0].req.valid, UInt<1>("h00")) node T_5291 = and(io.requestor[0].req.ready, T_5290) io.requestor[1].req.ready <= T_5291 io.mem.req.bits <- io.requestor[1].req.bits node T_5293 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01")) io.mem.req.bits.tag <= T_5293 when io.requestor[0].req.valid : io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd io.mem.req.bits.typ <= io.requestor[0].req.bits.typ io.mem.req.bits.addr <= io.requestor[0].req.bits.addr io.mem.req.bits.phys <= io.requestor[0].req.bits.phys node T_5295 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00")) io.mem.req.bits.tag <= T_5295 skip when T_5286 : io.mem.req.bits.kill <= io.requestor[0].req.bits.kill io.mem.req.bits.data <= io.requestor[0].req.bits.data skip node T_5296 = bits(io.mem.resp.bits.tag, 0, 0) node T_5298 = eq(T_5296, UInt<1>("h00")) node T_5299 = and(io.mem.resp.valid, T_5298) io.requestor[0].resp.valid <= T_5299 io.requestor[0].xcpt <- io.mem.xcpt io.requestor[0].ordered <= io.mem.ordered io.requestor[0].resp.bits <- io.mem.resp.bits node T_5300 = shr(io.mem.resp.bits.tag, 1) io.requestor[0].resp.bits.tag <= T_5300 node T_5301 = and(io.mem.resp.bits.nack, T_5298) io.requestor[0].resp.bits.nack <= T_5301 node T_5302 = and(io.mem.resp.bits.replay, T_5298) io.requestor[0].resp.bits.replay <= T_5302 node T_5303 = bits(io.mem.replay_next.bits, 0, 0) node T_5305 = eq(T_5303, UInt<1>("h00")) node T_5306 = and(io.mem.replay_next.valid, T_5305) io.requestor[0].replay_next.valid <= T_5306 node T_5307 = shr(io.mem.replay_next.bits, 1) io.requestor[0].replay_next.bits <= T_5307 node T_5308 = bits(io.mem.resp.bits.tag, 0, 0) node T_5310 = eq(T_5308, UInt<1>("h01")) node T_5311 = and(io.mem.resp.valid, T_5310) io.requestor[1].resp.valid <= T_5311 io.requestor[1].xcpt <- io.mem.xcpt io.requestor[1].ordered <= io.mem.ordered io.requestor[1].resp.bits <- io.mem.resp.bits node T_5312 = shr(io.mem.resp.bits.tag, 1) io.requestor[1].resp.bits.tag <= T_5312 node T_5313 = and(io.mem.resp.bits.nack, T_5310) io.requestor[1].resp.bits.nack <= T_5313 node T_5314 = and(io.mem.resp.bits.replay, T_5310) io.requestor[1].resp.bits.replay <= T_5314 node T_5315 = bits(io.mem.replay_next.bits, 0, 0) node T_5317 = eq(T_5315, UInt<1>("h01")) node T_5318 = and(io.mem.replay_next.valid, T_5317) io.requestor[1].replay_next.valid <= T_5318 node T_5319 = shr(io.mem.replay_next.bits, 1) io.requestor[1].replay_next.bits <= T_5319 module FPUDecoder : input clk : Clock input reset : UInt<1> output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} io.sigs.wflags <= UInt<1>("h00") io.sigs.round <= UInt<1>("h00") io.sigs.sqrt <= UInt<1>("h00") io.sigs.div <= UInt<1>("h00") io.sigs.fma <= UInt<1>("h00") io.sigs.fastpipe <= UInt<1>("h00") io.sigs.toint <= UInt<1>("h00") io.sigs.fromint <= UInt<1>("h00") io.sigs.single <= UInt<1>("h00") io.sigs.swap23 <= UInt<1>("h00") io.sigs.swap12 <= UInt<1>("h00") io.sigs.ren3 <= UInt<1>("h00") io.sigs.ren2 <= UInt<1>("h00") io.sigs.ren1 <= UInt<1>("h00") io.sigs.wen <= UInt<1>("h00") io.sigs.ldst <= UInt<1>("h00") io.sigs.cmd <= UInt<1>("h00") node T_42 = and(io.inst, UInt<32>("h04")) node T_44 = eq(T_42, UInt<32>("h04")) node T_46 = and(io.inst, UInt<32>("h08000010")) node T_48 = eq(T_46, UInt<32>("h08000010")) node T_50 = or(UInt<1>("h00"), T_44) node T_51 = or(T_50, T_48) node T_53 = and(io.inst, UInt<32>("h08")) node T_55 = eq(T_53, UInt<32>("h08")) node T_57 = and(io.inst, UInt<32>("h010000010")) node T_59 = eq(T_57, UInt<32>("h010000010")) node T_61 = or(UInt<1>("h00"), T_55) node T_62 = or(T_61, T_59) node T_64 = and(io.inst, UInt<32>("h040")) node T_66 = eq(T_64, UInt<32>("h00")) node T_68 = and(io.inst, UInt<32>("h020000000")) node T_70 = eq(T_68, UInt<32>("h020000000")) node T_72 = or(UInt<1>("h00"), T_66) node T_73 = or(T_72, T_70) node T_75 = and(io.inst, UInt<32>("h040000000")) node T_77 = eq(T_75, UInt<32>("h040000000")) node T_79 = or(UInt<1>("h00"), T_66) node T_80 = or(T_79, T_77) node T_82 = and(io.inst, UInt<32>("h010")) node T_84 = eq(T_82, UInt<32>("h00")) node T_86 = or(UInt<1>("h00"), T_84) node T_87 = cat(T_62, T_51) node T_88 = cat(T_73, T_87) node T_89 = cat(T_80, T_88) node T_90 = cat(T_86, T_89) node T_92 = or(UInt<1>("h00"), T_66) node T_94 = and(io.inst, UInt<32>("h080000020")) node T_96 = eq(T_94, UInt<32>("h00")) node T_98 = and(io.inst, UInt<32>("h030")) node T_100 = eq(T_98, UInt<32>("h00")) node T_102 = and(io.inst, UInt<32>("h010000020")) node T_104 = eq(T_102, UInt<32>("h010000000")) node T_106 = or(UInt<1>("h00"), T_96) node T_107 = or(T_106, T_100) node T_108 = or(T_107, T_104) node T_110 = and(io.inst, UInt<32>("h080000004")) node T_112 = eq(T_110, UInt<32>("h00")) node T_114 = and(io.inst, UInt<32>("h010000004")) node T_116 = eq(T_114, UInt<32>("h00")) node T_118 = and(io.inst, UInt<32>("h050")) node T_120 = eq(T_118, UInt<32>("h040")) node T_122 = or(UInt<1>("h00"), T_112) node T_123 = or(T_122, T_116) node T_124 = or(T_123, T_120) node T_126 = and(io.inst, UInt<32>("h040000004")) node T_128 = eq(T_126, UInt<32>("h00")) node T_130 = and(io.inst, UInt<32>("h020")) node T_132 = eq(T_130, UInt<32>("h020")) node T_134 = or(UInt<1>("h00"), T_128) node T_135 = or(T_134, T_132) node T_136 = or(T_135, T_120) node T_138 = or(UInt<1>("h00"), T_120) node T_140 = and(io.inst, UInt<32>("h050000010")) node T_142 = eq(T_140, UInt<32>("h050000010")) node T_144 = or(UInt<1>("h00"), T_66) node T_145 = or(T_144, T_142) node T_147 = and(io.inst, UInt<32>("h030000010")) node T_149 = eq(T_147, UInt<32>("h010")) node T_151 = or(UInt<1>("h00"), T_149) node T_153 = and(io.inst, UInt<32>("h01040")) node T_155 = eq(T_153, UInt<32>("h00")) node T_157 = and(io.inst, UInt<32>("h02000040")) node T_159 = eq(T_157, UInt<32>("h040")) node T_161 = or(UInt<1>("h00"), T_155) node T_162 = or(T_161, T_159) node T_164 = and(io.inst, UInt<32>("h090000010")) node T_166 = eq(T_164, UInt<32>("h090000010")) node T_168 = or(UInt<1>("h00"), T_166) node T_170 = and(io.inst, UInt<32>("h090000010")) node T_172 = eq(T_170, UInt<32>("h080000010")) node T_174 = or(UInt<1>("h00"), T_132) node T_175 = or(T_174, T_172) node T_177 = and(io.inst, UInt<32>("h0a0000010")) node T_179 = eq(T_177, UInt<32>("h020000010")) node T_181 = and(io.inst, UInt<32>("h0d0000010")) node T_183 = eq(T_181, UInt<32>("h040000010")) node T_185 = or(UInt<1>("h00"), T_179) node T_186 = or(T_185, T_183) node T_188 = and(io.inst, UInt<32>("h070000004")) node T_190 = eq(T_188, UInt<32>("h00")) node T_192 = and(io.inst, UInt<32>("h068000004")) node T_194 = eq(T_192, UInt<32>("h00")) node T_196 = or(UInt<1>("h00"), T_190) node T_197 = or(T_196, T_194) node T_198 = or(T_197, T_120) node T_200 = and(io.inst, UInt<32>("h058000010")) node T_202 = eq(T_200, UInt<32>("h018000010")) node T_204 = or(UInt<1>("h00"), T_202) node T_206 = and(io.inst, UInt<32>("h0d0000010")) node T_208 = eq(T_206, UInt<32>("h050000010")) node T_210 = or(UInt<1>("h00"), T_208) node T_212 = and(io.inst, UInt<32>("h020000004")) node T_214 = eq(T_212, UInt<32>("h00")) node T_216 = and(io.inst, UInt<32>("h040002000")) node T_218 = eq(T_216, UInt<32>("h040000000")) node T_220 = or(UInt<1>("h00"), T_214) node T_221 = or(T_220, T_120) node T_222 = or(T_221, T_218) node T_224 = and(io.inst, UInt<32>("h08002000")) node T_226 = eq(T_224, UInt<32>("h08000000")) node T_228 = and(io.inst, UInt<32>("h0c0000004")) node T_230 = eq(T_228, UInt<32>("h080000000")) node T_232 = or(UInt<1>("h00"), T_214) node T_233 = or(T_232, T_120) node T_234 = or(T_233, T_226) node T_235 = or(T_234, T_230) io.sigs.cmd <= T_90 io.sigs.ldst <= T_92 io.sigs.wen <= T_108 io.sigs.ren1 <= T_124 io.sigs.ren2 <= T_136 io.sigs.ren3 <= T_138 io.sigs.swap12 <= T_145 io.sigs.swap23 <= T_151 io.sigs.single <= T_162 io.sigs.fromint <= T_168 io.sigs.toint <= T_175 io.sigs.fastpipe <= T_186 io.sigs.fma <= T_198 io.sigs.div <= T_204 io.sigs.sqrt <= T_210 io.sigs.round <= T_222 io.sigs.wflags <= T_235 module MulAddRecFN_preMul : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} io.toPostMul.roundingMode <= UInt<1>("h00") io.toPostMul.sExpSum <= UInt<1>("h00") io.toPostMul.highAlignedNegSigC <= UInt<1>("h00") io.toPostMul.bit0AlignedNegSigC <= UInt<1>("h00") io.toPostMul.CAlignDist <= UInt<1>("h00") io.toPostMul.CAlignDist_0 <= UInt<1>("h00") io.toPostMul.isCDominant <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNC <= UInt<1>("h00") io.toPostMul.highExpC <= UInt<1>("h00") io.toPostMul.opSignC <= UInt<1>("h00") io.toPostMul.isZeroProd <= UInt<1>("h00") io.toPostMul.signProd <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNB <= UInt<1>("h00") io.toPostMul.highExpB <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNA <= UInt<1>("h00") io.toPostMul.highExpA <= UInt<1>("h00") io.mulAddC <= UInt<1>("h00") io.mulAddB <= UInt<1>("h00") io.mulAddA <= UInt<1>("h00") node signA = bit(io.a, 32) node expA = bits(io.a, 31, 23) node fractA = bits(io.a, 22, 0) node T_50 = bits(expA, 8, 6) node isZeroA = eq(T_50, UInt<1>("h00")) node T_54 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_54, fractA) node signB = bit(io.b, 32) node expB = bits(io.b, 31, 23) node fractB = bits(io.b, 22, 0) node T_59 = bits(expB, 8, 6) node isZeroB = eq(T_59, UInt<1>("h00")) node T_63 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_63, fractB) node T_65 = bit(io.c, 32) node T_66 = bit(io.op, 0) node opSignC = xor(T_65, T_66) node expC = bits(io.c, 31, 23) node fractC = bits(io.c, 22, 0) node T_70 = bits(expC, 8, 6) node isZeroC = eq(T_70, UInt<1>("h00")) node T_74 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_74, fractC) node T_76 = xor(signA, signB) node T_77 = bit(io.op, 1) node signProd = xor(T_76, T_77) node isZeroProd = or(isZeroA, isZeroB) node T_80 = bit(expB, 8) node T_82 = eq(T_80, UInt<1>("h00")) node T_84 = subw(UInt<3>("h00"), T_82) node T_85 = bits(expB, 7, 0) node T_86 = cat(T_84, T_85) node T_87 = addw(expA, T_86) node sExpAlignedProd = addw(T_87, UInt<5>("h01b")) node doSubMags = xor(signProd, opSignC) node sNatCAlignDist = subw(sExpAlignedProd, expC) node T_92 = bit(sNatCAlignDist, 10) node CAlignDist_floor = or(isZeroProd, T_92) node T_94 = bits(sNatCAlignDist, 9, 0) node T_96 = eq(T_94, UInt<1>("h00")) node CAlignDist_0 = or(CAlignDist_floor, T_96) node T_99 = eq(isZeroC, UInt<1>("h00")) node T_100 = bits(sNatCAlignDist, 9, 0) node T_102 = lt(T_100, UInt<5>("h019")) node T_103 = or(CAlignDist_floor, T_102) node isCDominant = and(T_99, T_103) node T_106 = bits(sNatCAlignDist, 9, 0) node T_108 = lt(T_106, UInt<7>("h04a")) node T_109 = bits(sNatCAlignDist, 6, 0) node T_111 = mux(T_108, T_109, UInt<7>("h04a")) node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_111) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) node T_115 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) node T_116 = bits(T_115, 77, 54) node T_117 = bits(T_116, 15, 0) node T_120 = shl(UInt<8>("h0ff"), 8) node T_121 = xor(UInt<16>("h0ffff"), T_120) node T_122 = shr(T_117, 8) node T_123 = and(T_122, T_121) node T_124 = bits(T_117, 7, 0) node T_125 = shl(T_124, 8) node T_126 = not(T_121) node T_127 = and(T_125, T_126) node T_128 = or(T_123, T_127) node T_129 = bits(T_121, 11, 0) node T_130 = shl(T_129, 4) node T_131 = xor(T_121, T_130) node T_132 = shr(T_128, 4) node T_133 = and(T_132, T_131) node T_134 = bits(T_128, 11, 0) node T_135 = shl(T_134, 4) node T_136 = not(T_131) node T_137 = and(T_135, T_136) node T_138 = or(T_133, T_137) node T_139 = bits(T_131, 13, 0) node T_140 = shl(T_139, 2) node T_141 = xor(T_131, T_140) node T_142 = shr(T_138, 2) node T_143 = and(T_142, T_141) node T_144 = bits(T_138, 13, 0) node T_145 = shl(T_144, 2) node T_146 = not(T_141) node T_147 = and(T_145, T_146) node T_148 = or(T_143, T_147) node T_149 = bits(T_141, 14, 0) node T_150 = shl(T_149, 1) node T_151 = xor(T_141, T_150) node T_152 = shr(T_148, 1) node T_153 = and(T_152, T_151) node T_154 = bits(T_148, 14, 0) node T_155 = shl(T_154, 1) node T_156 = not(T_151) node T_157 = and(T_155, T_156) node T_158 = or(T_153, T_157) node T_159 = bits(T_116, 23, 16) node T_162 = shl(UInt<4>("h0f"), 4) node T_163 = xor(UInt<8>("h0ff"), T_162) node T_164 = shr(T_159, 4) node T_165 = and(T_164, T_163) node T_166 = bits(T_159, 3, 0) node T_167 = shl(T_166, 4) node T_168 = not(T_163) node T_169 = and(T_167, T_168) node T_170 = or(T_165, T_169) node T_171 = bits(T_163, 5, 0) node T_172 = shl(T_171, 2) node T_173 = xor(T_163, T_172) node T_174 = shr(T_170, 2) node T_175 = and(T_174, T_173) node T_176 = bits(T_170, 5, 0) node T_177 = shl(T_176, 2) node T_178 = not(T_173) node T_179 = and(T_177, T_178) node T_180 = or(T_175, T_179) node T_181 = bits(T_173, 6, 0) node T_182 = shl(T_181, 1) node T_183 = xor(T_173, T_182) node T_184 = shr(T_180, 1) node T_185 = and(T_184, T_183) node T_186 = bits(T_180, 6, 0) node T_187 = shl(T_186, 1) node T_188 = not(T_183) node T_189 = and(T_187, T_188) node T_190 = or(T_185, T_189) node CExtraMask = cat(T_158, T_190) node T_192 = not(sigC) node negSigC = mux(doSubMags, T_192, sigC) node T_195 = subw(UInt<50>("h00"), doSubMags) node T_196 = cat(negSigC, T_195) node T_197 = cat(doSubMags, T_196) node T_198 = asSInt(T_197) node T_199 = dshr(T_198, CAlignDist) node T_200 = and(sigC, CExtraMask) node T_202 = neq(T_200, UInt<1>("h00")) node T_203 = xor(T_202, doSubMags) node T_204 = asUInt(T_199) node T_205 = cat(T_204, T_203) node alignedNegSigC = bits(T_205, 74, 0) io.mulAddA <= sigA io.mulAddB <= sigB node T_207 = bits(alignedNegSigC, 48, 1) io.mulAddC <= T_207 node T_208 = bits(expA, 8, 6) io.toPostMul.highExpA <= T_208 node T_209 = bit(fractA, 22) io.toPostMul.isNaN_isQuietNaNA <= T_209 node T_210 = bits(expB, 8, 6) io.toPostMul.highExpB <= T_210 node T_211 = bit(fractB, 22) io.toPostMul.isNaN_isQuietNaNB <= T_211 io.toPostMul.signProd <= signProd io.toPostMul.isZeroProd <= isZeroProd io.toPostMul.opSignC <= opSignC node T_212 = bits(expC, 8, 6) io.toPostMul.highExpC <= T_212 node T_213 = bit(fractC, 22) io.toPostMul.isNaN_isQuietNaNC <= T_213 io.toPostMul.isCDominant <= isCDominant io.toPostMul.CAlignDist_0 <= CAlignDist_0 io.toPostMul.CAlignDist <= CAlignDist node T_214 = bit(alignedNegSigC, 0) io.toPostMul.bit0AlignedNegSigC <= T_214 node T_215 = bits(alignedNegSigC, 74, 49) io.toPostMul.highAlignedNegSigC <= T_215 io.toPostMul.sExpSum <= sExpSum io.toPostMul.roundingMode <= io.roundingMode module MulAddRecFN_postMul : input clk : Clock input reset : UInt<1> output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) node T_44 = bits(io.fromPreMul.highExpA, 2, 1) node isSpecialA = eq(T_44, UInt<2>("h03")) node T_47 = bit(io.fromPreMul.highExpA, 0) node T_49 = eq(T_47, UInt<1>("h00")) node isInfA = and(isSpecialA, T_49) node T_51 = bit(io.fromPreMul.highExpA, 0) node isNaNA = and(isSpecialA, T_51) node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_54) node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) node T_58 = bits(io.fromPreMul.highExpB, 2, 1) node isSpecialB = eq(T_58, UInt<2>("h03")) node T_61 = bit(io.fromPreMul.highExpB, 0) node T_63 = eq(T_61, UInt<1>("h00")) node isInfB = and(isSpecialB, T_63) node T_65 = bit(io.fromPreMul.highExpB, 0) node isNaNB = and(isSpecialB, T_65) node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_68) node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) node T_72 = bits(io.fromPreMul.highExpC, 2, 1) node isSpecialC = eq(T_72, UInt<2>("h03")) node T_75 = bit(io.fromPreMul.highExpC, 0) node T_77 = eq(T_75, UInt<1>("h00")) node isInfC = and(isSpecialC, T_77) node T_79 = bit(io.fromPreMul.highExpC, 0) node isNaNC = and(isSpecialC, T_79) node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_82) node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) node T_96 = bit(io.mulAddResult, 48) node T_98 = addw(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) node T_99 = mux(T_96, T_98, io.fromPreMul.highAlignedNegSigC) node T_100 = bits(io.mulAddResult, 47, 0) node T_101 = cat(T_100, io.fromPreMul.bit0AlignedNegSigC) node sigSum = cat(T_99, T_101) node T_104 = bits(sigSum, 50, 1) node T_105 = xor(UInt<50>("h00"), T_104) node T_106 = or(UInt<50>("h00"), T_104) node T_107 = shl(T_106, 1) node T_108 = xor(T_105, T_107) node T_110 = bits(T_108, 49, 0) node T_111 = bit(T_110, 49) node T_113 = bit(T_110, 48) node T_115 = bit(T_110, 47) node T_117 = bit(T_110, 46) node T_119 = bit(T_110, 45) node T_121 = bit(T_110, 44) node T_123 = bit(T_110, 43) node T_125 = bit(T_110, 42) node T_127 = bit(T_110, 41) node T_129 = bit(T_110, 40) node T_131 = bit(T_110, 39) node T_133 = bit(T_110, 38) node T_135 = bit(T_110, 37) node T_137 = bit(T_110, 36) node T_139 = bit(T_110, 35) node T_141 = bit(T_110, 34) node T_143 = bit(T_110, 33) node T_145 = bit(T_110, 32) node T_147 = bit(T_110, 31) node T_149 = bit(T_110, 30) node T_151 = bit(T_110, 29) node T_153 = bit(T_110, 28) node T_155 = bit(T_110, 27) node T_157 = bit(T_110, 26) node T_159 = bit(T_110, 25) node T_161 = bit(T_110, 24) node T_163 = bit(T_110, 23) node T_165 = bit(T_110, 22) node T_167 = bit(T_110, 21) node T_169 = bit(T_110, 20) node T_171 = bit(T_110, 19) node T_173 = bit(T_110, 18) node T_175 = bit(T_110, 17) node T_177 = bit(T_110, 16) node T_179 = bit(T_110, 15) node T_181 = bit(T_110, 14) node T_183 = bit(T_110, 13) node T_185 = bit(T_110, 12) node T_187 = bit(T_110, 11) node T_189 = bit(T_110, 10) node T_191 = bit(T_110, 9) node T_193 = bit(T_110, 8) node T_195 = bit(T_110, 7) node T_197 = bit(T_110, 6) node T_199 = bit(T_110, 5) node T_201 = bit(T_110, 4) node T_203 = bit(T_110, 3) node T_205 = bit(T_110, 2) node T_207 = bit(T_110, 1) node T_208 = shl(T_207, 0) node T_209 = mux(T_205, UInt<2>("h02"), T_208) node T_210 = mux(T_203, UInt<2>("h03"), T_209) node T_211 = mux(T_201, UInt<3>("h04"), T_210) node T_212 = mux(T_199, UInt<3>("h05"), T_211) node T_213 = mux(T_197, UInt<3>("h06"), T_212) node T_214 = mux(T_195, UInt<3>("h07"), T_213) node T_215 = mux(T_193, UInt<4>("h08"), T_214) node T_216 = mux(T_191, UInt<4>("h09"), T_215) node T_217 = mux(T_189, UInt<4>("h0a"), T_216) node T_218 = mux(T_187, UInt<4>("h0b"), T_217) node T_219 = mux(T_185, UInt<4>("h0c"), T_218) node T_220 = mux(T_183, UInt<4>("h0d"), T_219) node T_221 = mux(T_181, UInt<4>("h0e"), T_220) node T_222 = mux(T_179, UInt<4>("h0f"), T_221) node T_223 = mux(T_177, UInt<5>("h010"), T_222) node T_224 = mux(T_175, UInt<5>("h011"), T_223) node T_225 = mux(T_173, UInt<5>("h012"), T_224) node T_226 = mux(T_171, UInt<5>("h013"), T_225) node T_227 = mux(T_169, UInt<5>("h014"), T_226) node T_228 = mux(T_167, UInt<5>("h015"), T_227) node T_229 = mux(T_165, UInt<5>("h016"), T_228) node T_230 = mux(T_163, UInt<5>("h017"), T_229) node T_231 = mux(T_161, UInt<5>("h018"), T_230) node T_232 = mux(T_159, UInt<5>("h019"), T_231) node T_233 = mux(T_157, UInt<5>("h01a"), T_232) node T_234 = mux(T_155, UInt<5>("h01b"), T_233) node T_235 = mux(T_153, UInt<5>("h01c"), T_234) node T_236 = mux(T_151, UInt<5>("h01d"), T_235) node T_237 = mux(T_149, UInt<5>("h01e"), T_236) node T_238 = mux(T_147, UInt<5>("h01f"), T_237) node T_239 = mux(T_145, UInt<6>("h020"), T_238) node T_240 = mux(T_143, UInt<6>("h021"), T_239) node T_241 = mux(T_141, UInt<6>("h022"), T_240) node T_242 = mux(T_139, UInt<6>("h023"), T_241) node T_243 = mux(T_137, UInt<6>("h024"), T_242) node T_244 = mux(T_135, UInt<6>("h025"), T_243) node T_245 = mux(T_133, UInt<6>("h026"), T_244) node T_246 = mux(T_131, UInt<6>("h027"), T_245) node T_247 = mux(T_129, UInt<6>("h028"), T_246) node T_248 = mux(T_127, UInt<6>("h029"), T_247) node T_249 = mux(T_125, UInt<6>("h02a"), T_248) node T_250 = mux(T_123, UInt<6>("h02b"), T_249) node T_251 = mux(T_121, UInt<6>("h02c"), T_250) node T_252 = mux(T_119, UInt<6>("h02d"), T_251) node T_253 = mux(T_117, UInt<6>("h02e"), T_252) node T_254 = mux(T_115, UInt<6>("h02f"), T_253) node T_255 = mux(T_113, UInt<6>("h030"), T_254) node T_256 = mux(T_111, UInt<6>("h031"), T_255) node estNormPos_dist = subw(UInt<7>("h049"), T_256) node T_258 = bits(sigSum, 33, 18) node T_260 = neq(T_258, UInt<1>("h00")) node T_261 = bits(sigSum, 17, 0) node T_263 = neq(T_261, UInt<1>("h00")) node firstReduceSigSum = cat(T_260, T_263) node notSigSum = not(sigSum) node T_266 = bits(notSigSum, 33, 18) node T_268 = neq(T_266, UInt<1>("h00")) node T_269 = bits(notSigSum, 17, 0) node T_271 = neq(T_269, UInt<1>("h00")) node firstReduceNotSigSum = cat(T_268, T_271) node T_273 = or(io.fromPreMul.CAlignDist_0, doSubMags) node T_275 = subw(io.fromPreMul.CAlignDist, UInt<1>("h01")) node T_276 = bits(T_275, 4, 0) node CDom_estNormDist = mux(T_273, io.fromPreMul.CAlignDist, T_276) node T_278 = not(doSubMags) node T_279 = bit(CDom_estNormDist, 4) node T_280 = not(T_279) node T_281 = and(T_278, T_280) node T_282 = asSInt(T_281) node T_283 = bits(sigSum, 74, 34) node T_285 = neq(firstReduceSigSum, UInt<1>("h00")) node T_286 = cat(T_283, T_285) node T_287 = asSInt(T_286) node T_288 = and(T_282, T_287) node T_289 = not(doSubMags) node T_290 = bit(CDom_estNormDist, 4) node T_291 = and(T_289, T_290) node T_292 = asSInt(T_291) node T_293 = bits(sigSum, 58, 18) node T_294 = bit(firstReduceSigSum, 0) node T_295 = cat(T_293, T_294) node T_296 = asSInt(T_295) node T_297 = and(T_292, T_296) node T_298 = or(T_288, T_297) node T_299 = bit(CDom_estNormDist, 4) node T_300 = not(T_299) node T_301 = and(doSubMags, T_300) node T_302 = asSInt(T_301) node T_303 = bits(notSigSum, 74, 34) node T_305 = neq(firstReduceNotSigSum, UInt<1>("h00")) node T_306 = cat(T_303, T_305) node T_307 = asSInt(T_306) node T_308 = and(T_302, T_307) node T_309 = or(T_298, T_308) node T_310 = bit(CDom_estNormDist, 4) node T_311 = and(doSubMags, T_310) node T_312 = asSInt(T_311) node T_313 = bits(notSigSum, 58, 18) node T_314 = bit(firstReduceNotSigSum, 0) node T_315 = cat(T_313, T_314) node T_316 = asSInt(T_315) node T_317 = and(T_312, T_316) node T_318 = or(T_309, T_317) node CDom_firstNormAbsSigSum = asUInt(T_318) node T_320 = bits(sigSum, 50, 18) node T_321 = bit(firstReduceNotSigSum, 0) node T_322 = not(T_321) node T_323 = bit(firstReduceSigSum, 0) node T_324 = mux(doSubMags, T_322, T_323) node T_325 = cat(T_320, T_324) node T_326 = bits(sigSum, 42, 1) node T_327 = bit(estNormPos_dist, 5) node T_328 = bit(estNormPos_dist, 4) node T_329 = bits(sigSum, 26, 1) node T_331 = subw(UInt<16>("h00"), doSubMags) node T_332 = cat(T_329, T_331) node T_333 = mux(T_328, T_332, T_326) node T_334 = bit(estNormPos_dist, 4) node T_335 = bits(sigSum, 10, 1) node T_337 = subw(UInt<32>("h00"), doSubMags) node T_338 = cat(T_335, T_337) node T_339 = mux(T_334, T_325, T_338) node notCDom_pos_firstNormAbsSigSum = mux(T_327, T_333, T_339) node T_341 = bits(notSigSum, 49, 18) node T_342 = bit(firstReduceNotSigSum, 0) node T_343 = cat(T_341, T_342) node T_344 = bits(notSigSum, 42, 1) node T_345 = bit(estNormPos_dist, 5) node T_346 = bit(estNormPos_dist, 4) node T_347 = bits(notSigSum, 27, 1) node T_349 = dshl(T_347, UInt<5>("h010")) node T_350 = mux(T_346, T_349, T_344) node T_351 = bit(estNormPos_dist, 4) node T_352 = bits(notSigSum, 11, 1) node T_354 = dshl(T_352, UInt<6>("h020")) node T_355 = mux(T_351, T_343, T_354) node notCDom_neg_cFirstNormAbsSigSum = mux(T_345, T_350, T_355) node notCDom_signSigSum = bit(sigSum, 51) node T_358 = not(isZeroC) node T_359 = and(doSubMags, T_358) node doNegSignSum = mux(io.fromPreMul.isCDominant, T_359, notCDom_signSigSum) node T_361 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_361) node T_363 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) node T_364 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_363, T_364) node T_366 = not(io.fromPreMul.isCDominant) node T_367 = not(notCDom_signSigSum) node T_368 = and(T_366, T_367) node doIncrSig = and(T_368, doSubMags) node estNormDist_5 = bits(estNormDist, 3, 0) node normTo2ShiftDist = not(estNormDist_5) node T_373 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) node T_374 = bits(T_373, 15, 1) node T_375 = bits(T_374, 7, 0) node T_378 = shl(UInt<4>("h0f"), 4) node T_379 = xor(UInt<8>("h0ff"), T_378) node T_380 = shr(T_375, 4) node T_381 = and(T_380, T_379) node T_382 = bits(T_375, 3, 0) node T_383 = shl(T_382, 4) node T_384 = not(T_379) node T_385 = and(T_383, T_384) node T_386 = or(T_381, T_385) node T_387 = bits(T_379, 5, 0) node T_388 = shl(T_387, 2) node T_389 = xor(T_379, T_388) node T_390 = shr(T_386, 2) node T_391 = and(T_390, T_389) node T_392 = bits(T_386, 5, 0) node T_393 = shl(T_392, 2) node T_394 = not(T_389) node T_395 = and(T_393, T_394) node T_396 = or(T_391, T_395) node T_397 = bits(T_389, 6, 0) node T_398 = shl(T_397, 1) node T_399 = xor(T_389, T_398) node T_400 = shr(T_396, 1) node T_401 = and(T_400, T_399) node T_402 = bits(T_396, 6, 0) node T_403 = shl(T_402, 1) node T_404 = not(T_399) node T_405 = and(T_403, T_404) node T_406 = or(T_401, T_405) node T_407 = bits(T_374, 14, 8) node T_408 = bits(T_407, 3, 0) node T_409 = bits(T_408, 1, 0) node T_410 = bits(T_409, 0, 0) node T_411 = bits(T_409, 1, 1) node T_412 = cat(T_410, T_411) node T_413 = bits(T_408, 3, 2) node T_414 = bits(T_413, 0, 0) node T_415 = bits(T_413, 1, 1) node T_416 = cat(T_414, T_415) node T_417 = cat(T_412, T_416) node T_418 = bits(T_407, 6, 4) node T_419 = bits(T_418, 1, 0) node T_420 = bits(T_419, 0, 0) node T_421 = bits(T_419, 1, 1) node T_422 = cat(T_420, T_421) node T_423 = bits(T_418, 2, 2) node T_424 = cat(T_422, T_423) node T_425 = cat(T_417, T_424) node T_426 = cat(T_406, T_425) node absSigSumExtraMask = cat(T_426, UInt<1>("h01")) node T_429 = bits(cFirstNormAbsSigSum, 42, 1) node T_430 = dshr(T_429, normTo2ShiftDist) node T_431 = bits(cFirstNormAbsSigSum, 15, 0) node T_432 = not(T_431) node T_433 = and(T_432, absSigSumExtraMask) node T_435 = eq(T_433, UInt<1>("h00")) node T_436 = bits(cFirstNormAbsSigSum, 15, 0) node T_437 = and(T_436, absSigSumExtraMask) node T_439 = neq(T_437, UInt<1>("h00")) node T_440 = mux(doIncrSig, T_435, T_439) node T_441 = cat(T_430, T_440) node sigX3 = bits(T_441, 27, 0) node T_443 = bits(sigX3, 27, 26) node sigX3Shift1 = eq(T_443, UInt<1>("h00")) node sExpX3 = subw(io.fromPreMul.sExpSum, estNormDist) node T_447 = bits(sigX3, 27, 25) node isZeroY = eq(T_447, UInt<1>("h00")) node T_450 = xor(io.fromPreMul.signProd, doNegSignSum) node signY = mux(isZeroY, signZeroNotEqOpSigns, T_450) node sExpX3_13 = bits(sExpX3, 9, 0) node T_453 = bit(sExpX3, 10) node T_455 = subw(UInt<27>("h00"), T_453) node T_456 = not(sExpX3_13) node T_458 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_456) node T_459 = bits(T_458, 131, 107) node T_460 = bits(T_459, 15, 0) node T_463 = shl(UInt<8>("h0ff"), 8) node T_464 = xor(UInt<16>("h0ffff"), T_463) node T_465 = shr(T_460, 8) node T_466 = and(T_465, T_464) node T_467 = bits(T_460, 7, 0) node T_468 = shl(T_467, 8) node T_469 = not(T_464) node T_470 = and(T_468, T_469) node T_471 = or(T_466, T_470) node T_472 = bits(T_464, 11, 0) node T_473 = shl(T_472, 4) node T_474 = xor(T_464, T_473) node T_475 = shr(T_471, 4) node T_476 = and(T_475, T_474) node T_477 = bits(T_471, 11, 0) node T_478 = shl(T_477, 4) node T_479 = not(T_474) node T_480 = and(T_478, T_479) node T_481 = or(T_476, T_480) node T_482 = bits(T_474, 13, 0) node T_483 = shl(T_482, 2) node T_484 = xor(T_474, T_483) node T_485 = shr(T_481, 2) node T_486 = and(T_485, T_484) node T_487 = bits(T_481, 13, 0) node T_488 = shl(T_487, 2) node T_489 = not(T_484) node T_490 = and(T_488, T_489) node T_491 = or(T_486, T_490) node T_492 = bits(T_484, 14, 0) node T_493 = shl(T_492, 1) node T_494 = xor(T_484, T_493) node T_495 = shr(T_491, 1) node T_496 = and(T_495, T_494) node T_497 = bits(T_491, 14, 0) node T_498 = shl(T_497, 1) node T_499 = not(T_494) node T_500 = and(T_498, T_499) node T_501 = or(T_496, T_500) node T_502 = bits(T_459, 24, 16) node T_503 = bits(T_502, 7, 0) node T_506 = shl(UInt<4>("h0f"), 4) node T_507 = xor(UInt<8>("h0ff"), T_506) node T_508 = shr(T_503, 4) node T_509 = and(T_508, T_507) node T_510 = bits(T_503, 3, 0) node T_511 = shl(T_510, 4) node T_512 = not(T_507) node T_513 = and(T_511, T_512) node T_514 = or(T_509, T_513) node T_515 = bits(T_507, 5, 0) node T_516 = shl(T_515, 2) node T_517 = xor(T_507, T_516) node T_518 = shr(T_514, 2) node T_519 = and(T_518, T_517) node T_520 = bits(T_514, 5, 0) node T_521 = shl(T_520, 2) node T_522 = not(T_517) node T_523 = and(T_521, T_522) node T_524 = or(T_519, T_523) node T_525 = bits(T_517, 6, 0) node T_526 = shl(T_525, 1) node T_527 = xor(T_517, T_526) node T_528 = shr(T_524, 1) node T_529 = and(T_528, T_527) node T_530 = bits(T_524, 6, 0) node T_531 = shl(T_530, 1) node T_532 = not(T_527) node T_533 = and(T_531, T_532) node T_534 = or(T_529, T_533) node T_535 = bits(T_502, 8, 8) node T_536 = cat(T_534, T_535) node T_537 = cat(T_501, T_536) node T_538 = bit(sigX3, 26) node T_539 = or(T_537, T_538) node T_541 = cat(T_539, UInt<2>("h03")) node roundMask = or(T_455, T_541) node T_543 = shr(roundMask, 1) node T_544 = not(T_543) node roundPosMask = and(T_544, roundMask) node T_546 = and(sigX3, roundPosMask) node roundPosBit = neq(T_546, UInt<1>("h00")) node T_549 = shr(roundMask, 1) node T_550 = and(sigX3, T_549) node anyRoundExtra = neq(T_550, UInt<1>("h00")) node T_553 = not(sigX3) node T_554 = shr(roundMask, 1) node T_555 = and(T_553, T_554) node allRoundExtra = eq(T_555, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) node T_561 = not(doIncrSig) node T_562 = and(T_561, roundingMode_nearest_even) node T_563 = and(T_562, roundPosBit) node T_564 = and(T_563, anyRoundExtra) node T_565 = not(doIncrSig) node T_566 = and(T_565, roundDirectUp) node T_567 = and(T_566, anyRound) node T_568 = or(T_564, T_567) node T_569 = and(doIncrSig, allRound) node T_570 = or(T_568, T_569) node T_571 = and(doIncrSig, roundingMode_nearest_even) node T_572 = and(T_571, roundPosBit) node T_573 = or(T_570, T_572) node T_574 = and(doIncrSig, roundDirectUp) node T_576 = and(T_574, UInt<1>("h01")) node roundUp = or(T_573, T_576) node T_578 = not(roundPosBit) node T_579 = and(roundingMode_nearest_even, T_578) node T_580 = and(T_579, allRoundExtra) node T_581 = and(roundingMode_nearest_even, roundPosBit) node T_582 = not(anyRoundExtra) node T_583 = and(T_581, T_582) node roundEven = mux(doIncrSig, T_580, T_583) node T_585 = not(allRound) node roundInexact = mux(doIncrSig, T_585, anyRound) node T_587 = or(sigX3, roundMask) node T_588 = shr(T_587, 2) node T_590 = addw(T_588, UInt<1>("h01")) node roundUp_sigY3 = bits(T_590, 25, 0) node T_592 = not(roundUp) node T_593 = not(roundEven) node T_594 = and(T_592, T_593) node T_595 = bit(T_594, 0) node T_596 = not(roundMask) node T_597 = and(sigX3, T_596) node T_598 = shr(T_597, 2) node T_600 = mux(T_595, T_598, UInt<1>("h00")) node T_601 = bit(roundUp, 0) node T_603 = mux(T_601, roundUp_sigY3, UInt<1>("h00")) node T_604 = or(T_600, T_603) node T_605 = shr(roundMask, 1) node T_606 = not(T_605) node T_607 = and(roundUp_sigY3, T_606) node T_609 = mux(roundEven, T_607, UInt<1>("h00")) node sigY3 = or(T_604, T_609) node T_611 = bit(sigY3, 25) node T_613 = addw(sExpX3, UInt<1>("h01")) node T_615 = mux(T_611, T_613, UInt<1>("h00")) node T_616 = bit(sigY3, 24) node T_618 = mux(T_616, sExpX3, UInt<1>("h00")) node T_619 = or(T_615, T_618) node T_620 = bits(sigY3, 25, 24) node T_622 = eq(T_620, UInt<1>("h00")) node T_624 = subw(sExpX3, UInt<1>("h01")) node T_626 = mux(T_622, T_624, UInt<1>("h00")) node sExpY = or(T_619, T_626) node expY = bits(sExpY, 8, 0) node T_629 = bits(sigY3, 22, 0) node T_630 = bits(sigY3, 23, 1) node fractY = mux(sigX3Shift1, T_629, T_630) node T_632 = bits(sExpY, 9, 7) node overflowY = eq(T_632, UInt<2>("h03")) node T_635 = not(isZeroY) node T_636 = bit(sExpY, 9) node T_637 = bits(sExpY, 8, 0) node T_639 = lt(T_637, UInt<7>("h06b")) node T_640 = or(T_636, T_639) node totalUnderflowY = and(T_635, T_640) node T_642 = bit(sExpX3, 10) node T_645 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) node T_646 = leq(sExpX3_13, T_645) node T_647 = or(T_642, T_646) node underflowY = and(roundInexact, T_647) node T_649 = and(roundingMode_min, signY) node T_650 = not(signY) node T_651 = and(roundingMode_max, T_650) node roundMagUp = or(T_649, T_651) node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) node T_657 = not(addSpecial) node T_658 = not(notSpecial_addZeros) node commonCase = and(T_657, T_658) node T_660 = and(isInfA, isZeroB) node T_661 = and(isZeroA, isInfB) node T_662 = or(T_660, T_661) node T_663 = not(isNaNA) node T_664 = not(isNaNB) node T_665 = and(T_663, T_664) node T_666 = or(isInfA, isInfB) node T_667 = and(T_665, T_666) node T_668 = and(T_667, isInfC) node T_669 = and(T_668, doSubMags) node notSigNaN_invalid = or(T_662, T_669) node T_671 = or(isSigNaNA, isSigNaNB) node T_672 = or(T_671, isSigNaNC) node invalid = or(T_672, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) node T_676 = and(commonCase, roundInexact) node inexact = or(overflow, T_676) node T_678 = or(notSpecial_addZeros, isZeroY) node notSpecial_isZeroOut = or(T_678, totalUnderflowY) node T_680 = and(commonCase, totalUnderflowY) node pegMinFiniteMagOut = and(T_680, roundMagUp) node T_682 = not(overflowY_roundMagUp) node pegMaxFiniteMagOut = and(overflow, T_682) node T_684 = or(isInfA, isInfB) node T_685 = or(T_684, isInfC) node T_686 = and(overflow, overflowY_roundMagUp) node notNaN_isInfOut = or(T_685, T_686) node T_688 = or(isNaNA, isNaNB) node T_689 = or(T_688, isNaNC) node isNaNOut = or(T_689, notSigNaN_invalid) node T_692 = eq(doSubMags, UInt<1>("h00")) node T_693 = and(T_692, io.fromPreMul.opSignC) node T_695 = eq(isSpecialC, UInt<1>("h00")) node T_696 = and(mulSpecial, T_695) node T_697 = and(T_696, io.fromPreMul.signProd) node T_698 = or(T_693, T_697) node T_700 = eq(mulSpecial, UInt<1>("h00")) node T_701 = and(T_700, isSpecialC) node T_702 = and(T_701, io.fromPreMul.opSignC) node T_703 = or(T_698, T_702) node T_705 = eq(mulSpecial, UInt<1>("h00")) node T_706 = and(T_705, notSpecial_addZeros) node T_707 = and(T_706, doSubMags) node T_708 = and(T_707, signZeroNotEqOpSigns) node uncommonCaseSignOut = or(T_703, T_708) node T_711 = eq(isNaNOut, UInt<1>("h00")) node T_712 = and(T_711, uncommonCaseSignOut) node T_713 = and(commonCase, signY) node signOut = or(T_712, T_713) node T_717 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) node T_718 = not(T_717) node T_719 = and(expY, T_718) node T_721 = not(UInt<9>("h06b")) node T_723 = mux(pegMinFiniteMagOut, T_721, UInt<9>("h00")) node T_724 = not(T_723) node T_725 = and(T_719, T_724) node T_728 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) node T_729 = not(T_728) node T_730 = and(T_725, T_729) node T_733 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) node T_734 = not(T_733) node T_735 = and(T_730, T_734) node T_738 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) node T_739 = or(T_735, T_738) node T_742 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) node T_743 = or(T_739, T_742) node T_746 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) node T_747 = or(T_743, T_746) node T_750 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) node expOut = or(T_747, T_750) node T_752 = and(totalUnderflowY, roundMagUp) node T_753 = or(T_752, isNaNOut) node T_755 = mux(T_753, UInt<1>("h00"), fractY) node T_756 = shl(isNaNOut, 22) node T_757 = or(T_755, T_756) node T_759 = subw(UInt<23>("h00"), pegMaxFiniteMagOut) node fractOut = or(T_757, T_759) node T_761 = cat(expOut, fractOut) node T_762 = cat(signOut, T_761) io.out <= T_762 node T_764 = cat(invalid, UInt<1>("h00")) node T_765 = cat(underflow, inexact) node T_766 = cat(overflow, T_765) node T_767 = cat(T_764, T_766) io.exceptionFlags <= T_767 module MulAddRecFN : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") inst mulAddRecFN_preMul of MulAddRecFN_preMul mulAddRecFN_preMul.io.roundingMode <= UInt<1>("h00") mulAddRecFN_preMul.io.c <= UInt<1>("h00") mulAddRecFN_preMul.io.b <= UInt<1>("h00") mulAddRecFN_preMul.io.a <= UInt<1>("h00") mulAddRecFN_preMul.io.op <= UInt<1>("h00") mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset inst mulAddRecFN_postMul of MulAddRecFN_postMul mulAddRecFN_postMul.io.mulAddResult <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.roundingMode <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.sExpSum <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highAlignedNegSigC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.bit0AlignedNegSigC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.CAlignDist <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.CAlignDist_0 <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isCDominant <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.opSignC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isZeroProd <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.signProd <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNB <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpB <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNA <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpA <= UInt<1>("h00") mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset mulAddRecFN_preMul.io.op <= io.op mulAddRecFN_preMul.io.a <= io.a mulAddRecFN_preMul.io.b <= io.b mulAddRecFN_preMul.io.c <= io.c mulAddRecFN_preMul.io.roundingMode <= io.roundingMode mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul node T_36 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) node T_38 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) node T_39 = addw(T_36, T_38) mulAddRecFN_postMul.io.mulAddResult <= T_39 io.out <= mulAddRecFN_postMul.io.out io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags module FPUFMAPipe : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") node one = shl(UInt<1>("h01"), 31) node T_136 = bit(io.in.bits.in1, 32) node T_137 = bit(io.in.bits.in2, 32) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 32) reg valid : UInt<1>, clk, UInt<1>("h00"), valid valid <= io.in.valid reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in when io.in.valid : in <- io.in.bits node T_187 = bit(io.in.bits.cmd, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) node T_190 = bit(io.in.bits.cmd, 0) node T_191 = cat(T_189, T_190) in.cmd <= T_191 when io.in.bits.swap23 : in.in2 <= one skip node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) node T_194 = eq(T_192, UInt<1>("h00")) when T_194 : in.in3 <= zero skip skip inst fma of MulAddRecFN fma.io.roundingMode <= UInt<1>("h00") fma.io.c <= UInt<1>("h00") fma.io.b <= UInt<1>("h00") fma.io.a <= UInt<1>("h00") fma.io.op <= UInt<1>("h00") fma.clk <= clk fma.reset <= reset fma.io.op <= in.cmd fma.io.roundingMode <= in.rm fma.io.a <= in.in1 fma.io.b <= in.in2 fma.io.c <= in.in3 wire res : {data : UInt<65>, exc : UInt<5>} res.exc <= UInt<1>("h00") res.data <= UInt<1>("h00") node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_211 = cat(T_210, fma.io.out) res.data <= T_211 res.exc <= fma.io.exceptionFlags reg T_214 : UInt<1>, clk, reset, UInt<1>("h00") T_214 <= valid reg T_215 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_215 when valid : T_215 <- res skip wire T_226 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_226.bits.exc <= UInt<1>("h00") T_226.bits.data <= UInt<1>("h00") T_226.valid <= UInt<1>("h00") T_226.valid <= T_214 T_226.bits <- T_215 io.out <- T_226 module MulAddRecFN_preMul_115 : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} io.toPostMul.roundingMode <= UInt<1>("h00") io.toPostMul.sExpSum <= UInt<1>("h00") io.toPostMul.highAlignedNegSigC <= UInt<1>("h00") io.toPostMul.bit0AlignedNegSigC <= UInt<1>("h00") io.toPostMul.CAlignDist <= UInt<1>("h00") io.toPostMul.CAlignDist_0 <= UInt<1>("h00") io.toPostMul.isCDominant <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNC <= UInt<1>("h00") io.toPostMul.highExpC <= UInt<1>("h00") io.toPostMul.opSignC <= UInt<1>("h00") io.toPostMul.isZeroProd <= UInt<1>("h00") io.toPostMul.signProd <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNB <= UInt<1>("h00") io.toPostMul.highExpB <= UInt<1>("h00") io.toPostMul.isNaN_isQuietNaNA <= UInt<1>("h00") io.toPostMul.highExpA <= UInt<1>("h00") io.mulAddC <= UInt<1>("h00") io.mulAddB <= UInt<1>("h00") io.mulAddA <= UInt<1>("h00") node signA = bit(io.a, 64) node expA = bits(io.a, 63, 52) node fractA = bits(io.a, 51, 0) node T_50 = bits(expA, 11, 9) node isZeroA = eq(T_50, UInt<1>("h00")) node T_54 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_54, fractA) node signB = bit(io.b, 64) node expB = bits(io.b, 63, 52) node fractB = bits(io.b, 51, 0) node T_59 = bits(expB, 11, 9) node isZeroB = eq(T_59, UInt<1>("h00")) node T_63 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_63, fractB) node T_65 = bit(io.c, 64) node T_66 = bit(io.op, 0) node opSignC = xor(T_65, T_66) node expC = bits(io.c, 63, 52) node fractC = bits(io.c, 51, 0) node T_70 = bits(expC, 11, 9) node isZeroC = eq(T_70, UInt<1>("h00")) node T_74 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_74, fractC) node T_76 = xor(signA, signB) node T_77 = bit(io.op, 1) node signProd = xor(T_76, T_77) node isZeroProd = or(isZeroA, isZeroB) node T_80 = bit(expB, 11) node T_82 = eq(T_80, UInt<1>("h00")) node T_84 = subw(UInt<3>("h00"), T_82) node T_85 = bits(expB, 10, 0) node T_86 = cat(T_84, T_85) node T_87 = addw(expA, T_86) node sExpAlignedProd = addw(T_87, UInt<6>("h038")) node doSubMags = xor(signProd, opSignC) node sNatCAlignDist = subw(sExpAlignedProd, expC) node T_92 = bit(sNatCAlignDist, 13) node CAlignDist_floor = or(isZeroProd, T_92) node T_94 = bits(sNatCAlignDist, 12, 0) node T_96 = eq(T_94, UInt<1>("h00")) node CAlignDist_0 = or(CAlignDist_floor, T_96) node T_99 = eq(isZeroC, UInt<1>("h00")) node T_100 = bits(sNatCAlignDist, 12, 0) node T_102 = lt(T_100, UInt<6>("h036")) node T_103 = or(CAlignDist_floor, T_102) node isCDominant = and(T_99, T_103) node T_106 = bits(sNatCAlignDist, 12, 0) node T_108 = lt(T_106, UInt<8>("h0a1")) node T_109 = bits(sNatCAlignDist, 7, 0) node T_111 = mux(T_108, T_109, UInt<8>("h0a1")) node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_111) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) node T_115 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) node T_116 = bits(T_115, 147, 95) node T_117 = bits(T_116, 31, 0) node T_120 = shl(UInt<16>("h0ffff"), 16) node T_121 = xor(UInt<32>("h0ffffffff"), T_120) node T_122 = shr(T_117, 16) node T_123 = and(T_122, T_121) node T_124 = bits(T_117, 15, 0) node T_125 = shl(T_124, 16) node T_126 = not(T_121) node T_127 = and(T_125, T_126) node T_128 = or(T_123, T_127) node T_129 = bits(T_121, 23, 0) node T_130 = shl(T_129, 8) node T_131 = xor(T_121, T_130) node T_132 = shr(T_128, 8) node T_133 = and(T_132, T_131) node T_134 = bits(T_128, 23, 0) node T_135 = shl(T_134, 8) node T_136 = not(T_131) node T_137 = and(T_135, T_136) node T_138 = or(T_133, T_137) node T_139 = bits(T_131, 27, 0) node T_140 = shl(T_139, 4) node T_141 = xor(T_131, T_140) node T_142 = shr(T_138, 4) node T_143 = and(T_142, T_141) node T_144 = bits(T_138, 27, 0) node T_145 = shl(T_144, 4) node T_146 = not(T_141) node T_147 = and(T_145, T_146) node T_148 = or(T_143, T_147) node T_149 = bits(T_141, 29, 0) node T_150 = shl(T_149, 2) node T_151 = xor(T_141, T_150) node T_152 = shr(T_148, 2) node T_153 = and(T_152, T_151) node T_154 = bits(T_148, 29, 0) node T_155 = shl(T_154, 2) node T_156 = not(T_151) node T_157 = and(T_155, T_156) node T_158 = or(T_153, T_157) node T_159 = bits(T_151, 30, 0) node T_160 = shl(T_159, 1) node T_161 = xor(T_151, T_160) node T_162 = shr(T_158, 1) node T_163 = and(T_162, T_161) node T_164 = bits(T_158, 30, 0) node T_165 = shl(T_164, 1) node T_166 = not(T_161) node T_167 = and(T_165, T_166) node T_168 = or(T_163, T_167) node T_169 = bits(T_116, 52, 32) node T_170 = bits(T_169, 15, 0) node T_173 = shl(UInt<8>("h0ff"), 8) node T_174 = xor(UInt<16>("h0ffff"), T_173) node T_175 = shr(T_170, 8) node T_176 = and(T_175, T_174) node T_177 = bits(T_170, 7, 0) node T_178 = shl(T_177, 8) node T_179 = not(T_174) node T_180 = and(T_178, T_179) node T_181 = or(T_176, T_180) node T_182 = bits(T_174, 11, 0) node T_183 = shl(T_182, 4) node T_184 = xor(T_174, T_183) node T_185 = shr(T_181, 4) node T_186 = and(T_185, T_184) node T_187 = bits(T_181, 11, 0) node T_188 = shl(T_187, 4) node T_189 = not(T_184) node T_190 = and(T_188, T_189) node T_191 = or(T_186, T_190) node T_192 = bits(T_184, 13, 0) node T_193 = shl(T_192, 2) node T_194 = xor(T_184, T_193) node T_195 = shr(T_191, 2) node T_196 = and(T_195, T_194) node T_197 = bits(T_191, 13, 0) node T_198 = shl(T_197, 2) node T_199 = not(T_194) node T_200 = and(T_198, T_199) node T_201 = or(T_196, T_200) node T_202 = bits(T_194, 14, 0) node T_203 = shl(T_202, 1) node T_204 = xor(T_194, T_203) node T_205 = shr(T_201, 1) node T_206 = and(T_205, T_204) node T_207 = bits(T_201, 14, 0) node T_208 = shl(T_207, 1) node T_209 = not(T_204) node T_210 = and(T_208, T_209) node T_211 = or(T_206, T_210) node T_212 = bits(T_169, 20, 16) node T_213 = bits(T_212, 3, 0) node T_214 = bits(T_213, 1, 0) node T_215 = bits(T_214, 0, 0) node T_216 = bits(T_214, 1, 1) node T_217 = cat(T_215, T_216) node T_218 = bits(T_213, 3, 2) node T_219 = bits(T_218, 0, 0) node T_220 = bits(T_218, 1, 1) node T_221 = cat(T_219, T_220) node T_222 = cat(T_217, T_221) node T_223 = bits(T_212, 4, 4) node T_224 = cat(T_222, T_223) node T_225 = cat(T_211, T_224) node CExtraMask = cat(T_168, T_225) node T_227 = not(sigC) node negSigC = mux(doSubMags, T_227, sigC) node T_230 = subw(UInt<108>("h00"), doSubMags) node T_231 = cat(negSigC, T_230) node T_232 = cat(doSubMags, T_231) node T_233 = asSInt(T_232) node T_234 = dshr(T_233, CAlignDist) node T_235 = and(sigC, CExtraMask) node T_237 = neq(T_235, UInt<1>("h00")) node T_238 = xor(T_237, doSubMags) node T_239 = asUInt(T_234) node T_240 = cat(T_239, T_238) node alignedNegSigC = bits(T_240, 161, 0) io.mulAddA <= sigA io.mulAddB <= sigB node T_242 = bits(alignedNegSigC, 106, 1) io.mulAddC <= T_242 node T_243 = bits(expA, 11, 9) io.toPostMul.highExpA <= T_243 node T_244 = bit(fractA, 51) io.toPostMul.isNaN_isQuietNaNA <= T_244 node T_245 = bits(expB, 11, 9) io.toPostMul.highExpB <= T_245 node T_246 = bit(fractB, 51) io.toPostMul.isNaN_isQuietNaNB <= T_246 io.toPostMul.signProd <= signProd io.toPostMul.isZeroProd <= isZeroProd io.toPostMul.opSignC <= opSignC node T_247 = bits(expC, 11, 9) io.toPostMul.highExpC <= T_247 node T_248 = bit(fractC, 51) io.toPostMul.isNaN_isQuietNaNC <= T_248 io.toPostMul.isCDominant <= isCDominant io.toPostMul.CAlignDist_0 <= CAlignDist_0 io.toPostMul.CAlignDist <= CAlignDist node T_249 = bit(alignedNegSigC, 0) io.toPostMul.bit0AlignedNegSigC <= T_249 node T_250 = bits(alignedNegSigC, 161, 107) io.toPostMul.highAlignedNegSigC <= T_250 io.toPostMul.sExpSum <= sExpSum io.toPostMul.roundingMode <= io.roundingMode module MulAddRecFN_postMul_116 : input clk : Clock input reset : UInt<1> output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) node T_44 = bits(io.fromPreMul.highExpA, 2, 1) node isSpecialA = eq(T_44, UInt<2>("h03")) node T_47 = bit(io.fromPreMul.highExpA, 0) node T_49 = eq(T_47, UInt<1>("h00")) node isInfA = and(isSpecialA, T_49) node T_51 = bit(io.fromPreMul.highExpA, 0) node isNaNA = and(isSpecialA, T_51) node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_54) node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) node T_58 = bits(io.fromPreMul.highExpB, 2, 1) node isSpecialB = eq(T_58, UInt<2>("h03")) node T_61 = bit(io.fromPreMul.highExpB, 0) node T_63 = eq(T_61, UInt<1>("h00")) node isInfB = and(isSpecialB, T_63) node T_65 = bit(io.fromPreMul.highExpB, 0) node isNaNB = and(isSpecialB, T_65) node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_68) node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) node T_72 = bits(io.fromPreMul.highExpC, 2, 1) node isSpecialC = eq(T_72, UInt<2>("h03")) node T_75 = bit(io.fromPreMul.highExpC, 0) node T_77 = eq(T_75, UInt<1>("h00")) node isInfC = and(isSpecialC, T_77) node T_79 = bit(io.fromPreMul.highExpC, 0) node isNaNC = and(isSpecialC, T_79) node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_82) node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) node T_92 = bit(io.mulAddResult, 106) node T_94 = addw(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) node T_95 = mux(T_92, T_94, io.fromPreMul.highAlignedNegSigC) node T_96 = bits(io.mulAddResult, 105, 0) node T_97 = cat(T_96, io.fromPreMul.bit0AlignedNegSigC) node sigSum = cat(T_95, T_97) node T_100 = bits(sigSum, 108, 1) node T_101 = xor(UInt<108>("h00"), T_100) node T_102 = or(UInt<108>("h00"), T_100) node T_103 = shl(T_102, 1) node T_104 = xor(T_101, T_103) node T_106 = bits(T_104, 107, 0) node T_107 = bit(T_106, 107) node T_109 = bit(T_106, 106) node T_111 = bit(T_106, 105) node T_113 = bit(T_106, 104) node T_115 = bit(T_106, 103) node T_117 = bit(T_106, 102) node T_119 = bit(T_106, 101) node T_121 = bit(T_106, 100) node T_123 = bit(T_106, 99) node T_125 = bit(T_106, 98) node T_127 = bit(T_106, 97) node T_129 = bit(T_106, 96) node T_131 = bit(T_106, 95) node T_133 = bit(T_106, 94) node T_135 = bit(T_106, 93) node T_137 = bit(T_106, 92) node T_139 = bit(T_106, 91) node T_141 = bit(T_106, 90) node T_143 = bit(T_106, 89) node T_145 = bit(T_106, 88) node T_147 = bit(T_106, 87) node T_149 = bit(T_106, 86) node T_151 = bit(T_106, 85) node T_153 = bit(T_106, 84) node T_155 = bit(T_106, 83) node T_157 = bit(T_106, 82) node T_159 = bit(T_106, 81) node T_161 = bit(T_106, 80) node T_163 = bit(T_106, 79) node T_165 = bit(T_106, 78) node T_167 = bit(T_106, 77) node T_169 = bit(T_106, 76) node T_171 = bit(T_106, 75) node T_173 = bit(T_106, 74) node T_175 = bit(T_106, 73) node T_177 = bit(T_106, 72) node T_179 = bit(T_106, 71) node T_181 = bit(T_106, 70) node T_183 = bit(T_106, 69) node T_185 = bit(T_106, 68) node T_187 = bit(T_106, 67) node T_189 = bit(T_106, 66) node T_191 = bit(T_106, 65) node T_193 = bit(T_106, 64) node T_195 = bit(T_106, 63) node T_197 = bit(T_106, 62) node T_199 = bit(T_106, 61) node T_201 = bit(T_106, 60) node T_203 = bit(T_106, 59) node T_205 = bit(T_106, 58) node T_207 = bit(T_106, 57) node T_209 = bit(T_106, 56) node T_211 = bit(T_106, 55) node T_213 = bit(T_106, 54) node T_215 = bit(T_106, 53) node T_217 = bit(T_106, 52) node T_219 = bit(T_106, 51) node T_221 = bit(T_106, 50) node T_223 = bit(T_106, 49) node T_225 = bit(T_106, 48) node T_227 = bit(T_106, 47) node T_229 = bit(T_106, 46) node T_231 = bit(T_106, 45) node T_233 = bit(T_106, 44) node T_235 = bit(T_106, 43) node T_237 = bit(T_106, 42) node T_239 = bit(T_106, 41) node T_241 = bit(T_106, 40) node T_243 = bit(T_106, 39) node T_245 = bit(T_106, 38) node T_247 = bit(T_106, 37) node T_249 = bit(T_106, 36) node T_251 = bit(T_106, 35) node T_253 = bit(T_106, 34) node T_255 = bit(T_106, 33) node T_257 = bit(T_106, 32) node T_259 = bit(T_106, 31) node T_261 = bit(T_106, 30) node T_263 = bit(T_106, 29) node T_265 = bit(T_106, 28) node T_267 = bit(T_106, 27) node T_269 = bit(T_106, 26) node T_271 = bit(T_106, 25) node T_273 = bit(T_106, 24) node T_275 = bit(T_106, 23) node T_277 = bit(T_106, 22) node T_279 = bit(T_106, 21) node T_281 = bit(T_106, 20) node T_283 = bit(T_106, 19) node T_285 = bit(T_106, 18) node T_287 = bit(T_106, 17) node T_289 = bit(T_106, 16) node T_291 = bit(T_106, 15) node T_293 = bit(T_106, 14) node T_295 = bit(T_106, 13) node T_297 = bit(T_106, 12) node T_299 = bit(T_106, 11) node T_301 = bit(T_106, 10) node T_303 = bit(T_106, 9) node T_305 = bit(T_106, 8) node T_307 = bit(T_106, 7) node T_309 = bit(T_106, 6) node T_311 = bit(T_106, 5) node T_313 = bit(T_106, 4) node T_315 = bit(T_106, 3) node T_317 = bit(T_106, 2) node T_319 = bit(T_106, 1) node T_320 = shl(T_319, 0) node T_321 = mux(T_317, UInt<2>("h02"), T_320) node T_322 = mux(T_315, UInt<2>("h03"), T_321) node T_323 = mux(T_313, UInt<3>("h04"), T_322) node T_324 = mux(T_311, UInt<3>("h05"), T_323) node T_325 = mux(T_309, UInt<3>("h06"), T_324) node T_326 = mux(T_307, UInt<3>("h07"), T_325) node T_327 = mux(T_305, UInt<4>("h08"), T_326) node T_328 = mux(T_303, UInt<4>("h09"), T_327) node T_329 = mux(T_301, UInt<4>("h0a"), T_328) node T_330 = mux(T_299, UInt<4>("h0b"), T_329) node T_331 = mux(T_297, UInt<4>("h0c"), T_330) node T_332 = mux(T_295, UInt<4>("h0d"), T_331) node T_333 = mux(T_293, UInt<4>("h0e"), T_332) node T_334 = mux(T_291, UInt<4>("h0f"), T_333) node T_335 = mux(T_289, UInt<5>("h010"), T_334) node T_336 = mux(T_287, UInt<5>("h011"), T_335) node T_337 = mux(T_285, UInt<5>("h012"), T_336) node T_338 = mux(T_283, UInt<5>("h013"), T_337) node T_339 = mux(T_281, UInt<5>("h014"), T_338) node T_340 = mux(T_279, UInt<5>("h015"), T_339) node T_341 = mux(T_277, UInt<5>("h016"), T_340) node T_342 = mux(T_275, UInt<5>("h017"), T_341) node T_343 = mux(T_273, UInt<5>("h018"), T_342) node T_344 = mux(T_271, UInt<5>("h019"), T_343) node T_345 = mux(T_269, UInt<5>("h01a"), T_344) node T_346 = mux(T_267, UInt<5>("h01b"), T_345) node T_347 = mux(T_265, UInt<5>("h01c"), T_346) node T_348 = mux(T_263, UInt<5>("h01d"), T_347) node T_349 = mux(T_261, UInt<5>("h01e"), T_348) node T_350 = mux(T_259, UInt<5>("h01f"), T_349) node T_351 = mux(T_257, UInt<6>("h020"), T_350) node T_352 = mux(T_255, UInt<6>("h021"), T_351) node T_353 = mux(T_253, UInt<6>("h022"), T_352) node T_354 = mux(T_251, UInt<6>("h023"), T_353) node T_355 = mux(T_249, UInt<6>("h024"), T_354) node T_356 = mux(T_247, UInt<6>("h025"), T_355) node T_357 = mux(T_245, UInt<6>("h026"), T_356) node T_358 = mux(T_243, UInt<6>("h027"), T_357) node T_359 = mux(T_241, UInt<6>("h028"), T_358) node T_360 = mux(T_239, UInt<6>("h029"), T_359) node T_361 = mux(T_237, UInt<6>("h02a"), T_360) node T_362 = mux(T_235, UInt<6>("h02b"), T_361) node T_363 = mux(T_233, UInt<6>("h02c"), T_362) node T_364 = mux(T_231, UInt<6>("h02d"), T_363) node T_365 = mux(T_229, UInt<6>("h02e"), T_364) node T_366 = mux(T_227, UInt<6>("h02f"), T_365) node T_367 = mux(T_225, UInt<6>("h030"), T_366) node T_368 = mux(T_223, UInt<6>("h031"), T_367) node T_369 = mux(T_221, UInt<6>("h032"), T_368) node T_370 = mux(T_219, UInt<6>("h033"), T_369) node T_371 = mux(T_217, UInt<6>("h034"), T_370) node T_372 = mux(T_215, UInt<6>("h035"), T_371) node T_373 = mux(T_213, UInt<6>("h036"), T_372) node T_374 = mux(T_211, UInt<6>("h037"), T_373) node T_375 = mux(T_209, UInt<6>("h038"), T_374) node T_376 = mux(T_207, UInt<6>("h039"), T_375) node T_377 = mux(T_205, UInt<6>("h03a"), T_376) node T_378 = mux(T_203, UInt<6>("h03b"), T_377) node T_379 = mux(T_201, UInt<6>("h03c"), T_378) node T_380 = mux(T_199, UInt<6>("h03d"), T_379) node T_381 = mux(T_197, UInt<6>("h03e"), T_380) node T_382 = mux(T_195, UInt<6>("h03f"), T_381) node T_383 = mux(T_193, UInt<7>("h040"), T_382) node T_384 = mux(T_191, UInt<7>("h041"), T_383) node T_385 = mux(T_189, UInt<7>("h042"), T_384) node T_386 = mux(T_187, UInt<7>("h043"), T_385) node T_387 = mux(T_185, UInt<7>("h044"), T_386) node T_388 = mux(T_183, UInt<7>("h045"), T_387) node T_389 = mux(T_181, UInt<7>("h046"), T_388) node T_390 = mux(T_179, UInt<7>("h047"), T_389) node T_391 = mux(T_177, UInt<7>("h048"), T_390) node T_392 = mux(T_175, UInt<7>("h049"), T_391) node T_393 = mux(T_173, UInt<7>("h04a"), T_392) node T_394 = mux(T_171, UInt<7>("h04b"), T_393) node T_395 = mux(T_169, UInt<7>("h04c"), T_394) node T_396 = mux(T_167, UInt<7>("h04d"), T_395) node T_397 = mux(T_165, UInt<7>("h04e"), T_396) node T_398 = mux(T_163, UInt<7>("h04f"), T_397) node T_399 = mux(T_161, UInt<7>("h050"), T_398) node T_400 = mux(T_159, UInt<7>("h051"), T_399) node T_401 = mux(T_157, UInt<7>("h052"), T_400) node T_402 = mux(T_155, UInt<7>("h053"), T_401) node T_403 = mux(T_153, UInt<7>("h054"), T_402) node T_404 = mux(T_151, UInt<7>("h055"), T_403) node T_405 = mux(T_149, UInt<7>("h056"), T_404) node T_406 = mux(T_147, UInt<7>("h057"), T_405) node T_407 = mux(T_145, UInt<7>("h058"), T_406) node T_408 = mux(T_143, UInt<7>("h059"), T_407) node T_409 = mux(T_141, UInt<7>("h05a"), T_408) node T_410 = mux(T_139, UInt<7>("h05b"), T_409) node T_411 = mux(T_137, UInt<7>("h05c"), T_410) node T_412 = mux(T_135, UInt<7>("h05d"), T_411) node T_413 = mux(T_133, UInt<7>("h05e"), T_412) node T_414 = mux(T_131, UInt<7>("h05f"), T_413) node T_415 = mux(T_129, UInt<7>("h060"), T_414) node T_416 = mux(T_127, UInt<7>("h061"), T_415) node T_417 = mux(T_125, UInt<7>("h062"), T_416) node T_418 = mux(T_123, UInt<7>("h063"), T_417) node T_419 = mux(T_121, UInt<7>("h064"), T_418) node T_420 = mux(T_119, UInt<7>("h065"), T_419) node T_421 = mux(T_117, UInt<7>("h066"), T_420) node T_422 = mux(T_115, UInt<7>("h067"), T_421) node T_423 = mux(T_113, UInt<7>("h068"), T_422) node T_424 = mux(T_111, UInt<7>("h069"), T_423) node T_425 = mux(T_109, UInt<7>("h06a"), T_424) node T_426 = mux(T_107, UInt<7>("h06b"), T_425) node estNormPos_dist = subw(UInt<8>("h0a0"), T_426) node T_428 = bits(sigSum, 75, 44) node T_430 = neq(T_428, UInt<1>("h00")) node T_431 = bits(sigSum, 43, 0) node T_433 = neq(T_431, UInt<1>("h00")) node firstReduceSigSum = cat(T_430, T_433) node notSigSum = not(sigSum) node T_436 = bits(notSigSum, 75, 44) node T_438 = neq(T_436, UInt<1>("h00")) node T_439 = bits(notSigSum, 43, 0) node T_441 = neq(T_439, UInt<1>("h00")) node firstReduceNotSigSum = cat(T_438, T_441) node T_443 = or(io.fromPreMul.CAlignDist_0, doSubMags) node T_445 = subw(io.fromPreMul.CAlignDist, UInt<1>("h01")) node T_446 = bits(T_445, 5, 0) node CDom_estNormDist = mux(T_443, io.fromPreMul.CAlignDist, T_446) node T_448 = not(doSubMags) node T_449 = bit(CDom_estNormDist, 5) node T_450 = not(T_449) node T_451 = and(T_448, T_450) node T_452 = asSInt(T_451) node T_453 = bits(sigSum, 161, 76) node T_455 = neq(firstReduceSigSum, UInt<1>("h00")) node T_456 = cat(T_453, T_455) node T_457 = asSInt(T_456) node T_458 = and(T_452, T_457) node T_459 = not(doSubMags) node T_460 = bit(CDom_estNormDist, 5) node T_461 = and(T_459, T_460) node T_462 = asSInt(T_461) node T_463 = bits(sigSum, 129, 44) node T_464 = bit(firstReduceSigSum, 0) node T_465 = cat(T_463, T_464) node T_466 = asSInt(T_465) node T_467 = and(T_462, T_466) node T_468 = or(T_458, T_467) node T_469 = bit(CDom_estNormDist, 5) node T_470 = not(T_469) node T_471 = and(doSubMags, T_470) node T_472 = asSInt(T_471) node T_473 = bits(notSigSum, 161, 76) node T_475 = neq(firstReduceNotSigSum, UInt<1>("h00")) node T_476 = cat(T_473, T_475) node T_477 = asSInt(T_476) node T_478 = and(T_472, T_477) node T_479 = or(T_468, T_478) node T_480 = bit(CDom_estNormDist, 5) node T_481 = and(doSubMags, T_480) node T_482 = asSInt(T_481) node T_483 = bits(notSigSum, 129, 44) node T_484 = bit(firstReduceNotSigSum, 0) node T_485 = cat(T_483, T_484) node T_486 = asSInt(T_485) node T_487 = and(T_482, T_486) node T_488 = or(T_479, T_487) node CDom_firstNormAbsSigSum = asUInt(T_488) node T_490 = bits(sigSum, 108, 44) node T_491 = bit(firstReduceNotSigSum, 0) node T_492 = not(T_491) node T_493 = bit(firstReduceSigSum, 0) node T_494 = mux(doSubMags, T_492, T_493) node T_495 = cat(T_490, T_494) node T_496 = bits(sigSum, 97, 1) node T_497 = bit(estNormPos_dist, 4) node T_498 = bits(sigSum, 1, 1) node T_500 = subw(UInt<86>("h00"), doSubMags) node T_501 = cat(T_498, T_500) node T_502 = mux(T_497, T_495, T_501) node T_503 = bits(sigSum, 97, 12) node T_504 = bits(notSigSum, 11, 1) node T_506 = eq(T_504, UInt<1>("h00")) node T_507 = bits(sigSum, 11, 1) node T_509 = neq(T_507, UInt<1>("h00")) node T_510 = mux(doSubMags, T_506, T_509) node T_511 = cat(T_503, T_510) node T_512 = bit(estNormPos_dist, 6) node T_513 = bit(estNormPos_dist, 5) node T_514 = bits(sigSum, 65, 1) node T_516 = subw(UInt<22>("h00"), doSubMags) node T_517 = cat(T_514, T_516) node T_518 = mux(T_513, T_517, T_511) node T_519 = bit(estNormPos_dist, 5) node T_520 = bits(sigSum, 33, 1) node T_522 = subw(UInt<54>("h00"), doSubMags) node T_523 = cat(T_520, T_522) node T_524 = mux(T_519, T_502, T_523) node notCDom_pos_firstNormAbsSigSum = mux(T_512, T_518, T_524) node T_526 = bits(notSigSum, 107, 44) node T_527 = bit(firstReduceNotSigSum, 0) node T_528 = cat(T_526, T_527) node T_529 = bits(notSigSum, 97, 1) node T_530 = bit(estNormPos_dist, 4) node T_531 = bits(notSigSum, 2, 1) node T_533 = dshl(T_531, UInt<7>("h056")) node T_534 = mux(T_530, T_528, T_533) node T_535 = bits(notSigSum, 98, 12) node T_536 = bits(notSigSum, 11, 1) node T_538 = neq(T_536, UInt<1>("h00")) node T_539 = cat(T_535, T_538) node T_540 = bit(estNormPos_dist, 6) node T_541 = bit(estNormPos_dist, 5) node T_542 = bits(notSigSum, 66, 1) node T_544 = dshl(T_542, UInt<5>("h016")) node T_545 = mux(T_541, T_544, T_539) node T_546 = bit(estNormPos_dist, 5) node T_547 = bits(notSigSum, 34, 1) node T_549 = dshl(T_547, UInt<6>("h036")) node T_550 = mux(T_546, T_534, T_549) node notCDom_neg_cFirstNormAbsSigSum = mux(T_540, T_545, T_550) node notCDom_signSigSum = bit(sigSum, 109) node T_553 = not(isZeroC) node T_554 = and(doSubMags, T_553) node doNegSignSum = mux(io.fromPreMul.isCDominant, T_554, notCDom_signSigSum) node T_556 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_556) node T_558 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) node T_559 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_558, T_559) node T_561 = not(io.fromPreMul.isCDominant) node T_562 = not(notCDom_signSigSum) node T_563 = and(T_561, T_562) node doIncrSig = and(T_563, doSubMags) node estNormDist_5 = bits(estNormDist, 4, 0) node normTo2ShiftDist = not(estNormDist_5) node T_568 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) node T_569 = bits(T_568, 31, 1) node T_570 = bits(T_569, 15, 0) node T_573 = shl(UInt<8>("h0ff"), 8) node T_574 = xor(UInt<16>("h0ffff"), T_573) node T_575 = shr(T_570, 8) node T_576 = and(T_575, T_574) node T_577 = bits(T_570, 7, 0) node T_578 = shl(T_577, 8) node T_579 = not(T_574) node T_580 = and(T_578, T_579) node T_581 = or(T_576, T_580) node T_582 = bits(T_574, 11, 0) node T_583 = shl(T_582, 4) node T_584 = xor(T_574, T_583) node T_585 = shr(T_581, 4) node T_586 = and(T_585, T_584) node T_587 = bits(T_581, 11, 0) node T_588 = shl(T_587, 4) node T_589 = not(T_584) node T_590 = and(T_588, T_589) node T_591 = or(T_586, T_590) node T_592 = bits(T_584, 13, 0) node T_593 = shl(T_592, 2) node T_594 = xor(T_584, T_593) node T_595 = shr(T_591, 2) node T_596 = and(T_595, T_594) node T_597 = bits(T_591, 13, 0) node T_598 = shl(T_597, 2) node T_599 = not(T_594) node T_600 = and(T_598, T_599) node T_601 = or(T_596, T_600) node T_602 = bits(T_594, 14, 0) node T_603 = shl(T_602, 1) node T_604 = xor(T_594, T_603) node T_605 = shr(T_601, 1) node T_606 = and(T_605, T_604) node T_607 = bits(T_601, 14, 0) node T_608 = shl(T_607, 1) node T_609 = not(T_604) node T_610 = and(T_608, T_609) node T_611 = or(T_606, T_610) node T_612 = bits(T_569, 30, 16) node T_613 = bits(T_612, 7, 0) node T_616 = shl(UInt<4>("h0f"), 4) node T_617 = xor(UInt<8>("h0ff"), T_616) node T_618 = shr(T_613, 4) node T_619 = and(T_618, T_617) node T_620 = bits(T_613, 3, 0) node T_621 = shl(T_620, 4) node T_622 = not(T_617) node T_623 = and(T_621, T_622) node T_624 = or(T_619, T_623) node T_625 = bits(T_617, 5, 0) node T_626 = shl(T_625, 2) node T_627 = xor(T_617, T_626) node T_628 = shr(T_624, 2) node T_629 = and(T_628, T_627) node T_630 = bits(T_624, 5, 0) node T_631 = shl(T_630, 2) node T_632 = not(T_627) node T_633 = and(T_631, T_632) node T_634 = or(T_629, T_633) node T_635 = bits(T_627, 6, 0) node T_636 = shl(T_635, 1) node T_637 = xor(T_627, T_636) node T_638 = shr(T_634, 1) node T_639 = and(T_638, T_637) node T_640 = bits(T_634, 6, 0) node T_641 = shl(T_640, 1) node T_642 = not(T_637) node T_643 = and(T_641, T_642) node T_644 = or(T_639, T_643) node T_645 = bits(T_612, 14, 8) node T_646 = bits(T_645, 3, 0) node T_647 = bits(T_646, 1, 0) node T_648 = bits(T_647, 0, 0) node T_649 = bits(T_647, 1, 1) node T_650 = cat(T_648, T_649) node T_651 = bits(T_646, 3, 2) node T_652 = bits(T_651, 0, 0) node T_653 = bits(T_651, 1, 1) node T_654 = cat(T_652, T_653) node T_655 = cat(T_650, T_654) node T_656 = bits(T_645, 6, 4) node T_657 = bits(T_656, 1, 0) node T_658 = bits(T_657, 0, 0) node T_659 = bits(T_657, 1, 1) node T_660 = cat(T_658, T_659) node T_661 = bits(T_656, 2, 2) node T_662 = cat(T_660, T_661) node T_663 = cat(T_655, T_662) node T_664 = cat(T_644, T_663) node T_665 = cat(T_611, T_664) node absSigSumExtraMask = cat(T_665, UInt<1>("h01")) node T_668 = bits(cFirstNormAbsSigSum, 87, 1) node T_669 = dshr(T_668, normTo2ShiftDist) node T_670 = bits(cFirstNormAbsSigSum, 31, 0) node T_671 = not(T_670) node T_672 = and(T_671, absSigSumExtraMask) node T_674 = eq(T_672, UInt<1>("h00")) node T_675 = bits(cFirstNormAbsSigSum, 31, 0) node T_676 = and(T_675, absSigSumExtraMask) node T_678 = neq(T_676, UInt<1>("h00")) node T_679 = mux(doIncrSig, T_674, T_678) node T_680 = cat(T_669, T_679) node sigX3 = bits(T_680, 56, 0) node T_682 = bits(sigX3, 56, 55) node sigX3Shift1 = eq(T_682, UInt<1>("h00")) node sExpX3 = subw(io.fromPreMul.sExpSum, estNormDist) node T_686 = bits(sigX3, 56, 54) node isZeroY = eq(T_686, UInt<1>("h00")) node T_689 = xor(io.fromPreMul.signProd, doNegSignSum) node signY = mux(isZeroY, signZeroNotEqOpSigns, T_689) node sExpX3_13 = bits(sExpX3, 12, 0) node T_692 = bit(sExpX3, 13) node T_694 = subw(UInt<56>("h00"), T_692) node T_695 = not(sExpX3_13) node T_697 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_695) node T_698 = bits(T_697, 1027, 974) node T_699 = bits(T_698, 31, 0) node T_702 = shl(UInt<16>("h0ffff"), 16) node T_703 = xor(UInt<32>("h0ffffffff"), T_702) node T_704 = shr(T_699, 16) node T_705 = and(T_704, T_703) node T_706 = bits(T_699, 15, 0) node T_707 = shl(T_706, 16) node T_708 = not(T_703) node T_709 = and(T_707, T_708) node T_710 = or(T_705, T_709) node T_711 = bits(T_703, 23, 0) node T_712 = shl(T_711, 8) node T_713 = xor(T_703, T_712) node T_714 = shr(T_710, 8) node T_715 = and(T_714, T_713) node T_716 = bits(T_710, 23, 0) node T_717 = shl(T_716, 8) node T_718 = not(T_713) node T_719 = and(T_717, T_718) node T_720 = or(T_715, T_719) node T_721 = bits(T_713, 27, 0) node T_722 = shl(T_721, 4) node T_723 = xor(T_713, T_722) node T_724 = shr(T_720, 4) node T_725 = and(T_724, T_723) node T_726 = bits(T_720, 27, 0) node T_727 = shl(T_726, 4) node T_728 = not(T_723) node T_729 = and(T_727, T_728) node T_730 = or(T_725, T_729) node T_731 = bits(T_723, 29, 0) node T_732 = shl(T_731, 2) node T_733 = xor(T_723, T_732) node T_734 = shr(T_730, 2) node T_735 = and(T_734, T_733) node T_736 = bits(T_730, 29, 0) node T_737 = shl(T_736, 2) node T_738 = not(T_733) node T_739 = and(T_737, T_738) node T_740 = or(T_735, T_739) node T_741 = bits(T_733, 30, 0) node T_742 = shl(T_741, 1) node T_743 = xor(T_733, T_742) node T_744 = shr(T_740, 1) node T_745 = and(T_744, T_743) node T_746 = bits(T_740, 30, 0) node T_747 = shl(T_746, 1) node T_748 = not(T_743) node T_749 = and(T_747, T_748) node T_750 = or(T_745, T_749) node T_751 = bits(T_698, 53, 32) node T_752 = bits(T_751, 15, 0) node T_755 = shl(UInt<8>("h0ff"), 8) node T_756 = xor(UInt<16>("h0ffff"), T_755) node T_757 = shr(T_752, 8) node T_758 = and(T_757, T_756) node T_759 = bits(T_752, 7, 0) node T_760 = shl(T_759, 8) node T_761 = not(T_756) node T_762 = and(T_760, T_761) node T_763 = or(T_758, T_762) node T_764 = bits(T_756, 11, 0) node T_765 = shl(T_764, 4) node T_766 = xor(T_756, T_765) node T_767 = shr(T_763, 4) node T_768 = and(T_767, T_766) node T_769 = bits(T_763, 11, 0) node T_770 = shl(T_769, 4) node T_771 = not(T_766) node T_772 = and(T_770, T_771) node T_773 = or(T_768, T_772) node T_774 = bits(T_766, 13, 0) node T_775 = shl(T_774, 2) node T_776 = xor(T_766, T_775) node T_777 = shr(T_773, 2) node T_778 = and(T_777, T_776) node T_779 = bits(T_773, 13, 0) node T_780 = shl(T_779, 2) node T_781 = not(T_776) node T_782 = and(T_780, T_781) node T_783 = or(T_778, T_782) node T_784 = bits(T_776, 14, 0) node T_785 = shl(T_784, 1) node T_786 = xor(T_776, T_785) node T_787 = shr(T_783, 1) node T_788 = and(T_787, T_786) node T_789 = bits(T_783, 14, 0) node T_790 = shl(T_789, 1) node T_791 = not(T_786) node T_792 = and(T_790, T_791) node T_793 = or(T_788, T_792) node T_794 = bits(T_751, 21, 16) node T_795 = bits(T_794, 3, 0) node T_796 = bits(T_795, 1, 0) node T_797 = bits(T_796, 0, 0) node T_798 = bits(T_796, 1, 1) node T_799 = cat(T_797, T_798) node T_800 = bits(T_795, 3, 2) node T_801 = bits(T_800, 0, 0) node T_802 = bits(T_800, 1, 1) node T_803 = cat(T_801, T_802) node T_804 = cat(T_799, T_803) node T_805 = bits(T_794, 5, 4) node T_806 = bits(T_805, 0, 0) node T_807 = bits(T_805, 1, 1) node T_808 = cat(T_806, T_807) node T_809 = cat(T_804, T_808) node T_810 = cat(T_793, T_809) node T_811 = cat(T_750, T_810) node T_812 = bit(sigX3, 55) node T_813 = or(T_811, T_812) node T_815 = cat(T_813, UInt<2>("h03")) node roundMask = or(T_694, T_815) node T_817 = shr(roundMask, 1) node T_818 = not(T_817) node roundPosMask = and(T_818, roundMask) node T_820 = and(sigX3, roundPosMask) node roundPosBit = neq(T_820, UInt<1>("h00")) node T_823 = shr(roundMask, 1) node T_824 = and(sigX3, T_823) node anyRoundExtra = neq(T_824, UInt<1>("h00")) node T_827 = not(sigX3) node T_828 = shr(roundMask, 1) node T_829 = and(T_827, T_828) node allRoundExtra = eq(T_829, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) node T_835 = not(doIncrSig) node T_836 = and(T_835, roundingMode_nearest_even) node T_837 = and(T_836, roundPosBit) node T_838 = and(T_837, anyRoundExtra) node T_839 = not(doIncrSig) node T_840 = and(T_839, roundDirectUp) node T_841 = and(T_840, anyRound) node T_842 = or(T_838, T_841) node T_843 = and(doIncrSig, allRound) node T_844 = or(T_842, T_843) node T_845 = and(doIncrSig, roundingMode_nearest_even) node T_846 = and(T_845, roundPosBit) node T_847 = or(T_844, T_846) node T_848 = and(doIncrSig, roundDirectUp) node T_850 = and(T_848, UInt<1>("h01")) node roundUp = or(T_847, T_850) node T_852 = not(roundPosBit) node T_853 = and(roundingMode_nearest_even, T_852) node T_854 = and(T_853, allRoundExtra) node T_855 = and(roundingMode_nearest_even, roundPosBit) node T_856 = not(anyRoundExtra) node T_857 = and(T_855, T_856) node roundEven = mux(doIncrSig, T_854, T_857) node T_859 = not(allRound) node roundInexact = mux(doIncrSig, T_859, anyRound) node T_861 = or(sigX3, roundMask) node T_862 = shr(T_861, 2) node T_864 = addw(T_862, UInt<1>("h01")) node roundUp_sigY3 = bits(T_864, 54, 0) node T_866 = not(roundUp) node T_867 = not(roundEven) node T_868 = and(T_866, T_867) node T_869 = bit(T_868, 0) node T_870 = not(roundMask) node T_871 = and(sigX3, T_870) node T_872 = shr(T_871, 2) node T_874 = mux(T_869, T_872, UInt<1>("h00")) node T_875 = bit(roundUp, 0) node T_877 = mux(T_875, roundUp_sigY3, UInt<1>("h00")) node T_878 = or(T_874, T_877) node T_879 = shr(roundMask, 1) node T_880 = not(T_879) node T_881 = and(roundUp_sigY3, T_880) node T_883 = mux(roundEven, T_881, UInt<1>("h00")) node sigY3 = or(T_878, T_883) node T_885 = bit(sigY3, 54) node T_887 = addw(sExpX3, UInt<1>("h01")) node T_889 = mux(T_885, T_887, UInt<1>("h00")) node T_890 = bit(sigY3, 53) node T_892 = mux(T_890, sExpX3, UInt<1>("h00")) node T_893 = or(T_889, T_892) node T_894 = bits(sigY3, 54, 53) node T_896 = eq(T_894, UInt<1>("h00")) node T_898 = subw(sExpX3, UInt<1>("h01")) node T_900 = mux(T_896, T_898, UInt<1>("h00")) node sExpY = or(T_893, T_900) node expY = bits(sExpY, 11, 0) node T_903 = bits(sigY3, 51, 0) node T_904 = bits(sigY3, 52, 1) node fractY = mux(sigX3Shift1, T_903, T_904) node T_906 = bits(sExpY, 12, 10) node overflowY = eq(T_906, UInt<2>("h03")) node T_909 = not(isZeroY) node T_910 = bit(sExpY, 12) node T_911 = bits(sExpY, 11, 0) node T_913 = lt(T_911, UInt<10>("h03ce")) node T_914 = or(T_910, T_913) node totalUnderflowY = and(T_909, T_914) node T_916 = bit(sExpX3, 13) node T_919 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) node T_920 = leq(sExpX3_13, T_919) node T_921 = or(T_916, T_920) node underflowY = and(roundInexact, T_921) node T_923 = and(roundingMode_min, signY) node T_924 = not(signY) node T_925 = and(roundingMode_max, T_924) node roundMagUp = or(T_923, T_925) node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) node T_931 = not(addSpecial) node T_932 = not(notSpecial_addZeros) node commonCase = and(T_931, T_932) node T_934 = and(isInfA, isZeroB) node T_935 = and(isZeroA, isInfB) node T_936 = or(T_934, T_935) node T_937 = not(isNaNA) node T_938 = not(isNaNB) node T_939 = and(T_937, T_938) node T_940 = or(isInfA, isInfB) node T_941 = and(T_939, T_940) node T_942 = and(T_941, isInfC) node T_943 = and(T_942, doSubMags) node notSigNaN_invalid = or(T_936, T_943) node T_945 = or(isSigNaNA, isSigNaNB) node T_946 = or(T_945, isSigNaNC) node invalid = or(T_946, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) node T_950 = and(commonCase, roundInexact) node inexact = or(overflow, T_950) node T_952 = or(notSpecial_addZeros, isZeroY) node notSpecial_isZeroOut = or(T_952, totalUnderflowY) node T_954 = and(commonCase, totalUnderflowY) node pegMinFiniteMagOut = and(T_954, roundMagUp) node T_956 = not(overflowY_roundMagUp) node pegMaxFiniteMagOut = and(overflow, T_956) node T_958 = or(isInfA, isInfB) node T_959 = or(T_958, isInfC) node T_960 = and(overflow, overflowY_roundMagUp) node notNaN_isInfOut = or(T_959, T_960) node T_962 = or(isNaNA, isNaNB) node T_963 = or(T_962, isNaNC) node isNaNOut = or(T_963, notSigNaN_invalid) node T_966 = eq(doSubMags, UInt<1>("h00")) node T_967 = and(T_966, io.fromPreMul.opSignC) node T_969 = eq(isSpecialC, UInt<1>("h00")) node T_970 = and(mulSpecial, T_969) node T_971 = and(T_970, io.fromPreMul.signProd) node T_972 = or(T_967, T_971) node T_974 = eq(mulSpecial, UInt<1>("h00")) node T_975 = and(T_974, isSpecialC) node T_976 = and(T_975, io.fromPreMul.opSignC) node T_977 = or(T_972, T_976) node T_979 = eq(mulSpecial, UInt<1>("h00")) node T_980 = and(T_979, notSpecial_addZeros) node T_981 = and(T_980, doSubMags) node T_982 = and(T_981, signZeroNotEqOpSigns) node uncommonCaseSignOut = or(T_977, T_982) node T_985 = eq(isNaNOut, UInt<1>("h00")) node T_986 = and(T_985, uncommonCaseSignOut) node T_987 = and(commonCase, signY) node signOut = or(T_986, T_987) node T_991 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) node T_992 = not(T_991) node T_993 = and(expY, T_992) node T_995 = not(UInt<12>("h03ce")) node T_997 = mux(pegMinFiniteMagOut, T_995, UInt<12>("h00")) node T_998 = not(T_997) node T_999 = and(T_993, T_998) node T_1002 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) node T_1003 = not(T_1002) node T_1004 = and(T_999, T_1003) node T_1007 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) node T_1008 = not(T_1007) node T_1009 = and(T_1004, T_1008) node T_1012 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) node T_1013 = or(T_1009, T_1012) node T_1016 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) node T_1017 = or(T_1013, T_1016) node T_1020 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) node T_1021 = or(T_1017, T_1020) node T_1024 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) node expOut = or(T_1021, T_1024) node T_1026 = and(totalUnderflowY, roundMagUp) node T_1027 = or(T_1026, isNaNOut) node T_1029 = mux(T_1027, UInt<1>("h00"), fractY) node T_1030 = shl(isNaNOut, 51) node T_1031 = or(T_1029, T_1030) node T_1033 = subw(UInt<52>("h00"), pegMaxFiniteMagOut) node fractOut = or(T_1031, T_1033) node T_1035 = cat(expOut, fractOut) node T_1036 = cat(signOut, T_1035) io.out <= T_1036 node T_1038 = cat(invalid, UInt<1>("h00")) node T_1039 = cat(underflow, inexact) node T_1040 = cat(overflow, T_1039) node T_1041 = cat(T_1038, T_1040) io.exceptionFlags <= T_1041 module MulAddRecFN_114 : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") inst mulAddRecFN_preMul of MulAddRecFN_preMul_115 mulAddRecFN_preMul.io.roundingMode <= UInt<1>("h00") mulAddRecFN_preMul.io.c <= UInt<1>("h00") mulAddRecFN_preMul.io.b <= UInt<1>("h00") mulAddRecFN_preMul.io.a <= UInt<1>("h00") mulAddRecFN_preMul.io.op <= UInt<1>("h00") mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset inst mulAddRecFN_postMul of MulAddRecFN_postMul_116 mulAddRecFN_postMul.io.mulAddResult <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.roundingMode <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.sExpSum <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highAlignedNegSigC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.bit0AlignedNegSigC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.CAlignDist <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.CAlignDist_0 <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isCDominant <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.opSignC <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isZeroProd <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.signProd <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNB <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpB <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNA <= UInt<1>("h00") mulAddRecFN_postMul.io.fromPreMul.highExpA <= UInt<1>("h00") mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset mulAddRecFN_preMul.io.op <= io.op mulAddRecFN_preMul.io.a <= io.a mulAddRecFN_preMul.io.b <= io.b mulAddRecFN_preMul.io.c <= io.c mulAddRecFN_preMul.io.roundingMode <= io.roundingMode mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul node T_36 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) node T_38 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) node T_39 = addw(T_36, T_38) mulAddRecFN_postMul.io.mulAddResult <= T_39 io.out <= mulAddRecFN_postMul.io.out io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags module FPUFMAPipe_113 : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") node one = shl(UInt<1>("h01"), 63) node T_136 = bit(io.in.bits.in1, 64) node T_137 = bit(io.in.bits.in2, 64) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 64) reg valid : UInt<1>, clk, UInt<1>("h00"), valid valid <= io.in.valid reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in when io.in.valid : in <- io.in.bits node T_187 = bit(io.in.bits.cmd, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) node T_190 = bit(io.in.bits.cmd, 0) node T_191 = cat(T_189, T_190) in.cmd <= T_191 when io.in.bits.swap23 : in.in2 <= one skip node T_192 = or(io.in.bits.ren3, io.in.bits.swap23) node T_194 = eq(T_192, UInt<1>("h00")) when T_194 : in.in3 <= zero skip skip inst fma of MulAddRecFN_114 fma.io.roundingMode <= UInt<1>("h00") fma.io.c <= UInt<1>("h00") fma.io.b <= UInt<1>("h00") fma.io.a <= UInt<1>("h00") fma.io.op <= UInt<1>("h00") fma.clk <= clk fma.reset <= reset fma.io.op <= in.cmd fma.io.roundingMode <= in.rm fma.io.a <= in.in1 fma.io.b <= in.in2 fma.io.c <= in.in3 wire res : {data : UInt<65>, exc : UInt<5>} res.exc <= UInt<1>("h00") res.data <= UInt<1>("h00") node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_211 = cat(T_210, fma.io.out) res.data <= T_211 res.exc <= fma.io.exceptionFlags reg T_214 : UInt<1>, clk, reset, UInt<1>("h00") T_214 <= valid reg T_215 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_215 when valid : T_215 <- res skip reg T_220 : UInt<1>, clk, reset, UInt<1>("h00") T_220 <= T_214 reg T_221 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_221 when T_214 : T_221 <- T_215 skip wire T_232 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_232.bits.exc <= UInt<1>("h00") T_232.bits.data <= UInt<1>("h00") T_232.valid <= UInt<1>("h00") T_232.valid <= T_220 T_232.bits <- T_221 io.out <- T_232 module RecFNToRecFN : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node T_8 = bits(io.in, 31, 23) node T_9 = bits(T_8, 8, 7) node T_11 = eq(T_9, UInt<2>("h03")) wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} T_19.sig <= UInt<1>("h00") T_19.sExp <= asSInt(UInt<1>("h00")) T_19.isZero <= UInt<1>("h00") T_19.isInf <= UInt<1>("h00") T_19.isNaN <= UInt<1>("h00") T_19.sign <= UInt<1>("h00") node T_32 = bit(io.in, 32) T_19.sign <= T_32 node T_33 = bit(T_8, 6) node T_34 = and(T_11, T_33) T_19.isNaN <= T_34 node T_35 = bit(T_8, 6) node T_37 = eq(T_35, UInt<1>("h00")) node T_38 = and(T_11, T_37) T_19.isInf <= T_38 node T_39 = bits(T_8, 8, 6) node T_41 = eq(T_39, UInt<1>("h00")) T_19.isZero <= T_41 node T_42 = cvt(T_8) T_19.sExp <= T_42 node T_44 = bits(io.in, 22, 0) node T_46 = cat(T_44, UInt<2>("h00")) node T_47 = cat(UInt<2>("h01"), T_46) T_19.sig <= T_47 node T_49 = addw(T_19.sExp, asSInt(UInt<12>("h0700"))) wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} outRawFloat.sig <= UInt<1>("h00") outRawFloat.sExp <= asSInt(UInt<1>("h00")) outRawFloat.isZero <= UInt<1>("h00") outRawFloat.isInf <= UInt<1>("h00") outRawFloat.isNaN <= UInt<1>("h00") outRawFloat.sign <= UInt<1>("h00") outRawFloat.sign <= T_19.sign outRawFloat.isNaN <= T_19.isNaN outRawFloat.isInf <= T_19.isInf outRawFloat.isZero <= T_19.isZero outRawFloat.sExp <= T_49 node T_70 = shl(T_19.sig, 29) outRawFloat.sig <= T_70 node T_71 = bit(outRawFloat.sig, 53) node T_73 = eq(T_71, UInt<1>("h00")) node invalidExc = and(outRawFloat.isNaN, T_73) node T_75 = not(outRawFloat.isNaN) node T_76 = and(outRawFloat.sign, T_75) node T_77 = bits(outRawFloat.sExp, 11, 0) node T_80 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) node T_81 = not(T_80) node T_82 = and(T_77, T_81) node T_83 = or(outRawFloat.isZero, outRawFloat.isInf) node T_86 = mux(T_83, UInt<12>("h0200"), UInt<1>("h00")) node T_87 = not(T_86) node T_88 = and(T_82, T_87) node T_91 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) node T_92 = or(T_88, T_91) node T_95 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) node T_96 = or(T_92, T_95) node T_98 = bits(outRawFloat.sig, 53, 2) node T_99 = mux(outRawFloat.isNaN, UInt<52>("h08000000000000"), T_98) node T_100 = cat(T_96, T_99) node T_101 = cat(T_76, T_100) io.out <= T_101 node T_103 = cat(invalidExc, UInt<4>("h00")) io.exceptionFlags <= T_103 module CompareRecFN : input clk : Clock input reset : UInt<1> output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.gt <= UInt<1>("h00") io.eq <= UInt<1>("h00") io.lt <= UInt<1>("h00") node T_11 = bits(io.a, 63, 52) node T_12 = bits(T_11, 11, 10) node T_14 = eq(T_12, UInt<2>("h03")) wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} rawA.sig <= UInt<1>("h00") rawA.sExp <= asSInt(UInt<1>("h00")) rawA.isZero <= UInt<1>("h00") rawA.isInf <= UInt<1>("h00") rawA.isNaN <= UInt<1>("h00") rawA.sign <= UInt<1>("h00") node T_35 = bit(io.a, 64) rawA.sign <= T_35 node T_36 = bit(T_11, 9) node T_37 = and(T_14, T_36) rawA.isNaN <= T_37 node T_38 = bit(T_11, 9) node T_40 = eq(T_38, UInt<1>("h00")) node T_41 = and(T_14, T_40) rawA.isInf <= T_41 node T_42 = bits(T_11, 11, 9) node T_44 = eq(T_42, UInt<1>("h00")) rawA.isZero <= T_44 node T_45 = cvt(T_11) rawA.sExp <= T_45 node T_47 = bits(io.a, 51, 0) node T_49 = cat(T_47, UInt<2>("h00")) node T_50 = cat(UInt<2>("h01"), T_49) rawA.sig <= T_50 node T_51 = bits(io.b, 63, 52) node T_52 = bits(T_51, 11, 10) node T_54 = eq(T_52, UInt<2>("h03")) wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} rawB.sig <= UInt<1>("h00") rawB.sExp <= asSInt(UInt<1>("h00")) rawB.isZero <= UInt<1>("h00") rawB.isInf <= UInt<1>("h00") rawB.isNaN <= UInt<1>("h00") rawB.sign <= UInt<1>("h00") node T_75 = bit(io.b, 64) rawB.sign <= T_75 node T_76 = bit(T_51, 9) node T_77 = and(T_54, T_76) rawB.isNaN <= T_77 node T_78 = bit(T_51, 9) node T_80 = eq(T_78, UInt<1>("h00")) node T_81 = and(T_54, T_80) rawB.isInf <= T_81 node T_82 = bits(T_51, 11, 9) node T_84 = eq(T_82, UInt<1>("h00")) rawB.isZero <= T_84 node T_85 = cvt(T_51) rawB.sExp <= T_85 node T_87 = bits(io.b, 51, 0) node T_89 = cat(T_87, UInt<2>("h00")) node T_90 = cat(UInt<2>("h01"), T_89) rawB.sig <= T_90 node T_91 = not(rawA.isNaN) node T_92 = not(rawB.isNaN) node ordered = and(T_91, T_92) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node T_97 = lt(rawA.sExp, rawB.sExp) node T_98 = lt(rawA.sig, rawB.sig) node T_99 = and(eqExps, T_98) node common_ltMags = or(T_97, T_99) node T_101 = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, T_101) node T_103 = not(bothZeros) node T_104 = not(rawB.sign) node T_105 = and(rawA.sign, T_104) node T_106 = not(bothInfs) node T_107 = not(common_ltMags) node T_108 = and(rawA.sign, T_107) node T_109 = not(common_eqMags) node T_110 = and(T_108, T_109) node T_111 = not(rawB.sign) node T_112 = and(T_111, common_ltMags) node T_113 = or(T_110, T_112) node T_114 = and(T_106, T_113) node T_115 = or(T_105, T_114) node ordered_lt = and(T_103, T_115) node T_117 = eq(rawA.sign, rawB.sign) node T_118 = or(bothInfs, common_eqMags) node T_119 = and(T_117, T_118) node ordered_eq = or(bothZeros, T_119) node T_121 = bit(rawA.sig, 53) node T_123 = eq(T_121, UInt<1>("h00")) node T_124 = and(rawA.isNaN, T_123) node T_125 = bit(rawB.sig, 53) node T_127 = eq(T_125, UInt<1>("h00")) node T_128 = and(rawB.isNaN, T_127) node T_129 = or(T_124, T_128) node T_130 = not(ordered) node T_131 = and(io.signaling, T_130) node invalid = or(T_129, T_131) node T_133 = and(ordered, ordered_lt) io.lt <= T_133 node T_134 = and(ordered, ordered_eq) io.eq <= T_134 node T_135 = not(ordered_lt) node T_136 = and(ordered, T_135) node T_137 = not(ordered_eq) node T_138 = and(T_136, T_137) io.gt <= T_138 node T_140 = cat(invalid, UInt<4>("h00")) io.exceptionFlags <= T_140 module RecFNToIN : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} io.intExceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node sign = bit(io.in, 64) node exp = bits(io.in, 63, 52) node fract = bits(io.in, 51, 0) node T_12 = bits(exp, 11, 9) node isZero = eq(T_12, UInt<1>("h00")) node T_15 = bits(exp, 11, 10) node T_16 = not(T_15) node isSpecial = eq(T_16, UInt<1>("h00")) node T_19 = bit(exp, 9) node isNaN = and(isSpecial, T_19) node notSpecial_magGeOne = bit(exp, 11) node T_22 = cat(notSpecial_magGeOne, fract) node T_23 = bits(exp, 5, 0) node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) node shiftedSig = dshl(T_22, T_25) node unroundedInt = bits(shiftedSig, 115, 52) node T_28 = bits(shiftedSig, 52, 51) node T_29 = bits(shiftedSig, 50, 0) node T_31 = neq(T_29, UInt<1>("h00")) node roundBits = cat(T_28, T_31) node T_33 = bits(roundBits, 1, 0) node T_35 = neq(T_33, UInt<1>("h00")) node T_37 = eq(isZero, UInt<1>("h00")) node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) node T_39 = bits(roundBits, 2, 1) node T_40 = not(T_39) node T_42 = eq(T_40, UInt<1>("h00")) node T_43 = bits(roundBits, 1, 0) node T_44 = not(T_43) node T_46 = eq(T_44, UInt<1>("h00")) node T_47 = or(T_42, T_46) node T_48 = bits(exp, 10, 0) node T_49 = not(T_48) node T_51 = eq(T_49, UInt<1>("h00")) node T_52 = bits(roundBits, 1, 0) node T_54 = neq(T_52, UInt<1>("h00")) node T_56 = mux(T_51, T_54, UInt<1>("h00")) node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) node T_58 = eq(io.roundingMode, UInt<2>("h00")) node T_59 = and(T_58, roundIncr_nearestEven) node T_60 = eq(io.roundingMode, UInt<2>("h02")) node T_61 = and(sign, roundInexact) node T_62 = and(T_60, T_61) node T_63 = or(T_59, T_62) node T_64 = eq(io.roundingMode, UInt<2>("h03")) node T_66 = eq(sign, UInt<1>("h00")) node T_67 = and(T_66, roundInexact) node T_68 = and(T_64, T_67) node roundIncr = or(T_63, T_68) node T_70 = not(unroundedInt) node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) node T_72 = xor(roundIncr, sign) node T_74 = addw(onesCompUnroundedInt, UInt<1>("h01")) node roundedInt = mux(T_72, T_74, onesCompUnroundedInt) node T_76 = bits(unroundedInt, 61, 0) node T_77 = not(T_76) node T_79 = eq(T_77, UInt<1>("h00")) node roundCarryBut2 = and(T_79, roundIncr) node posExp = bits(exp, 10, 0) node T_83 = geq(posExp, UInt<7>("h040")) node T_85 = eq(posExp, UInt<6>("h03f")) node T_87 = eq(sign, UInt<1>("h00")) node T_88 = bits(unroundedInt, 62, 0) node T_90 = neq(T_88, UInt<1>("h00")) node T_91 = or(T_87, T_90) node T_92 = or(T_91, roundIncr) node T_93 = and(T_85, T_92) node T_94 = or(T_83, T_93) node T_96 = eq(sign, UInt<1>("h00")) node T_98 = eq(posExp, UInt<6>("h03e")) node T_99 = and(T_96, T_98) node T_100 = and(T_99, roundCarryBut2) node T_101 = or(T_94, T_100) node overflow_signed = mux(notSpecial_magGeOne, T_101, UInt<1>("h00")) node T_105 = geq(posExp, UInt<7>("h040")) node T_106 = or(sign, T_105) node T_108 = eq(posExp, UInt<6>("h03f")) node T_109 = bit(unroundedInt, 62) node T_110 = and(T_108, T_109) node T_111 = and(T_110, roundCarryBut2) node T_112 = or(T_106, T_111) node T_113 = and(sign, roundIncr) node overflow_unsigned = mux(notSpecial_magGeOne, T_112, T_113) node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) node T_117 = eq(isNaN, UInt<1>("h00")) node excSign = and(sign, T_117) node T_119 = and(io.signedOut, excSign) node T_122 = mux(T_119, UInt<64>("h08000000000000000"), UInt<1>("h00")) node T_124 = eq(excSign, UInt<1>("h00")) node T_125 = and(io.signedOut, T_124) node T_128 = mux(T_125, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) node T_129 = or(T_122, T_128) node T_131 = eq(io.signedOut, UInt<1>("h00")) node T_134 = mux(T_131, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) node excValue = or(T_129, T_134) node T_137 = eq(isSpecial, UInt<1>("h00")) node T_138 = and(roundInexact, T_137) node T_140 = eq(overflow, UInt<1>("h00")) node inexact = and(T_138, T_140) node T_142 = or(isSpecial, overflow) node T_143 = mux(T_142, excValue, roundedInt) io.out <= T_143 node T_144 = cat(overflow, inexact) node T_145 = cat(isSpecial, T_144) io.intExceptionFlags <= T_145 module RecFNToIN_118 : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} io.intExceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node sign = bit(io.in, 64) node exp = bits(io.in, 63, 52) node fract = bits(io.in, 51, 0) node T_12 = bits(exp, 11, 9) node isZero = eq(T_12, UInt<1>("h00")) node T_15 = bits(exp, 11, 10) node T_16 = not(T_15) node isSpecial = eq(T_16, UInt<1>("h00")) node T_19 = bit(exp, 9) node isNaN = and(isSpecial, T_19) node notSpecial_magGeOne = bit(exp, 11) node T_22 = cat(notSpecial_magGeOne, fract) node T_23 = bits(exp, 4, 0) node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) node shiftedSig = dshl(T_22, T_25) node unroundedInt = bits(shiftedSig, 83, 52) node T_28 = bits(shiftedSig, 52, 51) node T_29 = bits(shiftedSig, 50, 0) node T_31 = neq(T_29, UInt<1>("h00")) node roundBits = cat(T_28, T_31) node T_33 = bits(roundBits, 1, 0) node T_35 = neq(T_33, UInt<1>("h00")) node T_37 = eq(isZero, UInt<1>("h00")) node roundInexact = mux(notSpecial_magGeOne, T_35, T_37) node T_39 = bits(roundBits, 2, 1) node T_40 = not(T_39) node T_42 = eq(T_40, UInt<1>("h00")) node T_43 = bits(roundBits, 1, 0) node T_44 = not(T_43) node T_46 = eq(T_44, UInt<1>("h00")) node T_47 = or(T_42, T_46) node T_48 = bits(exp, 10, 0) node T_49 = not(T_48) node T_51 = eq(T_49, UInt<1>("h00")) node T_52 = bits(roundBits, 1, 0) node T_54 = neq(T_52, UInt<1>("h00")) node T_56 = mux(T_51, T_54, UInt<1>("h00")) node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56) node T_58 = eq(io.roundingMode, UInt<2>("h00")) node T_59 = and(T_58, roundIncr_nearestEven) node T_60 = eq(io.roundingMode, UInt<2>("h02")) node T_61 = and(sign, roundInexact) node T_62 = and(T_60, T_61) node T_63 = or(T_59, T_62) node T_64 = eq(io.roundingMode, UInt<2>("h03")) node T_66 = eq(sign, UInt<1>("h00")) node T_67 = and(T_66, roundInexact) node T_68 = and(T_64, T_67) node roundIncr = or(T_63, T_68) node T_70 = not(unroundedInt) node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) node T_72 = xor(roundIncr, sign) node T_74 = addw(onesCompUnroundedInt, UInt<1>("h01")) node roundedInt = mux(T_72, T_74, onesCompUnroundedInt) node T_76 = bits(unroundedInt, 29, 0) node T_77 = not(T_76) node T_79 = eq(T_77, UInt<1>("h00")) node roundCarryBut2 = and(T_79, roundIncr) node posExp = bits(exp, 10, 0) node T_83 = geq(posExp, UInt<6>("h020")) node T_85 = eq(posExp, UInt<5>("h01f")) node T_87 = eq(sign, UInt<1>("h00")) node T_88 = bits(unroundedInt, 30, 0) node T_90 = neq(T_88, UInt<1>("h00")) node T_91 = or(T_87, T_90) node T_92 = or(T_91, roundIncr) node T_93 = and(T_85, T_92) node T_94 = or(T_83, T_93) node T_96 = eq(sign, UInt<1>("h00")) node T_98 = eq(posExp, UInt<5>("h01e")) node T_99 = and(T_96, T_98) node T_100 = and(T_99, roundCarryBut2) node T_101 = or(T_94, T_100) node overflow_signed = mux(notSpecial_magGeOne, T_101, UInt<1>("h00")) node T_105 = geq(posExp, UInt<6>("h020")) node T_106 = or(sign, T_105) node T_108 = eq(posExp, UInt<5>("h01f")) node T_109 = bit(unroundedInt, 30) node T_110 = and(T_108, T_109) node T_111 = and(T_110, roundCarryBut2) node T_112 = or(T_106, T_111) node T_113 = and(sign, roundIncr) node overflow_unsigned = mux(notSpecial_magGeOne, T_112, T_113) node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) node T_117 = eq(isNaN, UInt<1>("h00")) node excSign = and(sign, T_117) node T_119 = and(io.signedOut, excSign) node T_122 = mux(T_119, UInt<32>("h080000000"), UInt<1>("h00")) node T_124 = eq(excSign, UInt<1>("h00")) node T_125 = and(io.signedOut, T_124) node T_128 = mux(T_125, UInt<31>("h07fffffff"), UInt<1>("h00")) node T_129 = or(T_122, T_128) node T_131 = eq(io.signedOut, UInt<1>("h00")) node T_134 = mux(T_131, UInt<32>("h0ffffffff"), UInt<1>("h00")) node excValue = or(T_129, T_134) node T_137 = eq(isSpecial, UInt<1>("h00")) node T_138 = and(roundInexact, T_137) node T_140 = eq(overflow, UInt<1>("h00")) node inexact = and(T_138, T_140) node T_142 = or(isSpecial, overflow) node T_143 = mux(T_142, excValue, roundedInt) io.out <= T_143 node T_144 = cat(overflow, inexact) node T_145 = cat(isSpecial, T_144) io.intExceptionFlags <= T_145 module FPToInt : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} io.out.bits.exc <= UInt<1>("h00") io.out.bits.toint <= UInt<1>("h00") io.out.bits.store <= UInt<1>("h00") io.out.bits.lt <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") io.as_double.in3 <= UInt<1>("h00") io.as_double.in2 <= UInt<1>("h00") io.as_double.in1 <= UInt<1>("h00") io.as_double.typ <= UInt<1>("h00") io.as_double.rm <= UInt<1>("h00") io.as_double.wflags <= UInt<1>("h00") io.as_double.round <= UInt<1>("h00") io.as_double.sqrt <= UInt<1>("h00") io.as_double.div <= UInt<1>("h00") io.as_double.fma <= UInt<1>("h00") io.as_double.fastpipe <= UInt<1>("h00") io.as_double.toint <= UInt<1>("h00") io.as_double.fromint <= UInt<1>("h00") io.as_double.single <= UInt<1>("h00") io.as_double.swap23 <= UInt<1>("h00") io.as_double.swap12 <= UInt<1>("h00") io.as_double.ren3 <= UInt<1>("h00") io.as_double.ren2 <= UInt<1>("h00") io.as_double.ren1 <= UInt<1>("h00") io.as_double.wen <= UInt<1>("h00") io.as_double.ldst <= UInt<1>("h00") io.as_double.cmd <= UInt<1>("h00") reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in reg valid : UInt<1>, clk, UInt<1>("h00"), valid valid <= io.in.valid inst T_233 of RecFNToRecFN T_233.io.roundingMode <= UInt<1>("h00") T_233.io.in <= UInt<1>("h00") T_233.clk <= clk T_233.reset <= reset T_233.io.in <= io.in.bits.in1 T_233.io.roundingMode <= UInt<1>("h00") inst T_237 of RecFNToRecFN T_237.io.roundingMode <= UInt<1>("h00") T_237.io.in <= UInt<1>("h00") T_237.clk <= clk T_237.reset <= reset T_237.io.in <= io.in.bits.in2 T_237.io.roundingMode <= UInt<1>("h00") when io.in.valid : in <- io.in.bits node T_242 = eq(io.in.bits.ldst, UInt<1>("h00")) node T_243 = and(io.in.bits.single, T_242) node T_246 = and(io.in.bits.cmd, UInt<4>("h0c")) node T_247 = eq(UInt<4>("h0c"), T_246) node T_249 = eq(T_247, UInt<1>("h00")) node T_250 = and(T_243, T_249) when T_250 : in.in1 <= T_233.io.out in.in2 <= T_237.io.out skip skip node T_251 = bit(in.in1, 32) node T_252 = bits(in.in1, 31, 23) node T_253 = bits(in.in1, 22, 0) node T_254 = bits(T_252, 6, 0) node T_256 = lt(T_254, UInt<2>("h02")) node T_257 = bits(T_252, 8, 6) node T_259 = eq(T_257, UInt<1>("h01")) node T_260 = bits(T_252, 8, 7) node T_262 = eq(T_260, UInt<1>("h01")) node T_263 = and(T_262, T_256) node T_264 = or(T_259, T_263) node T_265 = bits(T_252, 8, 7) node T_267 = eq(T_265, UInt<1>("h01")) node T_269 = eq(T_256, UInt<1>("h00")) node T_270 = and(T_267, T_269) node T_271 = bits(T_252, 8, 7) node T_273 = eq(T_271, UInt<2>("h02")) node T_274 = or(T_270, T_273) node T_275 = bits(T_252, 8, 7) node T_277 = eq(T_275, UInt<2>("h03")) node T_278 = bit(T_252, 6) node T_279 = and(T_277, T_278) node T_281 = bits(T_252, 4, 0) node T_282 = subw(UInt<2>("h02"), T_281) node T_284 = cat(UInt<1>("h01"), T_253) node T_285 = dshr(T_284, T_282) node T_286 = bits(T_285, 22, 0) node T_287 = bits(T_252, 7, 0) node T_289 = subw(T_287, UInt<8>("h081")) node T_291 = subw(UInt<8>("h00"), T_277) node T_292 = mux(T_274, T_289, T_291) node T_293 = or(T_274, T_279) node T_295 = mux(T_264, T_286, UInt<1>("h00")) node T_296 = mux(T_293, T_253, T_295) node T_297 = cat(T_292, T_296) node unrec_s = cat(T_251, T_297) node T_299 = bit(in.in1, 64) node T_300 = bits(in.in1, 63, 52) node T_301 = bits(in.in1, 51, 0) node T_302 = bits(T_300, 9, 0) node T_304 = lt(T_302, UInt<2>("h02")) node T_305 = bits(T_300, 11, 9) node T_307 = eq(T_305, UInt<1>("h01")) node T_308 = bits(T_300, 11, 10) node T_310 = eq(T_308, UInt<1>("h01")) node T_311 = and(T_310, T_304) node T_312 = or(T_307, T_311) node T_313 = bits(T_300, 11, 10) node T_315 = eq(T_313, UInt<1>("h01")) node T_317 = eq(T_304, UInt<1>("h00")) node T_318 = and(T_315, T_317) node T_319 = bits(T_300, 11, 10) node T_321 = eq(T_319, UInt<2>("h02")) node T_322 = or(T_318, T_321) node T_323 = bits(T_300, 11, 10) node T_325 = eq(T_323, UInt<2>("h03")) node T_326 = bit(T_300, 9) node T_327 = and(T_325, T_326) node T_329 = bits(T_300, 5, 0) node T_330 = subw(UInt<2>("h02"), T_329) node T_332 = cat(UInt<1>("h01"), T_301) node T_333 = dshr(T_332, T_330) node T_334 = bits(T_333, 51, 0) node T_335 = bits(T_300, 10, 0) node T_337 = subw(T_335, UInt<11>("h0401")) node T_339 = subw(UInt<11>("h00"), T_325) node T_340 = mux(T_322, T_337, T_339) node T_341 = or(T_322, T_327) node T_343 = mux(T_312, T_334, UInt<1>("h00")) node T_344 = mux(T_341, T_301, T_343) node T_345 = cat(T_340, T_344) node unrec_d = cat(T_299, T_345) node T_347 = bit(unrec_s, 31) node T_349 = subw(UInt<32>("h00"), T_347) node T_350 = cat(T_349, unrec_s) node unrec_out = mux(in.single, T_350, unrec_d) node T_352 = bit(in.in1, 32) node T_353 = bits(in.in1, 31, 23) node T_354 = bits(in.in1, 22, 0) node T_355 = bits(T_353, 8, 6) node T_356 = bits(T_355, 2, 1) node T_358 = eq(T_356, UInt<2>("h03")) node T_359 = bits(T_353, 6, 0) node T_361 = lt(T_359, UInt<2>("h02")) node T_363 = eq(T_355, UInt<1>("h01")) node T_365 = eq(T_356, UInt<1>("h01")) node T_366 = and(T_365, T_361) node T_367 = or(T_363, T_366) node T_369 = eq(T_356, UInt<1>("h01")) node T_371 = eq(T_361, UInt<1>("h00")) node T_372 = and(T_369, T_371) node T_374 = eq(T_356, UInt<2>("h02")) node T_375 = or(T_372, T_374) node T_377 = eq(T_355, UInt<1>("h00")) node T_378 = bit(T_353, 6) node T_380 = eq(T_378, UInt<1>("h00")) node T_381 = and(T_358, T_380) node T_382 = not(T_355) node T_384 = eq(T_382, UInt<1>("h00")) node T_385 = bit(T_354, 22) node T_387 = eq(T_385, UInt<1>("h00")) node T_388 = and(T_384, T_387) node T_389 = bit(T_354, 22) node T_390 = and(T_384, T_389) node T_392 = eq(T_352, UInt<1>("h00")) node T_393 = and(T_381, T_392) node T_395 = eq(T_352, UInt<1>("h00")) node T_396 = and(T_375, T_395) node T_398 = eq(T_352, UInt<1>("h00")) node T_399 = and(T_367, T_398) node T_401 = eq(T_352, UInt<1>("h00")) node T_402 = and(T_377, T_401) node T_403 = and(T_377, T_352) node T_404 = and(T_367, T_352) node T_405 = and(T_375, T_352) node T_406 = and(T_381, T_352) node T_407 = cat(T_390, T_388) node T_408 = cat(T_396, T_399) node T_409 = cat(T_393, T_408) node T_410 = cat(T_407, T_409) node T_411 = cat(T_402, T_403) node T_412 = cat(T_405, T_406) node T_413 = cat(T_404, T_412) node T_414 = cat(T_411, T_413) node classify_s = cat(T_410, T_414) node T_416 = bit(in.in1, 64) node T_417 = bits(in.in1, 63, 52) node T_418 = bits(in.in1, 51, 0) node T_419 = bits(T_417, 11, 9) node T_420 = bits(T_419, 2, 1) node T_422 = eq(T_420, UInt<2>("h03")) node T_423 = bits(T_417, 9, 0) node T_425 = lt(T_423, UInt<2>("h02")) node T_427 = eq(T_419, UInt<1>("h01")) node T_429 = eq(T_420, UInt<1>("h01")) node T_430 = and(T_429, T_425) node T_431 = or(T_427, T_430) node T_433 = eq(T_420, UInt<1>("h01")) node T_435 = eq(T_425, UInt<1>("h00")) node T_436 = and(T_433, T_435) node T_438 = eq(T_420, UInt<2>("h02")) node T_439 = or(T_436, T_438) node T_441 = eq(T_419, UInt<1>("h00")) node T_442 = bit(T_417, 9) node T_444 = eq(T_442, UInt<1>("h00")) node T_445 = and(T_422, T_444) node T_446 = not(T_419) node T_448 = eq(T_446, UInt<1>("h00")) node T_449 = bit(T_418, 51) node T_451 = eq(T_449, UInt<1>("h00")) node T_452 = and(T_448, T_451) node T_453 = bit(T_418, 51) node T_454 = and(T_448, T_453) node T_456 = eq(T_416, UInt<1>("h00")) node T_457 = and(T_445, T_456) node T_459 = eq(T_416, UInt<1>("h00")) node T_460 = and(T_439, T_459) node T_462 = eq(T_416, UInt<1>("h00")) node T_463 = and(T_431, T_462) node T_465 = eq(T_416, UInt<1>("h00")) node T_466 = and(T_441, T_465) node T_467 = and(T_441, T_416) node T_468 = and(T_431, T_416) node T_469 = and(T_439, T_416) node T_470 = and(T_445, T_416) node T_471 = cat(T_454, T_452) node T_472 = cat(T_460, T_463) node T_473 = cat(T_457, T_472) node T_474 = cat(T_471, T_473) node T_475 = cat(T_466, T_467) node T_476 = cat(T_469, T_470) node T_477 = cat(T_468, T_476) node T_478 = cat(T_475, T_477) node classify_d = cat(T_474, T_478) node classify_out = mux(in.single, classify_s, classify_d) inst dcmp of CompareRecFN dcmp.io.signaling <= UInt<1>("h00") dcmp.io.b <= UInt<1>("h00") dcmp.io.a <= UInt<1>("h00") dcmp.clk <= clk dcmp.reset <= reset dcmp.io.a <= in.in1 dcmp.io.b <= in.in2 dcmp.io.signaling <= UInt<1>("h01") node T_486 = not(in.rm) node T_487 = cat(dcmp.io.lt, dcmp.io.eq) node T_488 = and(T_486, T_487) node dcmp_out = neq(T_488, UInt<1>("h00")) inst d2l of RecFNToIN d2l.io.signedOut <= UInt<1>("h00") d2l.io.roundingMode <= UInt<1>("h00") d2l.io.in <= UInt<1>("h00") d2l.clk <= clk d2l.reset <= reset inst d2w of RecFNToIN_118 d2w.io.signedOut <= UInt<1>("h00") d2w.io.roundingMode <= UInt<1>("h00") d2w.io.in <= UInt<1>("h00") d2w.clk <= clk d2w.reset <= reset d2l.io.in <= in.in1 d2l.io.roundingMode <= in.rm node T_499 = bit(in.typ, 0) node T_500 = not(T_499) d2l.io.signedOut <= T_500 d2w.io.in <= in.in1 d2w.io.roundingMode <= in.rm node T_501 = bit(in.typ, 0) node T_502 = not(T_501) d2w.io.signedOut <= T_502 node T_503 = bit(in.rm, 0) node T_504 = mux(T_503, classify_out, unrec_out) io.out.bits.toint <= T_504 io.out.bits.store <= unrec_out io.out.bits.exc <= UInt<1>("h00") node T_508 = and(in.cmd, UInt<4>("h0c")) node T_509 = eq(UInt<3>("h04"), T_508) when T_509 : io.out.bits.toint <= dcmp_out io.out.bits.exc <= dcmp.io.exceptionFlags skip node T_512 = and(in.cmd, UInt<4>("h0c")) node T_513 = eq(UInt<4>("h08"), T_512) when T_513 : node T_514 = bit(in.typ, 1) node T_515 = asSInt(d2l.io.out) node T_516 = asSInt(d2w.io.out) node T_517 = mux(T_514, T_515, T_516) node T_518 = asUInt(T_517) io.out.bits.toint <= T_518 node T_519 = bit(in.typ, 1) node T_520 = mux(T_519, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags) node T_521 = bits(T_520, 2, 1) node T_523 = neq(T_521, UInt<1>("h00")) node T_525 = bit(T_520, 0) node T_526 = cat(UInt<3>("h00"), T_525) node T_527 = cat(T_523, T_526) io.out.bits.exc <= T_527 skip io.out.valid <= valid io.out.bits.lt <= dcmp.io.lt io.as_double <- in module INToRecFN : input clk : Clock input reset : UInt<1> output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node T_9 = bit(io.in, 63) node sign = and(io.signedIn, T_9) node T_12 = subw(UInt<1>("h00"), io.in) node absIn = mux(sign, T_12, io.in) node T_14 = shl(absIn, 0) node T_15 = bit(T_14, 63) node T_17 = bit(T_14, 62) node T_19 = bit(T_14, 61) node T_21 = bit(T_14, 60) node T_23 = bit(T_14, 59) node T_25 = bit(T_14, 58) node T_27 = bit(T_14, 57) node T_29 = bit(T_14, 56) node T_31 = bit(T_14, 55) node T_33 = bit(T_14, 54) node T_35 = bit(T_14, 53) node T_37 = bit(T_14, 52) node T_39 = bit(T_14, 51) node T_41 = bit(T_14, 50) node T_43 = bit(T_14, 49) node T_45 = bit(T_14, 48) node T_47 = bit(T_14, 47) node T_49 = bit(T_14, 46) node T_51 = bit(T_14, 45) node T_53 = bit(T_14, 44) node T_55 = bit(T_14, 43) node T_57 = bit(T_14, 42) node T_59 = bit(T_14, 41) node T_61 = bit(T_14, 40) node T_63 = bit(T_14, 39) node T_65 = bit(T_14, 38) node T_67 = bit(T_14, 37) node T_69 = bit(T_14, 36) node T_71 = bit(T_14, 35) node T_73 = bit(T_14, 34) node T_75 = bit(T_14, 33) node T_77 = bit(T_14, 32) node T_79 = bit(T_14, 31) node T_81 = bit(T_14, 30) node T_83 = bit(T_14, 29) node T_85 = bit(T_14, 28) node T_87 = bit(T_14, 27) node T_89 = bit(T_14, 26) node T_91 = bit(T_14, 25) node T_93 = bit(T_14, 24) node T_95 = bit(T_14, 23) node T_97 = bit(T_14, 22) node T_99 = bit(T_14, 21) node T_101 = bit(T_14, 20) node T_103 = bit(T_14, 19) node T_105 = bit(T_14, 18) node T_107 = bit(T_14, 17) node T_109 = bit(T_14, 16) node T_111 = bit(T_14, 15) node T_113 = bit(T_14, 14) node T_115 = bit(T_14, 13) node T_117 = bit(T_14, 12) node T_119 = bit(T_14, 11) node T_121 = bit(T_14, 10) node T_123 = bit(T_14, 9) node T_125 = bit(T_14, 8) node T_127 = bit(T_14, 7) node T_129 = bit(T_14, 6) node T_131 = bit(T_14, 5) node T_133 = bit(T_14, 4) node T_135 = bit(T_14, 3) node T_137 = bit(T_14, 2) node T_139 = bit(T_14, 1) node T_140 = shl(T_139, 0) node T_141 = mux(T_137, UInt<2>("h02"), T_140) node T_142 = mux(T_135, UInt<2>("h03"), T_141) node T_143 = mux(T_133, UInt<3>("h04"), T_142) node T_144 = mux(T_131, UInt<3>("h05"), T_143) node T_145 = mux(T_129, UInt<3>("h06"), T_144) node T_146 = mux(T_127, UInt<3>("h07"), T_145) node T_147 = mux(T_125, UInt<4>("h08"), T_146) node T_148 = mux(T_123, UInt<4>("h09"), T_147) node T_149 = mux(T_121, UInt<4>("h0a"), T_148) node T_150 = mux(T_119, UInt<4>("h0b"), T_149) node T_151 = mux(T_117, UInt<4>("h0c"), T_150) node T_152 = mux(T_115, UInt<4>("h0d"), T_151) node T_153 = mux(T_113, UInt<4>("h0e"), T_152) node T_154 = mux(T_111, UInt<4>("h0f"), T_153) node T_155 = mux(T_109, UInt<5>("h010"), T_154) node T_156 = mux(T_107, UInt<5>("h011"), T_155) node T_157 = mux(T_105, UInt<5>("h012"), T_156) node T_158 = mux(T_103, UInt<5>("h013"), T_157) node T_159 = mux(T_101, UInt<5>("h014"), T_158) node T_160 = mux(T_99, UInt<5>("h015"), T_159) node T_161 = mux(T_97, UInt<5>("h016"), T_160) node T_162 = mux(T_95, UInt<5>("h017"), T_161) node T_163 = mux(T_93, UInt<5>("h018"), T_162) node T_164 = mux(T_91, UInt<5>("h019"), T_163) node T_165 = mux(T_89, UInt<5>("h01a"), T_164) node T_166 = mux(T_87, UInt<5>("h01b"), T_165) node T_167 = mux(T_85, UInt<5>("h01c"), T_166) node T_168 = mux(T_83, UInt<5>("h01d"), T_167) node T_169 = mux(T_81, UInt<5>("h01e"), T_168) node T_170 = mux(T_79, UInt<5>("h01f"), T_169) node T_171 = mux(T_77, UInt<6>("h020"), T_170) node T_172 = mux(T_75, UInt<6>("h021"), T_171) node T_173 = mux(T_73, UInt<6>("h022"), T_172) node T_174 = mux(T_71, UInt<6>("h023"), T_173) node T_175 = mux(T_69, UInt<6>("h024"), T_174) node T_176 = mux(T_67, UInt<6>("h025"), T_175) node T_177 = mux(T_65, UInt<6>("h026"), T_176) node T_178 = mux(T_63, UInt<6>("h027"), T_177) node T_179 = mux(T_61, UInt<6>("h028"), T_178) node T_180 = mux(T_59, UInt<6>("h029"), T_179) node T_181 = mux(T_57, UInt<6>("h02a"), T_180) node T_182 = mux(T_55, UInt<6>("h02b"), T_181) node T_183 = mux(T_53, UInt<6>("h02c"), T_182) node T_184 = mux(T_51, UInt<6>("h02d"), T_183) node T_185 = mux(T_49, UInt<6>("h02e"), T_184) node T_186 = mux(T_47, UInt<6>("h02f"), T_185) node T_187 = mux(T_45, UInt<6>("h030"), T_186) node T_188 = mux(T_43, UInt<6>("h031"), T_187) node T_189 = mux(T_41, UInt<6>("h032"), T_188) node T_190 = mux(T_39, UInt<6>("h033"), T_189) node T_191 = mux(T_37, UInt<6>("h034"), T_190) node T_192 = mux(T_35, UInt<6>("h035"), T_191) node T_193 = mux(T_33, UInt<6>("h036"), T_192) node T_194 = mux(T_31, UInt<6>("h037"), T_193) node T_195 = mux(T_29, UInt<6>("h038"), T_194) node T_196 = mux(T_27, UInt<6>("h039"), T_195) node T_197 = mux(T_25, UInt<6>("h03a"), T_196) node T_198 = mux(T_23, UInt<6>("h03b"), T_197) node T_199 = mux(T_21, UInt<6>("h03c"), T_198) node T_200 = mux(T_19, UInt<6>("h03d"), T_199) node T_201 = mux(T_17, UInt<6>("h03e"), T_200) node T_202 = mux(T_15, UInt<6>("h03f"), T_201) node normCount = not(T_202) node T_204 = dshl(absIn, normCount) node normAbsIn = bits(T_204, 63, 0) node T_207 = bits(normAbsIn, 40, 39) node T_208 = bits(normAbsIn, 38, 0) node T_210 = neq(T_208, UInt<1>("h00")) node roundBits = cat(T_207, T_210) node T_212 = bits(roundBits, 1, 0) node roundInexact = neq(T_212, UInt<1>("h00")) node T_215 = eq(io.roundingMode, UInt<2>("h00")) node T_216 = bits(roundBits, 2, 1) node T_217 = not(T_216) node T_219 = eq(T_217, UInt<1>("h00")) node T_220 = bits(roundBits, 1, 0) node T_221 = not(T_220) node T_223 = eq(T_221, UInt<1>("h00")) node T_224 = or(T_219, T_223) node T_226 = mux(T_215, T_224, UInt<1>("h00")) node T_227 = eq(io.roundingMode, UInt<2>("h02")) node T_228 = and(sign, roundInexact) node T_230 = mux(T_227, T_228, UInt<1>("h00")) node T_231 = or(T_226, T_230) node T_232 = eq(io.roundingMode, UInt<2>("h03")) node T_234 = eq(sign, UInt<1>("h00")) node T_235 = and(T_234, roundInexact) node T_237 = mux(T_232, T_235, UInt<1>("h00")) node round = or(T_231, T_237) node T_240 = bits(normAbsIn, 63, 40) node unroundedNorm = cat(UInt<1>("h00"), T_240) node T_244 = addw(unroundedNorm, UInt<1>("h01")) node roundedNorm = mux(round, T_244, unroundedNorm) node T_247 = not(normCount) node unroundedExp = cat(UInt<1>("h00"), T_247) node T_251 = cat(UInt<1>("h00"), unroundedExp) node T_252 = bit(roundedNorm, 24) node roundedExp = addw(T_251, T_252) node T_255 = bit(normAbsIn, 63) node T_257 = bits(roundedExp, 7, 0) node T_258 = mux(UInt<1>("h00"), UInt<8>("h080"), T_257) node expOut = cat(T_255, T_258) node overflow = or(UInt<1>("h00"), UInt<1>("h00")) node inexact = or(roundInexact, overflow) node T_262 = bits(roundedNorm, 22, 0) node T_263 = cat(expOut, T_262) node T_264 = cat(sign, T_263) io.out <= T_264 node T_267 = cat(UInt<2>("h00"), overflow) node T_268 = cat(UInt<1>("h00"), inexact) node T_269 = cat(T_267, T_268) io.exceptionFlags <= T_269 module INToRecFN_119 : input clk : Clock input reset : UInt<1> output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node T_9 = bit(io.in, 63) node sign = and(io.signedIn, T_9) node T_12 = subw(UInt<1>("h00"), io.in) node absIn = mux(sign, T_12, io.in) node T_14 = shl(absIn, 0) node T_15 = bit(T_14, 63) node T_17 = bit(T_14, 62) node T_19 = bit(T_14, 61) node T_21 = bit(T_14, 60) node T_23 = bit(T_14, 59) node T_25 = bit(T_14, 58) node T_27 = bit(T_14, 57) node T_29 = bit(T_14, 56) node T_31 = bit(T_14, 55) node T_33 = bit(T_14, 54) node T_35 = bit(T_14, 53) node T_37 = bit(T_14, 52) node T_39 = bit(T_14, 51) node T_41 = bit(T_14, 50) node T_43 = bit(T_14, 49) node T_45 = bit(T_14, 48) node T_47 = bit(T_14, 47) node T_49 = bit(T_14, 46) node T_51 = bit(T_14, 45) node T_53 = bit(T_14, 44) node T_55 = bit(T_14, 43) node T_57 = bit(T_14, 42) node T_59 = bit(T_14, 41) node T_61 = bit(T_14, 40) node T_63 = bit(T_14, 39) node T_65 = bit(T_14, 38) node T_67 = bit(T_14, 37) node T_69 = bit(T_14, 36) node T_71 = bit(T_14, 35) node T_73 = bit(T_14, 34) node T_75 = bit(T_14, 33) node T_77 = bit(T_14, 32) node T_79 = bit(T_14, 31) node T_81 = bit(T_14, 30) node T_83 = bit(T_14, 29) node T_85 = bit(T_14, 28) node T_87 = bit(T_14, 27) node T_89 = bit(T_14, 26) node T_91 = bit(T_14, 25) node T_93 = bit(T_14, 24) node T_95 = bit(T_14, 23) node T_97 = bit(T_14, 22) node T_99 = bit(T_14, 21) node T_101 = bit(T_14, 20) node T_103 = bit(T_14, 19) node T_105 = bit(T_14, 18) node T_107 = bit(T_14, 17) node T_109 = bit(T_14, 16) node T_111 = bit(T_14, 15) node T_113 = bit(T_14, 14) node T_115 = bit(T_14, 13) node T_117 = bit(T_14, 12) node T_119 = bit(T_14, 11) node T_121 = bit(T_14, 10) node T_123 = bit(T_14, 9) node T_125 = bit(T_14, 8) node T_127 = bit(T_14, 7) node T_129 = bit(T_14, 6) node T_131 = bit(T_14, 5) node T_133 = bit(T_14, 4) node T_135 = bit(T_14, 3) node T_137 = bit(T_14, 2) node T_139 = bit(T_14, 1) node T_140 = shl(T_139, 0) node T_141 = mux(T_137, UInt<2>("h02"), T_140) node T_142 = mux(T_135, UInt<2>("h03"), T_141) node T_143 = mux(T_133, UInt<3>("h04"), T_142) node T_144 = mux(T_131, UInt<3>("h05"), T_143) node T_145 = mux(T_129, UInt<3>("h06"), T_144) node T_146 = mux(T_127, UInt<3>("h07"), T_145) node T_147 = mux(T_125, UInt<4>("h08"), T_146) node T_148 = mux(T_123, UInt<4>("h09"), T_147) node T_149 = mux(T_121, UInt<4>("h0a"), T_148) node T_150 = mux(T_119, UInt<4>("h0b"), T_149) node T_151 = mux(T_117, UInt<4>("h0c"), T_150) node T_152 = mux(T_115, UInt<4>("h0d"), T_151) node T_153 = mux(T_113, UInt<4>("h0e"), T_152) node T_154 = mux(T_111, UInt<4>("h0f"), T_153) node T_155 = mux(T_109, UInt<5>("h010"), T_154) node T_156 = mux(T_107, UInt<5>("h011"), T_155) node T_157 = mux(T_105, UInt<5>("h012"), T_156) node T_158 = mux(T_103, UInt<5>("h013"), T_157) node T_159 = mux(T_101, UInt<5>("h014"), T_158) node T_160 = mux(T_99, UInt<5>("h015"), T_159) node T_161 = mux(T_97, UInt<5>("h016"), T_160) node T_162 = mux(T_95, UInt<5>("h017"), T_161) node T_163 = mux(T_93, UInt<5>("h018"), T_162) node T_164 = mux(T_91, UInt<5>("h019"), T_163) node T_165 = mux(T_89, UInt<5>("h01a"), T_164) node T_166 = mux(T_87, UInt<5>("h01b"), T_165) node T_167 = mux(T_85, UInt<5>("h01c"), T_166) node T_168 = mux(T_83, UInt<5>("h01d"), T_167) node T_169 = mux(T_81, UInt<5>("h01e"), T_168) node T_170 = mux(T_79, UInt<5>("h01f"), T_169) node T_171 = mux(T_77, UInt<6>("h020"), T_170) node T_172 = mux(T_75, UInt<6>("h021"), T_171) node T_173 = mux(T_73, UInt<6>("h022"), T_172) node T_174 = mux(T_71, UInt<6>("h023"), T_173) node T_175 = mux(T_69, UInt<6>("h024"), T_174) node T_176 = mux(T_67, UInt<6>("h025"), T_175) node T_177 = mux(T_65, UInt<6>("h026"), T_176) node T_178 = mux(T_63, UInt<6>("h027"), T_177) node T_179 = mux(T_61, UInt<6>("h028"), T_178) node T_180 = mux(T_59, UInt<6>("h029"), T_179) node T_181 = mux(T_57, UInt<6>("h02a"), T_180) node T_182 = mux(T_55, UInt<6>("h02b"), T_181) node T_183 = mux(T_53, UInt<6>("h02c"), T_182) node T_184 = mux(T_51, UInt<6>("h02d"), T_183) node T_185 = mux(T_49, UInt<6>("h02e"), T_184) node T_186 = mux(T_47, UInt<6>("h02f"), T_185) node T_187 = mux(T_45, UInt<6>("h030"), T_186) node T_188 = mux(T_43, UInt<6>("h031"), T_187) node T_189 = mux(T_41, UInt<6>("h032"), T_188) node T_190 = mux(T_39, UInt<6>("h033"), T_189) node T_191 = mux(T_37, UInt<6>("h034"), T_190) node T_192 = mux(T_35, UInt<6>("h035"), T_191) node T_193 = mux(T_33, UInt<6>("h036"), T_192) node T_194 = mux(T_31, UInt<6>("h037"), T_193) node T_195 = mux(T_29, UInt<6>("h038"), T_194) node T_196 = mux(T_27, UInt<6>("h039"), T_195) node T_197 = mux(T_25, UInt<6>("h03a"), T_196) node T_198 = mux(T_23, UInt<6>("h03b"), T_197) node T_199 = mux(T_21, UInt<6>("h03c"), T_198) node T_200 = mux(T_19, UInt<6>("h03d"), T_199) node T_201 = mux(T_17, UInt<6>("h03e"), T_200) node T_202 = mux(T_15, UInt<6>("h03f"), T_201) node normCount = not(T_202) node T_204 = dshl(absIn, normCount) node normAbsIn = bits(T_204, 63, 0) node T_207 = bits(normAbsIn, 11, 10) node T_208 = bits(normAbsIn, 9, 0) node T_210 = neq(T_208, UInt<1>("h00")) node roundBits = cat(T_207, T_210) node T_212 = bits(roundBits, 1, 0) node roundInexact = neq(T_212, UInt<1>("h00")) node T_215 = eq(io.roundingMode, UInt<2>("h00")) node T_216 = bits(roundBits, 2, 1) node T_217 = not(T_216) node T_219 = eq(T_217, UInt<1>("h00")) node T_220 = bits(roundBits, 1, 0) node T_221 = not(T_220) node T_223 = eq(T_221, UInt<1>("h00")) node T_224 = or(T_219, T_223) node T_226 = mux(T_215, T_224, UInt<1>("h00")) node T_227 = eq(io.roundingMode, UInt<2>("h02")) node T_228 = and(sign, roundInexact) node T_230 = mux(T_227, T_228, UInt<1>("h00")) node T_231 = or(T_226, T_230) node T_232 = eq(io.roundingMode, UInt<2>("h03")) node T_234 = eq(sign, UInt<1>("h00")) node T_235 = and(T_234, roundInexact) node T_237 = mux(T_232, T_235, UInt<1>("h00")) node round = or(T_231, T_237) node T_240 = bits(normAbsIn, 63, 11) node unroundedNorm = cat(UInt<1>("h00"), T_240) node T_244 = addw(unroundedNorm, UInt<1>("h01")) node roundedNorm = mux(round, T_244, unroundedNorm) node T_247 = not(normCount) node unroundedExp = cat(UInt<4>("h00"), T_247) node T_251 = cat(UInt<1>("h00"), unroundedExp) node T_252 = bit(roundedNorm, 53) node roundedExp = addw(T_251, T_252) node T_255 = bit(normAbsIn, 63) node T_257 = bits(roundedExp, 10, 0) node T_258 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_257) node expOut = cat(T_255, T_258) node overflow = or(UInt<1>("h00"), UInt<1>("h00")) node inexact = or(roundInexact, overflow) node T_262 = bits(roundedNorm, 51, 0) node T_263 = cat(expOut, T_262) node T_264 = cat(sign, T_263) io.out <= T_264 node T_267 = cat(UInt<2>("h00"), overflow) node T_268 = cat(UInt<1>("h00"), inexact) node T_269 = cat(T_267, T_268) io.exceptionFlags <= T_269 module IntToFP : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.out.bits.exc <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") reg T_136 : UInt<1>, clk, reset, UInt<1>("h00") T_136 <= io.in.valid reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), T_137 when io.in.valid : T_137 <- io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} in.bits.in3 <= UInt<1>("h00") in.bits.in2 <= UInt<1>("h00") in.bits.in1 <= UInt<1>("h00") in.bits.typ <= UInt<1>("h00") in.bits.rm <= UInt<1>("h00") in.bits.wflags <= UInt<1>("h00") in.bits.round <= UInt<1>("h00") in.bits.sqrt <= UInt<1>("h00") in.bits.div <= UInt<1>("h00") in.bits.fma <= UInt<1>("h00") in.bits.fastpipe <= UInt<1>("h00") in.bits.toint <= UInt<1>("h00") in.bits.fromint <= UInt<1>("h00") in.bits.single <= UInt<1>("h00") in.bits.swap23 <= UInt<1>("h00") in.bits.swap12 <= UInt<1>("h00") in.bits.ren3 <= UInt<1>("h00") in.bits.ren2 <= UInt<1>("h00") in.bits.ren1 <= UInt<1>("h00") in.bits.wen <= UInt<1>("h00") in.bits.ldst <= UInt<1>("h00") in.bits.cmd <= UInt<1>("h00") in.valid <= UInt<1>("h00") in.valid <= T_136 in.bits <- T_137 wire mux : {data : UInt<65>, exc : UInt<5>} mux.exc <= UInt<1>("h00") mux.data <= UInt<1>("h00") mux.exc <= UInt<1>("h00") node T_288 = bit(in.bits.in1, 63) node T_289 = bits(in.bits.in1, 62, 52) node T_290 = bits(in.bits.in1, 51, 0) node T_292 = eq(T_289, UInt<1>("h00")) node T_294 = eq(T_290, UInt<1>("h00")) node T_295 = and(T_292, T_294) node T_296 = shl(T_290, 12) node T_297 = bit(T_296, 63) node T_299 = bit(T_296, 62) node T_301 = bit(T_296, 61) node T_303 = bit(T_296, 60) node T_305 = bit(T_296, 59) node T_307 = bit(T_296, 58) node T_309 = bit(T_296, 57) node T_311 = bit(T_296, 56) node T_313 = bit(T_296, 55) node T_315 = bit(T_296, 54) node T_317 = bit(T_296, 53) node T_319 = bit(T_296, 52) node T_321 = bit(T_296, 51) node T_323 = bit(T_296, 50) node T_325 = bit(T_296, 49) node T_327 = bit(T_296, 48) node T_329 = bit(T_296, 47) node T_331 = bit(T_296, 46) node T_333 = bit(T_296, 45) node T_335 = bit(T_296, 44) node T_337 = bit(T_296, 43) node T_339 = bit(T_296, 42) node T_341 = bit(T_296, 41) node T_343 = bit(T_296, 40) node T_345 = bit(T_296, 39) node T_347 = bit(T_296, 38) node T_349 = bit(T_296, 37) node T_351 = bit(T_296, 36) node T_353 = bit(T_296, 35) node T_355 = bit(T_296, 34) node T_357 = bit(T_296, 33) node T_359 = bit(T_296, 32) node T_361 = bit(T_296, 31) node T_363 = bit(T_296, 30) node T_365 = bit(T_296, 29) node T_367 = bit(T_296, 28) node T_369 = bit(T_296, 27) node T_371 = bit(T_296, 26) node T_373 = bit(T_296, 25) node T_375 = bit(T_296, 24) node T_377 = bit(T_296, 23) node T_379 = bit(T_296, 22) node T_381 = bit(T_296, 21) node T_383 = bit(T_296, 20) node T_385 = bit(T_296, 19) node T_387 = bit(T_296, 18) node T_389 = bit(T_296, 17) node T_391 = bit(T_296, 16) node T_393 = bit(T_296, 15) node T_395 = bit(T_296, 14) node T_397 = bit(T_296, 13) node T_399 = bit(T_296, 12) node T_401 = bit(T_296, 11) node T_403 = bit(T_296, 10) node T_405 = bit(T_296, 9) node T_407 = bit(T_296, 8) node T_409 = bit(T_296, 7) node T_411 = bit(T_296, 6) node T_413 = bit(T_296, 5) node T_415 = bit(T_296, 4) node T_417 = bit(T_296, 3) node T_419 = bit(T_296, 2) node T_421 = bit(T_296, 1) node T_422 = shl(T_421, 0) node T_423 = mux(T_419, UInt<2>("h02"), T_422) node T_424 = mux(T_417, UInt<2>("h03"), T_423) node T_425 = mux(T_415, UInt<3>("h04"), T_424) node T_426 = mux(T_413, UInt<3>("h05"), T_425) node T_427 = mux(T_411, UInt<3>("h06"), T_426) node T_428 = mux(T_409, UInt<3>("h07"), T_427) node T_429 = mux(T_407, UInt<4>("h08"), T_428) node T_430 = mux(T_405, UInt<4>("h09"), T_429) node T_431 = mux(T_403, UInt<4>("h0a"), T_430) node T_432 = mux(T_401, UInt<4>("h0b"), T_431) node T_433 = mux(T_399, UInt<4>("h0c"), T_432) node T_434 = mux(T_397, UInt<4>("h0d"), T_433) node T_435 = mux(T_395, UInt<4>("h0e"), T_434) node T_436 = mux(T_393, UInt<4>("h0f"), T_435) node T_437 = mux(T_391, UInt<5>("h010"), T_436) node T_438 = mux(T_389, UInt<5>("h011"), T_437) node T_439 = mux(T_387, UInt<5>("h012"), T_438) node T_440 = mux(T_385, UInt<5>("h013"), T_439) node T_441 = mux(T_383, UInt<5>("h014"), T_440) node T_442 = mux(T_381, UInt<5>("h015"), T_441) node T_443 = mux(T_379, UInt<5>("h016"), T_442) node T_444 = mux(T_377, UInt<5>("h017"), T_443) node T_445 = mux(T_375, UInt<5>("h018"), T_444) node T_446 = mux(T_373, UInt<5>("h019"), T_445) node T_447 = mux(T_371, UInt<5>("h01a"), T_446) node T_448 = mux(T_369, UInt<5>("h01b"), T_447) node T_449 = mux(T_367, UInt<5>("h01c"), T_448) node T_450 = mux(T_365, UInt<5>("h01d"), T_449) node T_451 = mux(T_363, UInt<5>("h01e"), T_450) node T_452 = mux(T_361, UInt<5>("h01f"), T_451) node T_453 = mux(T_359, UInt<6>("h020"), T_452) node T_454 = mux(T_357, UInt<6>("h021"), T_453) node T_455 = mux(T_355, UInt<6>("h022"), T_454) node T_456 = mux(T_353, UInt<6>("h023"), T_455) node T_457 = mux(T_351, UInt<6>("h024"), T_456) node T_458 = mux(T_349, UInt<6>("h025"), T_457) node T_459 = mux(T_347, UInt<6>("h026"), T_458) node T_460 = mux(T_345, UInt<6>("h027"), T_459) node T_461 = mux(T_343, UInt<6>("h028"), T_460) node T_462 = mux(T_341, UInt<6>("h029"), T_461) node T_463 = mux(T_339, UInt<6>("h02a"), T_462) node T_464 = mux(T_337, UInt<6>("h02b"), T_463) node T_465 = mux(T_335, UInt<6>("h02c"), T_464) node T_466 = mux(T_333, UInt<6>("h02d"), T_465) node T_467 = mux(T_331, UInt<6>("h02e"), T_466) node T_468 = mux(T_329, UInt<6>("h02f"), T_467) node T_469 = mux(T_327, UInt<6>("h030"), T_468) node T_470 = mux(T_325, UInt<6>("h031"), T_469) node T_471 = mux(T_323, UInt<6>("h032"), T_470) node T_472 = mux(T_321, UInt<6>("h033"), T_471) node T_473 = mux(T_319, UInt<6>("h034"), T_472) node T_474 = mux(T_317, UInt<6>("h035"), T_473) node T_475 = mux(T_315, UInt<6>("h036"), T_474) node T_476 = mux(T_313, UInt<6>("h037"), T_475) node T_477 = mux(T_311, UInt<6>("h038"), T_476) node T_478 = mux(T_309, UInt<6>("h039"), T_477) node T_479 = mux(T_307, UInt<6>("h03a"), T_478) node T_480 = mux(T_305, UInt<6>("h03b"), T_479) node T_481 = mux(T_303, UInt<6>("h03c"), T_480) node T_482 = mux(T_301, UInt<6>("h03d"), T_481) node T_483 = mux(T_299, UInt<6>("h03e"), T_482) node T_484 = mux(T_297, UInt<6>("h03f"), T_483) node T_485 = not(T_484) node T_486 = dshl(T_290, T_485) node T_487 = bits(T_486, 50, 0) node T_489 = cat(T_487, UInt<1>("h00")) node T_492 = subw(UInt<12>("h00"), UInt<1>("h01")) node T_493 = xor(T_485, T_492) node T_494 = mux(T_292, T_493, T_289) node T_498 = mux(T_292, UInt<2>("h02"), UInt<1>("h01")) node T_499 = or(UInt<11>("h0400"), T_498) node T_500 = addw(T_494, T_499) node T_501 = bits(T_500, 11, 10) node T_503 = eq(T_501, UInt<2>("h03")) node T_505 = eq(T_294, UInt<1>("h00")) node T_506 = and(T_503, T_505) node T_508 = subw(UInt<3>("h00"), T_295) node T_509 = shl(T_508, 9) node T_510 = not(T_509) node T_511 = and(T_500, T_510) node T_512 = shl(T_506, 9) node T_513 = or(T_511, T_512) node T_514 = mux(T_292, T_489, T_290) node T_515 = cat(T_513, T_514) node T_516 = cat(T_288, T_515) mux.data <= T_516 when in.bits.single : node T_518 = bit(in.bits.in1, 31) node T_519 = bits(in.bits.in1, 30, 23) node T_520 = bits(in.bits.in1, 22, 0) node T_522 = eq(T_519, UInt<1>("h00")) node T_524 = eq(T_520, UInt<1>("h00")) node T_525 = and(T_522, T_524) node T_526 = shl(T_520, 9) node T_527 = bit(T_526, 31) node T_529 = bit(T_526, 30) node T_531 = bit(T_526, 29) node T_533 = bit(T_526, 28) node T_535 = bit(T_526, 27) node T_537 = bit(T_526, 26) node T_539 = bit(T_526, 25) node T_541 = bit(T_526, 24) node T_543 = bit(T_526, 23) node T_545 = bit(T_526, 22) node T_547 = bit(T_526, 21) node T_549 = bit(T_526, 20) node T_551 = bit(T_526, 19) node T_553 = bit(T_526, 18) node T_555 = bit(T_526, 17) node T_557 = bit(T_526, 16) node T_559 = bit(T_526, 15) node T_561 = bit(T_526, 14) node T_563 = bit(T_526, 13) node T_565 = bit(T_526, 12) node T_567 = bit(T_526, 11) node T_569 = bit(T_526, 10) node T_571 = bit(T_526, 9) node T_573 = bit(T_526, 8) node T_575 = bit(T_526, 7) node T_577 = bit(T_526, 6) node T_579 = bit(T_526, 5) node T_581 = bit(T_526, 4) node T_583 = bit(T_526, 3) node T_585 = bit(T_526, 2) node T_587 = bit(T_526, 1) node T_588 = shl(T_587, 0) node T_589 = mux(T_585, UInt<2>("h02"), T_588) node T_590 = mux(T_583, UInt<2>("h03"), T_589) node T_591 = mux(T_581, UInt<3>("h04"), T_590) node T_592 = mux(T_579, UInt<3>("h05"), T_591) node T_593 = mux(T_577, UInt<3>("h06"), T_592) node T_594 = mux(T_575, UInt<3>("h07"), T_593) node T_595 = mux(T_573, UInt<4>("h08"), T_594) node T_596 = mux(T_571, UInt<4>("h09"), T_595) node T_597 = mux(T_569, UInt<4>("h0a"), T_596) node T_598 = mux(T_567, UInt<4>("h0b"), T_597) node T_599 = mux(T_565, UInt<4>("h0c"), T_598) node T_600 = mux(T_563, UInt<4>("h0d"), T_599) node T_601 = mux(T_561, UInt<4>("h0e"), T_600) node T_602 = mux(T_559, UInt<4>("h0f"), T_601) node T_603 = mux(T_557, UInt<5>("h010"), T_602) node T_604 = mux(T_555, UInt<5>("h011"), T_603) node T_605 = mux(T_553, UInt<5>("h012"), T_604) node T_606 = mux(T_551, UInt<5>("h013"), T_605) node T_607 = mux(T_549, UInt<5>("h014"), T_606) node T_608 = mux(T_547, UInt<5>("h015"), T_607) node T_609 = mux(T_545, UInt<5>("h016"), T_608) node T_610 = mux(T_543, UInt<5>("h017"), T_609) node T_611 = mux(T_541, UInt<5>("h018"), T_610) node T_612 = mux(T_539, UInt<5>("h019"), T_611) node T_613 = mux(T_537, UInt<5>("h01a"), T_612) node T_614 = mux(T_535, UInt<5>("h01b"), T_613) node T_615 = mux(T_533, UInt<5>("h01c"), T_614) node T_616 = mux(T_531, UInt<5>("h01d"), T_615) node T_617 = mux(T_529, UInt<5>("h01e"), T_616) node T_618 = mux(T_527, UInt<5>("h01f"), T_617) node T_619 = not(T_618) node T_620 = dshl(T_520, T_619) node T_621 = bits(T_620, 21, 0) node T_623 = cat(T_621, UInt<1>("h00")) node T_626 = subw(UInt<9>("h00"), UInt<1>("h01")) node T_627 = xor(T_619, T_626) node T_628 = mux(T_522, T_627, T_519) node T_632 = mux(T_522, UInt<2>("h02"), UInt<1>("h01")) node T_633 = or(UInt<8>("h080"), T_632) node T_634 = addw(T_628, T_633) node T_635 = bits(T_634, 8, 7) node T_637 = eq(T_635, UInt<2>("h03")) node T_639 = eq(T_524, UInt<1>("h00")) node T_640 = and(T_637, T_639) node T_642 = subw(UInt<3>("h00"), T_525) node T_643 = shl(T_642, 6) node T_644 = not(T_643) node T_645 = and(T_634, T_644) node T_646 = shl(T_640, 6) node T_647 = or(T_645, T_646) node T_648 = mux(T_522, T_623, T_520) node T_649 = cat(T_647, T_648) node T_650 = cat(T_518, T_649) node T_651 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_652 = cat(T_651, T_650) mux.data <= T_652 skip node T_653 = bit(in.bits.typ, 1) node T_654 = asSInt(in.bits.in1) node T_655 = bit(in.bits.typ, 0) node T_656 = bits(in.bits.in1, 31, 0) node T_657 = cvt(T_656) node T_658 = bits(in.bits.in1, 31, 0) node T_659 = asSInt(T_658) node T_660 = mux(T_655, T_657, T_659) node longValue = mux(T_653, T_654, T_660) inst l2s of INToRecFN l2s.io.roundingMode <= UInt<1>("h00") l2s.io.in <= UInt<1>("h00") l2s.io.signedIn <= UInt<1>("h00") l2s.clk <= clk l2s.reset <= reset node T_666 = bit(in.bits.typ, 0) node T_667 = not(T_666) l2s.io.signedIn <= T_667 node T_668 = asUInt(longValue) l2s.io.in <= T_668 l2s.io.roundingMode <= in.bits.rm inst l2d of INToRecFN_119 l2d.io.roundingMode <= UInt<1>("h00") l2d.io.in <= UInt<1>("h00") l2d.io.signedIn <= UInt<1>("h00") l2d.clk <= clk l2d.reset <= reset node T_673 = bit(in.bits.typ, 0) node T_674 = not(T_673) l2d.io.signedIn <= T_674 node T_675 = asUInt(longValue) l2d.io.in <= T_675 l2d.io.roundingMode <= in.bits.rm node T_678 = and(in.bits.cmd, UInt<3>("h04")) node T_679 = eq(UInt<1>("h00"), T_678) when T_679 : when in.bits.single : node T_681 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_682 = cat(T_681, l2s.io.out) mux.data <= T_682 mux.exc <= l2s.io.exceptionFlags skip node T_684 = eq(in.bits.single, UInt<1>("h00")) when T_684 : mux.data <= l2d.io.out mux.exc <= l2d.io.exceptionFlags skip skip reg T_687 : UInt<1>, clk, reset, UInt<1>("h00") T_687 <= in.valid reg T_688 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_688 when in.valid : T_688 <- mux skip reg T_693 : UInt<1>, clk, reset, UInt<1>("h00") T_693 <= T_687 reg T_694 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_694 when T_687 : T_694 <- T_688 skip wire T_705 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_705.bits.exc <= UInt<1>("h00") T_705.bits.data <= UInt<1>("h00") T_705.valid <= UInt<1>("h00") T_705.valid <= T_693 T_705.bits <- T_694 io.out <- T_705 module RoundRawFNToRecFN : input clk : Clock input reset : UInt<1> output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) node T_27 = and(roundingMode_min, io.in.sign) node T_28 = not(io.in.sign) node T_29 = and(roundingMode_max, T_28) node roundMagUp = or(T_27, T_29) node doShiftSigDown1 = bit(io.in.sig, 26) node T_33 = lt(io.in.sExp, asSInt(UInt<1>("h00"))) node T_35 = subw(UInt<25>("h00"), T_33) node T_36 = bits(io.in.sExp, 8, 0) node T_37 = not(T_36) node T_39 = dshr(asSInt(UInt<513>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_37) node T_40 = bits(T_39, 130, 106) node T_41 = bits(T_40, 15, 0) node T_44 = shl(UInt<8>("h0ff"), 8) node T_45 = xor(UInt<16>("h0ffff"), T_44) node T_46 = shr(T_41, 8) node T_47 = and(T_46, T_45) node T_48 = bits(T_41, 7, 0) node T_49 = shl(T_48, 8) node T_50 = not(T_45) node T_51 = and(T_49, T_50) node T_52 = or(T_47, T_51) node T_53 = bits(T_45, 11, 0) node T_54 = shl(T_53, 4) node T_55 = xor(T_45, T_54) node T_56 = shr(T_52, 4) node T_57 = and(T_56, T_55) node T_58 = bits(T_52, 11, 0) node T_59 = shl(T_58, 4) node T_60 = not(T_55) node T_61 = and(T_59, T_60) node T_62 = or(T_57, T_61) node T_63 = bits(T_55, 13, 0) node T_64 = shl(T_63, 2) node T_65 = xor(T_55, T_64) node T_66 = shr(T_62, 2) node T_67 = and(T_66, T_65) node T_68 = bits(T_62, 13, 0) node T_69 = shl(T_68, 2) node T_70 = not(T_65) node T_71 = and(T_69, T_70) node T_72 = or(T_67, T_71) node T_73 = bits(T_65, 14, 0) node T_74 = shl(T_73, 1) node T_75 = xor(T_65, T_74) node T_76 = shr(T_72, 1) node T_77 = and(T_76, T_75) node T_78 = bits(T_72, 14, 0) node T_79 = shl(T_78, 1) node T_80 = not(T_75) node T_81 = and(T_79, T_80) node T_82 = or(T_77, T_81) node T_83 = bits(T_40, 24, 16) node T_84 = bits(T_83, 7, 0) node T_87 = shl(UInt<4>("h0f"), 4) node T_88 = xor(UInt<8>("h0ff"), T_87) node T_89 = shr(T_84, 4) node T_90 = and(T_89, T_88) node T_91 = bits(T_84, 3, 0) node T_92 = shl(T_91, 4) node T_93 = not(T_88) node T_94 = and(T_92, T_93) node T_95 = or(T_90, T_94) node T_96 = bits(T_88, 5, 0) node T_97 = shl(T_96, 2) node T_98 = xor(T_88, T_97) node T_99 = shr(T_95, 2) node T_100 = and(T_99, T_98) node T_101 = bits(T_95, 5, 0) node T_102 = shl(T_101, 2) node T_103 = not(T_98) node T_104 = and(T_102, T_103) node T_105 = or(T_100, T_104) node T_106 = bits(T_98, 6, 0) node T_107 = shl(T_106, 1) node T_108 = xor(T_98, T_107) node T_109 = shr(T_105, 1) node T_110 = and(T_109, T_108) node T_111 = bits(T_105, 6, 0) node T_112 = shl(T_111, 1) node T_113 = not(T_108) node T_114 = and(T_112, T_113) node T_115 = or(T_110, T_114) node T_116 = bits(T_83, 8, 8) node T_117 = cat(T_115, T_116) node T_118 = cat(T_82, T_117) node T_119 = or(T_35, T_118) node T_120 = or(T_119, doShiftSigDown1) node roundMask = cat(T_120, UInt<2>("h03")) node T_123 = shr(roundMask, 1) node T_124 = not(T_123) node roundPosMask = and(T_124, roundMask) node T_126 = and(io.in.sig, roundPosMask) node roundPosBit = neq(T_126, UInt<1>("h00")) node T_129 = shr(roundMask, 1) node T_130 = and(io.in.sig, T_129) node anyRoundExtra = neq(T_130, UInt<1>("h00")) node common_inexact = or(roundPosBit, anyRoundExtra) node T_134 = and(roundingMode_nearest_even, roundPosBit) node T_135 = and(roundMagUp, common_inexact) node T_136 = or(T_134, T_135) node T_137 = or(io.in.sig, roundMask) node T_138 = shr(T_137, 2) node T_140 = addw(T_138, UInt<1>("h01")) node T_141 = and(roundingMode_nearest_even, roundPosBit) node T_142 = not(anyRoundExtra) node T_143 = and(T_141, T_142) node T_144 = shr(roundMask, 1) node T_146 = mux(T_143, T_144, UInt<26>("h00")) node T_147 = not(T_146) node T_148 = and(T_140, T_147) node T_149 = not(roundMask) node T_150 = and(io.in.sig, T_149) node T_151 = shr(T_150, 2) node roundedSig = mux(T_136, T_148, T_151) node T_153 = shr(roundedSig, 24) node T_154 = cvt(T_153) node sRoundedExp = addw(io.in.sExp, T_154) node common_expOut = bits(sRoundedExp, 8, 0) node T_157 = bits(roundedSig, 23, 1) node T_158 = bits(roundedSig, 22, 0) node common_fractOut = mux(doShiftSigDown1, T_157, T_158) node T_160 = shr(sRoundedExp, 7) node common_overflow = geq(T_160, asSInt(UInt<3>("h03"))) node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) node T_167 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) node T_168 = lt(io.in.sExp, T_167) node common_underflow = and(common_inexact, T_168) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node T_172 = not(isNaNOut) node T_173 = not(notNaN_isSpecialInfOut) node T_174 = and(T_172, T_173) node T_175 = not(io.in.isZero) node commonCase = and(T_174, T_175) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node T_179 = and(commonCase, common_inexact) node inexact = or(overflow, T_179) node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) node T_182 = and(commonCase, common_totalUnderflow) node pegMinNonzeroMagOut = and(T_182, roundMagUp) node T_184 = and(commonCase, overflow) node T_185 = not(overflow_roundMagUp) node pegMaxFiniteMagOut = and(T_184, T_185) node T_187 = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_187) node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) node T_191 = or(io.in.isZero, common_totalUnderflow) node T_194 = mux(T_191, UInt<9>("h01c0"), UInt<1>("h00")) node T_195 = not(T_194) node T_196 = and(common_expOut, T_195) node T_198 = not(UInt<9>("h06b")) node T_200 = mux(pegMinNonzeroMagOut, T_198, UInt<1>("h00")) node T_201 = not(T_200) node T_202 = and(T_196, T_201) node T_205 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) node T_206 = not(T_205) node T_207 = and(T_202, T_206) node T_210 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) node T_211 = not(T_210) node T_212 = and(T_207, T_211) node T_215 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) node T_216 = or(T_212, T_215) node T_219 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) node T_220 = or(T_216, T_219) node T_223 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) node T_224 = or(T_220, T_223) node T_227 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) node expOut = or(T_224, T_227) node T_229 = and(common_totalUnderflow, roundMagUp) node T_230 = or(T_229, isNaNOut) node T_232 = mux(T_230, UInt<1>("h00"), common_fractOut) node T_234 = subw(UInt<23>("h00"), pegMaxFiniteMagOut) node T_235 = or(T_232, T_234) node T_236 = shl(isNaNOut, 22) node fractOut = or(T_235, T_236) node T_238 = cat(expOut, fractOut) node T_239 = cat(signOut, T_238) io.out <= T_239 node T_240 = cat(io.invalidExc, io.infiniteExc) node T_241 = cat(underflow, inexact) node T_242 = cat(overflow, T_241) node T_243 = cat(T_240, T_242) io.exceptionFlags <= T_243 module RecFNToRecFN_121 : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") node T_8 = bits(io.in, 63, 52) node T_9 = bits(T_8, 11, 10) node T_11 = eq(T_9, UInt<2>("h03")) wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} T_19.sig <= UInt<1>("h00") T_19.sExp <= asSInt(UInt<1>("h00")) T_19.isZero <= UInt<1>("h00") T_19.isInf <= UInt<1>("h00") T_19.isNaN <= UInt<1>("h00") T_19.sign <= UInt<1>("h00") node T_32 = bit(io.in, 64) T_19.sign <= T_32 node T_33 = bit(T_8, 9) node T_34 = and(T_11, T_33) T_19.isNaN <= T_34 node T_35 = bit(T_8, 9) node T_37 = eq(T_35, UInt<1>("h00")) node T_38 = and(T_11, T_37) T_19.isInf <= T_38 node T_39 = bits(T_8, 11, 9) node T_41 = eq(T_39, UInt<1>("h00")) T_19.isZero <= T_41 node T_42 = cvt(T_8) T_19.sExp <= T_42 node T_44 = bits(io.in, 51, 0) node T_46 = cat(T_44, UInt<2>("h00")) node T_47 = cat(UInt<2>("h01"), T_46) T_19.sig <= T_47 node T_49 = addw(T_19.sExp, asSInt(UInt<12>("h0900"))) wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} outRawFloat.sig <= UInt<1>("h00") outRawFloat.sExp <= asSInt(UInt<1>("h00")) outRawFloat.isZero <= UInt<1>("h00") outRawFloat.isInf <= UInt<1>("h00") outRawFloat.isNaN <= UInt<1>("h00") outRawFloat.sign <= UInt<1>("h00") outRawFloat.sign <= T_19.sign outRawFloat.isNaN <= T_19.isNaN outRawFloat.isInf <= T_19.isInf outRawFloat.isZero <= T_19.isZero node T_71 = lt(T_49, asSInt(UInt<1>("h00"))) node T_72 = bits(T_49, 11, 9) node T_74 = neq(T_72, UInt<1>("h00")) node T_76 = cat(UInt<1>("h01"), UInt<1>("h01")) node T_77 = cat(T_76, T_76) node T_78 = cat(T_76, T_77) node T_79 = cat(UInt<1>("h01"), T_78) node T_81 = cat(T_79, UInt<2>("h00")) node T_82 = bits(T_49, 8, 0) node T_83 = mux(T_74, T_81, T_82) node T_84 = cat(T_71, T_83) node T_85 = asSInt(T_84) outRawFloat.sExp <= T_85 node T_86 = bits(T_19.sig, 55, 30) node T_87 = bits(T_19.sig, 29, 0) node T_89 = neq(T_87, UInt<1>("h00")) node T_90 = cat(T_86, T_89) outRawFloat.sig <= T_90 node T_91 = bit(outRawFloat.sig, 24) node T_93 = eq(T_91, UInt<1>("h00")) node invalidExc = and(outRawFloat.isNaN, T_93) inst T_95 of RoundRawFNToRecFN T_95.io.roundingMode <= UInt<1>("h00") T_95.io.in.sig <= UInt<1>("h00") T_95.io.in.sExp <= asSInt(UInt<1>("h00")) T_95.io.in.isZero <= UInt<1>("h00") T_95.io.in.isInf <= UInt<1>("h00") T_95.io.in.isNaN <= UInt<1>("h00") T_95.io.in.sign <= UInt<1>("h00") T_95.io.infiniteExc <= UInt<1>("h00") T_95.io.invalidExc <= UInt<1>("h00") T_95.clk <= clk T_95.reset <= reset T_95.io.invalidExc <= invalidExc T_95.io.infiniteExc <= UInt<1>("h00") T_95.io.in <- outRawFloat T_95.io.roundingMode <= io.roundingMode io.out <= T_95.io.out io.exceptionFlags <= T_95.io.exceptionFlags module FPToFP : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} io.out.bits.exc <= UInt<1>("h00") io.out.bits.data <= UInt<1>("h00") io.out.valid <= UInt<1>("h00") reg T_137 : UInt<1>, clk, reset, UInt<1>("h00") T_137 <= io.in.valid reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), T_138 when io.in.valid : T_138 <- io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} in.bits.in3 <= UInt<1>("h00") in.bits.in2 <= UInt<1>("h00") in.bits.in1 <= UInt<1>("h00") in.bits.typ <= UInt<1>("h00") in.bits.rm <= UInt<1>("h00") in.bits.wflags <= UInt<1>("h00") in.bits.round <= UInt<1>("h00") in.bits.sqrt <= UInt<1>("h00") in.bits.div <= UInt<1>("h00") in.bits.fma <= UInt<1>("h00") in.bits.fastpipe <= UInt<1>("h00") in.bits.toint <= UInt<1>("h00") in.bits.fromint <= UInt<1>("h00") in.bits.single <= UInt<1>("h00") in.bits.swap23 <= UInt<1>("h00") in.bits.swap12 <= UInt<1>("h00") in.bits.ren3 <= UInt<1>("h00") in.bits.ren2 <= UInt<1>("h00") in.bits.ren1 <= UInt<1>("h00") in.bits.wen <= UInt<1>("h00") in.bits.ldst <= UInt<1>("h00") in.bits.cmd <= UInt<1>("h00") in.valid <= UInt<1>("h00") in.valid <= T_137 in.bits <- T_138 node T_282 = and(in.bits.cmd, UInt<3>("h05")) node isSgnj = eq(UInt<3>("h04"), T_282) node T_284 = and(in.bits.single, isSgnj) node T_285 = bit(in.bits.rm, 1) node T_287 = eq(T_284, UInt<1>("h00")) node T_288 = or(T_285, T_287) node T_289 = bit(in.bits.in1, 32) node T_290 = bit(in.bits.rm, 0) node T_291 = mux(T_288, T_289, T_290) node T_292 = bit(in.bits.in2, 32) node T_293 = and(T_284, T_292) node sign_s = xor(T_291, T_293) node T_296 = eq(in.bits.single, UInt<1>("h00")) node T_297 = and(T_296, isSgnj) node T_298 = bit(in.bits.rm, 1) node T_300 = eq(T_297, UInt<1>("h00")) node T_301 = or(T_298, T_300) node T_302 = bit(in.bits.in1, 64) node T_303 = bit(in.bits.rm, 0) node T_304 = mux(T_301, T_302, T_303) node T_305 = bit(in.bits.in2, 64) node T_306 = and(T_297, T_305) node sign_d = xor(T_304, T_306) node T_308 = bits(in.bits.in1, 63, 33) node T_309 = bits(in.bits.in1, 31, 0) node T_310 = cat(sign_d, T_308) node T_311 = cat(sign_s, T_309) node fsgnj = cat(T_310, T_311) inst s2d of RecFNToRecFN s2d.io.roundingMode <= UInt<1>("h00") s2d.io.in <= UInt<1>("h00") s2d.clk <= clk s2d.reset <= reset inst d2s of RecFNToRecFN_121 d2s.io.roundingMode <= UInt<1>("h00") d2s.io.in <= UInt<1>("h00") d2s.clk <= clk d2s.reset <= reset s2d.io.in <= in.bits.in1 s2d.io.roundingMode <= in.bits.rm d2s.io.in <= in.bits.in1 d2s.io.roundingMode <= in.bits.rm node T_319 = bits(in.bits.in1, 31, 29) node T_320 = not(T_319) node T_322 = eq(T_320, UInt<1>("h00")) node T_323 = bits(in.bits.in1, 63, 61) node T_324 = not(T_323) node T_326 = eq(T_324, UInt<1>("h00")) node isnan1 = mux(in.bits.single, T_322, T_326) node T_328 = bits(in.bits.in2, 31, 29) node T_329 = not(T_328) node T_331 = eq(T_329, UInt<1>("h00")) node T_332 = bits(in.bits.in2, 63, 61) node T_333 = not(T_332) node T_335 = eq(T_333, UInt<1>("h00")) node isnan2 = mux(in.bits.single, T_331, T_335) node T_337 = bit(in.bits.in1, 22) node T_338 = bit(in.bits.in1, 51) node T_339 = mux(in.bits.single, T_337, T_338) node T_340 = not(T_339) node issnan1 = and(isnan1, T_340) node T_342 = bit(in.bits.in2, 22) node T_343 = bit(in.bits.in2, 51) node T_344 = mux(in.bits.single, T_342, T_343) node T_345 = not(T_344) node issnan2 = and(isnan2, T_345) node T_347 = or(issnan1, issnan2) node minmax_exc = cat(T_347, UInt<4>("h00")) node isMax = bit(in.bits.rm, 0) node T_351 = neq(isMax, io.lt) node T_353 = eq(isnan1, UInt<1>("h00")) node T_354 = and(T_351, T_353) node isLHS = or(isnan2, T_354) wire mux : {data : UInt<65>, exc : UInt<5>} mux.exc <= UInt<1>("h00") mux.data <= UInt<1>("h00") mux.exc <= minmax_exc mux.data <= in.bits.in2 when isSgnj : mux.exc <= UInt<1>("h00") skip node T_365 = or(isSgnj, isLHS) when T_365 : mux.data <= fsgnj skip node T_368 = and(in.bits.cmd, UInt<3>("h04")) node T_369 = eq(UInt<1>("h00"), T_368) when T_369 : when in.bits.single : node T_371 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_372 = cat(T_371, d2s.io.out) mux.data <= T_372 mux.exc <= d2s.io.exceptionFlags skip node T_374 = eq(in.bits.single, UInt<1>("h00")) when T_374 : mux.data <= s2d.io.out mux.exc <= s2d.io.exceptionFlags skip skip reg T_377 : UInt<1>, clk, reset, UInt<1>("h00") T_377 <= in.valid reg T_378 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_378 when in.valid : T_378 <- mux skip wire T_389 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} T_389.bits.exc <= UInt<1>("h00") T_389.bits.data <= UInt<1>("h00") T_389.valid <= UInt<1>("h00") T_389.valid <= T_377 T_389.bits <- T_378 io.out <- T_389 module DivSqrtRecF64_mulAddZ31 : input clk : Clock input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} io.mulAddC_2 <= UInt<1>("h00") io.mulAddB_0 <= UInt<1>("h00") io.latchMulAddB_0 <= UInt<1>("h00") io.mulAddA_0 <= UInt<1>("h00") io.latchMulAddA_0 <= UInt<1>("h00") io.usingMulAdd <= UInt<1>("h00") io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") io.outValid_sqrt <= UInt<1>("h00") io.outValid_div <= UInt<1>("h00") io.inReady_sqrt <= UInt<1>("h00") io.inReady_div <= UInt<1>("h00") reg valid_PA : UInt<1>, clk, reset, UInt<1>("h00") reg sqrtOp_PA : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PA reg sign_PA : UInt<1>, clk, UInt<1>("h00"), sign_PA reg specialCodeB_PA : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PA reg fractB_51_PA : UInt<1>, clk, UInt<1>("h00"), fractB_51_PA reg roundingMode_PA : UInt<2>, clk, UInt<1>("h00"), roundingMode_PA reg specialCodeA_PA : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PA reg fractA_51_PA : UInt<1>, clk, UInt<1>("h00"), fractA_51_PA reg exp_PA : UInt<14>, clk, UInt<1>("h00"), exp_PA reg fractB_other_PA : UInt<51>, clk, UInt<1>("h00"), fractB_other_PA reg fractA_other_PA : UInt<51>, clk, UInt<1>("h00"), fractA_other_PA reg valid_PB : UInt<1>, clk, reset, UInt<1>("h00") reg sqrtOp_PB : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PB reg sign_PB : UInt<1>, clk, UInt<1>("h00"), sign_PB reg specialCodeA_PB : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PB reg fractA_51_PB : UInt<1>, clk, UInt<1>("h00"), fractA_51_PB reg specialCodeB_PB : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PB reg fractB_51_PB : UInt<1>, clk, UInt<1>("h00"), fractB_51_PB reg roundingMode_PB : UInt<2>, clk, UInt<1>("h00"), roundingMode_PB reg exp_PB : UInt<14>, clk, UInt<1>("h00"), exp_PB reg fractA_0_PB : UInt<1>, clk, UInt<1>("h00"), fractA_0_PB reg fractB_other_PB : UInt<51>, clk, UInt<1>("h00"), fractB_other_PB reg valid_PC : UInt<1>, clk, reset, UInt<1>("h00") reg sqrtOp_PC : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PC reg sign_PC : UInt<1>, clk, UInt<1>("h00"), sign_PC reg specialCodeA_PC : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PC reg fractA_51_PC : UInt<1>, clk, UInt<1>("h00"), fractA_51_PC reg specialCodeB_PC : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PC reg fractB_51_PC : UInt<1>, clk, UInt<1>("h00"), fractB_51_PC reg roundingMode_PC : UInt<2>, clk, UInt<1>("h00"), roundingMode_PC reg exp_PC : UInt<14>, clk, UInt<1>("h00"), exp_PC reg fractA_0_PC : UInt<1>, clk, UInt<1>("h00"), fractA_0_PC reg fractB_other_PC : UInt<51>, clk, UInt<1>("h00"), fractB_other_PC reg cycleNum_A : UInt<3>, clk, reset, UInt<3>("h00") reg cycleNum_B : UInt<4>, clk, reset, UInt<4>("h00") reg cycleNum_C : UInt<3>, clk, reset, UInt<3>("h00") reg cycleNum_E : UInt<3>, clk, reset, UInt<3>("h00") reg fractR0_A : UInt<9>, clk, UInt<1>("h00"), fractR0_A reg hiSqrR0_A_sqrt : UInt<10>, clk, UInt<1>("h00"), hiSqrR0_A_sqrt reg partNegSigma0_A : UInt<21>, clk, UInt<1>("h00"), partNegSigma0_A reg nextMulAdd9A_A : UInt<9>, clk, UInt<1>("h00"), nextMulAdd9A_A reg nextMulAdd9B_A : UInt<9>, clk, UInt<1>("h00"), nextMulAdd9B_A reg ER1_B_sqrt : UInt<17>, clk, UInt<1>("h00"), ER1_B_sqrt reg ESqrR1_B_sqrt : UInt<32>, clk, UInt<1>("h00"), ESqrR1_B_sqrt reg sigX1_B : UInt<58>, clk, UInt<1>("h00"), sigX1_B reg sqrSigma1_C : UInt<33>, clk, UInt<1>("h00"), sqrSigma1_C reg sigXN_C : UInt<58>, clk, UInt<1>("h00"), sigXN_C reg u_C_sqrt : UInt<31>, clk, UInt<1>("h00"), u_C_sqrt reg E_E_div : UInt<1>, clk, UInt<1>("h00"), E_E_div reg sigT_E : UInt<53>, clk, UInt<1>("h00"), sigT_E reg extraT_E : UInt<1>, clk, UInt<1>("h00"), extraT_E reg isNegRemT_E : UInt<1>, clk, UInt<1>("h00"), isNegRemT_E reg trueEqX_E1 : UInt<1>, clk, UInt<1>("h00"), trueEqX_E1 wire ready_PA : UInt<1> ready_PA <= UInt<1>("h00") wire ready_PB : UInt<1> ready_PB <= UInt<1>("h00") wire ready_PC : UInt<1> ready_PC <= UInt<1>("h00") wire leaving_PA : UInt<1> leaving_PA <= UInt<1>("h00") wire leaving_PB : UInt<1> leaving_PB <= UInt<1>("h00") wire leaving_PC : UInt<1> leaving_PC <= UInt<1>("h00") wire cyc_B10_sqrt : UInt<1> cyc_B10_sqrt <= UInt<1>("h00") wire cyc_B9_sqrt : UInt<1> cyc_B9_sqrt <= UInt<1>("h00") wire cyc_B8_sqrt : UInt<1> cyc_B8_sqrt <= UInt<1>("h00") wire cyc_B7_sqrt : UInt<1> cyc_B7_sqrt <= UInt<1>("h00") wire cyc_B6 : UInt<1> cyc_B6 <= UInt<1>("h00") wire cyc_B5 : UInt<1> cyc_B5 <= UInt<1>("h00") wire cyc_B4 : UInt<1> cyc_B4 <= UInt<1>("h00") wire cyc_B3 : UInt<1> cyc_B3 <= UInt<1>("h00") wire cyc_B2 : UInt<1> cyc_B2 <= UInt<1>("h00") wire cyc_B1 : UInt<1> cyc_B1 <= UInt<1>("h00") wire cyc_B6_div : UInt<1> cyc_B6_div <= UInt<1>("h00") wire cyc_B5_div : UInt<1> cyc_B5_div <= UInt<1>("h00") wire cyc_B4_div : UInt<1> cyc_B4_div <= UInt<1>("h00") wire cyc_B3_div : UInt<1> cyc_B3_div <= UInt<1>("h00") wire cyc_B2_div : UInt<1> cyc_B2_div <= UInt<1>("h00") wire cyc_B1_div : UInt<1> cyc_B1_div <= UInt<1>("h00") wire cyc_B6_sqrt : UInt<1> cyc_B6_sqrt <= UInt<1>("h00") wire cyc_B5_sqrt : UInt<1> cyc_B5_sqrt <= UInt<1>("h00") wire cyc_B4_sqrt : UInt<1> cyc_B4_sqrt <= UInt<1>("h00") wire cyc_B3_sqrt : UInt<1> cyc_B3_sqrt <= UInt<1>("h00") wire cyc_B2_sqrt : UInt<1> cyc_B2_sqrt <= UInt<1>("h00") wire cyc_B1_sqrt : UInt<1> cyc_B1_sqrt <= UInt<1>("h00") wire cyc_C5 : UInt<1> cyc_C5 <= UInt<1>("h00") wire cyc_C4 : UInt<1> cyc_C4 <= UInt<1>("h00") wire valid_normalCase_leaving_PB : UInt<1> valid_normalCase_leaving_PB <= UInt<1>("h00") wire cyc_C2 : UInt<1> cyc_C2 <= UInt<1>("h00") wire cyc_C1 : UInt<1> cyc_C1 <= UInt<1>("h00") wire cyc_E4 : UInt<1> cyc_E4 <= UInt<1>("h00") wire cyc_E3 : UInt<1> cyc_E3 <= UInt<1>("h00") wire cyc_E2 : UInt<1> cyc_E2 <= UInt<1>("h00") wire cyc_E1 : UInt<1> cyc_E1 <= UInt<1>("h00") wire zSigma1_B4 : UInt zSigma1_B4 <= UInt<1>("h00") wire sigXNU_B3_CX : UInt sigXNU_B3_CX <= UInt<1>("h00") wire zComplSigT_C1_sqrt : UInt zComplSigT_C1_sqrt <= UInt<1>("h00") wire zComplSigT_C1 : UInt zComplSigT_C1 <= UInt<1>("h00") node T_251 = not(cyc_B7_sqrt) node T_252 = and(ready_PA, T_251) node T_253 = not(cyc_B6_sqrt) node T_254 = and(T_252, T_253) node T_255 = not(cyc_B5_sqrt) node T_256 = and(T_254, T_255) node T_257 = not(cyc_B4_sqrt) node T_258 = and(T_256, T_257) node T_259 = not(cyc_B3) node T_260 = and(T_258, T_259) node T_261 = not(cyc_B2) node T_262 = and(T_260, T_261) node T_263 = not(cyc_B1_sqrt) node T_264 = and(T_262, T_263) node T_265 = not(cyc_C5) node T_266 = and(T_264, T_265) node T_267 = not(cyc_C4) node T_268 = and(T_266, T_267) io.inReady_div <= T_268 node T_269 = not(cyc_B6_sqrt) node T_270 = and(ready_PA, T_269) node T_271 = not(cyc_B5_sqrt) node T_272 = and(T_270, T_271) node T_273 = not(cyc_B4_sqrt) node T_274 = and(T_272, T_273) node T_275 = not(cyc_B2_div) node T_276 = and(T_274, T_275) node T_277 = not(cyc_B1_sqrt) node T_278 = and(T_276, T_277) io.inReady_sqrt <= T_278 node T_279 = and(io.inReady_div, io.inValid) node T_280 = not(io.sqrtOp) node cyc_S_div = and(T_279, T_280) node T_282 = and(io.inReady_sqrt, io.inValid) node cyc_S_sqrt = and(T_282, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) node signA_S = bit(io.a, 64) node expA_S = bits(io.a, 63, 52) node fractA_S = bits(io.a, 51, 0) node specialCodeA_S = bits(expA_S, 11, 9) node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) node T_291 = bits(specialCodeA_S, 2, 1) node isSpecialA_S = eq(T_291, UInt<2>("h03")) node signB_S = bit(io.b, 64) node expB_S = bits(io.b, 63, 52) node fractB_S = bits(io.b, 51, 0) node specialCodeB_S = bits(expB_S, 11, 9) node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) node T_300 = bits(specialCodeB_S, 2, 1) node isSpecialB_S = eq(T_300, UInt<2>("h03")) node T_303 = xor(signA_S, signB_S) node sign_S = mux(io.sqrtOp, signB_S, T_303) node T_305 = not(isSpecialA_S) node T_306 = not(isSpecialB_S) node T_307 = and(T_305, T_306) node T_308 = not(isZeroA_S) node T_309 = and(T_307, T_308) node T_310 = not(isZeroB_S) node normalCase_S_div = and(T_309, T_310) node T_312 = not(isSpecialB_S) node T_313 = not(isZeroB_S) node T_314 = and(T_312, T_313) node T_315 = not(signB_S) node normalCase_S_sqrt = and(T_314, T_315) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) node T_321 = not(ready_PB) node T_322 = or(valid_PA, T_321) node T_323 = and(cyc_S, T_322) node entering_PA = or(entering_PA_normalCase, T_323) node T_325 = not(normalCase_S) node T_326 = and(cyc_S, T_325) node T_327 = not(valid_PA) node T_328 = and(T_326, T_327) node T_329 = not(valid_PB) node T_330 = not(ready_PC) node T_331 = and(T_329, T_330) node T_332 = or(leaving_PB, T_331) node entering_PB_S = and(T_328, T_332) node T_334 = not(normalCase_S) node T_335 = and(cyc_S, T_334) node T_336 = not(valid_PA) node T_337 = and(T_335, T_336) node T_338 = not(valid_PB) node T_339 = and(T_337, T_338) node entering_PC_S = and(T_339, ready_PC) node T_341 = or(entering_PA, leaving_PA) when T_341 : valid_PA <= entering_PA skip when entering_PA : sqrtOp_PA <= io.sqrtOp sign_PA <= sign_S specialCodeB_PA <= specialCodeB_S node T_342 = bit(fractB_S, 51) fractB_51_PA <= T_342 roundingMode_PA <= io.roundingMode skip node T_343 = not(io.sqrtOp) node T_344 = and(entering_PA, T_343) when T_344 : specialCodeA_PA <= specialCodeA_S node T_345 = bit(fractA_S, 51) fractA_51_PA <= T_345 skip when entering_PA_normalCase : node T_346 = bit(expB_S, 11) node T_348 = subw(UInt<3>("h00"), T_346) node T_349 = bits(expB_S, 10, 0) node T_350 = not(T_349) node T_351 = cat(T_348, T_350) node T_352 = addw(expA_S, T_351) node T_353 = mux(io.sqrtOp, expB_S, T_352) exp_PA <= T_353 node T_354 = bits(fractB_S, 50, 0) fractB_other_PA <= T_354 skip when entering_PA_normalCase_div : node T_355 = bits(fractA_S, 50, 0) fractA_other_PA <= T_355 skip node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) node T_358 = bits(specialCodeA_PA, 2, 1) node isSpecialA_PA = eq(T_358, UInt<2>("h03")) node T_362 = cat(fractA_51_PA, fractA_other_PA) node sigA_PA = cat(UInt<1>("h01"), T_362) node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) node T_366 = bits(specialCodeB_PA, 2, 1) node isSpecialB_PA = eq(T_366, UInt<2>("h03")) node T_370 = cat(fractB_51_PA, fractB_other_PA) node sigB_PA = cat(UInt<1>("h01"), T_370) node T_372 = not(isSpecialB_PA) node T_373 = not(isZeroB_PA) node T_374 = and(T_372, T_373) node T_375 = not(sign_PA) node T_376 = and(T_374, T_375) node T_377 = not(isSpecialA_PA) node T_378 = not(isSpecialB_PA) node T_379 = and(T_377, T_378) node T_380 = not(isZeroA_PA) node T_381 = and(T_379, T_380) node T_382 = not(isZeroB_PA) node T_383 = and(T_381, T_382) node normalCase_PA = mux(sqrtOp_PA, T_376, T_383) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) node T_387 = and(valid_PA, valid_leaving_PA) leaving_PA <= T_387 node T_388 = not(valid_PA) node T_389 = or(T_388, valid_leaving_PA) ready_PA <= T_389 node T_390 = and(valid_PA, normalCase_PA) node entering_PB_normalCase = and(T_390, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) node T_393 = or(entering_PB, leaving_PB) when T_393 : valid_PB <= entering_PB skip when entering_PB : node T_394 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) sqrtOp_PB <= T_394 node T_395 = mux(valid_PA, sign_PA, sign_S) sign_PB <= T_395 node T_396 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) specialCodeA_PB <= T_396 node T_397 = bit(fractA_S, 51) node T_398 = mux(valid_PA, fractA_51_PA, T_397) fractA_51_PB <= T_398 node T_399 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) specialCodeB_PB <= T_399 node T_400 = bit(fractB_S, 51) node T_401 = mux(valid_PA, fractB_51_PA, T_400) fractB_51_PB <= T_401 node T_402 = mux(valid_PA, roundingMode_PA, io.roundingMode) roundingMode_PB <= T_402 skip when entering_PB_normalCase : exp_PB <= exp_PA node T_403 = bit(fractA_other_PA, 0) fractA_0_PB <= T_403 fractB_other_PB <= fractB_other_PA skip node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) node T_406 = bits(specialCodeA_PB, 2, 1) node isSpecialA_PB = eq(T_406, UInt<2>("h03")) node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) node T_411 = bits(specialCodeB_PB, 2, 1) node isSpecialB_PB = eq(T_411, UInt<2>("h03")) node T_414 = not(isSpecialB_PB) node T_415 = not(isZeroB_PB) node T_416 = and(T_414, T_415) node T_417 = not(sign_PB) node T_418 = and(T_416, T_417) node T_419 = not(isSpecialA_PB) node T_420 = not(isSpecialB_PB) node T_421 = and(T_419, T_420) node T_422 = not(isZeroA_PB) node T_423 = and(T_421, T_422) node T_424 = not(isZeroB_PB) node T_425 = and(T_423, T_424) node normalCase_PB = mux(sqrtOp_PB, T_418, T_425) node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) node T_428 = and(valid_PB, valid_leaving_PB) leaving_PB <= T_428 node T_429 = not(valid_PB) node T_430 = or(T_429, valid_leaving_PB) ready_PB <= T_430 node T_431 = and(valid_PB, normalCase_PB) node entering_PC_normalCase = and(T_431, valid_normalCase_leaving_PB) node entering_PC = or(entering_PC_S, leaving_PB) node T_434 = or(entering_PC, leaving_PC) when T_434 : valid_PC <= entering_PC skip when entering_PC : node T_435 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) sqrtOp_PC <= T_435 node T_436 = mux(valid_PB, sign_PB, sign_S) sign_PC <= T_436 node T_437 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) specialCodeA_PC <= T_437 node T_438 = bit(fractA_S, 51) node T_439 = mux(valid_PB, fractA_51_PB, T_438) fractA_51_PC <= T_439 node T_440 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) specialCodeB_PC <= T_440 node T_441 = bit(fractB_S, 51) node T_442 = mux(valid_PB, fractB_51_PB, T_441) fractB_51_PC <= T_442 node T_443 = mux(valid_PB, roundingMode_PB, io.roundingMode) roundingMode_PC <= T_443 skip when entering_PC_normalCase : exp_PC <= exp_PB fractA_0_PC <= fractA_0_PB fractB_other_PC <= fractB_other_PB skip node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) node T_446 = bits(specialCodeA_PC, 2, 1) node isSpecialA_PC = eq(T_446, UInt<2>("h03")) node T_449 = bit(specialCodeA_PC, 0) node T_450 = not(T_449) node isInfA_PC = and(isSpecialA_PC, T_450) node T_452 = bit(specialCodeA_PC, 0) node isNaNA_PC = and(isSpecialA_PC, T_452) node T_454 = not(fractA_51_PC) node isSigNaNA_PC = and(isNaNA_PC, T_454) node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) node T_458 = bits(specialCodeB_PC, 2, 1) node isSpecialB_PC = eq(T_458, UInt<2>("h03")) node T_461 = bit(specialCodeB_PC, 0) node T_462 = not(T_461) node isInfB_PC = and(isSpecialB_PC, T_462) node T_464 = bit(specialCodeB_PC, 0) node isNaNB_PC = and(isSpecialB_PC, T_464) node T_466 = not(fractB_51_PC) node isSigNaNB_PC = and(isNaNB_PC, T_466) node T_469 = cat(fractB_51_PC, fractB_other_PC) node sigB_PC = cat(UInt<1>("h01"), T_469) node T_471 = not(isSpecialB_PC) node T_472 = not(isZeroB_PC) node T_473 = and(T_471, T_472) node T_474 = not(sign_PC) node T_475 = and(T_473, T_474) node T_476 = not(isSpecialA_PC) node T_477 = not(isSpecialB_PC) node T_478 = and(T_476, T_477) node T_479 = not(isZeroA_PC) node T_480 = and(T_478, T_479) node T_481 = not(isZeroB_PC) node T_482 = and(T_480, T_481) node normalCase_PC = mux(sqrtOp_PC, T_475, T_482) node expP2_PC = addw(exp_PC, UInt<2>("h02")) node T_486 = bit(exp_PC, 0) node T_487 = bits(expP2_PC, 13, 1) node T_489 = cat(T_487, UInt<1>("h00")) node T_490 = bits(exp_PC, 13, 1) node T_492 = cat(T_490, UInt<1>("h01")) node expP1_PC = mux(T_486, T_489, T_492) node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) node T_500 = not(roundMagUp_PC) node T_501 = not(roundingMode_near_even_PC) node roundMagDown_PC = and(T_500, T_501) node T_503 = not(normalCase_PC) node valid_leaving_PC = or(T_503, cyc_E1) node T_505 = and(valid_PC, valid_leaving_PC) leaving_PC <= T_505 node T_506 = not(valid_PC) node T_507 = or(T_506, valid_leaving_PC) ready_PC <= T_507 node T_508 = not(sqrtOp_PC) node T_509 = and(leaving_PC, T_508) io.outValid_div <= T_509 node T_510 = and(leaving_PC, sqrtOp_PC) io.outValid_sqrt <= T_510 node T_512 = neq(cycleNum_A, UInt<1>("h00")) node T_513 = or(entering_PA_normalCase, T_512) when T_513 : node T_516 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) node T_519 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) node T_520 = or(T_516, T_519) node T_521 = not(entering_PA_normalCase) node T_523 = subw(cycleNum_A, UInt<1>("h01")) node T_525 = mux(T_521, T_523, UInt<1>("h00")) node T_526 = or(T_520, T_525) cycleNum_A <= T_526 skip node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) node T_540 = not(sqrtOp_PA) node cyc_A3_div = and(cyc_A3, T_540) node T_542 = not(sqrtOp_PA) node cyc_A2_div = and(cyc_A2, T_542) node T_544 = not(sqrtOp_PA) node cyc_A1_div = and(cyc_A1, T_544) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) node T_550 = neq(cycleNum_B, UInt<1>("h00")) node T_551 = or(cyc_A1, T_550) when T_551 : node T_554 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) node T_556 = subw(cycleNum_B, UInt<1>("h01")) node T_557 = mux(cyc_A1, T_554, T_556) cycleNum_B <= T_557 skip node T_559 = eq(cycleNum_B, UInt<4>("h0a")) cyc_B10_sqrt <= T_559 node T_561 = eq(cycleNum_B, UInt<4>("h09")) cyc_B9_sqrt <= T_561 node T_563 = eq(cycleNum_B, UInt<4>("h08")) cyc_B8_sqrt <= T_563 node T_565 = eq(cycleNum_B, UInt<3>("h07")) cyc_B7_sqrt <= T_565 node T_567 = eq(cycleNum_B, UInt<3>("h06")) cyc_B6 <= T_567 node T_569 = eq(cycleNum_B, UInt<3>("h05")) cyc_B5 <= T_569 node T_571 = eq(cycleNum_B, UInt<3>("h04")) cyc_B4 <= T_571 node T_573 = eq(cycleNum_B, UInt<2>("h03")) cyc_B3 <= T_573 node T_575 = eq(cycleNum_B, UInt<2>("h02")) cyc_B2 <= T_575 node T_577 = eq(cycleNum_B, UInt<1>("h01")) cyc_B1 <= T_577 node T_578 = and(cyc_B6, valid_PA) node T_579 = not(sqrtOp_PA) node T_580 = and(T_578, T_579) cyc_B6_div <= T_580 node T_581 = and(cyc_B5, valid_PA) node T_582 = not(sqrtOp_PA) node T_583 = and(T_581, T_582) cyc_B5_div <= T_583 node T_584 = and(cyc_B4, valid_PA) node T_585 = not(sqrtOp_PA) node T_586 = and(T_584, T_585) cyc_B4_div <= T_586 node T_587 = not(sqrtOp_PB) node T_588 = and(cyc_B3, T_587) cyc_B3_div <= T_588 node T_589 = not(sqrtOp_PB) node T_590 = and(cyc_B2, T_589) cyc_B2_div <= T_590 node T_591 = not(sqrtOp_PB) node T_592 = and(cyc_B1, T_591) cyc_B1_div <= T_592 node T_593 = and(cyc_B6, valid_PB) node T_594 = and(T_593, sqrtOp_PB) cyc_B6_sqrt <= T_594 node T_595 = and(cyc_B5, valid_PB) node T_596 = and(T_595, sqrtOp_PB) cyc_B5_sqrt <= T_596 node T_597 = and(cyc_B4, valid_PB) node T_598 = and(T_597, sqrtOp_PB) cyc_B4_sqrt <= T_598 node T_599 = and(cyc_B3, sqrtOp_PB) cyc_B3_sqrt <= T_599 node T_600 = and(cyc_B2, sqrtOp_PB) cyc_B2_sqrt <= T_600 node T_601 = and(cyc_B1, sqrtOp_PB) cyc_B1_sqrt <= T_601 node T_603 = neq(cycleNum_C, UInt<1>("h00")) node T_604 = or(cyc_B1, T_603) when T_604 : node T_607 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) node T_609 = subw(cycleNum_C, UInt<1>("h01")) node T_610 = mux(cyc_B1, T_607, T_609) cycleNum_C <= T_610 skip node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) node T_614 = eq(cycleNum_C, UInt<3>("h05")) cyc_C5 <= T_614 node T_616 = eq(cycleNum_C, UInt<3>("h04")) cyc_C4 <= T_616 node T_618 = eq(cycleNum_C, UInt<2>("h03")) valid_normalCase_leaving_PB <= T_618 node T_620 = eq(cycleNum_C, UInt<2>("h02")) cyc_C2 <= T_620 node T_622 = eq(cycleNum_C, UInt<1>("h01")) cyc_C1 <= T_622 node T_623 = not(sqrtOp_PB) node cyc_C5_div = and(cyc_C5, T_623) node T_625 = not(sqrtOp_PB) node cyc_C4_div = and(cyc_C4, T_625) node T_627 = not(sqrtOp_PB) node cyc_C3_div = and(valid_normalCase_leaving_PB, T_627) node T_629 = not(sqrtOp_PC) node cyc_C2_div = and(cyc_C2, T_629) node T_631 = not(sqrtOp_PC) node cyc_C1_div = and(cyc_C1, T_631) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) node T_639 = neq(cycleNum_E, UInt<1>("h00")) node T_640 = or(cyc_C1, T_639) when T_640 : node T_643 = subw(cycleNum_E, UInt<1>("h01")) node T_644 = mux(cyc_C1, UInt<3>("h04"), T_643) cycleNum_E <= T_644 skip node T_646 = eq(cycleNum_E, UInt<3>("h04")) cyc_E4 <= T_646 node T_648 = eq(cycleNum_E, UInt<2>("h03")) cyc_E3 <= T_648 node T_650 = eq(cycleNum_E, UInt<2>("h02")) cyc_E2 <= T_650 node T_652 = eq(cycleNum_E, UInt<1>("h01")) cyc_E1 <= T_652 node T_653 = not(sqrtOp_PC) node cyc_E4_div = and(cyc_E4, T_653) node T_655 = not(sqrtOp_PC) node cyc_E3_div = and(cyc_E3, T_655) node T_657 = not(sqrtOp_PC) node cyc_E2_div = and(cyc_E2, T_657) node T_659 = not(sqrtOp_PC) node cyc_E1_div = and(cyc_E1, T_659) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) node T_667 = bits(fractB_S, 51, 49) node T_669 = eq(T_667, UInt<1>("h00")) node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_669) node T_671 = bits(fractB_S, 51, 49) node T_673 = eq(T_671, UInt<1>("h01")) node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_673) node T_675 = bits(fractB_S, 51, 49) node T_677 = eq(T_675, UInt<2>("h02")) node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_677) node T_679 = bits(fractB_S, 51, 49) node T_681 = eq(T_679, UInt<2>("h03")) node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_681) node T_683 = bits(fractB_S, 51, 49) node T_685 = eq(T_683, UInt<3>("h04")) node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_685) node T_687 = bits(fractB_S, 51, 49) node T_689 = eq(T_687, UInt<3>("h05")) node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_689) node T_691 = bits(fractB_S, 51, 49) node T_693 = eq(T_691, UInt<3>("h06")) node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_693) node T_695 = bits(fractB_S, 51, 49) node T_697 = eq(T_695, UInt<3>("h07")) node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_697) node T_701 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) node T_704 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) node T_705 = or(T_701, T_704) node T_708 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) node T_709 = or(T_705, T_708) node T_712 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) node T_713 = or(T_709, T_712) node T_716 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) node T_717 = or(T_713, T_716) node T_720 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) node T_721 = or(T_717, T_720) node T_724 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) node T_725 = or(T_721, T_724) node T_728 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) node zK1_A4_div = or(T_725, T_728) node T_731 = not(UInt<12>("h0fe3")) node T_733 = mux(zLinPiece_0_A4_div, T_731, UInt<1>("h00")) node T_735 = not(UInt<12>("h0c5d")) node T_737 = mux(zLinPiece_1_A4_div, T_735, UInt<1>("h00")) node T_738 = or(T_733, T_737) node T_740 = not(UInt<12>("h098a")) node T_742 = mux(zLinPiece_2_A4_div, T_740, UInt<1>("h00")) node T_743 = or(T_738, T_742) node T_745 = not(UInt<12>("h0739")) node T_747 = mux(zLinPiece_3_A4_div, T_745, UInt<1>("h00")) node T_748 = or(T_743, T_747) node T_750 = not(UInt<12>("h054b")) node T_752 = mux(zLinPiece_4_A4_div, T_750, UInt<1>("h00")) node T_753 = or(T_748, T_752) node T_755 = not(UInt<12>("h03a9")) node T_757 = mux(zLinPiece_5_A4_div, T_755, UInt<1>("h00")) node T_758 = or(T_753, T_757) node T_760 = not(UInt<12>("h0242")) node T_762 = mux(zLinPiece_6_A4_div, T_760, UInt<1>("h00")) node T_763 = or(T_758, T_762) node T_765 = not(UInt<12>("h010b")) node T_767 = mux(zLinPiece_7_A4_div, T_765, UInt<1>("h00")) node zComplFractK0_A4_div = or(T_763, T_767) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) node T_771 = bit(expB_S, 0) node T_772 = not(T_771) node T_773 = and(entering_PA_normalCase_sqrt, T_772) node T_774 = bit(fractB_S, 51) node T_775 = not(T_774) node zQuadPiece_0_A7_sqrt = and(T_773, T_775) node T_777 = bit(expB_S, 0) node T_778 = not(T_777) node T_779 = and(entering_PA_normalCase_sqrt, T_778) node T_780 = bit(fractB_S, 51) node zQuadPiece_1_A7_sqrt = and(T_779, T_780) node T_782 = bit(expB_S, 0) node T_783 = and(entering_PA_normalCase_sqrt, T_782) node T_784 = bit(fractB_S, 51) node T_785 = not(T_784) node zQuadPiece_2_A7_sqrt = and(T_783, T_785) node T_787 = bit(expB_S, 0) node T_788 = and(entering_PA_normalCase_sqrt, T_787) node T_789 = bit(fractB_S, 51) node zQuadPiece_3_A7_sqrt = and(T_788, T_789) node T_793 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) node T_796 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) node T_797 = or(T_793, T_796) node T_800 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) node T_801 = or(T_797, T_800) node T_804 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) node zK2_A7_sqrt = or(T_801, T_804) node T_807 = not(UInt<10>("h03d0")) node T_809 = mux(zQuadPiece_0_A7_sqrt, T_807, UInt<1>("h00")) node T_811 = not(UInt<10>("h0220")) node T_813 = mux(zQuadPiece_1_A7_sqrt, T_811, UInt<1>("h00")) node T_814 = or(T_809, T_813) node T_816 = not(UInt<10>("h02b2")) node T_818 = mux(zQuadPiece_2_A7_sqrt, T_816, UInt<1>("h00")) node T_819 = or(T_814, T_818) node T_821 = not(UInt<10>("h0181")) node T_823 = mux(zQuadPiece_3_A7_sqrt, T_821, UInt<1>("h00")) node zComplK1_A7_sqrt = or(T_819, T_823) node T_825 = bit(exp_PA, 0) node T_826 = not(T_825) node T_827 = and(cyc_A6_sqrt, T_826) node T_828 = bit(sigB_PA, 51) node T_829 = not(T_828) node zQuadPiece_0_A6_sqrt = and(T_827, T_829) node T_831 = bit(exp_PA, 0) node T_832 = not(T_831) node T_833 = and(cyc_A6_sqrt, T_832) node T_834 = bit(sigB_PA, 51) node zQuadPiece_1_A6_sqrt = and(T_833, T_834) node T_836 = bit(exp_PA, 0) node T_837 = and(cyc_A6_sqrt, T_836) node T_838 = bit(sigB_PA, 51) node T_839 = not(T_838) node zQuadPiece_2_A6_sqrt = and(T_837, T_839) node T_841 = bit(exp_PA, 0) node T_842 = and(cyc_A6_sqrt, T_841) node T_843 = bit(sigB_PA, 51) node zQuadPiece_3_A6_sqrt = and(T_842, T_843) node T_846 = not(UInt<13>("h01fe5")) node T_848 = mux(zQuadPiece_0_A6_sqrt, T_846, UInt<1>("h00")) node T_850 = not(UInt<13>("h01435")) node T_852 = mux(zQuadPiece_1_A6_sqrt, T_850, UInt<1>("h00")) node T_853 = or(T_848, T_852) node T_855 = not(UInt<13>("h0d2c")) node T_857 = mux(zQuadPiece_2_A6_sqrt, T_855, UInt<1>("h00")) node T_858 = or(T_853, T_857) node T_860 = not(UInt<13>("h04e8")) node T_862 = mux(zQuadPiece_3_A6_sqrt, T_860, UInt<1>("h00")) node zComplFractK0_A6_sqrt = or(T_858, T_862) node T_864 = bits(zFractB_A4_div, 48, 40) node T_865 = or(T_864, zK2_A7_sqrt) node T_866 = not(cyc_S) node T_868 = mux(T_866, nextMulAdd9A_A, UInt<1>("h00")) node mulAdd9A_A = or(T_865, T_868) node T_870 = bits(zFractB_A7_sqrt, 50, 42) node T_871 = or(zK1_A4_div, T_870) node T_872 = not(cyc_S) node T_874 = mux(T_872, nextMulAdd9B_A, UInt<1>("h00")) node mulAdd9B_A = or(T_871, T_874) node T_876 = shl(zComplK1_A7_sqrt, 10) node T_878 = subw(UInt<6>("h00"), cyc_A6_sqrt) node T_879 = cat(zComplFractK0_A6_sqrt, T_878) node T_880 = cat(cyc_A6_sqrt, T_879) node T_881 = or(T_876, T_880) node T_883 = subw(UInt<8>("h00"), entering_PA_normalCase_div) node T_884 = cat(zComplFractK0_A4_div, T_883) node T_885 = cat(entering_PA_normalCase_div, T_884) node T_886 = or(T_881, T_885) node T_888 = shl(fractR0_A, 10) node T_889 = addw(UInt<20>("h040000"), T_888) node T_891 = mux(cyc_A5_sqrt, T_889, UInt<1>("h00")) node T_892 = or(T_886, T_891) node T_893 = bit(hiSqrR0_A_sqrt, 9) node T_894 = not(T_893) node T_895 = and(cyc_A4_sqrt, T_894) node T_898 = mux(T_895, UInt<11>("h0400"), UInt<1>("h00")) node T_899 = or(T_892, T_898) node T_900 = bit(hiSqrR0_A_sqrt, 9) node T_901 = and(cyc_A4_sqrt, T_900) node T_902 = or(T_901, cyc_A3_div) node T_903 = bits(sigB_PA, 46, 26) node T_905 = addw(T_903, UInt<11>("h0400")) node T_907 = mux(T_902, T_905, UInt<1>("h00")) node T_908 = or(T_899, T_907) node T_909 = or(cyc_A3_sqrt, cyc_A2) node T_911 = mux(T_909, partNegSigma0_A, UInt<1>("h00")) node T_912 = or(T_908, T_911) node T_913 = shl(fractR0_A, 16) node T_915 = mux(cyc_A1_sqrt, T_913, UInt<1>("h00")) node T_916 = or(T_912, T_915) node T_917 = shl(fractR0_A, 15) node T_919 = mux(cyc_A1_div, T_917, UInt<1>("h00")) node mulAdd9C_A = or(T_916, T_919) node T_921 = mul(mulAdd9A_A, mulAdd9B_A) node T_923 = bits(mulAdd9C_A, 17, 0) node T_924 = cat(UInt<1>("h00"), T_923) node loMulAdd9Out_A = addw(T_921, T_924) node T_926 = bit(loMulAdd9Out_A, 18) node T_927 = bits(mulAdd9C_A, 24, 18) node T_929 = addw(T_927, UInt<1>("h01")) node T_930 = bits(mulAdd9C_A, 24, 18) node T_931 = mux(T_926, T_929, T_930) node T_932 = bits(loMulAdd9Out_A, 17, 0) node mulAdd9Out_A = cat(T_931, T_932) node T_934 = bit(mulAdd9Out_A, 19) node T_935 = and(cyc_A6_sqrt, T_934) node T_936 = not(mulAdd9Out_A) node T_937 = shr(T_936, 10) node T_939 = mux(T_935, T_937, UInt<1>("h00")) node zFractR0_A6_sqrt = bits(T_939, 8, 0) node T_941 = bit(exp_PA, 0) node T_942 = shl(mulAdd9Out_A, 1) node sqrR0_A5_sqrt = mux(T_941, T_942, mulAdd9Out_A) node T_944 = bit(mulAdd9Out_A, 20) node T_945 = and(entering_PA_normalCase_div, T_944) node T_946 = not(mulAdd9Out_A) node T_947 = shr(T_946, 11) node T_949 = mux(T_945, T_947, UInt<1>("h00")) node zFractR0_A4_div = bits(T_949, 8, 0) node T_951 = bit(mulAdd9Out_A, 11) node T_952 = and(cyc_A2, T_951) node T_953 = not(mulAdd9Out_A) node T_954 = shr(T_953, 2) node T_956 = mux(T_952, T_954, UInt<1>("h00")) node zSigma0_A2 = bits(T_956, 8, 0) node T_958 = shr(mulAdd9Out_A, 10) node T_959 = shr(mulAdd9Out_A, 9) node T_960 = mux(sqrtOp_PA, T_958, T_959) node fractR1_A1 = bits(T_960, 14, 0) node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) node T_964 = bit(exp_PA, 0) node T_965 = shl(r1_A1, 1) node ER1_A1_sqrt = mux(T_964, T_965, r1_A1) node T_967 = or(cyc_A6_sqrt, entering_PA_normalCase_div) when T_967 : node T_968 = or(zFractR0_A6_sqrt, zFractR0_A4_div) fractR0_A <= T_968 skip when cyc_A5_sqrt : node T_969 = shr(sqrR0_A5_sqrt, 10) hiSqrR0_A_sqrt <= T_969 skip node T_970 = or(cyc_A4_sqrt, cyc_A3) when T_970 : node T_971 = shr(mulAdd9Out_A, 9) node T_972 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_971) node T_973 = bits(T_972, 20, 0) partNegSigma0_A <= T_973 skip node T_974 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node T_975 = or(T_974, cyc_A5_sqrt) node T_976 = or(T_975, cyc_A4) node T_977 = or(T_976, cyc_A3) node T_978 = or(T_977, cyc_A2) when T_978 : node T_979 = not(mulAdd9Out_A) node T_980 = shr(T_979, 11) node T_982 = mux(entering_PA_normalCase_sqrt, T_980, UInt<1>("h00")) node T_983 = or(T_982, zFractR0_A6_sqrt) node T_984 = bits(sigB_PA, 43, 35) node T_986 = mux(cyc_A4_sqrt, T_984, UInt<1>("h00")) node T_987 = or(T_983, T_986) node T_988 = bits(zFractB_A4_div, 43, 35) node T_989 = or(T_987, T_988) node T_990 = or(cyc_A5_sqrt, cyc_A3) node T_991 = bits(sigB_PA, 52, 44) node T_993 = mux(T_990, T_991, UInt<1>("h00")) node T_994 = or(T_989, T_993) node T_995 = or(T_994, zSigma0_A2) nextMulAdd9A_A <= T_995 skip node T_996 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node T_997 = or(T_996, cyc_A5_sqrt) node T_998 = or(T_997, cyc_A4) node T_999 = or(T_998, cyc_A2) when T_999 : node T_1000 = bits(zFractB_A7_sqrt, 50, 42) node T_1001 = or(T_1000, zFractR0_A6_sqrt) node T_1002 = bits(sqrR0_A5_sqrt, 9, 1) node T_1004 = mux(cyc_A5_sqrt, T_1002, UInt<1>("h00")) node T_1005 = or(T_1001, T_1004) node T_1006 = or(T_1005, zFractR0_A4_div) node T_1007 = bits(hiSqrR0_A_sqrt, 8, 0) node T_1009 = mux(cyc_A4_sqrt, T_1007, UInt<1>("h00")) node T_1010 = or(T_1006, T_1009) node T_1012 = bits(fractR0_A, 8, 1) node T_1013 = cat(UInt<1>("h01"), T_1012) node T_1015 = mux(cyc_A2, T_1013, UInt<1>("h00")) node T_1016 = or(T_1010, T_1015) nextMulAdd9B_A <= T_1016 skip when cyc_A1_sqrt : ER1_B_sqrt <= ER1_A1_sqrt skip node T_1017 = or(cyc_A1, cyc_B7_sqrt) node T_1018 = or(T_1017, cyc_B6_div) node T_1019 = or(T_1018, cyc_B4) node T_1020 = or(T_1019, cyc_B3) node T_1021 = or(T_1020, cyc_C6_sqrt) node T_1022 = or(T_1021, cyc_C4) node T_1023 = or(T_1022, cyc_C1) io.latchMulAddA_0 <= T_1023 node T_1024 = shl(ER1_A1_sqrt, 36) node T_1026 = mux(cyc_A1_sqrt, T_1024, UInt<1>("h00")) node T_1027 = or(cyc_B7_sqrt, cyc_A1_div) node T_1029 = mux(T_1027, sigB_PA, UInt<1>("h00")) node T_1030 = or(T_1026, T_1029) node T_1032 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) node T_1033 = or(T_1030, T_1032) node T_1034 = bits(zSigma1_B4, 45, 12) node T_1035 = or(T_1033, T_1034) node T_1036 = or(cyc_B3, cyc_C6_sqrt) node T_1037 = bits(sigXNU_B3_CX, 57, 12) node T_1039 = mux(T_1036, T_1037, UInt<1>("h00")) node T_1040 = or(T_1035, T_1039) node T_1041 = bits(sigXN_C, 57, 25) node T_1042 = shl(T_1041, 13) node T_1044 = mux(cyc_C4_div, T_1042, UInt<1>("h00")) node T_1045 = or(T_1040, T_1044) node T_1046 = shl(u_C_sqrt, 15) node T_1048 = mux(cyc_C4_sqrt, T_1046, UInt<1>("h00")) node T_1049 = or(T_1045, T_1048) node T_1051 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) node T_1052 = or(T_1049, T_1051) node T_1053 = or(T_1052, zComplSigT_C1_sqrt) io.mulAddA_0 <= T_1053 node T_1054 = or(cyc_A1, cyc_B7_sqrt) node T_1055 = or(T_1054, cyc_B6_sqrt) node T_1056 = or(T_1055, cyc_B4) node T_1057 = or(T_1056, cyc_C6_sqrt) node T_1058 = or(T_1057, cyc_C4) node T_1059 = or(T_1058, cyc_C1) io.latchMulAddB_0 <= T_1059 node T_1060 = shl(r1_A1, 36) node T_1062 = mux(cyc_A1, T_1060, UInt<1>("h00")) node T_1063 = shl(ESqrR1_B_sqrt, 19) node T_1065 = mux(cyc_B7_sqrt, T_1063, UInt<1>("h00")) node T_1066 = or(T_1062, T_1065) node T_1067 = shl(ER1_B_sqrt, 36) node T_1069 = mux(cyc_B6_sqrt, T_1067, UInt<1>("h00")) node T_1070 = or(T_1066, T_1069) node T_1071 = or(T_1070, zSigma1_B4) node T_1072 = bits(sqrSigma1_C, 30, 1) node T_1074 = mux(cyc_C6_sqrt, T_1072, UInt<1>("h00")) node T_1075 = or(T_1071, T_1074) node T_1077 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) node T_1078 = or(T_1075, T_1077) node T_1079 = or(T_1078, zComplSigT_C1) io.mulAddB_0 <= T_1079 node T_1080 = or(cyc_A4, cyc_A3_div) node T_1081 = or(T_1080, cyc_A1_div) node T_1082 = or(T_1081, cyc_B10_sqrt) node T_1083 = or(T_1082, cyc_B9_sqrt) node T_1084 = or(T_1083, cyc_B7_sqrt) node T_1085 = or(T_1084, cyc_B6) node T_1086 = or(T_1085, cyc_B5_sqrt) node T_1087 = or(T_1086, cyc_B3_sqrt) node T_1088 = or(T_1087, cyc_B2_div) node T_1089 = or(T_1088, cyc_B1_sqrt) node T_1090 = or(T_1089, cyc_C4) node T_1091 = or(cyc_A3, cyc_A2_div) node T_1092 = or(T_1091, cyc_B9_sqrt) node T_1093 = or(T_1092, cyc_B8_sqrt) node T_1094 = or(T_1093, cyc_B6) node T_1095 = or(T_1094, cyc_B5) node T_1096 = or(T_1095, cyc_B4_sqrt) node T_1097 = or(T_1096, cyc_B2_sqrt) node T_1098 = or(T_1097, cyc_B1_div) node T_1099 = or(T_1098, cyc_C6_sqrt) node T_1100 = or(T_1099, valid_normalCase_leaving_PB) node T_1101 = or(cyc_A2, cyc_A1_div) node T_1102 = or(T_1101, cyc_B8_sqrt) node T_1103 = or(T_1102, cyc_B7_sqrt) node T_1104 = or(T_1103, cyc_B5) node T_1105 = or(T_1104, cyc_B4) node T_1106 = or(T_1105, cyc_B3_sqrt) node T_1107 = or(T_1106, cyc_B1_sqrt) node T_1108 = or(T_1107, cyc_C5) node T_1109 = or(T_1108, cyc_C2) node T_1110 = or(io.latchMulAddA_0, cyc_B6) node T_1111 = or(T_1110, cyc_B2_sqrt) node T_1112 = cat(T_1090, T_1100) node T_1113 = cat(T_1109, T_1111) node T_1114 = cat(T_1112, T_1113) io.usingMulAdd <= T_1114 node T_1115 = shl(sigX1_B, 47) node T_1117 = mux(cyc_B1, T_1115, UInt<1>("h00")) node T_1118 = shl(sigX1_B, 46) node T_1120 = mux(cyc_C6_sqrt, T_1118, UInt<1>("h00")) node T_1121 = or(T_1117, T_1120) node T_1122 = or(cyc_C4_sqrt, cyc_C2) node T_1123 = shl(sigXN_C, 47) node T_1125 = mux(T_1122, T_1123, UInt<1>("h00")) node T_1126 = or(T_1121, T_1125) node T_1127 = not(E_E_div) node T_1128 = and(cyc_E3_div, T_1127) node T_1129 = shl(fractA_0_PC, 53) node T_1131 = mux(T_1128, T_1129, UInt<1>("h00")) node T_1132 = or(T_1126, T_1131) node T_1133 = bit(exp_PC, 0) node T_1134 = bit(sigB_PC, 0) node T_1136 = cat(T_1134, UInt<1>("h00")) node T_1137 = bit(sigB_PC, 1) node T_1138 = bit(sigB_PC, 0) node T_1139 = xor(T_1137, T_1138) node T_1140 = bit(sigB_PC, 0) node T_1141 = cat(T_1139, T_1140) node T_1142 = mux(T_1133, T_1136, T_1141) node T_1143 = not(extraT_E) node T_1145 = cat(T_1143, UInt<1>("h00")) node T_1146 = xor(T_1142, T_1145) node T_1147 = shl(T_1146, 54) node T_1149 = mux(cyc_E3_sqrt, T_1147, UInt<1>("h00")) node T_1150 = or(T_1132, T_1149) io.mulAddC_2 <= T_1150 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) node T_1152 = bits(io.mulAddResult_3, 90, 45) node T_1153 = not(T_1152) node T_1155 = mux(cyc_B4, T_1153, UInt<1>("h00")) zSigma1_B4 <= T_1155 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) node T_1157 = bits(io.mulAddResult_3, 104, 47) sigXNU_B3_CX <= T_1157 node T_1158 = bit(io.mulAddResult_3, 104) node E_C1_div = not(T_1158) node T_1160 = not(E_C1_div) node T_1161 = and(cyc_C1_div, T_1160) node T_1162 = or(T_1161, cyc_C1_sqrt) node T_1163 = bits(io.mulAddResult_3, 104, 51) node T_1164 = not(T_1163) node T_1166 = mux(T_1162, T_1164, UInt<1>("h00")) node T_1167 = and(cyc_C1_div, E_C1_div) node T_1169 = bits(io.mulAddResult_3, 102, 50) node T_1170 = not(T_1169) node T_1171 = cat(UInt<1>("h00"), T_1170) node T_1173 = mux(T_1167, T_1171, UInt<1>("h00")) node T_1174 = or(T_1166, T_1173) zComplSigT_C1 <= T_1174 node T_1175 = bits(io.mulAddResult_3, 104, 51) node T_1176 = not(T_1175) node T_1178 = mux(cyc_C1_sqrt, T_1176, UInt<1>("h00")) zComplSigT_C1_sqrt <= T_1178 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : ESqrR1_B_sqrt <= ESqrR1_B8_sqrt skip when cyc_B3 : sigX1_B <= sigXNU_B3_CX skip when cyc_B1 : sqrSigma1_C <= sqrSigma1_B1 skip node T_1181 = or(cyc_C6_sqrt, cyc_C5_div) node T_1182 = or(T_1181, cyc_C3_sqrt) when T_1182 : sigXN_C <= sigXNU_B3_CX skip when cyc_C5_sqrt : node T_1183 = bits(sigXNU_B3_CX, 56, 26) u_C_sqrt <= T_1183 skip when cyc_C1 : E_E_div <= E_C1_div node T_1184 = bits(sigT_C1, 53, 1) sigT_E <= T_1184 node T_1185 = bit(sigT_C1, 0) extraT_E <= T_1185 skip when cyc_E2 : node T_1186 = bit(remT_E2, 55) node T_1187 = bit(remT_E2, 53) node T_1188 = mux(sqrtOp_PC, T_1186, T_1187) isNegRemT_E <= T_1188 node T_1189 = bits(remT_E2, 53, 0) node T_1191 = eq(T_1189, UInt<1>("h00")) node T_1192 = not(sqrtOp_PC) node T_1193 = bits(remT_E2, 55, 54) node T_1195 = eq(T_1193, UInt<1>("h00")) node T_1196 = or(T_1192, T_1195) node T_1197 = and(T_1191, T_1196) trueEqX_E1 <= T_1197 skip node T_1198 = not(sqrtOp_PC) node T_1199 = and(T_1198, E_E_div) node T_1201 = mux(T_1199, exp_PC, UInt<1>("h00")) node T_1202 = not(sqrtOp_PC) node T_1203 = not(E_E_div) node T_1204 = and(T_1202, T_1203) node T_1206 = mux(T_1204, expP1_PC, UInt<1>("h00")) node T_1207 = or(T_1201, T_1206) node T_1208 = shr(exp_PC, 1) node T_1210 = addw(T_1208, UInt<12>("h0400")) node T_1212 = mux(sqrtOp_PC, T_1210, UInt<1>("h00")) node sExpX_E = or(T_1207, T_1212) node posExpX_E = bits(sExpX_E, 12, 0) node T_1215 = not(posExpX_E) node T_1217 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1215) node T_1218 = bits(T_1217, 1026, 974) node T_1219 = bits(T_1218, 31, 0) node T_1222 = shl(UInt<16>("h0ffff"), 16) node T_1223 = xor(UInt<32>("h0ffffffff"), T_1222) node T_1224 = shr(T_1219, 16) node T_1225 = and(T_1224, T_1223) node T_1226 = bits(T_1219, 15, 0) node T_1227 = shl(T_1226, 16) node T_1228 = not(T_1223) node T_1229 = and(T_1227, T_1228) node T_1230 = or(T_1225, T_1229) node T_1231 = bits(T_1223, 23, 0) node T_1232 = shl(T_1231, 8) node T_1233 = xor(T_1223, T_1232) node T_1234 = shr(T_1230, 8) node T_1235 = and(T_1234, T_1233) node T_1236 = bits(T_1230, 23, 0) node T_1237 = shl(T_1236, 8) node T_1238 = not(T_1233) node T_1239 = and(T_1237, T_1238) node T_1240 = or(T_1235, T_1239) node T_1241 = bits(T_1233, 27, 0) node T_1242 = shl(T_1241, 4) node T_1243 = xor(T_1233, T_1242) node T_1244 = shr(T_1240, 4) node T_1245 = and(T_1244, T_1243) node T_1246 = bits(T_1240, 27, 0) node T_1247 = shl(T_1246, 4) node T_1248 = not(T_1243) node T_1249 = and(T_1247, T_1248) node T_1250 = or(T_1245, T_1249) node T_1251 = bits(T_1243, 29, 0) node T_1252 = shl(T_1251, 2) node T_1253 = xor(T_1243, T_1252) node T_1254 = shr(T_1250, 2) node T_1255 = and(T_1254, T_1253) node T_1256 = bits(T_1250, 29, 0) node T_1257 = shl(T_1256, 2) node T_1258 = not(T_1253) node T_1259 = and(T_1257, T_1258) node T_1260 = or(T_1255, T_1259) node T_1261 = bits(T_1253, 30, 0) node T_1262 = shl(T_1261, 1) node T_1263 = xor(T_1253, T_1262) node T_1264 = shr(T_1260, 1) node T_1265 = and(T_1264, T_1263) node T_1266 = bits(T_1260, 30, 0) node T_1267 = shl(T_1266, 1) node T_1268 = not(T_1263) node T_1269 = and(T_1267, T_1268) node T_1270 = or(T_1265, T_1269) node T_1271 = bits(T_1218, 52, 32) node T_1272 = bits(T_1271, 15, 0) node T_1275 = shl(UInt<8>("h0ff"), 8) node T_1276 = xor(UInt<16>("h0ffff"), T_1275) node T_1277 = shr(T_1272, 8) node T_1278 = and(T_1277, T_1276) node T_1279 = bits(T_1272, 7, 0) node T_1280 = shl(T_1279, 8) node T_1281 = not(T_1276) node T_1282 = and(T_1280, T_1281) node T_1283 = or(T_1278, T_1282) node T_1284 = bits(T_1276, 11, 0) node T_1285 = shl(T_1284, 4) node T_1286 = xor(T_1276, T_1285) node T_1287 = shr(T_1283, 4) node T_1288 = and(T_1287, T_1286) node T_1289 = bits(T_1283, 11, 0) node T_1290 = shl(T_1289, 4) node T_1291 = not(T_1286) node T_1292 = and(T_1290, T_1291) node T_1293 = or(T_1288, T_1292) node T_1294 = bits(T_1286, 13, 0) node T_1295 = shl(T_1294, 2) node T_1296 = xor(T_1286, T_1295) node T_1297 = shr(T_1293, 2) node T_1298 = and(T_1297, T_1296) node T_1299 = bits(T_1293, 13, 0) node T_1300 = shl(T_1299, 2) node T_1301 = not(T_1296) node T_1302 = and(T_1300, T_1301) node T_1303 = or(T_1298, T_1302) node T_1304 = bits(T_1296, 14, 0) node T_1305 = shl(T_1304, 1) node T_1306 = xor(T_1296, T_1305) node T_1307 = shr(T_1303, 1) node T_1308 = and(T_1307, T_1306) node T_1309 = bits(T_1303, 14, 0) node T_1310 = shl(T_1309, 1) node T_1311 = not(T_1306) node T_1312 = and(T_1310, T_1311) node T_1313 = or(T_1308, T_1312) node T_1314 = bits(T_1271, 20, 16) node T_1315 = bits(T_1314, 3, 0) node T_1316 = bits(T_1315, 1, 0) node T_1317 = bits(T_1316, 0, 0) node T_1318 = bits(T_1316, 1, 1) node T_1319 = cat(T_1317, T_1318) node T_1320 = bits(T_1315, 3, 2) node T_1321 = bits(T_1320, 0, 0) node T_1322 = bits(T_1320, 1, 1) node T_1323 = cat(T_1321, T_1322) node T_1324 = cat(T_1319, T_1323) node T_1325 = bits(T_1314, 4, 4) node T_1326 = cat(T_1324, T_1325) node T_1327 = cat(T_1313, T_1326) node roundMask_E = cat(T_1270, T_1327) node T_1330 = cat(UInt<1>("h00"), roundMask_E) node T_1331 = not(T_1330) node T_1333 = cat(roundMask_E, UInt<1>("h01")) node incrPosMask_E = and(T_1331, T_1333) node T_1335 = shr(incrPosMask_E, 1) node T_1336 = and(sigT_E, T_1335) node hiRoundPosBitT_E = neq(T_1336, UInt<1>("h00")) node T_1339 = shr(roundMask_E, 1) node T_1340 = and(sigT_E, T_1339) node all0sHiRoundExtraT_E = eq(T_1340, UInt<1>("h00")) node T_1343 = not(sigT_E) node T_1344 = shr(roundMask_E, 1) node T_1345 = and(T_1343, T_1344) node all1sHiRoundExtraT_E = eq(T_1345, UInt<1>("h00")) node T_1348 = bit(roundMask_E, 0) node T_1349 = not(T_1348) node T_1350 = or(T_1349, hiRoundPosBitT_E) node all1sHiRoundT_E = and(T_1350, all1sHiRoundExtraT_E) node T_1353 = addw(UInt<54>("h00"), sigT_E) node sigAdjT_E = addw(T_1353, roundMagUp_PC) node T_1356 = not(roundMask_E) node T_1357 = cat(UInt<1>("h01"), T_1356) node sigY0_E = and(sigAdjT_E, T_1357) node T_1360 = cat(UInt<1>("h00"), roundMask_E) node T_1361 = or(sigAdjT_E, T_1360) node sigY1_E = addw(T_1361, UInt<1>("h01")) node T_1364 = not(isNegRemT_E) node T_1365 = not(trueEqX_E1) node T_1366 = and(T_1364, T_1365) node trueLtX_E1 = mux(sqrtOp_PC, T_1366, isNegRemT_E) node T_1368 = bit(roundMask_E, 0) node T_1369 = not(trueLtX_E1) node T_1370 = and(T_1368, T_1369) node T_1371 = and(T_1370, all1sHiRoundExtraT_E) node T_1372 = and(T_1371, extraT_E) node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1372) node T_1374 = not(trueEqX_E1) node T_1375 = not(extraT_E) node T_1376 = or(T_1374, T_1375) node T_1377 = not(all1sHiRoundExtraT_E) node anyRoundExtra_E1 = or(T_1376, T_1377) node T_1379 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) node T_1380 = not(anyRoundExtra_E1) node T_1381 = and(T_1379, T_1380) node roundEvenMask_E1 = mux(T_1381, incrPosMask_E, UInt<1>("h00")) node T_1384 = and(roundMagDown_PC, extraT_E) node T_1385 = not(trueLtX_E1) node T_1386 = and(T_1384, T_1385) node T_1387 = and(T_1386, all1sHiRoundT_E) node T_1388 = not(trueLtX_E1) node T_1389 = and(extraT_E, T_1388) node T_1390 = not(trueEqX_E1) node T_1391 = and(T_1389, T_1390) node T_1392 = not(all1sHiRoundT_E) node T_1393 = or(T_1391, T_1392) node T_1394 = and(roundMagUp_PC, T_1393) node T_1395 = or(T_1387, T_1394) node T_1396 = not(trueLtX_E1) node T_1397 = or(extraT_E, T_1396) node T_1398 = bit(roundMask_E, 0) node T_1399 = not(T_1398) node T_1400 = and(T_1397, T_1399) node T_1401 = or(hiRoundPosBitT_E, T_1400) node T_1402 = not(trueLtX_E1) node T_1403 = and(extraT_E, T_1402) node T_1404 = and(T_1403, all1sHiRoundExtraT_E) node T_1405 = or(T_1401, T_1404) node T_1406 = and(roundingMode_near_even_PC, T_1405) node T_1407 = or(T_1395, T_1406) node T_1408 = mux(T_1407, sigY1_E, sigY0_E) node T_1409 = not(roundEvenMask_E1) node sigY_E1 = and(T_1408, T_1409) node fractY_E1 = bits(sigY_E1, 51, 0) node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) node T_1413 = bit(sigY_E1, 53) node T_1414 = not(T_1413) node T_1416 = mux(T_1414, sExpX_E, UInt<1>("h00")) node T_1417 = bit(sigY_E1, 53) node T_1418 = not(sqrtOp_PC) node T_1419 = and(T_1417, T_1418) node T_1420 = and(T_1419, E_E_div) node T_1422 = mux(T_1420, expP1_PC, UInt<1>("h00")) node T_1423 = or(T_1416, T_1422) node T_1424 = bit(sigY_E1, 53) node T_1425 = not(sqrtOp_PC) node T_1426 = and(T_1424, T_1425) node T_1427 = not(E_E_div) node T_1428 = and(T_1426, T_1427) node T_1430 = mux(T_1428, expP2_PC, UInt<1>("h00")) node T_1431 = or(T_1423, T_1430) node T_1432 = bit(sigY_E1, 53) node T_1433 = and(T_1432, sqrtOp_PC) node T_1434 = shr(expP2_PC, 1) node T_1436 = addw(T_1434, UInt<12>("h0400")) node T_1438 = mux(T_1433, T_1436, UInt<1>("h00")) node sExpY_E1 = or(T_1431, T_1438) node expY_E1 = bits(sExpY_E1, 11, 0) node T_1441 = bit(sExpY_E1, 13) node T_1442 = not(T_1441) node T_1444 = bits(sExpY_E1, 12, 10) node T_1445 = leq(UInt<3>("h03"), T_1444) node overflowY_E1 = and(T_1442, T_1445) node T_1447 = bit(sExpY_E1, 13) node T_1448 = bits(sExpY_E1, 12, 0) node T_1450 = lt(T_1448, UInt<13>("h03ce")) node totalUnderflowY_E1 = or(T_1447, T_1450) node T_1453 = leq(posExpX_E, UInt<13>("h0401")) node T_1454 = and(T_1453, inexactY_E1) node underflowY_E1 = or(totalUnderflowY_E1, T_1454) node T_1456 = not(isNaNB_PC) node T_1457 = not(isZeroB_PC) node T_1458 = and(T_1456, T_1457) node T_1459 = and(T_1458, sign_PC) node T_1460 = and(isZeroA_PC, isZeroB_PC) node T_1461 = and(isInfA_PC, isInfB_PC) node T_1462 = or(T_1460, T_1461) node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1459, T_1462) node T_1464 = not(sqrtOp_PC) node T_1465 = and(T_1464, isSigNaNA_PC) node T_1466 = or(T_1465, isSigNaNB_PC) node invalid_PC = or(T_1466, notSigNaN_invalid_PC) node T_1468 = not(sqrtOp_PC) node T_1469 = not(isSpecialA_PC) node T_1470 = and(T_1468, T_1469) node T_1471 = not(isZeroA_PC) node T_1472 = and(T_1470, T_1471) node infinity_PC = and(T_1472, isZeroB_PC) node overflow_E1 = and(normalCase_PC, overflowY_E1) node underflow_E1 = and(normalCase_PC, underflowY_E1) node T_1476 = or(overflow_E1, underflow_E1) node T_1477 = and(normalCase_PC, inexactY_E1) node inexact_E1 = or(T_1476, T_1477) node T_1479 = or(isZeroA_PC, isInfB_PC) node T_1480 = not(roundMagUp_PC) node T_1481 = and(totalUnderflowY_E1, T_1480) node T_1482 = or(T_1479, T_1481) node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1482) node T_1484 = and(normalCase_PC, totalUnderflowY_E1) node pegMinFiniteMagOut_E1 = and(T_1484, roundMagUp_PC) node T_1486 = not(overflowY_roundMagUp_PC) node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1486) node T_1488 = or(isInfA_PC, isZeroB_PC) node T_1489 = and(overflow_E1, overflowY_roundMagUp_PC) node T_1490 = or(T_1488, T_1489) node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1490) node T_1492 = not(sqrtOp_PC) node T_1493 = and(T_1492, isNaNA_PC) node T_1494 = or(T_1493, isNaNB_PC) node isNaNOut_PC = or(T_1494, notSigNaN_invalid_PC) node T_1496 = not(isNaNOut_PC) node T_1497 = and(isZeroB_PC, sign_PC) node T_1498 = mux(sqrtOp_PC, T_1497, sign_PC) node signOut_PC = and(T_1496, T_1498) node T_1501 = not(UInt<12>("h01ff")) node T_1503 = mux(notSpecial_isZeroOut_E1, T_1501, UInt<1>("h00")) node T_1504 = not(T_1503) node T_1505 = and(expY_E1, T_1504) node T_1507 = not(UInt<12>("h03ce")) node T_1509 = mux(pegMinFiniteMagOut_E1, T_1507, UInt<1>("h00")) node T_1510 = not(T_1509) node T_1511 = and(T_1505, T_1510) node T_1513 = not(UInt<12>("h0bff")) node T_1515 = mux(pegMaxFiniteMagOut_E1, T_1513, UInt<1>("h00")) node T_1516 = not(T_1515) node T_1517 = and(T_1511, T_1516) node T_1519 = not(UInt<12>("h0dff")) node T_1521 = mux(notNaN_isInfOut_E1, T_1519, UInt<1>("h00")) node T_1522 = not(T_1521) node T_1523 = and(T_1517, T_1522) node T_1526 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) node T_1527 = or(T_1523, T_1526) node T_1530 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) node T_1531 = or(T_1527, T_1530) node T_1534 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) node T_1535 = or(T_1531, T_1534) node T_1538 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) node expOut_E1 = or(T_1535, T_1538) node T_1540 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) node T_1541 = or(T_1540, isNaNOut_PC) node T_1543 = mux(T_1541, UInt<1>("h00"), fractY_E1) node T_1545 = subw(UInt<52>("h00"), pegMaxFiniteMagOut_E1) node T_1546 = or(T_1543, T_1545) node T_1547 = shl(isNaNOut_PC, 51) node fractOut_E1 = or(T_1546, T_1547) node T_1549 = cat(expOut_E1, fractOut_E1) node T_1550 = cat(signOut_PC, T_1549) io.out <= T_1550 node T_1551 = cat(invalid_PC, infinity_PC) node T_1552 = cat(underflow_E1, inexact_E1) node T_1553 = cat(overflow_E1, T_1552) node T_1554 = cat(T_1551, T_1553) io.exceptionFlags <= T_1554 module Mul54 : input clk : Clock input reset : UInt<1> output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} io.result_s3 <= UInt<1>("h00") reg val_s1 : UInt<1>, clk, UInt<1>("h00"), val_s1 reg val_s2 : UInt<1>, clk, UInt<1>("h00"), val_s2 reg reg_a_s1 : UInt<54>, clk, UInt<1>("h00"), reg_a_s1 reg reg_b_s1 : UInt<54>, clk, UInt<1>("h00"), reg_b_s1 reg reg_a_s2 : UInt<54>, clk, UInt<1>("h00"), reg_a_s2 reg reg_b_s2 : UInt<54>, clk, UInt<1>("h00"), reg_b_s2 reg reg_result_s3 : UInt<105>, clk, UInt<1>("h00"), reg_result_s3 val_s1 <= io.val_s0 val_s2 <= val_s1 when io.val_s0 : when io.latch_a_s0 : reg_a_s1 <= io.a_s0 skip when io.latch_b_s0 : reg_b_s1 <= io.b_s0 skip skip when val_s1 : reg_a_s2 <= reg_a_s1 reg_b_s2 <= reg_b_s1 skip when val_s2 : node T_25 = mul(reg_a_s2, reg_b_s2) node T_26 = bits(T_25, 104, 0) node T_27 = addw(T_26, io.c_s2) reg_result_s3 <= T_27 skip io.result_s3 <= reg_result_s3 module DivSqrtRecF64 : input clk : Clock input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} io.exceptionFlags <= UInt<1>("h00") io.out <= UInt<1>("h00") io.outValid_sqrt <= UInt<1>("h00") io.outValid_div <= UInt<1>("h00") io.inReady_sqrt <= UInt<1>("h00") io.inReady_div <= UInt<1>("h00") inst ds of DivSqrtRecF64_mulAddZ31 ds.io.mulAddResult_3 <= UInt<1>("h00") ds.io.roundingMode <= UInt<1>("h00") ds.io.b <= UInt<1>("h00") ds.io.a <= UInt<1>("h00") ds.io.sqrtOp <= UInt<1>("h00") ds.io.inValid <= UInt<1>("h00") ds.clk <= clk ds.reset <= reset io.inReady_div <= ds.io.inReady_div io.inReady_sqrt <= ds.io.inReady_sqrt ds.io.inValid <= io.inValid ds.io.sqrtOp <= io.sqrtOp ds.io.a <= io.a ds.io.b <= io.b ds.io.roundingMode <= io.roundingMode io.outValid_div <= ds.io.outValid_div io.outValid_sqrt <= ds.io.outValid_sqrt io.out <= ds.io.out io.exceptionFlags <= ds.io.exceptionFlags inst mul of Mul54 mul.io.c_s2 <= UInt<1>("h00") mul.io.b_s0 <= UInt<1>("h00") mul.io.latch_b_s0 <= UInt<1>("h00") mul.io.a_s0 <= UInt<1>("h00") mul.io.latch_a_s0 <= UInt<1>("h00") mul.io.val_s0 <= UInt<1>("h00") mul.clk <= clk mul.reset <= reset node T_29 = bit(ds.io.usingMulAdd, 0) mul.io.val_s0 <= T_29 mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 mul.io.a_s0 <= ds.io.mulAddA_0 mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 mul.io.b_s0 <= ds.io.mulAddB_0 mul.io.c_s2 <= ds.io.mulAddC_2 ds.io.mulAddResult_3 <= mul.io.result_s3 module FPU : input clk : Clock input reset : UInt<1> output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} io.cp_resp.bits.exc <= UInt<1>("h00") io.cp_resp.bits.data <= UInt<1>("h00") io.cp_resp.valid <= UInt<1>("h00") io.cp_req.ready <= UInt<1>("h00") io.sboard_clra <= UInt<1>("h00") io.sboard_clr <= UInt<1>("h00") io.sboard_set <= UInt<1>("h00") io.dec.wflags <= UInt<1>("h00") io.dec.round <= UInt<1>("h00") io.dec.sqrt <= UInt<1>("h00") io.dec.div <= UInt<1>("h00") io.dec.fma <= UInt<1>("h00") io.dec.fastpipe <= UInt<1>("h00") io.dec.toint <= UInt<1>("h00") io.dec.fromint <= UInt<1>("h00") io.dec.single <= UInt<1>("h00") io.dec.swap23 <= UInt<1>("h00") io.dec.swap12 <= UInt<1>("h00") io.dec.ren3 <= UInt<1>("h00") io.dec.ren2 <= UInt<1>("h00") io.dec.ren1 <= UInt<1>("h00") io.dec.wen <= UInt<1>("h00") io.dec.ldst <= UInt<1>("h00") io.dec.cmd <= UInt<1>("h00") io.illegal_rm <= UInt<1>("h00") io.nack_mem <= UInt<1>("h00") io.fcsr_rdy <= UInt<1>("h00") io.toint_data <= UInt<1>("h00") io.store_data <= UInt<1>("h00") io.fcsr_flags.bits <= UInt<1>("h00") io.fcsr_flags.valid <= UInt<1>("h00") reg ex_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") ex_reg_valid <= io.valid node req_valid = or(ex_reg_valid, io.cp_req.valid) reg ex_reg_inst : UInt<32>, clk, UInt<1>("h00"), ex_reg_inst when io.valid : ex_reg_inst <= io.inst skip node T_202 = eq(ex_reg_valid, UInt<1>("h00")) node ex_cp_valid = and(io.cp_req.valid, T_202) node T_205 = eq(io.killx, UInt<1>("h00")) node T_206 = and(ex_reg_valid, T_205) node T_207 = or(T_206, ex_cp_valid) reg mem_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") mem_reg_valid <= T_207 reg mem_reg_inst : UInt<32>, clk, UInt<1>("h00"), mem_reg_inst when ex_reg_valid : mem_reg_inst <= ex_reg_inst skip reg mem_cp_valid : UInt<1>, clk, reset, UInt<1>("h00") mem_cp_valid <= ex_cp_valid node T_213 = or(io.killm, io.nack_mem) node T_215 = eq(mem_cp_valid, UInt<1>("h00")) node killm = and(T_213, T_215) node T_218 = eq(killm, UInt<1>("h00")) node T_219 = or(T_218, mem_cp_valid) node T_220 = and(mem_reg_valid, T_219) reg wb_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") wb_reg_valid <= T_220 reg wb_cp_valid : UInt<1>, clk, reset, UInt<1>("h00") wb_cp_valid <= mem_cp_valid inst fp_decoder of FPUDecoder fp_decoder.io.inst <= UInt<1>("h00") fp_decoder.clk <= clk fp_decoder.reset <= reset fp_decoder.io.inst <= io.inst wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} cp_ctrl.wflags <= UInt<1>("h00") cp_ctrl.round <= UInt<1>("h00") cp_ctrl.sqrt <= UInt<1>("h00") cp_ctrl.div <= UInt<1>("h00") cp_ctrl.fma <= UInt<1>("h00") cp_ctrl.fastpipe <= UInt<1>("h00") cp_ctrl.toint <= UInt<1>("h00") cp_ctrl.fromint <= UInt<1>("h00") cp_ctrl.single <= UInt<1>("h00") cp_ctrl.swap23 <= UInt<1>("h00") cp_ctrl.swap12 <= UInt<1>("h00") cp_ctrl.ren3 <= UInt<1>("h00") cp_ctrl.ren2 <= UInt<1>("h00") cp_ctrl.ren1 <= UInt<1>("h00") cp_ctrl.wen <= UInt<1>("h00") cp_ctrl.ldst <= UInt<1>("h00") cp_ctrl.cmd <= UInt<1>("h00") cp_ctrl <- io.cp_req.bits io.cp_resp.valid <= UInt<1>("h00") io.cp_resp.bits.data <= UInt<1>("h00") reg T_282 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), T_282 when io.valid : T_282 <- fp_decoder.io.sigs skip wire ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} ex_ctrl <- cp_ctrl when ex_reg_valid : ex_ctrl <- T_282 skip reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), mem_ctrl when req_valid : mem_ctrl <- ex_ctrl skip reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), wb_ctrl when mem_reg_valid : wb_ctrl <- mem_ctrl skip reg load_wb : UInt<1>, clk, UInt<1>("h00"), load_wb load_wb <= io.dmem_resp_val node T_373 = eq(io.dmem_resp_type, UInt<3>("h02")) node T_374 = eq(io.dmem_resp_type, UInt<3>("h06")) node T_375 = or(T_373, T_374) reg load_wb_single : UInt<1>, clk, UInt<1>("h00"), load_wb_single when io.dmem_resp_val : load_wb_single <= T_375 skip reg load_wb_data : UInt<64>, clk, UInt<1>("h00"), load_wb_data when io.dmem_resp_val : load_wb_data <= io.dmem_resp_data skip reg load_wb_tag : UInt<5>, clk, UInt<1>("h00"), load_wb_tag when io.dmem_resp_val : load_wb_tag <= io.dmem_resp_tag skip node T_379 = bit(load_wb_data, 31) node T_380 = bits(load_wb_data, 30, 23) node T_381 = bits(load_wb_data, 22, 0) node T_383 = eq(T_380, UInt<1>("h00")) node T_385 = eq(T_381, UInt<1>("h00")) node T_386 = and(T_383, T_385) node T_387 = shl(T_381, 9) node T_388 = bit(T_387, 31) node T_390 = bit(T_387, 30) node T_392 = bit(T_387, 29) node T_394 = bit(T_387, 28) node T_396 = bit(T_387, 27) node T_398 = bit(T_387, 26) node T_400 = bit(T_387, 25) node T_402 = bit(T_387, 24) node T_404 = bit(T_387, 23) node T_406 = bit(T_387, 22) node T_408 = bit(T_387, 21) node T_410 = bit(T_387, 20) node T_412 = bit(T_387, 19) node T_414 = bit(T_387, 18) node T_416 = bit(T_387, 17) node T_418 = bit(T_387, 16) node T_420 = bit(T_387, 15) node T_422 = bit(T_387, 14) node T_424 = bit(T_387, 13) node T_426 = bit(T_387, 12) node T_428 = bit(T_387, 11) node T_430 = bit(T_387, 10) node T_432 = bit(T_387, 9) node T_434 = bit(T_387, 8) node T_436 = bit(T_387, 7) node T_438 = bit(T_387, 6) node T_440 = bit(T_387, 5) node T_442 = bit(T_387, 4) node T_444 = bit(T_387, 3) node T_446 = bit(T_387, 2) node T_448 = bit(T_387, 1) node T_449 = shl(T_448, 0) node T_450 = mux(T_446, UInt<2>("h02"), T_449) node T_451 = mux(T_444, UInt<2>("h03"), T_450) node T_452 = mux(T_442, UInt<3>("h04"), T_451) node T_453 = mux(T_440, UInt<3>("h05"), T_452) node T_454 = mux(T_438, UInt<3>("h06"), T_453) node T_455 = mux(T_436, UInt<3>("h07"), T_454) node T_456 = mux(T_434, UInt<4>("h08"), T_455) node T_457 = mux(T_432, UInt<4>("h09"), T_456) node T_458 = mux(T_430, UInt<4>("h0a"), T_457) node T_459 = mux(T_428, UInt<4>("h0b"), T_458) node T_460 = mux(T_426, UInt<4>("h0c"), T_459) node T_461 = mux(T_424, UInt<4>("h0d"), T_460) node T_462 = mux(T_422, UInt<4>("h0e"), T_461) node T_463 = mux(T_420, UInt<4>("h0f"), T_462) node T_464 = mux(T_418, UInt<5>("h010"), T_463) node T_465 = mux(T_416, UInt<5>("h011"), T_464) node T_466 = mux(T_414, UInt<5>("h012"), T_465) node T_467 = mux(T_412, UInt<5>("h013"), T_466) node T_468 = mux(T_410, UInt<5>("h014"), T_467) node T_469 = mux(T_408, UInt<5>("h015"), T_468) node T_470 = mux(T_406, UInt<5>("h016"), T_469) node T_471 = mux(T_404, UInt<5>("h017"), T_470) node T_472 = mux(T_402, UInt<5>("h018"), T_471) node T_473 = mux(T_400, UInt<5>("h019"), T_472) node T_474 = mux(T_398, UInt<5>("h01a"), T_473) node T_475 = mux(T_396, UInt<5>("h01b"), T_474) node T_476 = mux(T_394, UInt<5>("h01c"), T_475) node T_477 = mux(T_392, UInt<5>("h01d"), T_476) node T_478 = mux(T_390, UInt<5>("h01e"), T_477) node T_479 = mux(T_388, UInt<5>("h01f"), T_478) node T_480 = not(T_479) node T_481 = dshl(T_381, T_480) node T_482 = bits(T_481, 21, 0) node T_484 = cat(T_482, UInt<1>("h00")) node T_487 = subw(UInt<9>("h00"), UInt<1>("h01")) node T_488 = xor(T_480, T_487) node T_489 = mux(T_383, T_488, T_380) node T_493 = mux(T_383, UInt<2>("h02"), UInt<1>("h01")) node T_494 = or(UInt<8>("h080"), T_493) node T_495 = addw(T_489, T_494) node T_496 = bits(T_495, 8, 7) node T_498 = eq(T_496, UInt<2>("h03")) node T_500 = eq(T_385, UInt<1>("h00")) node T_501 = and(T_498, T_500) node T_503 = subw(UInt<3>("h00"), T_386) node T_504 = shl(T_503, 6) node T_505 = not(T_504) node T_506 = and(T_495, T_505) node T_507 = shl(T_501, 6) node T_508 = or(T_506, T_507) node T_509 = mux(T_383, T_484, T_381) node T_510 = cat(T_508, T_509) node rec_s = cat(T_379, T_510) node T_512 = bit(load_wb_data, 63) node T_513 = bits(load_wb_data, 62, 52) node T_514 = bits(load_wb_data, 51, 0) node T_516 = eq(T_513, UInt<1>("h00")) node T_518 = eq(T_514, UInt<1>("h00")) node T_519 = and(T_516, T_518) node T_520 = shl(T_514, 12) node T_521 = bit(T_520, 63) node T_523 = bit(T_520, 62) node T_525 = bit(T_520, 61) node T_527 = bit(T_520, 60) node T_529 = bit(T_520, 59) node T_531 = bit(T_520, 58) node T_533 = bit(T_520, 57) node T_535 = bit(T_520, 56) node T_537 = bit(T_520, 55) node T_539 = bit(T_520, 54) node T_541 = bit(T_520, 53) node T_543 = bit(T_520, 52) node T_545 = bit(T_520, 51) node T_547 = bit(T_520, 50) node T_549 = bit(T_520, 49) node T_551 = bit(T_520, 48) node T_553 = bit(T_520, 47) node T_555 = bit(T_520, 46) node T_557 = bit(T_520, 45) node T_559 = bit(T_520, 44) node T_561 = bit(T_520, 43) node T_563 = bit(T_520, 42) node T_565 = bit(T_520, 41) node T_567 = bit(T_520, 40) node T_569 = bit(T_520, 39) node T_571 = bit(T_520, 38) node T_573 = bit(T_520, 37) node T_575 = bit(T_520, 36) node T_577 = bit(T_520, 35) node T_579 = bit(T_520, 34) node T_581 = bit(T_520, 33) node T_583 = bit(T_520, 32) node T_585 = bit(T_520, 31) node T_587 = bit(T_520, 30) node T_589 = bit(T_520, 29) node T_591 = bit(T_520, 28) node T_593 = bit(T_520, 27) node T_595 = bit(T_520, 26) node T_597 = bit(T_520, 25) node T_599 = bit(T_520, 24) node T_601 = bit(T_520, 23) node T_603 = bit(T_520, 22) node T_605 = bit(T_520, 21) node T_607 = bit(T_520, 20) node T_609 = bit(T_520, 19) node T_611 = bit(T_520, 18) node T_613 = bit(T_520, 17) node T_615 = bit(T_520, 16) node T_617 = bit(T_520, 15) node T_619 = bit(T_520, 14) node T_621 = bit(T_520, 13) node T_623 = bit(T_520, 12) node T_625 = bit(T_520, 11) node T_627 = bit(T_520, 10) node T_629 = bit(T_520, 9) node T_631 = bit(T_520, 8) node T_633 = bit(T_520, 7) node T_635 = bit(T_520, 6) node T_637 = bit(T_520, 5) node T_639 = bit(T_520, 4) node T_641 = bit(T_520, 3) node T_643 = bit(T_520, 2) node T_645 = bit(T_520, 1) node T_646 = shl(T_645, 0) node T_647 = mux(T_643, UInt<2>("h02"), T_646) node T_648 = mux(T_641, UInt<2>("h03"), T_647) node T_649 = mux(T_639, UInt<3>("h04"), T_648) node T_650 = mux(T_637, UInt<3>("h05"), T_649) node T_651 = mux(T_635, UInt<3>("h06"), T_650) node T_652 = mux(T_633, UInt<3>("h07"), T_651) node T_653 = mux(T_631, UInt<4>("h08"), T_652) node T_654 = mux(T_629, UInt<4>("h09"), T_653) node T_655 = mux(T_627, UInt<4>("h0a"), T_654) node T_656 = mux(T_625, UInt<4>("h0b"), T_655) node T_657 = mux(T_623, UInt<4>("h0c"), T_656) node T_658 = mux(T_621, UInt<4>("h0d"), T_657) node T_659 = mux(T_619, UInt<4>("h0e"), T_658) node T_660 = mux(T_617, UInt<4>("h0f"), T_659) node T_661 = mux(T_615, UInt<5>("h010"), T_660) node T_662 = mux(T_613, UInt<5>("h011"), T_661) node T_663 = mux(T_611, UInt<5>("h012"), T_662) node T_664 = mux(T_609, UInt<5>("h013"), T_663) node T_665 = mux(T_607, UInt<5>("h014"), T_664) node T_666 = mux(T_605, UInt<5>("h015"), T_665) node T_667 = mux(T_603, UInt<5>("h016"), T_666) node T_668 = mux(T_601, UInt<5>("h017"), T_667) node T_669 = mux(T_599, UInt<5>("h018"), T_668) node T_670 = mux(T_597, UInt<5>("h019"), T_669) node T_671 = mux(T_595, UInt<5>("h01a"), T_670) node T_672 = mux(T_593, UInt<5>("h01b"), T_671) node T_673 = mux(T_591, UInt<5>("h01c"), T_672) node T_674 = mux(T_589, UInt<5>("h01d"), T_673) node T_675 = mux(T_587, UInt<5>("h01e"), T_674) node T_676 = mux(T_585, UInt<5>("h01f"), T_675) node T_677 = mux(T_583, UInt<6>("h020"), T_676) node T_678 = mux(T_581, UInt<6>("h021"), T_677) node T_679 = mux(T_579, UInt<6>("h022"), T_678) node T_680 = mux(T_577, UInt<6>("h023"), T_679) node T_681 = mux(T_575, UInt<6>("h024"), T_680) node T_682 = mux(T_573, UInt<6>("h025"), T_681) node T_683 = mux(T_571, UInt<6>("h026"), T_682) node T_684 = mux(T_569, UInt<6>("h027"), T_683) node T_685 = mux(T_567, UInt<6>("h028"), T_684) node T_686 = mux(T_565, UInt<6>("h029"), T_685) node T_687 = mux(T_563, UInt<6>("h02a"), T_686) node T_688 = mux(T_561, UInt<6>("h02b"), T_687) node T_689 = mux(T_559, UInt<6>("h02c"), T_688) node T_690 = mux(T_557, UInt<6>("h02d"), T_689) node T_691 = mux(T_555, UInt<6>("h02e"), T_690) node T_692 = mux(T_553, UInt<6>("h02f"), T_691) node T_693 = mux(T_551, UInt<6>("h030"), T_692) node T_694 = mux(T_549, UInt<6>("h031"), T_693) node T_695 = mux(T_547, UInt<6>("h032"), T_694) node T_696 = mux(T_545, UInt<6>("h033"), T_695) node T_697 = mux(T_543, UInt<6>("h034"), T_696) node T_698 = mux(T_541, UInt<6>("h035"), T_697) node T_699 = mux(T_539, UInt<6>("h036"), T_698) node T_700 = mux(T_537, UInt<6>("h037"), T_699) node T_701 = mux(T_535, UInt<6>("h038"), T_700) node T_702 = mux(T_533, UInt<6>("h039"), T_701) node T_703 = mux(T_531, UInt<6>("h03a"), T_702) node T_704 = mux(T_529, UInt<6>("h03b"), T_703) node T_705 = mux(T_527, UInt<6>("h03c"), T_704) node T_706 = mux(T_525, UInt<6>("h03d"), T_705) node T_707 = mux(T_523, UInt<6>("h03e"), T_706) node T_708 = mux(T_521, UInt<6>("h03f"), T_707) node T_709 = not(T_708) node T_710 = dshl(T_514, T_709) node T_711 = bits(T_710, 50, 0) node T_713 = cat(T_711, UInt<1>("h00")) node T_716 = subw(UInt<12>("h00"), UInt<1>("h01")) node T_717 = xor(T_709, T_716) node T_718 = mux(T_516, T_717, T_513) node T_722 = mux(T_516, UInt<2>("h02"), UInt<1>("h01")) node T_723 = or(UInt<11>("h0400"), T_722) node T_724 = addw(T_718, T_723) node T_725 = bits(T_724, 11, 10) node T_727 = eq(T_725, UInt<2>("h03")) node T_729 = eq(T_518, UInt<1>("h00")) node T_730 = and(T_727, T_729) node T_732 = subw(UInt<3>("h00"), T_519) node T_733 = shl(T_732, 9) node T_734 = not(T_733) node T_735 = and(T_724, T_734) node T_736 = shl(T_730, 9) node T_737 = or(T_735, T_736) node T_738 = mux(T_516, T_713, T_514) node T_739 = cat(T_737, T_738) node rec_d = cat(T_512, T_739) node T_742 = asUInt(asSInt(UInt<32>("h0ffffffff"))) node T_743 = cat(T_742, rec_s) node load_wb_data_recoded = mux(load_wb_single, T_743, rec_d) cmem regfile : UInt<65>[32] when load_wb : infer mport T_748 = regfile[load_wb_tag], clk T_748 <= load_wb_data_recoded skip reg ex_ra1 : UInt, clk, UInt<1>("h00"), ex_ra1 reg ex_ra2 : UInt, clk, UInt<1>("h00"), ex_ra2 reg ex_ra3 : UInt, clk, UInt<1>("h00"), ex_ra3 when io.valid : when fp_decoder.io.sigs.ren1 : node T_756 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) when T_756 : node T_757 = bits(io.inst, 19, 15) ex_ra1 <= T_757 skip when fp_decoder.io.sigs.swap12 : node T_758 = bits(io.inst, 19, 15) ex_ra2 <= T_758 skip skip when fp_decoder.io.sigs.ren2 : when fp_decoder.io.sigs.swap12 : node T_759 = bits(io.inst, 24, 20) ex_ra1 <= T_759 skip when fp_decoder.io.sigs.swap23 : node T_760 = bits(io.inst, 24, 20) ex_ra3 <= T_760 skip node T_762 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) node T_764 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) node T_765 = and(T_762, T_764) when T_765 : node T_766 = bits(io.inst, 24, 20) ex_ra2 <= T_766 skip skip when fp_decoder.io.sigs.ren3 : node T_767 = bits(io.inst, 31, 27) ex_ra3 <= T_767 skip skip infer mport ex_rs1 = regfile[ex_ra1], clk infer mport ex_rs2 = regfile[ex_ra2], clk infer mport ex_rs3 = regfile[ex_ra3], clk node T_771 = bits(ex_reg_inst, 14, 12) node T_773 = eq(T_771, UInt<3>("h07")) node T_774 = bits(ex_reg_inst, 14, 12) node ex_rm = mux(T_773, io.fcsr_rm, T_774) node cp_rs2 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in3, io.cp_req.bits.in2) node cp_rs3 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in2, io.cp_req.bits.in3) wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} req.in3 <= UInt<1>("h00") req.in2 <= UInt<1>("h00") req.in1 <= UInt<1>("h00") req.typ <= UInt<1>("h00") req.rm <= UInt<1>("h00") req.wflags <= UInt<1>("h00") req.round <= UInt<1>("h00") req.sqrt <= UInt<1>("h00") req.div <= UInt<1>("h00") req.fma <= UInt<1>("h00") req.fastpipe <= UInt<1>("h00") req.toint <= UInt<1>("h00") req.fromint <= UInt<1>("h00") req.single <= UInt<1>("h00") req.swap23 <= UInt<1>("h00") req.swap12 <= UInt<1>("h00") req.ren3 <= UInt<1>("h00") req.ren2 <= UInt<1>("h00") req.ren1 <= UInt<1>("h00") req.wen <= UInt<1>("h00") req.ldst <= UInt<1>("h00") req.cmd <= UInt<1>("h00") req <- ex_ctrl node T_846 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm) req.rm <= T_846 node T_847 = mux(ex_reg_valid, ex_rs1, io.cp_req.bits.in1) req.in1 <= T_847 node T_848 = mux(ex_reg_valid, ex_rs2, cp_rs2) req.in2 <= T_848 node T_849 = mux(ex_reg_valid, ex_rs3, cp_rs3) req.in3 <= T_849 node T_850 = bits(ex_reg_inst, 21, 20) node T_851 = mux(ex_reg_valid, T_850, io.cp_req.bits.typ) req.typ <= T_851 inst sfma of FPUFMAPipe sfma.io.in.bits.in3 <= UInt<1>("h00") sfma.io.in.bits.in2 <= UInt<1>("h00") sfma.io.in.bits.in1 <= UInt<1>("h00") sfma.io.in.bits.typ <= UInt<1>("h00") sfma.io.in.bits.rm <= UInt<1>("h00") sfma.io.in.bits.wflags <= UInt<1>("h00") sfma.io.in.bits.round <= UInt<1>("h00") sfma.io.in.bits.sqrt <= UInt<1>("h00") sfma.io.in.bits.div <= UInt<1>("h00") sfma.io.in.bits.fma <= UInt<1>("h00") sfma.io.in.bits.fastpipe <= UInt<1>("h00") sfma.io.in.bits.toint <= UInt<1>("h00") sfma.io.in.bits.fromint <= UInt<1>("h00") sfma.io.in.bits.single <= UInt<1>("h00") sfma.io.in.bits.swap23 <= UInt<1>("h00") sfma.io.in.bits.swap12 <= UInt<1>("h00") sfma.io.in.bits.ren3 <= UInt<1>("h00") sfma.io.in.bits.ren2 <= UInt<1>("h00") sfma.io.in.bits.ren1 <= UInt<1>("h00") sfma.io.in.bits.wen <= UInt<1>("h00") sfma.io.in.bits.ldst <= UInt<1>("h00") sfma.io.in.bits.cmd <= UInt<1>("h00") sfma.io.in.valid <= UInt<1>("h00") sfma.clk <= clk sfma.reset <= reset node T_876 = and(req_valid, ex_ctrl.fma) node T_877 = and(T_876, ex_ctrl.single) sfma.io.in.valid <= T_877 sfma.io.in.bits <- req inst dfma of FPUFMAPipe_113 dfma.io.in.bits.in3 <= UInt<1>("h00") dfma.io.in.bits.in2 <= UInt<1>("h00") dfma.io.in.bits.in1 <= UInt<1>("h00") dfma.io.in.bits.typ <= UInt<1>("h00") dfma.io.in.bits.rm <= UInt<1>("h00") dfma.io.in.bits.wflags <= UInt<1>("h00") dfma.io.in.bits.round <= UInt<1>("h00") dfma.io.in.bits.sqrt <= UInt<1>("h00") dfma.io.in.bits.div <= UInt<1>("h00") dfma.io.in.bits.fma <= UInt<1>("h00") dfma.io.in.bits.fastpipe <= UInt<1>("h00") dfma.io.in.bits.toint <= UInt<1>("h00") dfma.io.in.bits.fromint <= UInt<1>("h00") dfma.io.in.bits.single <= UInt<1>("h00") dfma.io.in.bits.swap23 <= UInt<1>("h00") dfma.io.in.bits.swap12 <= UInt<1>("h00") dfma.io.in.bits.ren3 <= UInt<1>("h00") dfma.io.in.bits.ren2 <= UInt<1>("h00") dfma.io.in.bits.ren1 <= UInt<1>("h00") dfma.io.in.bits.wen <= UInt<1>("h00") dfma.io.in.bits.ldst <= UInt<1>("h00") dfma.io.in.bits.cmd <= UInt<1>("h00") dfma.io.in.valid <= UInt<1>("h00") dfma.clk <= clk dfma.reset <= reset node T_902 = and(req_valid, ex_ctrl.fma) node T_904 = eq(ex_ctrl.single, UInt<1>("h00")) node T_905 = and(T_902, T_904) dfma.io.in.valid <= T_905 dfma.io.in.bits <- req inst fpiu of FPToInt fpiu.io.in.bits.in3 <= UInt<1>("h00") fpiu.io.in.bits.in2 <= UInt<1>("h00") fpiu.io.in.bits.in1 <= UInt<1>("h00") fpiu.io.in.bits.typ <= UInt<1>("h00") fpiu.io.in.bits.rm <= UInt<1>("h00") fpiu.io.in.bits.wflags <= UInt<1>("h00") fpiu.io.in.bits.round <= UInt<1>("h00") fpiu.io.in.bits.sqrt <= UInt<1>("h00") fpiu.io.in.bits.div <= UInt<1>("h00") fpiu.io.in.bits.fma <= UInt<1>("h00") fpiu.io.in.bits.fastpipe <= UInt<1>("h00") fpiu.io.in.bits.toint <= UInt<1>("h00") fpiu.io.in.bits.fromint <= UInt<1>("h00") fpiu.io.in.bits.single <= UInt<1>("h00") fpiu.io.in.bits.swap23 <= UInt<1>("h00") fpiu.io.in.bits.swap12 <= UInt<1>("h00") fpiu.io.in.bits.ren3 <= UInt<1>("h00") fpiu.io.in.bits.ren2 <= UInt<1>("h00") fpiu.io.in.bits.ren1 <= UInt<1>("h00") fpiu.io.in.bits.wen <= UInt<1>("h00") fpiu.io.in.bits.ldst <= UInt<1>("h00") fpiu.io.in.bits.cmd <= UInt<1>("h00") fpiu.io.in.valid <= UInt<1>("h00") fpiu.clk <= clk fpiu.reset <= reset node T_930 = or(ex_ctrl.toint, ex_ctrl.div) node T_931 = or(T_930, ex_ctrl.sqrt) node T_934 = and(ex_ctrl.cmd, UInt<4>("h0d")) node T_935 = eq(UInt<3>("h05"), T_934) node T_936 = or(T_931, T_935) node T_937 = and(req_valid, T_936) fpiu.io.in.valid <= T_937 fpiu.io.in.bits <- req io.store_data <= fpiu.io.out.bits.store io.toint_data <= fpiu.io.out.bits.toint node T_938 = and(fpiu.io.out.valid, mem_cp_valid) node T_939 = and(T_938, mem_ctrl.toint) when T_939 : io.cp_resp.bits.data <= fpiu.io.out.bits.toint io.cp_resp.valid <= UInt<1>("h01") skip inst ifpu of IntToFP ifpu.io.in.bits.in3 <= UInt<1>("h00") ifpu.io.in.bits.in2 <= UInt<1>("h00") ifpu.io.in.bits.in1 <= UInt<1>("h00") ifpu.io.in.bits.typ <= UInt<1>("h00") ifpu.io.in.bits.rm <= UInt<1>("h00") ifpu.io.in.bits.wflags <= UInt<1>("h00") ifpu.io.in.bits.round <= UInt<1>("h00") ifpu.io.in.bits.sqrt <= UInt<1>("h00") ifpu.io.in.bits.div <= UInt<1>("h00") ifpu.io.in.bits.fma <= UInt<1>("h00") ifpu.io.in.bits.fastpipe <= UInt<1>("h00") ifpu.io.in.bits.toint <= UInt<1>("h00") ifpu.io.in.bits.fromint <= UInt<1>("h00") ifpu.io.in.bits.single <= UInt<1>("h00") ifpu.io.in.bits.swap23 <= UInt<1>("h00") ifpu.io.in.bits.swap12 <= UInt<1>("h00") ifpu.io.in.bits.ren3 <= UInt<1>("h00") ifpu.io.in.bits.ren2 <= UInt<1>("h00") ifpu.io.in.bits.ren1 <= UInt<1>("h00") ifpu.io.in.bits.wen <= UInt<1>("h00") ifpu.io.in.bits.ldst <= UInt<1>("h00") ifpu.io.in.bits.cmd <= UInt<1>("h00") ifpu.io.in.valid <= UInt<1>("h00") ifpu.clk <= clk ifpu.reset <= reset node T_965 = and(req_valid, ex_ctrl.fromint) ifpu.io.in.valid <= T_965 ifpu.io.in.bits <- req node T_966 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1) ifpu.io.in.bits.in1 <= T_966 inst fpmu of FPToFP fpmu.io.lt <= UInt<1>("h00") fpmu.io.in.bits.in3 <= UInt<1>("h00") fpmu.io.in.bits.in2 <= UInt<1>("h00") fpmu.io.in.bits.in1 <= UInt<1>("h00") fpmu.io.in.bits.typ <= UInt<1>("h00") fpmu.io.in.bits.rm <= UInt<1>("h00") fpmu.io.in.bits.wflags <= UInt<1>("h00") fpmu.io.in.bits.round <= UInt<1>("h00") fpmu.io.in.bits.sqrt <= UInt<1>("h00") fpmu.io.in.bits.div <= UInt<1>("h00") fpmu.io.in.bits.fma <= UInt<1>("h00") fpmu.io.in.bits.fastpipe <= UInt<1>("h00") fpmu.io.in.bits.toint <= UInt<1>("h00") fpmu.io.in.bits.fromint <= UInt<1>("h00") fpmu.io.in.bits.single <= UInt<1>("h00") fpmu.io.in.bits.swap23 <= UInt<1>("h00") fpmu.io.in.bits.swap12 <= UInt<1>("h00") fpmu.io.in.bits.ren3 <= UInt<1>("h00") fpmu.io.in.bits.ren2 <= UInt<1>("h00") fpmu.io.in.bits.ren1 <= UInt<1>("h00") fpmu.io.in.bits.wen <= UInt<1>("h00") fpmu.io.in.bits.ldst <= UInt<1>("h00") fpmu.io.in.bits.cmd <= UInt<1>("h00") fpmu.io.in.valid <= UInt<1>("h00") fpmu.clk <= clk fpmu.reset <= reset node T_992 = and(req_valid, ex_ctrl.fastpipe) fpmu.io.in.valid <= T_992 fpmu.io.in.bits <- req fpmu.io.lt <= fpiu.io.out.bits.lt reg divSqrt_wen : UInt<1>, clk, UInt<1>("h00"), divSqrt_wen divSqrt_wen <= UInt<1>("h00") wire divSqrt_inReady : UInt<1> divSqrt_inReady <= UInt<1>("h00") reg divSqrt_waddr : UInt, clk, UInt<1>("h00"), divSqrt_waddr wire divSqrt_wdata : UInt divSqrt_wdata <= UInt<1>("h00") wire divSqrt_flags : UInt divSqrt_flags <= UInt<1>("h00") reg divSqrt_in_flight : UInt<1>, clk, reset, UInt<1>("h00") reg divSqrt_killed : UInt<1>, clk, UInt<1>("h00"), divSqrt_killed node T_1011 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) node T_1014 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) node T_1015 = and(mem_ctrl.fma, mem_ctrl.single) node T_1018 = mux(T_1015, UInt<1>("h01"), UInt<1>("h00")) node T_1020 = eq(mem_ctrl.single, UInt<1>("h00")) node T_1021 = and(mem_ctrl.fma, T_1020) node T_1024 = mux(T_1021, UInt<2>("h02"), UInt<1>("h00")) node T_1025 = or(T_1011, T_1014) node T_1026 = or(T_1025, T_1018) node memLatencyMask = or(T_1026, T_1024) reg wen : UInt<2>, clk, reset, UInt<2>("h00") reg winfo : UInt[2], clk, UInt<1>("h00"), winfo node T_1042 = or(mem_ctrl.fma, mem_ctrl.fastpipe) node T_1043 = or(T_1042, mem_ctrl.fromint) node mem_wen = and(mem_reg_valid, T_1043) node T_1047 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) node T_1050 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) node T_1051 = and(ex_ctrl.fma, ex_ctrl.single) node T_1054 = mux(T_1051, UInt<2>("h02"), UInt<1>("h00")) node T_1056 = eq(ex_ctrl.single, UInt<1>("h00")) node T_1057 = and(ex_ctrl.fma, T_1056) node T_1060 = mux(T_1057, UInt<3>("h04"), UInt<1>("h00")) node T_1061 = or(T_1047, T_1050) node T_1062 = or(T_1061, T_1054) node T_1063 = or(T_1062, T_1060) node T_1064 = and(memLatencyMask, T_1063) node T_1066 = neq(T_1064, UInt<1>("h00")) node T_1067 = and(mem_wen, T_1066) node T_1070 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) node T_1073 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) node T_1074 = and(ex_ctrl.fma, ex_ctrl.single) node T_1077 = mux(T_1074, UInt<3>("h04"), UInt<1>("h00")) node T_1079 = eq(ex_ctrl.single, UInt<1>("h00")) node T_1080 = and(ex_ctrl.fma, T_1079) node T_1083 = mux(T_1080, UInt<4>("h08"), UInt<1>("h00")) node T_1084 = or(T_1070, T_1073) node T_1085 = or(T_1084, T_1077) node T_1086 = or(T_1085, T_1083) node T_1087 = and(wen, T_1086) node T_1089 = neq(T_1087, UInt<1>("h00")) node T_1090 = or(T_1067, T_1089) reg write_port_busy : UInt<1>, clk, UInt<1>("h00"), write_port_busy when req_valid : write_port_busy <= T_1090 skip node T_1094 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) node T_1097 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) node T_1098 = and(mem_ctrl.fma, mem_ctrl.single) node T_1101 = mux(T_1098, UInt<2>("h02"), UInt<1>("h00")) node T_1103 = eq(mem_ctrl.single, UInt<1>("h00")) node T_1104 = and(mem_ctrl.fma, T_1103) node T_1107 = mux(T_1104, UInt<2>("h03"), UInt<1>("h00")) node T_1108 = or(T_1094, T_1097) node T_1109 = or(T_1108, T_1101) node T_1110 = or(T_1109, T_1107) node T_1111 = bits(mem_reg_inst, 11, 7) node T_1112 = cat(mem_cp_valid, T_1110) node T_1113 = cat(mem_ctrl.single, T_1111) node mem_winfo = cat(T_1112, T_1113) node T_1115 = bit(wen, 1) when T_1115 : winfo[0] <= winfo[1] skip node T_1116 = shr(wen, 1) wen <= T_1116 when mem_wen : node T_1118 = eq(killm, UInt<1>("h00")) when T_1118 : node T_1119 = shr(wen, 1) node T_1120 = or(T_1119, memLatencyMask) wen <= T_1120 skip node T_1122 = eq(write_port_busy, UInt<1>("h00")) node T_1123 = bit(memLatencyMask, 0) node T_1124 = and(T_1122, T_1123) when T_1124 : winfo[0] <= mem_winfo skip node T_1126 = eq(write_port_busy, UInt<1>("h00")) node T_1127 = bit(memLatencyMask, 1) node T_1128 = and(T_1126, T_1127) when T_1128 : winfo[1] <= mem_winfo skip skip node T_1129 = bits(winfo[0], 4, 0) node waddr = mux(divSqrt_wen, divSqrt_waddr, T_1129) node wsrc = shr(winfo[0], 6) node wcp = bit(winfo[0], 8) wire T_1134 : UInt<65>[4] T_1134[0] <= fpmu.io.out.bits.data T_1134[1] <= ifpu.io.out.bits.data T_1134[2] <= sfma.io.out.bits.data T_1134[3] <= dfma.io.out.bits.data node wdata = mux(divSqrt_wen, divSqrt_wdata, T_1134[wsrc]) wire T_1143 : UInt<5>[4] T_1143[0] <= fpmu.io.out.bits.exc T_1143[1] <= ifpu.io.out.bits.exc T_1143[2] <= sfma.io.out.bits.exc T_1143[3] <= dfma.io.out.bits.exc node T_1151 = eq(wcp, UInt<1>("h00")) node T_1152 = bit(wen, 0) node T_1153 = and(T_1151, T_1152) node T_1154 = or(T_1153, divSqrt_wen) when T_1154 : infer mport T_1155 = regfile[waddr], clk T_1155 <= wdata skip node T_1156 = bit(wen, 0) node T_1157 = and(wcp, T_1156) when T_1157 : io.cp_resp.bits.data <= wdata io.cp_resp.valid <= UInt<1>("h01") skip node T_1160 = eq(ex_reg_valid, UInt<1>("h00")) io.cp_req.ready <= T_1160 node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) reg wb_toint_exc : UInt<5>, clk, UInt<1>("h00"), wb_toint_exc when mem_ctrl.toint : wb_toint_exc <= fpiu.io.out.bits.exc skip node T_1163 = or(wb_toint_valid, divSqrt_wen) node T_1164 = bit(wen, 0) node T_1165 = or(T_1163, T_1164) io.fcsr_flags.valid <= T_1165 node T_1167 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) node T_1169 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) node T_1170 = or(T_1167, T_1169) node T_1171 = bit(wen, 0) node T_1173 = mux(T_1171, T_1143[wsrc], UInt<1>("h00")) node T_1174 = or(T_1170, T_1173) io.fcsr_flags.bits <= T_1174 node T_1175 = or(mem_ctrl.div, mem_ctrl.sqrt) node T_1176 = and(mem_reg_valid, T_1175) node T_1178 = eq(divSqrt_inReady, UInt<1>("h00")) node T_1180 = neq(wen, UInt<1>("h00")) node T_1181 = or(T_1178, T_1180) node units_busy = and(T_1176, T_1181) node T_1183 = and(ex_reg_valid, ex_ctrl.wflags) node T_1184 = and(mem_reg_valid, mem_ctrl.wflags) node T_1185 = or(T_1183, T_1184) node T_1186 = and(wb_reg_valid, wb_ctrl.toint) node T_1187 = or(T_1185, T_1186) node T_1189 = neq(wen, UInt<1>("h00")) node T_1190 = or(T_1187, T_1189) node T_1191 = or(T_1190, divSqrt_in_flight) node T_1193 = eq(T_1191, UInt<1>("h00")) io.fcsr_rdy <= T_1193 node T_1194 = or(units_busy, write_port_busy) node T_1195 = or(T_1194, divSqrt_in_flight) io.nack_mem <= T_1195 io.dec <- fp_decoder.io.sigs node T_1197 = eq(wb_cp_valid, UInt<1>("h00")) node T_1198 = and(wb_reg_valid, T_1197) node T_1200 = or(UInt<1>("h00"), mem_ctrl.div) node T_1201 = or(T_1200, mem_ctrl.sqrt) reg T_1202 : UInt<1>, clk, UInt<1>("h00"), T_1202 T_1202 <= T_1201 node T_1203 = and(T_1198, T_1202) io.sboard_set <= T_1203 node T_1205 = eq(wb_cp_valid, UInt<1>("h00")) node T_1206 = bit(wen, 0) node T_1208 = and(T_1206, UInt<1>("h00")) node T_1209 = or(divSqrt_wen, T_1208) node T_1210 = and(T_1205, T_1209) io.sboard_clr <= T_1210 io.sboard_clra <= waddr node T_1211 = bit(ex_rm, 2) node T_1212 = and(T_1211, ex_ctrl.round) io.illegal_rm <= T_1212 divSqrt_wdata <= UInt<1>("h00") divSqrt_flags <= UInt<1>("h00") reg T_1216 : UInt<1>, clk, UInt<1>("h00"), T_1216 reg T_1218 : UInt, clk, UInt<1>("h00"), T_1218 reg T_1220 : UInt, clk, UInt<1>("h00"), T_1220 reg T_1222 : UInt, clk, UInt<1>("h00"), T_1222 inst T_1223 of DivSqrtRecF64 T_1223.io.roundingMode <= UInt<1>("h00") T_1223.io.b <= UInt<1>("h00") T_1223.io.a <= UInt<1>("h00") T_1223.io.sqrtOp <= UInt<1>("h00") T_1223.io.inValid <= UInt<1>("h00") T_1223.clk <= clk T_1223.reset <= reset node T_1229 = mux(T_1223.io.sqrtOp, T_1223.io.inReady_sqrt, T_1223.io.inReady_div) divSqrt_inReady <= T_1229 node T_1230 = or(T_1223.io.outValid_div, T_1223.io.outValid_sqrt) node T_1231 = or(mem_ctrl.div, mem_ctrl.sqrt) node T_1232 = and(mem_reg_valid, T_1231) node T_1234 = eq(divSqrt_in_flight, UInt<1>("h00")) node T_1235 = and(T_1232, T_1234) T_1223.io.inValid <= T_1235 T_1223.io.sqrtOp <= mem_ctrl.sqrt T_1223.io.a <= fpiu.io.as_double.in1 T_1223.io.b <= fpiu.io.as_double.in2 T_1223.io.roundingMode <= fpiu.io.as_double.rm node T_1236 = and(T_1223.io.inValid, divSqrt_inReady) when T_1236 : divSqrt_in_flight <= UInt<1>("h01") divSqrt_killed <= killm T_1216 <= mem_ctrl.single node T_1238 = bits(mem_reg_inst, 11, 7) divSqrt_waddr <= T_1238 T_1218 <= T_1223.io.roundingMode skip when T_1230 : node T_1240 = eq(divSqrt_killed, UInt<1>("h00")) divSqrt_wen <= T_1240 T_1222 <= T_1223.io.out divSqrt_in_flight <= UInt<1>("h00") T_1220 <= T_1223.io.exceptionFlags skip inst T_1242 of RecFNToRecFN_121 T_1242.io.roundingMode <= UInt<1>("h00") T_1242.io.in <= UInt<1>("h00") T_1242.clk <= clk T_1242.reset <= reset T_1242.io.in <= T_1222 T_1242.io.roundingMode <= ex_rm node T_1245 = mux(T_1216, T_1242.io.out, T_1222) divSqrt_wdata <= T_1245 node T_1247 = mux(T_1216, T_1242.io.exceptionFlags, UInt<1>("h00")) node T_1248 = or(T_1220, T_1247) divSqrt_flags <= T_1248 module RocketTile : input clk : Clock input reset : UInt<1> output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} io.dma.resp.ready <= UInt<1>("h00") io.dma.req.bits.size <= UInt<1>("h00") io.dma.req.bits.length <= UInt<1>("h00") io.dma.req.bits.dest <= UInt<1>("h00") io.dma.req.bits.source <= UInt<1>("h00") io.dma.req.bits.cmd <= UInt<1>("h00") io.dma.req.bits.client_xact_id <= UInt<1>("h00") io.dma.req.valid <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.csr.resp.bits <= UInt<1>("h00") io.host.csr.resp.valid <= UInt<1>("h00") io.host.csr.req.ready <= UInt<1>("h00") io.uncached[0].grant.ready <= UInt<1>("h00") io.uncached[0].acquire.bits.data <= UInt<1>("h00") io.uncached[0].acquire.bits.union <= UInt<1>("h00") io.uncached[0].acquire.bits.a_type <= UInt<1>("h00") io.uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") io.uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") io.uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") io.uncached[0].acquire.bits.addr_block <= UInt<1>("h00") io.uncached[0].acquire.valid <= UInt<1>("h00") io.cached[0].release.bits.data <= UInt<1>("h00") io.cached[0].release.bits.r_type <= UInt<1>("h00") io.cached[0].release.bits.voluntary <= UInt<1>("h00") io.cached[0].release.bits.client_xact_id <= UInt<1>("h00") io.cached[0].release.bits.addr_block <= UInt<1>("h00") io.cached[0].release.bits.addr_beat <= UInt<1>("h00") io.cached[0].release.valid <= UInt<1>("h00") io.cached[0].probe.ready <= UInt<1>("h00") io.cached[0].grant.ready <= UInt<1>("h00") io.cached[0].acquire.bits.data <= UInt<1>("h00") io.cached[0].acquire.bits.union <= UInt<1>("h00") io.cached[0].acquire.bits.a_type <= UInt<1>("h00") io.cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") io.cached[0].acquire.bits.addr_beat <= UInt<1>("h00") io.cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") io.cached[0].acquire.bits.addr_block <= UInt<1>("h00") io.cached[0].acquire.valid <= UInt<1>("h00") inst core of Rocket core.io.rocc.dma.resp.ready <= UInt<1>("h00") core.io.rocc.dma.req.bits.size <= UInt<1>("h00") core.io.rocc.dma.req.bits.length <= UInt<1>("h00") core.io.rocc.dma.req.bits.dest <= UInt<1>("h00") core.io.rocc.dma.req.bits.source <= UInt<1>("h00") core.io.rocc.dma.req.bits.cmd <= UInt<1>("h00") core.io.rocc.dma.req.bits.client_xact_id <= UInt<1>("h00") core.io.rocc.dma.req.valid <= UInt<1>("h00") core.io.rocc.fpu_resp.ready <= UInt<1>("h00") core.io.rocc.fpu_req.bits.in3 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.in2 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.in1 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.typ <= UInt<1>("h00") core.io.rocc.fpu_req.bits.rm <= UInt<1>("h00") core.io.rocc.fpu_req.bits.wflags <= UInt<1>("h00") core.io.rocc.fpu_req.bits.round <= UInt<1>("h00") core.io.rocc.fpu_req.bits.sqrt <= UInt<1>("h00") core.io.rocc.fpu_req.bits.div <= UInt<1>("h00") core.io.rocc.fpu_req.bits.fma <= UInt<1>("h00") core.io.rocc.fpu_req.bits.fastpipe <= UInt<1>("h00") core.io.rocc.fpu_req.bits.toint <= UInt<1>("h00") core.io.rocc.fpu_req.bits.fromint <= UInt<1>("h00") core.io.rocc.fpu_req.bits.single <= UInt<1>("h00") core.io.rocc.fpu_req.bits.swap23 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.swap12 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.ren3 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.ren2 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.ren1 <= UInt<1>("h00") core.io.rocc.fpu_req.bits.wen <= UInt<1>("h00") core.io.rocc.fpu_req.bits.ldst <= UInt<1>("h00") core.io.rocc.fpu_req.bits.cmd <= UInt<1>("h00") core.io.rocc.fpu_req.valid <= UInt<1>("h00") core.io.rocc.pptw.req.bits.fetch <= UInt<1>("h00") core.io.rocc.pptw.req.bits.store <= UInt<1>("h00") core.io.rocc.pptw.req.bits.prv <= UInt<1>("h00") core.io.rocc.pptw.req.bits.addr <= UInt<1>("h00") core.io.rocc.pptw.req.valid <= UInt<1>("h00") core.io.rocc.dptw.req.bits.fetch <= UInt<1>("h00") core.io.rocc.dptw.req.bits.store <= UInt<1>("h00") core.io.rocc.dptw.req.bits.prv <= UInt<1>("h00") core.io.rocc.dptw.req.bits.addr <= UInt<1>("h00") core.io.rocc.dptw.req.valid <= UInt<1>("h00") core.io.rocc.iptw.req.bits.fetch <= UInt<1>("h00") core.io.rocc.iptw.req.bits.store <= UInt<1>("h00") core.io.rocc.iptw.req.bits.prv <= UInt<1>("h00") core.io.rocc.iptw.req.bits.addr <= UInt<1>("h00") core.io.rocc.iptw.req.valid <= UInt<1>("h00") core.io.rocc.autl.grant.ready <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.data <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.union <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.a_type <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.is_builtin_type <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.addr_beat <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.client_xact_id <= UInt<1>("h00") core.io.rocc.autl.acquire.bits.addr_block <= UInt<1>("h00") core.io.rocc.autl.acquire.valid <= UInt<1>("h00") core.io.rocc.interrupt <= UInt<1>("h00") core.io.rocc.busy <= UInt<1>("h00") core.io.rocc.mem.invalidate_lr <= UInt<1>("h00") core.io.rocc.mem.req.bits.data <= UInt<1>("h00") core.io.rocc.mem.req.bits.phys <= UInt<1>("h00") core.io.rocc.mem.req.bits.kill <= UInt<1>("h00") core.io.rocc.mem.req.bits.typ <= UInt<1>("h00") core.io.rocc.mem.req.bits.cmd <= UInt<1>("h00") core.io.rocc.mem.req.bits.tag <= UInt<1>("h00") core.io.rocc.mem.req.bits.addr <= UInt<1>("h00") core.io.rocc.mem.req.valid <= UInt<1>("h00") core.io.rocc.resp.bits.data <= UInt<1>("h00") core.io.rocc.resp.bits.rd <= UInt<1>("h00") core.io.rocc.resp.valid <= UInt<1>("h00") core.io.rocc.cmd.ready <= UInt<1>("h00") core.io.fpu.cp_resp.bits.exc <= UInt<1>("h00") core.io.fpu.cp_resp.bits.data <= UInt<1>("h00") core.io.fpu.cp_resp.valid <= UInt<1>("h00") core.io.fpu.cp_req.ready <= UInt<1>("h00") core.io.fpu.sboard_clra <= UInt<1>("h00") core.io.fpu.sboard_clr <= UInt<1>("h00") core.io.fpu.sboard_set <= UInt<1>("h00") core.io.fpu.dec.wflags <= UInt<1>("h00") core.io.fpu.dec.round <= UInt<1>("h00") core.io.fpu.dec.sqrt <= UInt<1>("h00") core.io.fpu.dec.div <= UInt<1>("h00") core.io.fpu.dec.fma <= UInt<1>("h00") core.io.fpu.dec.fastpipe <= UInt<1>("h00") core.io.fpu.dec.toint <= UInt<1>("h00") core.io.fpu.dec.fromint <= UInt<1>("h00") core.io.fpu.dec.single <= UInt<1>("h00") core.io.fpu.dec.swap23 <= UInt<1>("h00") core.io.fpu.dec.swap12 <= UInt<1>("h00") core.io.fpu.dec.ren3 <= UInt<1>("h00") core.io.fpu.dec.ren2 <= UInt<1>("h00") core.io.fpu.dec.ren1 <= UInt<1>("h00") core.io.fpu.dec.wen <= UInt<1>("h00") core.io.fpu.dec.ldst <= UInt<1>("h00") core.io.fpu.dec.cmd <= UInt<1>("h00") core.io.fpu.illegal_rm <= UInt<1>("h00") core.io.fpu.nack_mem <= UInt<1>("h00") core.io.fpu.fcsr_rdy <= UInt<1>("h00") core.io.fpu.toint_data <= UInt<1>("h00") core.io.fpu.store_data <= UInt<1>("h00") core.io.fpu.fcsr_flags.bits <= UInt<1>("h00") core.io.fpu.fcsr_flags.valid <= UInt<1>("h00") core.io.dmem.ordered <= UInt<1>("h00") core.io.dmem.xcpt.pf.st <= UInt<1>("h00") core.io.dmem.xcpt.pf.ld <= UInt<1>("h00") core.io.dmem.xcpt.ma.st <= UInt<1>("h00") core.io.dmem.xcpt.ma.ld <= UInt<1>("h00") core.io.dmem.replay_next.bits <= UInt<1>("h00") core.io.dmem.replay_next.valid <= UInt<1>("h00") core.io.dmem.resp.bits.store_data <= UInt<1>("h00") core.io.dmem.resp.bits.data_word_bypass <= UInt<1>("h00") core.io.dmem.resp.bits.has_data <= UInt<1>("h00") core.io.dmem.resp.bits.replay <= UInt<1>("h00") core.io.dmem.resp.bits.nack <= UInt<1>("h00") core.io.dmem.resp.bits.data <= UInt<1>("h00") core.io.dmem.resp.bits.typ <= UInt<1>("h00") core.io.dmem.resp.bits.cmd <= UInt<1>("h00") core.io.dmem.resp.bits.tag <= UInt<1>("h00") core.io.dmem.resp.bits.addr <= UInt<1>("h00") core.io.dmem.resp.valid <= UInt<1>("h00") core.io.dmem.req.ready <= UInt<1>("h00") core.io.imem.npc <= UInt<1>("h00") core.io.imem.btb_resp.bits.bht.value <= UInt<1>("h00") core.io.imem.btb_resp.bits.bht.history <= UInt<1>("h00") core.io.imem.btb_resp.bits.entry <= UInt<1>("h00") core.io.imem.btb_resp.bits.target <= UInt<1>("h00") core.io.imem.btb_resp.bits.bridx <= UInt<1>("h00") core.io.imem.btb_resp.bits.mask <= UInt<1>("h00") core.io.imem.btb_resp.bits.taken <= UInt<1>("h00") core.io.imem.btb_resp.valid <= UInt<1>("h00") core.io.imem.resp.bits.xcpt_if <= UInt<1>("h00") core.io.imem.resp.bits.mask <= UInt<1>("h00") core.io.imem.resp.bits.data[0] <= UInt<1>("h00") core.io.imem.resp.bits.pc <= UInt<1>("h00") core.io.imem.resp.valid <= UInt<1>("h00") core.io.host.csr.resp.ready <= UInt<1>("h00") core.io.host.csr.req.bits.data <= UInt<1>("h00") core.io.host.csr.req.bits.addr <= UInt<1>("h00") core.io.host.csr.req.bits.rw <= UInt<1>("h00") core.io.host.csr.req.valid <= UInt<1>("h00") core.io.host.id <= UInt<1>("h00") core.io.host.reset <= UInt<1>("h00") core.clk <= clk core.reset <= reset inst icache of Frontend icache.io.mem.grant.bits.data <= UInt<1>("h00") icache.io.mem.grant.bits.g_type <= UInt<1>("h00") icache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") icache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") icache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") icache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") icache.io.mem.grant.valid <= UInt<1>("h00") icache.io.mem.acquire.ready <= UInt<1>("h00") icache.io.ptw.invalidate <= UInt<1>("h00") icache.io.ptw.status.ie <= UInt<1>("h00") icache.io.ptw.status.prv <= UInt<1>("h00") icache.io.ptw.status.ie1 <= UInt<1>("h00") icache.io.ptw.status.prv1 <= UInt<1>("h00") icache.io.ptw.status.ie2 <= UInt<1>("h00") icache.io.ptw.status.prv2 <= UInt<1>("h00") icache.io.ptw.status.ie3 <= UInt<1>("h00") icache.io.ptw.status.prv3 <= UInt<1>("h00") icache.io.ptw.status.fs <= UInt<1>("h00") icache.io.ptw.status.xs <= UInt<1>("h00") icache.io.ptw.status.mprv <= UInt<1>("h00") icache.io.ptw.status.vm <= UInt<1>("h00") icache.io.ptw.status.zero1 <= UInt<1>("h00") icache.io.ptw.status.sd_rv32 <= UInt<1>("h00") icache.io.ptw.status.zero2 <= UInt<1>("h00") icache.io.ptw.status.sd <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.v <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.r <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.d <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") icache.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") icache.io.ptw.resp.bits.error <= UInt<1>("h00") icache.io.ptw.resp.valid <= UInt<1>("h00") icache.io.ptw.req.ready <= UInt<1>("h00") icache.io.cpu.invalidate <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.target <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") icache.io.cpu.ras_update.bits.prediction.valid <= UInt<1>("h00") icache.io.cpu.ras_update.bits.returnAddr <= UInt<1>("h00") icache.io.cpu.ras_update.bits.isReturn <= UInt<1>("h00") icache.io.cpu.ras_update.bits.isCall <= UInt<1>("h00") icache.io.cpu.ras_update.valid <= UInt<1>("h00") icache.io.cpu.bht_update.bits.mispredict <= UInt<1>("h00") icache.io.cpu.bht_update.bits.taken <= UInt<1>("h00") icache.io.cpu.bht_update.bits.pc <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.target <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") icache.io.cpu.bht_update.bits.prediction.valid <= UInt<1>("h00") icache.io.cpu.bht_update.valid <= UInt<1>("h00") icache.io.cpu.btb_update.bits.br_pc <= UInt<1>("h00") icache.io.cpu.btb_update.bits.isReturn <= UInt<1>("h00") icache.io.cpu.btb_update.bits.isJump <= UInt<1>("h00") icache.io.cpu.btb_update.bits.taken <= UInt<1>("h00") icache.io.cpu.btb_update.bits.target <= UInt<1>("h00") icache.io.cpu.btb_update.bits.pc <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.target <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") icache.io.cpu.btb_update.bits.prediction.valid <= UInt<1>("h00") icache.io.cpu.btb_update.valid <= UInt<1>("h00") icache.io.cpu.resp.ready <= UInt<1>("h00") icache.io.cpu.req.bits.pc <= UInt<1>("h00") icache.io.cpu.req.valid <= UInt<1>("h00") icache.clk <= clk icache.reset <= reset inst dcache of HellaCache dcache.io.mem.release.ready <= UInt<1>("h00") dcache.io.mem.probe.bits.p_type <= UInt<1>("h00") dcache.io.mem.probe.bits.addr_block <= UInt<1>("h00") dcache.io.mem.probe.valid <= UInt<1>("h00") dcache.io.mem.grant.bits.data <= UInt<1>("h00") dcache.io.mem.grant.bits.g_type <= UInt<1>("h00") dcache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") dcache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") dcache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") dcache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") dcache.io.mem.grant.valid <= UInt<1>("h00") dcache.io.mem.acquire.ready <= UInt<1>("h00") dcache.io.ptw.invalidate <= UInt<1>("h00") dcache.io.ptw.status.ie <= UInt<1>("h00") dcache.io.ptw.status.prv <= UInt<1>("h00") dcache.io.ptw.status.ie1 <= UInt<1>("h00") dcache.io.ptw.status.prv1 <= UInt<1>("h00") dcache.io.ptw.status.ie2 <= UInt<1>("h00") dcache.io.ptw.status.prv2 <= UInt<1>("h00") dcache.io.ptw.status.ie3 <= UInt<1>("h00") dcache.io.ptw.status.prv3 <= UInt<1>("h00") dcache.io.ptw.status.fs <= UInt<1>("h00") dcache.io.ptw.status.xs <= UInt<1>("h00") dcache.io.ptw.status.mprv <= UInt<1>("h00") dcache.io.ptw.status.vm <= UInt<1>("h00") dcache.io.ptw.status.zero1 <= UInt<1>("h00") dcache.io.ptw.status.sd_rv32 <= UInt<1>("h00") dcache.io.ptw.status.zero2 <= UInt<1>("h00") dcache.io.ptw.status.sd <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.v <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.r <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.d <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") dcache.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") dcache.io.ptw.resp.bits.error <= UInt<1>("h00") dcache.io.ptw.resp.valid <= UInt<1>("h00") dcache.io.ptw.req.ready <= UInt<1>("h00") dcache.io.cpu.invalidate_lr <= UInt<1>("h00") dcache.io.cpu.req.bits.data <= UInt<1>("h00") dcache.io.cpu.req.bits.phys <= UInt<1>("h00") dcache.io.cpu.req.bits.kill <= UInt<1>("h00") dcache.io.cpu.req.bits.typ <= UInt<1>("h00") dcache.io.cpu.req.bits.cmd <= UInt<1>("h00") dcache.io.cpu.req.bits.tag <= UInt<1>("h00") dcache.io.cpu.req.bits.addr <= UInt<1>("h00") dcache.io.cpu.req.valid <= UInt<1>("h00") dcache.clk <= clk dcache.reset <= reset inst ptw of PTW ptw.io.dpath.status.ie <= UInt<1>("h00") ptw.io.dpath.status.prv <= UInt<1>("h00") ptw.io.dpath.status.ie1 <= UInt<1>("h00") ptw.io.dpath.status.prv1 <= UInt<1>("h00") ptw.io.dpath.status.ie2 <= UInt<1>("h00") ptw.io.dpath.status.prv2 <= UInt<1>("h00") ptw.io.dpath.status.ie3 <= UInt<1>("h00") ptw.io.dpath.status.prv3 <= UInt<1>("h00") ptw.io.dpath.status.fs <= UInt<1>("h00") ptw.io.dpath.status.xs <= UInt<1>("h00") ptw.io.dpath.status.mprv <= UInt<1>("h00") ptw.io.dpath.status.vm <= UInt<1>("h00") ptw.io.dpath.status.zero1 <= UInt<1>("h00") ptw.io.dpath.status.sd_rv32 <= UInt<1>("h00") ptw.io.dpath.status.zero2 <= UInt<1>("h00") ptw.io.dpath.status.sd <= UInt<1>("h00") ptw.io.dpath.invalidate <= UInt<1>("h00") ptw.io.dpath.ptbr <= UInt<1>("h00") ptw.io.mem.ordered <= UInt<1>("h00") ptw.io.mem.xcpt.pf.st <= UInt<1>("h00") ptw.io.mem.xcpt.pf.ld <= UInt<1>("h00") ptw.io.mem.xcpt.ma.st <= UInt<1>("h00") ptw.io.mem.xcpt.ma.ld <= UInt<1>("h00") ptw.io.mem.replay_next.bits <= UInt<1>("h00") ptw.io.mem.replay_next.valid <= UInt<1>("h00") ptw.io.mem.resp.bits.store_data <= UInt<1>("h00") ptw.io.mem.resp.bits.data_word_bypass <= UInt<1>("h00") ptw.io.mem.resp.bits.has_data <= UInt<1>("h00") ptw.io.mem.resp.bits.replay <= UInt<1>("h00") ptw.io.mem.resp.bits.nack <= UInt<1>("h00") ptw.io.mem.resp.bits.data <= UInt<1>("h00") ptw.io.mem.resp.bits.typ <= UInt<1>("h00") ptw.io.mem.resp.bits.cmd <= UInt<1>("h00") ptw.io.mem.resp.bits.tag <= UInt<1>("h00") ptw.io.mem.resp.bits.addr <= UInt<1>("h00") ptw.io.mem.resp.valid <= UInt<1>("h00") ptw.io.mem.req.ready <= UInt<1>("h00") ptw.io.requestor[0].req.bits.fetch <= UInt<1>("h00") ptw.io.requestor[0].req.bits.store <= UInt<1>("h00") ptw.io.requestor[0].req.bits.prv <= UInt<1>("h00") ptw.io.requestor[0].req.bits.addr <= UInt<1>("h00") ptw.io.requestor[0].req.valid <= UInt<1>("h00") ptw.io.requestor[1].req.bits.fetch <= UInt<1>("h00") ptw.io.requestor[1].req.bits.store <= UInt<1>("h00") ptw.io.requestor[1].req.bits.prv <= UInt<1>("h00") ptw.io.requestor[1].req.bits.addr <= UInt<1>("h00") ptw.io.requestor[1].req.valid <= UInt<1>("h00") ptw.clk <= clk ptw.reset <= reset dcache.io.cpu.invalidate_lr <= core.io.dmem.invalidate_lr inst dcArb of HellaCacheArbiter dcArb.io.mem.ordered <= UInt<1>("h00") dcArb.io.mem.xcpt.pf.st <= UInt<1>("h00") dcArb.io.mem.xcpt.pf.ld <= UInt<1>("h00") dcArb.io.mem.xcpt.ma.st <= UInt<1>("h00") dcArb.io.mem.xcpt.ma.ld <= UInt<1>("h00") dcArb.io.mem.replay_next.bits <= UInt<1>("h00") dcArb.io.mem.replay_next.valid <= UInt<1>("h00") dcArb.io.mem.resp.bits.store_data <= UInt<1>("h00") dcArb.io.mem.resp.bits.data_word_bypass <= UInt<1>("h00") dcArb.io.mem.resp.bits.has_data <= UInt<1>("h00") dcArb.io.mem.resp.bits.replay <= UInt<1>("h00") dcArb.io.mem.resp.bits.nack <= UInt<1>("h00") dcArb.io.mem.resp.bits.data <= UInt<1>("h00") dcArb.io.mem.resp.bits.typ <= UInt<1>("h00") dcArb.io.mem.resp.bits.cmd <= UInt<1>("h00") dcArb.io.mem.resp.bits.tag <= UInt<1>("h00") dcArb.io.mem.resp.bits.addr <= UInt<1>("h00") dcArb.io.mem.resp.valid <= UInt<1>("h00") dcArb.io.mem.req.ready <= UInt<1>("h00") dcArb.io.requestor[0].invalidate_lr <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.data <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.phys <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.kill <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.typ <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.cmd <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.tag <= UInt<1>("h00") dcArb.io.requestor[0].req.bits.addr <= UInt<1>("h00") dcArb.io.requestor[0].req.valid <= UInt<1>("h00") dcArb.io.requestor[1].invalidate_lr <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.data <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.phys <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.kill <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.typ <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.cmd <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.tag <= UInt<1>("h00") dcArb.io.requestor[1].req.bits.addr <= UInt<1>("h00") dcArb.io.requestor[1].req.valid <= UInt<1>("h00") dcArb.clk <= clk dcArb.reset <= reset dcArb.io.requestor[0] <- ptw.io.mem dcArb.io.requestor[1] <- core.io.dmem dcache.io.cpu <- dcArb.io.mem ptw.io.requestor[0] <- icache.io.ptw ptw.io.requestor[1] <- dcache.io.ptw io.host <- core.io.host icache.io.cpu <- core.io.imem core.io.ptw <- ptw.io.dpath inst T_3634 of FPU T_3634.io.cp_resp.ready <= UInt<1>("h00") T_3634.io.cp_req.bits.in3 <= UInt<1>("h00") T_3634.io.cp_req.bits.in2 <= UInt<1>("h00") T_3634.io.cp_req.bits.in1 <= UInt<1>("h00") T_3634.io.cp_req.bits.typ <= UInt<1>("h00") T_3634.io.cp_req.bits.rm <= UInt<1>("h00") T_3634.io.cp_req.bits.wflags <= UInt<1>("h00") T_3634.io.cp_req.bits.round <= UInt<1>("h00") T_3634.io.cp_req.bits.sqrt <= UInt<1>("h00") T_3634.io.cp_req.bits.div <= UInt<1>("h00") T_3634.io.cp_req.bits.fma <= UInt<1>("h00") T_3634.io.cp_req.bits.fastpipe <= UInt<1>("h00") T_3634.io.cp_req.bits.toint <= UInt<1>("h00") T_3634.io.cp_req.bits.fromint <= UInt<1>("h00") T_3634.io.cp_req.bits.single <= UInt<1>("h00") T_3634.io.cp_req.bits.swap23 <= UInt<1>("h00") T_3634.io.cp_req.bits.swap12 <= UInt<1>("h00") T_3634.io.cp_req.bits.ren3 <= UInt<1>("h00") T_3634.io.cp_req.bits.ren2 <= UInt<1>("h00") T_3634.io.cp_req.bits.ren1 <= UInt<1>("h00") T_3634.io.cp_req.bits.wen <= UInt<1>("h00") T_3634.io.cp_req.bits.ldst <= UInt<1>("h00") T_3634.io.cp_req.bits.cmd <= UInt<1>("h00") T_3634.io.cp_req.valid <= UInt<1>("h00") T_3634.io.killm <= UInt<1>("h00") T_3634.io.killx <= UInt<1>("h00") T_3634.io.valid <= UInt<1>("h00") T_3634.io.dmem_resp_data <= UInt<1>("h00") T_3634.io.dmem_resp_tag <= UInt<1>("h00") T_3634.io.dmem_resp_type <= UInt<1>("h00") T_3634.io.dmem_resp_val <= UInt<1>("h00") T_3634.io.fcsr_rm <= UInt<1>("h00") T_3634.io.fromint_data <= UInt<1>("h00") T_3634.io.inst <= UInt<1>("h00") T_3634.clk <= clk T_3634.reset <= reset core.io.fpu <- T_3634.io io.cached[0] <- dcache.io.mem io.uncached[0] <- icache.io.mem T_3634.io.cp_req.valid <= UInt<1>("h00") T_3634.io.cp_resp.ready <= UInt<1>("h00") io.dma.req.valid <= UInt<1>("h00") io.dma.resp.ready <= UInt<1>("h00") module Queue_124 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits.data <= UInt<1>("h00") io.deq.bits.addr <= UInt<1>("h00") io.deq.bits.rw <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2] reg T_53 : UInt<1>, clk, reset, UInt<1>("h00") reg T_55 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_66 = and(io.enq.ready, io.enq.valid) node T_68 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_66, T_68) node T_70 = and(io.deq.ready, io.deq.valid) node T_72 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_70, T_72) when do_enq : infer mport T_74 = ram[T_53], clk T_74 <- io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) node T_84 = addw(T_53, UInt<1>("h01")) node T_85 = mux(T_81, UInt<1>("h00"), T_84) T_53 <= T_85 skip when do_deq : node T_87 = eq(T_55, UInt<1>("h01")) node T_89 = and(UInt<1>("h00"), T_87) node T_92 = addw(T_55, UInt<1>("h01")) node T_93 = mux(T_89, UInt<1>("h00"), T_92) T_55 <= T_93 skip node T_94 = neq(do_enq, do_deq) when T_94 : maybe_full <= do_enq skip node T_96 = eq(empty, UInt<1>("h00")) node T_98 = and(UInt<1>("h00"), io.enq.valid) node T_99 = or(T_96, T_98) io.deq.valid <= T_99 node T_101 = eq(full, UInt<1>("h00")) node T_103 = and(UInt<1>("h00"), io.deq.ready) node T_104 = or(T_101, T_103) io.enq.ready <= T_104 infer mport T_105 = ram[T_55], clk wire T_113 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>} T_113 <- T_105 when maybe_flow : T_113 <- io.enq.bits skip io.deq.bits <- T_113 node ptr_diff = subw(T_53, T_55) node T_118 = and(maybe_full, ptr_match) node T_119 = cat(T_118, ptr_diff) io.count <= T_119 module Queue_125 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>} io.count <= UInt<1>("h00") io.deq.bits <= UInt<1>("h00") io.deq.valid <= UInt<1>("h00") io.enq.ready <= UInt<1>("h00") cmem ram : UInt<64>[2] reg T_26 : UInt<1>, clk, reset, UInt<1>("h00") reg T_28 : UInt<1>, clk, reset, UInt<1>("h00") reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) node full = and(ptr_match, maybe_full) node maybe_flow = and(UInt<1>("h00"), empty) node do_flow = and(maybe_flow, io.deq.ready) node T_39 = and(io.enq.ready, io.enq.valid) node T_41 = eq(do_flow, UInt<1>("h00")) node do_enq = and(T_39, T_41) node T_43 = and(io.deq.ready, io.deq.valid) node T_45 = eq(do_flow, UInt<1>("h00")) node do_deq = and(T_43, T_45) when do_enq : infer mport T_47 = ram[T_26], clk T_47 <= io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) node T_54 = addw(T_26, UInt<1>("h01")) node T_55 = mux(T_51, UInt<1>("h00"), T_54) T_26 <= T_55 skip when do_deq : node T_57 = eq(T_28, UInt<1>("h01")) node T_59 = and(UInt<1>("h00"), T_57) node T_62 = addw(T_28, UInt<1>("h01")) node T_63 = mux(T_59, UInt<1>("h00"), T_62) T_28 <= T_63 skip node T_64 = neq(do_enq, do_deq) when T_64 : maybe_full <= do_enq skip node T_66 = eq(empty, UInt<1>("h00")) node T_68 = and(UInt<1>("h00"), io.enq.valid) node T_69 = or(T_66, T_68) io.deq.valid <= T_69 node T_71 = eq(full, UInt<1>("h00")) node T_73 = and(UInt<1>("h00"), io.deq.ready) node T_74 = or(T_71, T_73) io.enq.ready <= T_74 infer mport T_75 = ram[T_28], clk node T_76 = mux(maybe_flow, io.enq.bits, T_75) io.deq.bits <= T_76 node ptr_diff = subw(T_26, T_28) node T_78 = and(maybe_full, ptr_match) node T_79 = cat(T_78, ptr_diff) io.count <= T_79 module Top : input clk : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1]} io.mem[0].r.ready <= UInt<1>("h00") io.mem[0].ar.bits.user <= UInt<1>("h00") io.mem[0].ar.bits.id <= UInt<1>("h00") io.mem[0].ar.bits.region <= UInt<1>("h00") io.mem[0].ar.bits.qos <= UInt<1>("h00") io.mem[0].ar.bits.prot <= UInt<1>("h00") io.mem[0].ar.bits.cache <= UInt<1>("h00") io.mem[0].ar.bits.lock <= UInt<1>("h00") io.mem[0].ar.bits.burst <= UInt<1>("h00") io.mem[0].ar.bits.size <= UInt<1>("h00") io.mem[0].ar.bits.len <= UInt<1>("h00") io.mem[0].ar.bits.addr <= UInt<1>("h00") io.mem[0].ar.valid <= UInt<1>("h00") io.mem[0].b.ready <= UInt<1>("h00") io.mem[0].w.bits.user <= UInt<1>("h00") io.mem[0].w.bits.strb <= UInt<1>("h00") io.mem[0].w.bits.last <= UInt<1>("h00") io.mem[0].w.bits.data <= UInt<1>("h00") io.mem[0].w.valid <= UInt<1>("h00") io.mem[0].aw.bits.user <= UInt<1>("h00") io.mem[0].aw.bits.id <= UInt<1>("h00") io.mem[0].aw.bits.region <= UInt<1>("h00") io.mem[0].aw.bits.qos <= UInt<1>("h00") io.mem[0].aw.bits.prot <= UInt<1>("h00") io.mem[0].aw.bits.cache <= UInt<1>("h00") io.mem[0].aw.bits.lock <= UInt<1>("h00") io.mem[0].aw.bits.burst <= UInt<1>("h00") io.mem[0].aw.bits.size <= UInt<1>("h00") io.mem[0].aw.bits.len <= UInt<1>("h00") io.mem[0].aw.bits.addr <= UInt<1>("h00") io.mem[0].aw.valid <= UInt<1>("h00") io.mem_backup_ctrl.out_valid <= UInt<1>("h00") io.host.debug_stats_csr <= UInt<1>("h00") io.host.out.bits <= UInt<1>("h00") io.host.out.valid <= UInt<1>("h00") io.host.in.ready <= UInt<1>("h00") io.host.clk_edge <= UInt<1>("h00") io.host.clk <= UInt<1>("h00") inst uncore of Uncore uncore.io.dma[0].resp.ready <= UInt<1>("h00") uncore.io.dma[0].req.bits.size <= UInt<1>("h00") uncore.io.dma[0].req.bits.length <= UInt<1>("h00") uncore.io.dma[0].req.bits.dest <= UInt<1>("h00") uncore.io.dma[0].req.bits.source <= UInt<1>("h00") uncore.io.dma[0].req.bits.cmd <= UInt<1>("h00") uncore.io.dma[0].req.bits.client_xact_id <= UInt<1>("h00") uncore.io.dma[0].req.valid <= UInt<1>("h00") uncore.io.mmio.r.bits.user <= UInt<1>("h00") uncore.io.mmio.r.bits.id <= UInt<1>("h00") uncore.io.mmio.r.bits.last <= UInt<1>("h00") uncore.io.mmio.r.bits.data <= UInt<1>("h00") uncore.io.mmio.r.bits.resp <= UInt<1>("h00") uncore.io.mmio.r.valid <= UInt<1>("h00") uncore.io.mmio.ar.ready <= UInt<1>("h00") uncore.io.mmio.b.bits.user <= UInt<1>("h00") uncore.io.mmio.b.bits.id <= UInt<1>("h00") uncore.io.mmio.b.bits.resp <= UInt<1>("h00") uncore.io.mmio.b.valid <= UInt<1>("h00") uncore.io.mmio.w.ready <= UInt<1>("h00") uncore.io.mmio.aw.ready <= UInt<1>("h00") uncore.io.mem_backup_ctrl.out_ready <= UInt<1>("h00") uncore.io.mem_backup_ctrl.in_valid <= UInt<1>("h00") uncore.io.mem_backup_ctrl.en <= UInt<1>("h00") uncore.io.htif[0].debug_stats_csr <= UInt<1>("h00") uncore.io.htif[0].csr.resp.bits <= UInt<1>("h00") uncore.io.htif[0].csr.resp.valid <= UInt<1>("h00") uncore.io.htif[0].csr.req.ready <= UInt<1>("h00") uncore.io.tiles_uncached[0].grant.ready <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.data <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.union <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.a_type <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.bits.addr_block <= UInt<1>("h00") uncore.io.tiles_uncached[0].acquire.valid <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.data <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.r_type <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.voluntary <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.client_xact_id <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.addr_block <= UInt<1>("h00") uncore.io.tiles_cached[0].release.bits.addr_beat <= UInt<1>("h00") uncore.io.tiles_cached[0].release.valid <= UInt<1>("h00") uncore.io.tiles_cached[0].probe.ready <= UInt<1>("h00") uncore.io.tiles_cached[0].grant.ready <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.data <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.union <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.a_type <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.addr_beat <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.bits.addr_block <= UInt<1>("h00") uncore.io.tiles_cached[0].acquire.valid <= UInt<1>("h00") uncore.io.mem[0].r.bits.user <= UInt<1>("h00") uncore.io.mem[0].r.bits.id <= UInt<1>("h00") uncore.io.mem[0].r.bits.last <= UInt<1>("h00") uncore.io.mem[0].r.bits.data <= UInt<1>("h00") uncore.io.mem[0].r.bits.resp <= UInt<1>("h00") uncore.io.mem[0].r.valid <= UInt<1>("h00") uncore.io.mem[0].ar.ready <= UInt<1>("h00") uncore.io.mem[0].b.bits.user <= UInt<1>("h00") uncore.io.mem[0].b.bits.id <= UInt<1>("h00") uncore.io.mem[0].b.bits.resp <= UInt<1>("h00") uncore.io.mem[0].b.valid <= UInt<1>("h00") uncore.io.mem[0].w.ready <= UInt<1>("h00") uncore.io.mem[0].aw.ready <= UInt<1>("h00") uncore.io.host.out.ready <= UInt<1>("h00") uncore.io.host.in.bits <= UInt<1>("h00") uncore.io.host.in.valid <= UInt<1>("h00") uncore.clk <= clk uncore.reset <= reset inst T_739 of RocketTile T_739.io.dma.resp.bits.status <= UInt<1>("h00") T_739.io.dma.resp.bits.client_xact_id <= UInt<1>("h00") T_739.io.dma.resp.valid <= UInt<1>("h00") T_739.io.dma.req.ready <= UInt<1>("h00") T_739.io.host.csr.resp.ready <= UInt<1>("h00") T_739.io.host.csr.req.bits.data <= UInt<1>("h00") T_739.io.host.csr.req.bits.addr <= UInt<1>("h00") T_739.io.host.csr.req.bits.rw <= UInt<1>("h00") T_739.io.host.csr.req.valid <= UInt<1>("h00") T_739.io.host.id <= UInt<1>("h00") T_739.io.host.reset <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.data <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.g_type <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") T_739.io.uncached[0].grant.bits.addr_beat <= UInt<1>("h00") T_739.io.uncached[0].grant.valid <= UInt<1>("h00") T_739.io.uncached[0].acquire.ready <= UInt<1>("h00") T_739.io.cached[0].release.ready <= UInt<1>("h00") T_739.io.cached[0].probe.bits.p_type <= UInt<1>("h00") T_739.io.cached[0].probe.bits.addr_block <= UInt<1>("h00") T_739.io.cached[0].probe.valid <= UInt<1>("h00") T_739.io.cached[0].grant.bits.data <= UInt<1>("h00") T_739.io.cached[0].grant.bits.g_type <= UInt<1>("h00") T_739.io.cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") T_739.io.cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") T_739.io.cached[0].grant.bits.client_xact_id <= UInt<1>("h00") T_739.io.cached[0].grant.bits.addr_beat <= UInt<1>("h00") T_739.io.cached[0].grant.valid <= UInt<1>("h00") T_739.io.cached[0].acquire.ready <= UInt<1>("h00") T_739.clk <= clk T_739.reset <= uncore.io.htif[0].reset T_739.io.host.id <= UInt<1>("h00") reg T_772 : UInt<1>, clk, UInt<1>("h00"), T_772 T_772 <= uncore.io.htif[0].reset reg T_773 : UInt<1>, clk, UInt<1>("h00"), T_773 T_773 <= T_772 T_739.io.host.reset <= T_773 inst T_778 of Queue_124 T_778.io.deq.ready <= UInt<1>("h00") T_778.io.enq.bits.data <= UInt<1>("h00") T_778.io.enq.bits.addr <= UInt<1>("h00") T_778.io.enq.bits.rw <= UInt<1>("h00") T_778.io.enq.valid <= UInt<1>("h00") T_778.clk <= clk T_778.reset <= reset T_778.io.enq.valid <= uncore.io.htif[0].csr.req.valid T_778.io.enq.bits <- uncore.io.htif[0].csr.req.bits uncore.io.htif[0].csr.req.ready <= T_778.io.enq.ready T_739.io.host.csr.req <- T_778.io.deq inst T_785 of Queue_125 T_785.io.deq.ready <= UInt<1>("h00") T_785.io.enq.bits <= UInt<1>("h00") T_785.io.enq.valid <= UInt<1>("h00") T_785.clk <= clk T_785.reset <= reset T_785.io.enq.valid <= T_739.io.host.csr.resp.valid T_785.io.enq.bits <= T_739.io.host.csr.resp.bits T_739.io.host.csr.resp.ready <= T_785.io.enq.ready uncore.io.htif[0].csr.resp <- T_785.io.deq uncore.io.htif[0].debug_stats_csr <= T_739.io.host.debug_stats_csr uncore.io.tiles_cached[0] <- T_739.io.cached[0] uncore.io.tiles_uncached[0] <- T_739.io.uncached[0] io.host <- uncore.io.host io.mem_backup_ctrl <- uncore.io.mem_backup_ctrl inst T_801 of Queue_36 T_801.io.deq.ready <= UInt<1>("h00") T_801.io.enq.bits.user <= UInt<1>("h00") T_801.io.enq.bits.id <= UInt<1>("h00") T_801.io.enq.bits.region <= UInt<1>("h00") T_801.io.enq.bits.qos <= UInt<1>("h00") T_801.io.enq.bits.prot <= UInt<1>("h00") T_801.io.enq.bits.cache <= UInt<1>("h00") T_801.io.enq.bits.lock <= UInt<1>("h00") T_801.io.enq.bits.burst <= UInt<1>("h00") T_801.io.enq.bits.size <= UInt<1>("h00") T_801.io.enq.bits.len <= UInt<1>("h00") T_801.io.enq.bits.addr <= UInt<1>("h00") T_801.io.enq.valid <= UInt<1>("h00") T_801.clk <= clk T_801.reset <= reset T_801.io.enq.valid <= uncore.io.mem[0].ar.valid T_801.io.enq.bits <- uncore.io.mem[0].ar.bits uncore.io.mem[0].ar.ready <= T_801.io.enq.ready io.mem[0].ar <- T_801.io.deq inst T_827 of Queue_36 T_827.io.deq.ready <= UInt<1>("h00") T_827.io.enq.bits.user <= UInt<1>("h00") T_827.io.enq.bits.id <= UInt<1>("h00") T_827.io.enq.bits.region <= UInt<1>("h00") T_827.io.enq.bits.qos <= UInt<1>("h00") T_827.io.enq.bits.prot <= UInt<1>("h00") T_827.io.enq.bits.cache <= UInt<1>("h00") T_827.io.enq.bits.lock <= UInt<1>("h00") T_827.io.enq.bits.burst <= UInt<1>("h00") T_827.io.enq.bits.size <= UInt<1>("h00") T_827.io.enq.bits.len <= UInt<1>("h00") T_827.io.enq.bits.addr <= UInt<1>("h00") T_827.io.enq.valid <= UInt<1>("h00") T_827.clk <= clk T_827.reset <= reset T_827.io.enq.valid <= uncore.io.mem[0].aw.valid T_827.io.enq.bits <- uncore.io.mem[0].aw.bits uncore.io.mem[0].aw.ready <= T_827.io.enq.ready io.mem[0].aw <- T_827.io.deq inst T_846 of Queue_74 T_846.io.deq.ready <= UInt<1>("h00") T_846.io.enq.bits.user <= UInt<1>("h00") T_846.io.enq.bits.strb <= UInt<1>("h00") T_846.io.enq.bits.last <= UInt<1>("h00") T_846.io.enq.bits.data <= UInt<1>("h00") T_846.io.enq.valid <= UInt<1>("h00") T_846.clk <= clk T_846.reset <= reset T_846.io.enq.valid <= uncore.io.mem[0].w.valid T_846.io.enq.bits <- uncore.io.mem[0].w.bits uncore.io.mem[0].w.ready <= T_846.io.enq.ready io.mem[0].w <- T_846.io.deq inst T_859 of Queue_75 T_859.io.deq.ready <= UInt<1>("h00") T_859.io.enq.bits.user <= UInt<1>("h00") T_859.io.enq.bits.id <= UInt<1>("h00") T_859.io.enq.bits.last <= UInt<1>("h00") T_859.io.enq.bits.data <= UInt<1>("h00") T_859.io.enq.bits.resp <= UInt<1>("h00") T_859.io.enq.valid <= UInt<1>("h00") T_859.clk <= clk T_859.reset <= reset T_859.io.enq.valid <= io.mem[0].r.valid T_859.io.enq.bits <- io.mem[0].r.bits io.mem[0].r.ready <= T_859.io.enq.ready uncore.io.mem[0].r <- T_859.io.deq inst T_871 of Queue_76 T_871.io.deq.ready <= UInt<1>("h00") T_871.io.enq.bits.user <= UInt<1>("h00") T_871.io.enq.bits.id <= UInt<1>("h00") T_871.io.enq.bits.resp <= UInt<1>("h00") T_871.io.enq.valid <= UInt<1>("h00") T_871.clk <= clk T_871.reset <= reset T_871.io.enq.valid <= io.mem[0].b.valid T_871.io.enq.bits <- io.mem[0].b.bits io.mem[0].b.ready <= T_871.io.enq.ready uncore.io.mem[0].b <- T_871.io.deq io.mem[0].ar.bits.cache <= UInt<4>("h03") io.mem[0].aw.bits.cache <= UInt<4>("h03") inst errslave of NastiErrorSlave_40 errslave.io.r.ready <= UInt<1>("h00") errslave.io.ar.bits.user <= UInt<1>("h00") errslave.io.ar.bits.id <= UInt<1>("h00") errslave.io.ar.bits.region <= UInt<1>("h00") errslave.io.ar.bits.qos <= UInt<1>("h00") errslave.io.ar.bits.prot <= UInt<1>("h00") errslave.io.ar.bits.cache <= UInt<1>("h00") errslave.io.ar.bits.lock <= UInt<1>("h00") errslave.io.ar.bits.burst <= UInt<1>("h00") errslave.io.ar.bits.size <= UInt<1>("h00") errslave.io.ar.bits.len <= UInt<1>("h00") errslave.io.ar.bits.addr <= UInt<1>("h00") errslave.io.ar.valid <= UInt<1>("h00") errslave.io.b.ready <= UInt<1>("h00") errslave.io.w.bits.user <= UInt<1>("h00") errslave.io.w.bits.strb <= UInt<1>("h00") errslave.io.w.bits.last <= UInt<1>("h00") errslave.io.w.bits.data <= UInt<1>("h00") errslave.io.w.valid <= UInt<1>("h00") errslave.io.aw.bits.user <= UInt<1>("h00") errslave.io.aw.bits.id <= UInt<1>("h00") errslave.io.aw.bits.region <= UInt<1>("h00") errslave.io.aw.bits.qos <= UInt<1>("h00") errslave.io.aw.bits.prot <= UInt<1>("h00") errslave.io.aw.bits.cache <= UInt<1>("h00") errslave.io.aw.bits.lock <= UInt<1>("h00") errslave.io.aw.bits.burst <= UInt<1>("h00") errslave.io.aw.bits.size <= UInt<1>("h00") errslave.io.aw.bits.len <= UInt<1>("h00") errslave.io.aw.bits.addr <= UInt<1>("h00") errslave.io.aw.valid <= UInt<1>("h00") errslave.clk <= clk errslave.reset <= reset errslave.io <- uncore.io.mmio