======= Fixes to Jonathan's Front-end ======

== TODO ==
convert -> cvt
as-UInt -> asUInt
as-SInt -> asSInt
add-wrap -> addw
sub-wrap -> subw
bit-and -> and
bit-or -> or
bit-xor -> xor
on-reset -> onreset
reg now has reset and clock
cmem/smem now has clock
accessor -> infer accessor
"Clock" is now a type, so the following declares a clock port:
module Queue :
  input clk : Clock
  ...



Fixing chisel3 front-end bugs:
   LFSR16: "concat" -> "cat"
   MemorySearch: name collision with node done and output done
   Mul: shr/shl take one expression argument, and one int argument.
      node T_59 = UInt(2, 2)
      node T_60 = shl(x, T_59)
      ==>
      node T_60 = shl(x, 2)
   Outer: "instance" => "inst"
   Stack: bug in firrtl! thanks!

== Completed ==
Remove type from node emission

Currently, these are not equivalent because we will fail a type check:
output in { input x : UInt, input y : UInt}
=>
input in {x : UInt, y : UInt}

Switch "input" -> "flip" and "output" to "" within a bundle
Switch "add-mod" -> "add-wrap"
Switch "multiplex" -> "mux"
Switch "greater" -> "gt"