From f711861808e3ca914f71a3089c6879dbcb7dc08d Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:16:09 -0800
Subject: Changed register syntax for optional reset and init values

---
 test/features/OptionalRegisterReset.fir | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 test/features/OptionalRegisterReset.fir

(limited to 'test')

diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir
new file mode 100644
index 00000000..54a90b67
--- /dev/null
+++ b/test/features/OptionalRegisterReset.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input a : UInt<32>
+    input p : UInt<1>
+    output b : UInt<32>
+    reg r1:UInt<32> clk with : 
+      reset => (reset, a)
+    when p :
+      b <= r1
+    else :
+      b <= r1
+
+
+;CHECK: Done!
-- 
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