From 45946bba6942378970ae42502f7b2829c2d3c58f Mon Sep 17 00:00:00 2001 From: Jack Date: Tue, 6 Oct 2015 16:03:48 -0700 Subject: Added ability to test scala FIRRTL --- test/parser/gcd.fir | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 test/parser/gcd.fir (limited to 'test') diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir new file mode 100644 index 00000000..03eb6ba9 --- /dev/null +++ b/test/parser/gcd.fir @@ -0,0 +1,52 @@ +; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s +circuit GCD : + module GCD : + input e : UInt<1> + input clk : Clock + input reset : UInt<1> + output z : UInt<16> + output v : UInt<1> + input a : UInt<16> + input b : UInt<16> + + reg x : UInt<16>,clk,reset + reg y : UInt<16>,clk,reset + node T_17 = gt(x, y) + when T_17 : + node T_18 = subw(x, y) + x := T_18 + else : + node T_19 = subw(y, x) + y := T_19 + when e : + x := a + y := b + z := x + node T_20 = eq(y, UInt<1>(0)) + v := T_20 + +; CHECK: circuit GCD : +; CHECK: module GCD : +; CHECK: input e : UInt<1> +; CHECK: input clk : Clock +; CHECK: input reset : UInt<1> +; CHECK: output z : UInt<16> +; CHECK: output v : UInt<1> +; CHECK: input a : UInt<16> +; CHECK: input b : UInt<16> +; CHECK: reg x : UInt<16>, clk, reset +; CHECK: reg y : UInt<16>, clk, reset +; CHECK: node T_17 = gt(x, y) +; CHECK: when T_17 : +; CHECK: node T_18 = subw(x, y) +; CHECK: x := T_18 +; CHECK: else : +; CHECK: node T_19 = subw(y, x) +; CHECK: y := T_19 +; CHECK: when e : +; CHECK: x := a +; CHECK: y := b +; CHECK: z := x +; CHECK: node T_20 = eq(y, UInt<1>("h00")) +; CHECK: v := T_20 + -- cgit v1.2.3 From 0c288c48382f1b31fbfb1c202867fb444e46136c Mon Sep 17 00:00:00 2001 From: Jack Date: Mon, 12 Oct 2015 16:45:21 -0700 Subject: Added support for no width to mean unknown, and print nothing instead of for unknown width. Also added test to check this --- test/parser/bundle.fir | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 test/parser/bundle.fir (limited to 'test') diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir new file mode 100644 index 00000000..15fa26d0 --- /dev/null +++ b/test/parser/bundle.fir @@ -0,0 +1,43 @@ +; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s +circuit top : + module top : + wire z : { x : UInt, flip y: SInt} + z.x := UInt(1) + z.y := SInt(1) + node x = z.x + node y = z.y + wire a : UInt<3>[10] + a[0] := UInt(1) + a[1] := UInt(1) + a[2] := UInt(1) + a[3] := UInt(1) + a[4] := UInt(1) + a[5] := UInt(1) + a[6] := UInt(1) + a[7] := UInt(1) + a[8] := UInt(1) + a[9] := UInt(1) + node b = a[2] + read accessor c = a[UInt(3)] + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire z : { x : UInt, flip y : SInt } +; CHECK: z.x := UInt("h01") +; CHECK: z.y := SInt("h01") +; CHECK: node x = z.x +; CHECK: node y = z.y +; CHECK: wire a : UInt<3>[10] +; CHECK: a[0] := UInt("h01") +; CHECK: a[1] := UInt("h01") +; CHECK: a[2] := UInt("h01") +; CHECK: a[3] := UInt("h01") +; CHECK: a[4] := UInt("h01") +; CHECK: a[5] := UInt("h01") +; CHECK: a[6] := UInt("h01") +; CHECK: a[7] := UInt("h01") +; CHECK: a[8] := UInt("h01") +; CHECK: a[9] := UInt("h01") +; CHECK: node b = a[2] +; CHECK: read accessor c = a[UInt("h03")] + -- cgit v1.2.3 From 9b737de6551e7446dfd92d86cd009b4b2f95c980 Mon Sep 17 00:00:00 2001 From: Jack Date: Wed, 14 Oct 2015 13:53:22 -0700 Subject: Moved Logger to new private object DebugUtils, changed UInt/SInt value printing to match stanza implementation --- test/parser/bundle.fir | 26 +++++++++++++------------- test/parser/gcd.fir | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) (limited to 'test') diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir index 15fa26d0..c9f5e226 100644 --- a/test/parser/bundle.fir +++ b/test/parser/bundle.fir @@ -23,21 +23,21 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire z : { x : UInt, flip y : SInt } -; CHECK: z.x := UInt("h01") -; CHECK: z.y := SInt("h01") +; CHECK: z.x := UInt("h1") +; CHECK: z.y := SInt("h1") ; CHECK: node x = z.x ; CHECK: node y = z.y ; CHECK: wire a : UInt<3>[10] -; CHECK: a[0] := UInt("h01") -; CHECK: a[1] := UInt("h01") -; CHECK: a[2] := UInt("h01") -; CHECK: a[3] := UInt("h01") -; CHECK: a[4] := UInt("h01") -; CHECK: a[5] := UInt("h01") -; CHECK: a[6] := UInt("h01") -; CHECK: a[7] := UInt("h01") -; CHECK: a[8] := UInt("h01") -; CHECK: a[9] := UInt("h01") +; CHECK: a[0] := UInt("h1") +; CHECK: a[1] := UInt("h1") +; CHECK: a[2] := UInt("h1") +; CHECK: a[3] := UInt("h1") +; CHECK: a[4] := UInt("h1") +; CHECK: a[5] := UInt("h1") +; CHECK: a[6] := UInt("h1") +; CHECK: a[7] := UInt("h1") +; CHECK: a[8] := UInt("h1") +; CHECK: a[9] := UInt("h1") ; CHECK: node b = a[2] -; CHECK: read accessor c = a[UInt("h03")] +; CHECK: read accessor c = a[UInt("h3")] diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir index 03eb6ba9..3a9317b8 100644 --- a/test/parser/gcd.fir +++ b/test/parser/gcd.fir @@ -47,6 +47,6 @@ circuit GCD : ; CHECK: x := a ; CHECK: y := b ; CHECK: z := x -; CHECK: node T_20 = eq(y, UInt<1>("h00")) +; CHECK: node T_20 = eq(y, UInt<1>("h0")) ; CHECK: v := T_20 -- cgit v1.2.3 From edd57efbadf493b331e69c8686662500fe859372 Mon Sep 17 00:00:00 2001 From: Jack Date: Wed, 14 Oct 2015 14:04:33 -0700 Subject: Modified getType to return Type rather than Option[Type] which makes more sense for some applications, also fixed up printing to better match stanza implementation --- test/parser/bundle.fir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test') diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir index c9f5e226..c9600d10 100644 --- a/test/parser/bundle.fir +++ b/test/parser/bundle.fir @@ -22,7 +22,7 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : -; CHECK: wire z : { x : UInt, flip y : SInt } +; CHECK: wire z : { x : UInt, flip y : SInt} ; CHECK: z.x := UInt("h1") ; CHECK: z.y := SInt("h1") ; CHECK: node x = z.x -- cgit v1.2.3