From bd8b9669d1cdc4898be9d38ca9c492866d927d77 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 24 Apr 2015 14:46:44 -0700
Subject: Fixed width inference bug where later constraints on the output width
 were not propogating to the input widths, for primops

---
 test/passes/jacktest/Tlb.fir | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 test/passes/jacktest/Tlb.fir

(limited to 'test')

diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
new file mode 100644
index 00000000..35442ac8
--- /dev/null
+++ b/test/passes/jacktest/Tlb.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Tbl : 
+  module Tbl : 
+    output o : UInt(16)
+    input i : UInt(16)
+    input d : UInt(16)
+    input we : UInt(1)
+    
+    mem m : UInt(10)[256]
+    node T_12 = UInt(0, 1)
+    o := Pad(T_12,?)
+    when we : 
+      accessor T_13 = m[i]
+      T_13 := Pad(d,?)
+    else : 
+      accessor T_14 = m[i]
+      o := Pad(T_14,?)
-- 
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