From d98526e50f9dee6edd4d885c707972cfa9666e34 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 15:36:09 -0800
Subject: Added inference to mports

---
 test/chirrtl/infer-mport-dir.fir | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 test/chirrtl/infer-mport-dir.fir

(limited to 'test')

diff --git a/test/chirrtl/infer-mport-dir.fir b/test/chirrtl/infer-mport-dir.fir
new file mode 100644
index 00000000..50baeff2
--- /dev/null
+++ b/test/chirrtl/infer-mport-dir.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module top :
+      input clk : Clock
+      wire p : UInt
+      wire q : UInt
+      cmem m : {a:UInt<4>,b:UInt<4>}[10]
+      p <= UInt(1)
+      q <= UInt(1)
+      wire x : {a:UInt<4>,b:UInt<4>}
+      x.a <= UInt(1)
+      x.b <= UInt(1)
+      when p :
+         infer mport a = m[UInt(3)],clk
+         infer mport b = m[UInt(3)],clk
+         infer mport c = m[UInt(3)],clk
+         when q :
+            a <= x
+            x <= b
+            c <= x
+            x <= c
-- 
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