From 70e1a41b15632afd969fff7ed6100eba0be78297 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 10 Mar 2015 18:08:07 -0700
Subject: Finished resolve genders

---
 test/passes/resolve-genders/accessor.fir | 19 ++++++++++++
 test/passes/resolve-genders/bulk.fir     | 14 +++++++++
 test/passes/resolve-genders/gcd.fir      | 52 ++++++++++++++++++++++++++++++++
 test/passes/resolve-genders/ports.fir    | 21 +++++++++++++
 4 files changed, 106 insertions(+)
 create mode 100644 test/passes/resolve-genders/accessor.fir
 create mode 100644 test/passes/resolve-genders/bulk.fir
 create mode 100644 test/passes/resolve-genders/gcd.fir
 create mode 100644 test/passes/resolve-genders/ports.fir

(limited to 'test')

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
new file mode 100644
index 00000000..c6e2a905
--- /dev/null
+++ b/test/passes/resolve-genders/accessor.fir
@@ -0,0 +1,19 @@
+; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module top :
+      wire m : UInt(32)[10][10][10]
+      wire i : UInt
+      accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
+      accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
+      accessor c = b[i] ;CHECK: accessor c = b@<g:male>[i@<g:male>]@<g:male>
+      wire j : UInt
+      j := c
+
+      accessor x = m[i] ;CHECK: accessor x = m@<g:female>[i@<g:male>]@<g:female>
+      accessor y = x[i] ;CHECK: accessor y = x@<g:female>[i@<g:male>]@<g:female>
+      accessor z = y[i] ;CHECK: accessor z = y@<g:female>[i@<g:male>]@<g:female>
+      z := j
+
+; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir
new file mode 100644
index 00000000..0276715f
--- /dev/null
+++ b/test/passes/resolve-genders/bulk.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module source :
+      output bundle : { male data : UInt(16), female ready : UInt(1) }
+   module sink :
+      input bundle : { male data : UInt(16), female ready : UInt(1) }
+   module top :
+      inst src of source
+      inst snk of sink
+      snk.bundle := src.bundle
+
+; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
new file mode 100644
index 00000000..7e0a22c0
--- /dev/null
+++ b/test/passes/resolve-genders/gcd.fir
@@ -0,0 +1,52 @@
+; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output z : UInt
+      z := sub-wrap(x, y)
+      ;CHECK: z@<g:female> := sub-wrap(x@<g:male>, y@<g:male>)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+; CHECK: reg x : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt(x, y) :
+      ;CHECK: when gt(x@<g:male>, y@<g:male>) :
+         inst s of subtracter
+         ;CHECK: inst s of subtracter@<g:female>
+         s.x := x
+         s.y := y
+         x := s.z
+         ;CHECK: s@<g:female>.x@<g:female> := x@<g:male>
+         ;CHECK: s@<g:female>.y@<g:female> := y@<g:male>
+         ;CHECK: x@<g:female> := s@<g:female>.z@<g:male>
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.z
+      when e :
+         x := a
+         y := b
+      v := equal(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
new file mode 100644
index 00000000..ea92cd24
--- /dev/null
+++ b/test/passes/resolve-genders/ports.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module source :
+      output data : UInt(16)
+      input ready : UInt(1)
+      data := UInt(16)
+   module sink :
+      input data : UInt(16)
+      output ready : UInt(1)
+   module top: 
+      wire connect : { male data : UInt(16), female ready: UInt(1) }
+      inst src of source         ;CHECK: inst src of source@<g:female>
+      inst snk of sink           ;CHECK: inst snk of sink@<g:female>
+      connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
+      src.ready := connect.ready ;CHECK: src@<g:female>.ready@<g:female> := connect@<g:female>.ready@<g:male>
+      snk.data := connect.data   ;CHECK: snk@<g:female>.data@<g:female> := connect@<g:male>.data@<g:male>
+      connect.ready := snk.ready ;CHECK: connect@<g:male>.ready@<g:female> := snk@<g:female>.ready@<g:male>
+
+; CHECK: Finished Resolve Genders
-- 
cgit v1.2.3