From 612132bf95b529d2fafbe96e622f716ca9514679 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 25 Mar 2015 12:56:29 -0700
Subject: Correctly do when expansion, minus enables and outputting lowered
 form

---
 test/passes/expand-whens/one-when.fir    | 12 ++++++++++++
 test/passes/lower-to-ground/register.fir |  4 ++--
 2 files changed, 14 insertions(+), 2 deletions(-)

(limited to 'test')

diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 9745d087..66fc2ef6 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -6,7 +6,12 @@ circuit top :
       mem m : UInt(1)[2]
       wire i : UInt(1)
       wire p : UInt(1)
+      wire j : UInt(1)
+      reg r : UInt(1)
+
+      p := j
       when p :
+        r.init := i
         accessor a = m[i] 
         i := a
         accessor b = m[i]
@@ -16,5 +21,12 @@ circuit top :
         i := c
         accessor d = m[i] 
         d := i
+      accessor e = m[i]
+      when p :
+        p := i
+        when e :
+           p := p
+           r.init := p
+        
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 9021d0c2..f270bacb 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -15,7 +15,7 @@
       ; CHECK: reg r1#y : SInt
       ; CHECK: wire q#x : UInt
       ; CHECK: wire q#y : SInt
-      ; CHECK: r1#init#x := q#x
-      ; CHECK: q#y := r1#init#y
+      ; CHECK: r1#x.init := q#x
+      ; CHECK: q#y := r1#y.init
 
 ; CHECK: Finished Lower To Ground
-- 
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