From 5db4abebb7ceb5939a9efca158d78e3dc0e32c44 Mon Sep 17 00:00:00 2001
From: Angie Wang
Date: Wed, 17 Aug 2016 13:34:14 -0700
Subject: Change RW port names (#236)

* Updated FIRRTL spec + related code for readwrite ports.
    (write) data -> wdata & mask -> wmask for clarity

* Also removed simple.fir that snuck into master branch.---
 test/integration/MemTester.fir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'test')

diff --git a/test/integration/MemTester.fir b/test/integration/MemTester.fir
index c41fe1cc..451ec5d3 100644
--- a/test/integration/MemTester.fir
+++ b/test/integration/MemTester.fir
@@ -28,14 +28,14 @@ circuit MemTester :
     m.rw.clk <= clk
     m.rw.addr <= addr
     m.rw.wmode <= wmode
-    m.rw.data <= n
-    m.rw.mask <= UInt(1)
+    m.rw.wdata <= n
+    m.rw.wmask <= UInt(1)
     m.rw.en <= UInt(1)
 
     when not(reset) :
       when eq(wmode, UInt(0)) :
         when neq(m.rw.rdata, n) :
-          printf(clk, UInt(1), "Assertion failed! m.rw.data has the wrong value!\n")
+          printf(clk, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
           stop(clk, UInt(1), 1)
 
   module MemTester :
-- 
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