From 4183c648b719eac9da26e2d9d34fa852ebdbfd20 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 7 Oct 2015 14:48:04 -0700 Subject: Added Printf and Stop to firrtl. #23 #24. --- test/errors/high-form/Printf.fir | 15 +++++++++++++++ test/features/Printf.fir | 19 +++++++++++++++++++ test/features/Stop.fir | 20 ++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 test/errors/high-form/Printf.fir create mode 100644 test/features/Printf.fir create mode 100644 test/features/Stop.fir (limited to 'test') diff --git a/test/errors/high-form/Printf.fir b/test/errors/high-form/Printf.fir new file mode 100644 index 00000000..7f285d3e --- /dev/null +++ b/test/errors/high-form/Printf.fir @@ -0,0 +1,15 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +circuit Top : + module Top : + input x : {y : UInt<1>} + input p : UInt<1> + printf("Hello World%!\n",x) + printf("Hello World%") + printf("Hello World%d %s %h %x",x,x,x) + +;CHECK: Bad printf format: "%!" +;CHECK: Bad printf format: trailing "%" +;CHECK: Bad printf format: incorrect number of arguments +;CHECK: Bad printf format: "%h" +;CHECK: Bad printf format: incorrect number of arguments diff --git a/test/features/Printf.fir b/test/features/Printf.fir new file mode 100644 index 00000000..8449825f --- /dev/null +++ b/test/features/Printf.fir @@ -0,0 +1,19 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Lower To Ground +circuit Top : + module Top : + input x : {y : UInt<1>} + input p : UInt<1> + printf("Hello World!\n") + printf("Hello World! %x\n", x.y) + when p : + printf("In consequence\n") + else : + printf("In alternate\n") + +;CHECK: printf("Hello World!\n") +;CHECK: printf("Hello World! %x\n", x$y) +;CHECK: when p : printf("In consequence\n") +;CHECK: when not(p) : printf("In alternate\n") +;CHECK: Done! diff --git a/test/features/Stop.fir b/test/features/Stop.fir new file mode 100644 index 00000000..fc8869fa --- /dev/null +++ b/test/features/Stop.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Lower To Ground + +circuit Top : + module Top : + input p : UInt<1> + input q : UInt<1> + when p : + stop(0) + when q : + stop(1) + stop(3) + +;CHECK: when p : stop(0) +;CHECK: when q : stop(1) +;CHECK: stop(3) + +;CHECK: Done! + -- cgit v1.2.3