From 2428d391d02a9ff413884e073ae3e6ac37f2df2d Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 14:18:09 -0800
Subject: Added addw to working ir as an optimized verilog emission

---
 test/passes/lower-to-ground/bundle-vecs.fir | 34 ++++++++++++-----------------
 test/passes/split-exp/split-in-when.fir     | 18 ++++++---------
 2 files changed, 21 insertions(+), 31 deletions(-)

(limited to 'test')

diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index c42766ad..cf581ab7 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -19,26 +19,20 @@ circuit top :
       j <= a[i]
       a[i] <= j
 
-;CHECK: wire GEN_0 : UInt<32>
-;CHECK: wire GEN_1 : UInt<32>
-;CHECK: wire GEN_2 : UInt<32>
-;CHECK: wire GEN_3 : UInt<32>
-;CHECK: j_x <= GEN_0
-;CHECK: j_y <= GEN_3
-;CHECK: node GEN_4 = eq(UInt("h0"), i)
-;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0"))
-;CHECK: node GEN_5 = eq(UInt("h0"), i)
-;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0"))
-;CHECK: node GEN_6 = eq(UInt("h1"), i)
-;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0"))
-;CHECK: node GEN_7 = eq(UInt("h1"), i)
-;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0"))
-;CHECK: node GEN_8 = eq(UInt("h1"), i)
-;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x)
-;CHECK: GEN_1 <= j_y
-;CHECK: GEN_2 <= j_x
-;CHECK: node GEN_9 = eq(UInt("h1"), i)
-;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y)   
+; CHECK: wire GEN_0 : UInt<32>
+; CHECK: wire GEN_1 : UInt<32>
+; CHECK: wire GEN_2 : UInt<32>
+; CHECK: wire GEN_3 : UInt<32>
+; CHECK: j_x <= GEN_0
+; CHECK: j_y <= GEN_3
+; CHECK: a_0_x <= mux(eq(UInt("h0"), i), GEN_2, UInt("h0"))
+; CHECK: a_0_y <= mux(eq(UInt("h0"), i), GEN_1, UInt("h0"))
+; CHECK: a_1_x <= mux(eq(UInt("h1"), i), GEN_2, UInt("h0"))
+; CHECK: a_1_y <= mux(eq(UInt("h1"), i), GEN_1, UInt("h0"))
+; CHECK: GEN_0 <= mux(eq(UInt("h1"), i), a_1_x, a_0_x)
+; CHECK: GEN_1 <= j_y
+; CHECK: GEN_2 <= j_x
+; CHECK: GEN_3 <= mux(eq(UInt("h1"), i), a_1_y, a_0_y)   
 
 ; CHECK: Finished Lower Types
 
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index 06d1463d..207ad757 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -14,16 +14,12 @@ circuit Top :
 
       when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
 
-;CHECK: node GEN_0 = sub(a, c)
-;CHECK: node GEN_1 = tail(GEN_0, 1)
-;CHECK: node GEN_2 = bits(GEN_1, 3, 3)
-;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd"))
-;CHECK: node GEN_4 = add(b, c)
-;CHECK: node GEN_5 = tail(GEN_4, 1)
-;CHECK: node GEN_6 = add(a, GEN_5)
-;CHECK: node GEN_7 = tail(GEN_6, 1)
-;CHECK: node GEN_8 = sub(c, b)
-;CHECK: node GEN_9 = tail(GEN_8, 1)
-;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out)   
+;CHECK: node GEN_0 = subw(a, c)
+;CHECK: node GEN_1 = bits(GEN_0, 3, 3)
+;CHECK: node GEN_2 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_3 = addw(b, c)
+;CHECK: node GEN_4 = addw(a, GEN_3)
+;CHECK: node GEN_5 = subw(c, b)
+;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)   
 
 ;CHECK: Finished Split Expressions
-- 
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