From 2353d640907a7b04477b06a5b3da6b7bbafc448d Mon Sep 17 00:00:00 2001 From: azidar Date: Tue, 24 Feb 2015 09:40:02 -0800 Subject: Updated tests, and included a check for the name of the pass, which allows the compiler to print after each pass to ease debugging --- test/passes/infer-types/gcd.fir | 46 +++++++++++++++++++++++++ test/passes/infer-types/primops.fir | 8 +++++ test/passes/initialize-register/begin.fir | 2 ++ test/passes/initialize-register/when.fir | 3 +- test/passes/make-explicit-reset/abc.fir | 27 --------------- test/passes/make-explicit-reset/mix-reset.fir | 28 +++++++++++++++ test/passes/resolve-kinds/ab.fir | 48 -------------------------- test/passes/resolve-kinds/gcd.fir | 49 +++++++++++++++++++++++++++ 8 files changed, 135 insertions(+), 76 deletions(-) create mode 100644 test/passes/infer-types/gcd.fir create mode 100644 test/passes/infer-types/primops.fir delete mode 100644 test/passes/make-explicit-reset/abc.fir create mode 100644 test/passes/make-explicit-reset/mix-reset.fir delete mode 100644 test/passes/resolve-kinds/ab.fir create mode 100644 test/passes/resolve-kinds/gcd.fir (limited to 'test') diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir new file mode 100644 index 00000000..b261f0d1 --- /dev/null +++ b/test/passes/infer-types/gcd.fir @@ -0,0 +1,46 @@ +; RUN: firrtl %s abcde | tee %s.out | FileCheck %s + +;CHECK: Infer Types +circuit top : + module subtracter : + input x : UInt + input y : UInt + output z : UInt + z := sub-mod(x, y) + module gcd : + input a : UInt(16) + input b : UInt(16) + input e : UInt(1) + output z : UInt(16) + output v : UInt(1) + reg x : UInt + reg y : UInt +; CHECK: reg x : UInt + x.init := UInt(0) + y.init := UInt(42) + when greater(x, y) : + inst s of subtracter + s.x := x + s.y := y + x := s.z + else : + inst s2 of subtracter + s2.x := x + s2.y := y + y := s2.z + when e : + x := a + y := b + v := equal(v, UInt(0)) + z := x + module top : + input a : UInt(16) + input b : UInt(16) + output z : UInt + inst i of gcd + i.a := a + i.b := b + i.e := UInt(1) + z := i.z + + diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir new file mode 100644 index 00000000..fa0f0c90 --- /dev/null +++ b/test/passes/infer-types/primops.fir @@ -0,0 +1,8 @@ +; RUN: firrtl %s abcde | tee %s.out | FileCheck %s + +;CHECK: Infer Types +circuit top : + module top : + wire io : {input x : UInt, output y : UInt} + io.x := add(io.x,io.y) +;CHECK: n:io:{input x : UInt, output y : UInt}.x := add(n:io:{input x : UInt, output y : UInt}.x, n:io:{input x : UInt, output y : UInt}.y) diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir index 9d4de49e..4f64b071 100644 --- a/test/passes/initialize-register/begin.fir +++ b/test/passes/initialize-register/begin.fir @@ -1,5 +1,6 @@ ; RUN: firrtl %s abcd | tee %s.out | FileCheck %s +; CHECK: Initialize Registers circuit top : module top : input a : UInt(16) @@ -12,6 +13,7 @@ reg r2 : UInt r2.init := UInt(0) +; CHECK-NOT: r2.init := UInt(0) ; CHECK: wire [[R2:gen[0-9]*]] : UInt ; CHECK-NOT: reg:r2 := n:[[R2]] ; CHECK: n:[[R2]] := Null diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir index e4749abe..c563d639 100644 --- a/test/passes/initialize-register/when.fir +++ b/test/passes/initialize-register/when.fir @@ -1,5 +1,6 @@ ; RUN: firrtl %s abcd | tee %s.out | FileCheck %s -; CHECK: circuit top : + +; CHECK: Initialize Registers circuit top : module top : input a : UInt(16) diff --git a/test/passes/make-explicit-reset/abc.fir b/test/passes/make-explicit-reset/abc.fir deleted file mode 100644 index caed07ab..00000000 --- a/test/passes/make-explicit-reset/abc.fir +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: firrtl %s abc | tee %s.out | FileCheck %s - -circuit top : - module A : - ;CHECK: input reset : UInt(1) - input x : UInt(16) - output y : UInt(16) - inst b of B - ;CHECK: inst:b.reset := port:reset - module B : - input reset : UInt(1) - ;CHECK: input reset : UInt(1) - input x : UInt(16) - output y : UInt(16) - inst c of C - ;CHECK: inst:c.reset := port:reset - module C : - ;CHECK: input reset : UInt(1) - input a : UInt(16) - input b : UInt(16) - module top : - ;CHECK: input reset : UInt(1) - input a : UInt(16) - input b : UInt(16) - output z : UInt - inst a of A - ;CHECK: inst:a.reset := port:reset diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir new file mode 100644 index 00000000..23a1232a --- /dev/null +++ b/test/passes/make-explicit-reset/mix-reset.fir @@ -0,0 +1,28 @@ +; RUN: firrtl %s abc | tee %s.out | FileCheck %s + +; CHECK: Make Explicit Reset +circuit top : + module A : + ;CHECK: input reset : UInt(1) + input x : UInt(16) + output y : UInt(16) + inst b of B + ;CHECK: inst:b.reset := port:reset + module B : + input reset : UInt(1) + ;CHECK: input reset : UInt(1) + input x : UInt(16) + output y : UInt(16) + inst c of C + ;CHECK: inst:c.reset := port:reset + module C : + ;CHECK: input reset : UInt(1) + input a : UInt(16) + input b : UInt(16) + module top : + ;CHECK: input reset : UInt(1) + input a : UInt(16) + input b : UInt(16) + output z : UInt + inst a of A + ;CHECK: inst:a.reset := port:reset diff --git a/test/passes/resolve-kinds/ab.fir b/test/passes/resolve-kinds/ab.fir deleted file mode 100644 index e6f28c21..00000000 --- a/test/passes/resolve-kinds/ab.fir +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: firrtl %s ab | tee %s.out | FileCheck %s - -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z := sub-mod(x, y) -; CHECK: port:z := sub-mod(port:x, port:y) - module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) - reg x : UInt - reg y : UInt - x.init := UInt(0) - y.init := UInt(42) - when greater(x, y) : - inst s of subtracter - s.x := x -; CHECK: inst:s.x := reg:x - s.y := y - x := s.z - else : - inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.z - when e : - x := a - y := b - v := equal(v, UInt(0)) - z := x - module top : - input a : UInt(16) - input b : UInt(16) - output z : UInt - inst i of gcd -; CHECK: inst i of module:gcd - i.a := a - i.b := b - i.e := UInt(1) - z := i.z -; CHECK: port:z := inst:i.z - - diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir new file mode 100644 index 00000000..83091f67 --- /dev/null +++ b/test/passes/resolve-kinds/gcd.fir @@ -0,0 +1,49 @@ +; RUN: firrtl %s ab | tee %s.out | FileCheck %s + +; CHECK: Resolve Kinds +circuit top : + module subtracter : + input x : UInt + input y : UInt + output z : UInt + z := sub-mod(x, y) +; CHECK: port:z := sub-mod(port:x, port:y) + module gcd : + input a : UInt(16) + input b : UInt(16) + input e : UInt(1) + output z : UInt(16) + output v : UInt(1) + reg x : UInt + reg y : UInt + x.init := UInt(0) + y.init := UInt(42) + when greater(x, y) : + inst s of subtracter + s.x := x +; CHECK: inst:s.x := reg:x + s.y := y + x := s.z + else : + inst s2 of subtracter + s2.x := x + s2.y := y + y := s2.z + when e : + x := a + y := b + v := equal(v, UInt(0)) + z := x + module top : + input a : UInt(16) + input b : UInt(16) + output z : UInt + inst i of gcd +; CHECK: inst i of module:gcd + i.a := a + i.b := b + i.e := UInt(1) + z := i.z +; CHECK: port:z := inst:i.z + + -- cgit v1.2.3