From ddc0dfe7a5f942ad1066b86b4f3ba9494493c6ed Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 29 Apr 2015 11:42:37 -0700
Subject: Added dshl and dshr

---
 test/passes/infer-types/primops.fir |  8 ++++++++
 test/passes/infer-widths/dsh.fir    | 25 +++++++++++++++++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 test/passes/infer-widths/dsh.fir

(limited to 'test/passes')

diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index a17d8f67..589ab546 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -115,6 +115,14 @@ circuit top :
       node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@<t:UInt>, 10)@<t:UInt>
       node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@<t:SInt>, 10)@<t:SInt>
    
+      node vdshl = dshl(a, a)   ;CHECK: node vdshl = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node wdshl-u = dshl-u(a, a) ;CHECK: node wdshl-u = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node zdshl-s = dshl-s(c, a) ;CHECK: node zdshl-s = dshl-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt>
+   
+      node vdshr = dshr(a, a)   ;CHECK: node vdshr = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node wdshr-u = dshr-u(a, a) ;CHECK: node wdshr-u = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node zdshr-s = dshr-s(c, a) ;CHECK: node zdshr-s = dshr-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt>
+   
       node vshr = shr(a, 10)   ;CHECK: node vshr = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@<t:SInt>, 10)@<t:SInt>
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir
new file mode 100644
index 00000000..1eb23115
--- /dev/null
+++ b/test/passes/infer-widths/dsh.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s
+
+;CHECK: Infer Widths
+
+circuit top :
+   module M :
+      wire x : UInt<16>
+      wire z : SInt<16>
+      wire y : UInt<3>
+      wire a : UInt
+      wire b : SInt
+      wire c : UInt
+      wire d : SInt
+
+      a := dshl-u(x,y)
+      b := dshl-s(z,y)
+      c := dshr-u(x,y)
+      d := dshr-s(z,y)
+
+
+; CHECK: wire a : UInt<23>
+; CHECK: wire b : SInt<23>
+; CHECK: wire c : UInt<16>
+; CHECK: wire d : SInt<16>
+; CHECK: Finished Infer Widths
-- 
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