From 1644ed195522cd7343aaaa047e6669529907de9f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 28 Apr 2015 17:32:19 -0700
Subject: Instances are now male. Reworked lowering pass to be sane.
 chisel3/ModuleVec.fir doesn't work because incorrecly generated?

---
 test/passes/infer-types/gcd.fir            | 10 ++++-----
 test/passes/infer-widths/gcd.fir           |  2 +-
 test/passes/lower-to-ground/accessor.fir   |  2 +-
 test/passes/lower-to-ground/bundle.fir     |  2 +-
 test/passes/lower-to-ground/instance.fir   | 35 ++++++++++++++++++++++++++++++
 test/passes/lower-to-ground/nested-vec.fir | 10 +++++----
 test/passes/resolve-genders/accessor.fir   | 12 +++++-----
 test/passes/resolve-genders/gcd.fir        | 12 +++++-----
 test/passes/resolve-genders/ports.fir      | 12 +++++-----
 9 files changed, 67 insertions(+), 30 deletions(-)
 create mode 100644 test/passes/lower-to-ground/instance.fir

(limited to 'test/passes')

diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 0b6b19fa..6e3109a5 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -22,14 +22,14 @@ circuit top :
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.z@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 3cd5c542..435540ae 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 2b73a8e9..f15980b3 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index ca676ba5..722d569c 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 circuit top :
    module m :
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
new file mode 100644
index 00000000..4cd9f0cc
--- /dev/null
+++ b/test/passes/lower-to-ground/instance.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s
+
+circuit top :
+   module source :
+      output data : UInt<16>
+      input ready : UInt<1>
+      data := UInt(16)
+   module sink :
+      input data : UInt<16>
+      output ready : UInt<1>
+   module top: 
+      wire connect : { data : UInt<16>, flip ready: UInt<1> }
+      wire connect2 : { flip data : UInt<16>, ready: UInt<1> }
+      inst src of source         
+      inst snk of sink           
+      connect := src   
+      connect2 := snk
+
+
+; CHECK: Resolve Genders
+
+; CHECK: connect@<g:f> := src@<g:m>
+; CHECK: connect2@<g:f> := snk@<g:m>
+
+; CHECK: Finished Resolve Genders
+
+
+; CHECK: Lower To Ground
+
+; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
+; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
+
+; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1e9c8f9f..95b125f6 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -5,6 +5,7 @@ circuit top :
    module q :
       wire i : UInt
       wire j : { x : UInt<32>, flip y : UInt<32> }
+      wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
       ; CHECK: wire a$0$x : UInt<32>
@@ -19,16 +20,17 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, flip y : UInt<32> }[2]
+      mem m : { x : UInt<32>, y : UInt<32> }[2]
       ; CHECK: mem m$x : UInt<32>[2]
       ; CHECK: mem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]
       ; CHECK: accessor c$y = m$y[i]
-      ; CHECK: c$x := j$x
-      ; CHECK: j$y := c$y
-      c := j
+
+      c := k
+      ; CHECK: c$x := k$x
+      ; CHECK: c$y := k$y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 8cae8ba4..caf7d4b3 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -5,15 +5,15 @@ circuit top :
    module top :
       wire m : UInt<32>[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
-      accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
-      accessor c = b[i] ;CHECK: accessor c = b@<g:male>[i@<g:male>]@<g:male>
+      accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
+      accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
+      accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: accessor x = m@<g:female>[i@<g:male>]@<g:female>
-      accessor y = x[i] ;CHECK: accessor y = x@<g:female>[i@<g:male>]@<g:female>
-      accessor z = y[i] ;CHECK: accessor z = y@<g:female>[i@<g:male>]@<g:female>
+      accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
+      accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
+      accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
       z := j
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index b16c9b66..2f7aae73 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
+      ;CHECK: z@<g:f> := sub-wrap-uu(x@<g:m>, y@<g:m>)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -20,15 +20,15 @@ circuit top :
       on-reset x := UInt(0)
       on-reset y := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
+      ;CHECK: when gt-uu(x@<g:m>, y@<g:m>) :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<g:female>
+         ;CHECK: inst s of subtracter@<g:m>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<g:female>.x@<g:female> := x@<g:male>
-         ;CHECK: s@<g:female>.y@<g:female> := y@<g:male>
-         ;CHECK: x@<g:female> := s@<g:female>.z@<g:male>
+         ;CHECK: s@<g:m>.x@<g:f> := x@<g:m>
+         ;CHECK: s@<g:m>.y@<g:f> := y@<g:m>
+         ;CHECK: x@<g:f> := s@<g:m>.z@<g:m>
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 3155dbcf..9bc67c21 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -11,11 +11,11 @@ circuit top :
       output ready : UInt<1>
    module top: 
       wire connect : { data : UInt<16>, flip ready: UInt<1> }
-      inst src of source         ;CHECK: inst src of source@<g:female>
-      inst snk of sink           ;CHECK: inst snk of sink@<g:female>
-      connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
-      src.ready := connect.ready ;CHECK: src@<g:female>.ready@<g:female> := connect@<g:female>.ready@<g:male>
-      snk.data := connect.data   ;CHECK: snk@<g:female>.data@<g:female> := connect@<g:male>.data@<g:male>
-      connect.ready := snk.ready ;CHECK: connect@<g:male>.ready@<g:female> := snk@<g:female>.ready@<g:male>
+      inst src of source         ;CHECK: inst src of source@<g:m>
+      inst snk of sink           ;CHECK: inst snk of sink@<g:m>
+      connect.data := src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
+      src.ready := connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
+      snk.data := connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
+      connect.ready := snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Resolve Genders
-- 
cgit v1.2.3