From 271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 13 Jul 2015 16:22:43 -0700
Subject: Added tests for clocks. Added remove scope and special chars passes.
 Added tests. Made more tests pass

---
 test/passes/split-exp/gcd.fir | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

(limited to 'test/passes/split-exp')

diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index 5af83202..fc49335c 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -6,17 +6,19 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := subw(x, y)
    module gcd :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt
-      reg y : UInt
-      on-reset x := UInt(0)
-      on-reset y := UInt(42)
+      reg x : UInt,clk,reset
+      reg y : UInt,clk,reset
+      onreset x := UInt(0)
+      onreset y := UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -33,10 +35,14 @@ circuit top :
       v := eq(v, UInt(0))
       z := x
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       input a : UInt<16>
       input b : UInt<16>
       output z : UInt
       inst i of gcd
+      i.clk := clk
+      i.reset := reset
       i.a := a
       i.b := b
       i.e := UInt(1)
-- 
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