From 4569194392122ae4715549b2f0b9fffff051b278 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 7 Jan 2016 17:15:31 -0800
Subject: Fixed a bunch of tests, and minor bugs

---
 test/passes/split-exp/split-in-when.fir | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

(limited to 'test/passes/split-exp/split-in-when.fir')

diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index a6d0a2c5..06a3cc53 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -13,12 +13,13 @@ circuit Top :
 
       when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
 
-;CHECK: node out_1 = subw(a, c)
-;CHECK: node out_2 = bit(out_1, 3)
-;CHECK: node out_3 = eqv(UInt("h0"), UInt("hd"))
-;CHECK: node out_4 = addw(b, c)
-;CHECK: node out_5 = addw(a, out_4)
-;CHECK: node out_6 = subw(c, b)
-;CHECK: node out_7 = mux(out_3, out_5, out_6)
+;CHECK: node GEN = subw(a, c)
+;CHECK: node GEN_1 = bit(GEN, 3)
+;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_3 = addw(b, c)
+;CHECK: node GEN_4 = addw(a, GEN_3)
+;CHECK: node GEN_5 = subw(c, b)
+;CHECK: node GEN_6 = mux(GEN_2, GEN_4, GEN_5)
+;CHECK: out <= mux(GEN_1, GEN_6, out)   
 
 ;CHECK: Finished Split Expressions
-- 
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