From 81e47120c8586871fd96e22e0626591d3b5a7cc5 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 16 Jan 2016 15:49:30 -0800
Subject: Added a bunch of tests and added firrtl-stanza and firrtl-scala to
 .gitignore

---
 test/passes/remove-accesses/simple9.fir | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 test/passes/remove-accesses/simple9.fir

(limited to 'test/passes/remove-accesses/simple9.fir')

diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir
new file mode 100644
index 00000000..5405c42a
--- /dev/null
+++ b/test/passes/remove-accesses/simple9.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+  module top : 
+    input T_4910 : UInt<1>
+    input T_4581 : UInt<1>
+    input reset : UInt<1>
+    input clock : Clock
+    output out : UInt<1>
+    reg T_4590 : UInt<1>[2], clock, reset, T_4590
+    T_4590[0] <= UInt(0)
+    T_4590[1] <= UInt(0)
+    out <= UInt(0)
+    when T_4910 :
+      out <= T_4590[T_4581]
+;CHECK: Done!
-- 
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