From bebd04c4c68c320b2b72325e348c726dc33beae6 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 15 Aug 2016 10:32:41 -0700
Subject: Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
---
 test/passes/remove-accesses/simple6.fir | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100644 test/passes/remove-accesses/simple6.fir

(limited to 'test/passes/remove-accesses/simple6.fir')

diff --git a/test/passes/remove-accesses/simple6.fir b/test/passes/remove-accesses/simple6.fir
deleted file mode 100644
index eee62681..00000000
--- a/test/passes/remove-accesses/simple6.fir
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Remove Accesses
-circuit top :
-   module top :
-      input value : UInt<32>
-      input in : {x : UInt<32>, y : UInt<32>}
-      wire m :{x : UInt<32>, y : UInt<32>}[2][2] 
-      wire i : UInt
-      wire j : UInt
-
-      m[0][0] <= in
-      m[1][0] <= in
-      m[0][1] <= in
-      m[1][1] <= in
-      i <= UInt("h1")
-      j <= UInt("h1")
-
-      m[i][j].x <= value
-
-;CHECK: Done!
-- 
cgit v1.2.3