From a2a48576534f87b28566504bb1e0c7faa493f463 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 May 2015 15:43:15 -0700
Subject: Added external modules. Switched lower firrtl back to wire r; r :=
 Register, instead of using nodes. Added a renaming pass for different
 backends. This will likely get deprecated, as a more robust name mangling
 scheme could be needed

---
 test/passes/lower-to-ground/nested-vec.fir | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'test/passes/lower-to-ground/nested-vec.fir')

diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1a6ba2e8..b7915c5d 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -8,29 +8,29 @@ circuit top :
       wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a_0_x : UInt<32>
-      ; CHECK: wire a_0_y : UInt<32>
-      ; CHECK: wire a_1_x : UInt<32>
-      ; CHECK: wire a_1_y : UInt<32>
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b_x : UInt<32>
-      ; CHECK: wire b_y : UInt<32>
-      ; CHECK: b_x := (a_0_x a_1_x)[i]
-      ; CHECK: (a_0_y a_1_y)[i] := b_y
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
+      ; CHECK: b$x := (a$0$x a$1$x)[i]
+      ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
       mem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: mem m_x : UInt<32>[2]
-      ; CHECK: mem m_y : UInt<32>[2]
+      ; CHECK: mem m$x : UInt<32>[2]
+      ; CHECK: mem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
-      ; CHECK: accessor c_x = m_x[i]
-      ; CHECK: accessor c_y = m_y[i]
+      ; CHECK: accessor c$x = m$x[i]
+      ; CHECK: accessor c$y = m$y[i]
 
       c := k
-      ; CHECK: c_x := k_x
-      ; CHECK: c_y := k_y
+      ; CHECK: c$x := k$x
+      ; CHECK: c$y := k$y
 
 ; CHECK: Finished Lower To Ground
 
-- 
cgit v1.2.3


From b44b49e6a6589add30b5b1d89d85f2e20432a515 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 May 2015 17:15:44 -0700
Subject: Added sequential memories. mem no longer exists, must declare either
 cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

---
 test/passes/lower-to-ground/nested-vec.fir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'test/passes/lower-to-ground/nested-vec.fir')

diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index b7915c5d..c39850f4 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -20,9 +20,9 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: mem m$x : UInt<32>[2]
-      ; CHECK: mem m$y : UInt<32>[2]
+      cmem m : { x : UInt<32>, y : UInt<32> }[2]
+      ; CHECK: cmem m$x : UInt<32>[2]
+      ; CHECK: cmem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]
-- 
cgit v1.2.3