From 2d2120a05549a5d31072aa792dc96fb7e6e7c629 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 27 Apr 2015 11:14:06 -0700
Subject: Added on-reset

---
 test/passes/jacktest/Tlb.fir | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'test/passes/jacktest/Tlb.fir')

diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
index 35442ac8..b458ac4a 100644
--- a/test/passes/jacktest/Tlb.fir
+++ b/test/passes/jacktest/Tlb.fir
@@ -2,13 +2,13 @@
 ; CHECK: Done!
 circuit Tbl : 
   module Tbl : 
-    output o : UInt(16)
-    input i : UInt(16)
-    input d : UInt(16)
-    input we : UInt(1)
+    output o : UInt<16>
+    input i : UInt<16>
+    input d : UInt<16>
+    input we : UInt<1>
     
-    mem m : UInt(10)[256]
-    node T_12 = UInt(0, 1)
+    mem m : UInt<10>[256]
+    node T_12 = UInt<1>(0)
     o := Pad(T_12,?)
     when we : 
       accessor T_13 = m[i]
-- 
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