From 5ab30c681558d2a26000696e518ee5b28deb1303 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:18:34 -0800
Subject: Updated all tests to pass

---
 test/passes/jacktest/Stack.fir | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'test/passes/jacktest/Stack.fir')

diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 319e87d5..162bac25 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -11,25 +11,27 @@ circuit Stack :
     input dataIn : UInt<32>
     
     cmem stack_mem : UInt<32>[16]
-    reg sp : UInt<5>,clk,reset,UInt<5>(0)
-    reg out : UInt<32>,clk,reset,UInt<32>(0)
+    reg sp : UInt<5>,clk with :
+       reset => (reset,UInt<5>(0))
+    reg out : UInt<32>,clk with :
+       reset => (reset,UInt<32>(0))
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
         write mport T_32 = stack_mem[sp],clk
         T_32 <= dataIn
-        node T_33 = addw(sp, UInt<1>(1))
+        node T_33 = tail(add(sp, UInt<1>(1)),1)
         sp <= T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
         node T_35 = and(pop, T_34)
         when T_35 : 
-          node T_36 = subw(sp, UInt<1>(1))
+          node T_36 = tail(sub(sp, UInt<1>(1)),1)
           sp <= T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
-        node T_38 = subw(sp, UInt<1>(1))
+        node T_38 = tail(sub(sp, UInt<1>(1)),1)
         read mport T_39 = stack_mem[T_38],clk
         out <= T_39
     dataOut <= out
-- 
cgit v1.2.3


From cfedffd1fc7d5846e9f633bf13ea194b8ab2293d Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 Jan 2016 15:59:48 -0800
Subject: Changed rmode to wmode

---
 test/passes/jacktest/Stack.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/passes/jacktest/Stack.fir')

diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 162bac25..3eb9c67c 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
-- 
cgit v1.2.3