From 168843e45656b3569461f496b85def20b70779d2 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 8 Jan 2016 15:51:41 -0800
Subject: Finished first cut at new firrtl - time for testing! Chirrtl requires
 masks to be specified with write and rdwr mports

---
 test/passes/jacktest/Stack.fir | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'test/passes/jacktest/Stack.fir')

diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 9b35c3f4..c3ec4921 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,6 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Finished Low Form Check
-;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0")
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
@@ -19,7 +17,7 @@ circuit Stack :
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
-        write mport T_32 = stack_mem[sp],clk
+        write mport T_32 = stack_mem[sp],clk,UInt(1)
         T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
         sp <= T_33
-- 
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