From 9b6d8514a3be860562d8d524fa425c87d1537e8a Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 13 Jul 2015 16:22:43 -0700
Subject: Added tests for clocks. Added remove scope and special chars passes.
 Added tests. Made more tests pass

---
 test/passes/jacktest/RegisterVecShift.fir | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'test/passes/jacktest/RegisterVecShift.fir')

diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index d24bc383..cca645d1 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,11 +3,13 @@
 circuit RegisterVecShift : 
   module RegisterVecShift : 
     input load : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
     output out : UInt<4>
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4]
+    reg delays : UInt<4>[4],clk,reset
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] := UInt<4>(0)
-- 
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