From 0faab2b1efb266bc8000b11a474438401ff5af83 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 19 May 2015 20:16:53 -0700
Subject: Updated tests

---
 test/passes/jacktest/ModuleVec.fir | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 test/passes/jacktest/ModuleVec.fir

(limited to 'test/passes/jacktest/ModuleVec.fir')

diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
new file mode 100644
index 00000000..04c119a1
--- /dev/null
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -0,0 +1,28 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit ModuleVec : 
+  module PlusOne : 
+    input in : UInt<32>
+    output out : UInt<32>
+    
+    node T_33 = add-wrap(in, UInt<1>(1))
+    out := T_33
+  module PlusOne_25 : 
+    input in : UInt<32>
+    output out : UInt<32>
+    
+    node T_34 = add-wrap(in, UInt<1>(1))
+    out := T_34
+  module ModuleVec : 
+    input ins : UInt<32>[2]
+    output outs : UInt<32>[2]
+    
+    inst T_35 of PlusOne
+    inst T_36 of PlusOne_25
+    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_35
+    pluses[1] := T_36
+    pluses[0].in := ins[0]
+    outs[0] := pluses[0].out
+    pluses[1].in := ins[1]
+    outs[1] := pluses[1].out
-- 
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