From 5d3061bfed8445370e6fa97ec9238ba49e8fafbc Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 24 Aug 2015 11:45:37 -0700
Subject: Changed all tests to use verilog backend.

---
 test/passes/jacktest/ModuleVec.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/passes/jacktest/ModuleVec.fir')

diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 5f8d57a8..8ac27aaf 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit ModuleVec : 
   module PlusOne : 
-- 
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