From f201c512295d9ddb8181839c3e8b4160017e8dfc Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 13 Apr 2015 19:14:06 -0700
Subject: Stanza bug

---
 test/passes/inline/gcd.fir | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 test/passes/inline/gcd.fir

(limited to 'test/passes/inline')

diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
new file mode 100644
index 00000000..fb22204c
--- /dev/null
+++ b/test/passes/inline/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjkn c | tee %s.out | FileCheck %s
+
+;CHECK: Infer Widths
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap-uu(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt-uu(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal-uu(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Infer Widths
-- 
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