From 3e6d0e2b290aeb49aa9085b75b8a6c57fe1af28c Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 23 Mar 2015 16:12:38 -0700
Subject: Finished first two parts of expand-whens pass. Fixed inits by adding
 WRegInit and removing Null and initialize-register pass

---
 test/passes/initialize-register/begin.fir | 26 -------------------
 test/passes/initialize-register/when.fir  | 43 -------------------------------
 2 files changed, 69 deletions(-)
 delete mode 100644 test/passes/initialize-register/begin.fir
 delete mode 100644 test/passes/initialize-register/when.fir

(limited to 'test/passes/initialize-register')

diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
deleted file mode 100644
index fab45e64..00000000
--- a/test/passes/initialize-register/begin.fir
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
-
-; CHECK: Initialize Registers
-         circuit top :
-            module top :
-               input a : UInt(16)
-               input b : UInt(16)
-               output z : UInt
-
-               reg r1 : UInt
-; CHECK:       wire [[R1:gen[0-9]*]] : UInt
-; CHECK:       [[R1]] := Null
-
-               reg r2 : UInt
-               r2.init := UInt(0)
-; CHECK-NOT:   r2.init := UInt(0)
-; CHECK:       wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:   r2 := [[R2]]
-; CHECK:       [[R2]] := Null
-; CHECK:       [[R2]] := UInt(0)
-      
-; CHECK:       when reset :
-; CHECK-DAG:      r1 := [[R1]]
-; CHECK-DAG:      r2 := [[R2]]
-
-; CHECK: Finished Initialize Registers
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
deleted file mode 100644
index 4e0690d8..00000000
--- a/test/passes/initialize-register/when.fir
+++ /dev/null
@@ -1,43 +0,0 @@
-; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
-
-; CHECK: Initialize Registers
-         circuit top :
-            module top :
-               input a : UInt(16)
-               input b : UInt(16)
-               output z : UInt
-               when gt(1, 2) :
-                  reg r1: UInt
-                  r1.init := UInt(12)
-; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      r1 := [[R1]]
-; CHECK:          [[R1]] := Null
-; CHECK:          [[R1]] := UInt(12)
-; CHECK-NOT:      r1.init := UInt(12)
-                  reg r2: UInt
-; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      r2 := [[R2]]
-; CHECK:          [[R2]] := Null
-
-; CHECK:          when reset :
-; CHECK-DAG:         r2 := [[R2]]
-; CHECK-DAG:         r1 := [[R1]]
-               else :
-                  reg r1: UInt
-                  r1.init := UInt(12)
-; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      r1 := [[R1]]
-; CHECK:          [[R1]] := Null
-; CHECK:          [[R1]] := UInt(12)
-; CHECK-NOT:      r1.init := UInt(12)
-
-                  reg r2: UInt
-; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      r2 := [[R2]]
-; CHECK:          [[R2]] := Null
-
-; CHECK:          when reset :
-; CHECK-DAG:         r2 := [[R2]]
-; CHECK-DAG:         r1 := [[R1]]
-
-; CHECK: Finished Initialize Registers
-- 
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