From a9d23329a6f586d71a1a39908be872ec8f69d562 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 25 Feb 2015 12:50:00 -0800
Subject: Added debug print statements to dump fields from nodes, and updated
 tests to call firrtl correctly to enable/disable them

---
 test/passes/initialize-register/when.fir | 36 +++++++++++++++++---------------
 1 file changed, 19 insertions(+), 17 deletions(-)

(limited to 'test/passes/initialize-register/when.fir')

diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
index c563d639..4e2bef79 100644
--- a/test/passes/initialize-register/when.fir
+++ b/test/passes/initialize-register/when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
 
 ; CHECK: Initialize Registers
          circuit top :
@@ -10,32 +10,34 @@
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
                else :
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
 
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
+
+; CHECK: Finished Initialize Registers
-- 
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