From 5d3061bfed8445370e6fa97ec9238ba49e8fafbc Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 24 Aug 2015 11:45:37 -0700
Subject: Changed all tests to use verilog backend.

---
 test/passes/infer-types/bundle.fir | 2 +-
 test/passes/infer-types/gcd.fir    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/passes/infer-types')

diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index c24419b9..50f1c84b 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 20f4a340..fa14eb38 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
-- 
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