From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/passes/const-prop/bits.fir | 2 +-
 test/passes/const-prop/rsh.fir  | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'test/passes/const-prop')

diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir
index 16d678b3..78c450a9 100644
--- a/test/passes/const-prop/bits.fir
+++ b/test/passes/const-prop/bits.fir
@@ -8,4 +8,4 @@ circuit top :
    module top :
       output out : UInt
       node x = bits(UInt(127),2,0)
-      out := x
+      out <= x
diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir
index 8c13e410..4159899f 100644
--- a/test/passes/const-prop/rsh.fir
+++ b/test/passes/const-prop/rsh.fir
@@ -1,14 +1,14 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Constant Propagation
-;CHECK: x := UInt("h1f")
-;CHECK: y := SInt("h20")
+;CHECK: x <= UInt("h1f")
+;CHECK: y <= SInt("h20")
 ;CHECK: Finished Constant Propagation
 
 circuit top :
    module top :
       output x : UInt
       output y : SInt
-      x := shr(UInt(127),2)
-      y := shr(SInt(-128),2)
+      x <= shr(UInt(127),2)
+      y <= shr(SInt(-128),2)
 
-- 
cgit v1.2.3