From 45946bba6942378970ae42502f7b2829c2d3c58f Mon Sep 17 00:00:00 2001
From: Jack
Date: Tue, 6 Oct 2015 16:03:48 -0700
Subject: Added ability to test scala FIRRTL

---
 test/parser/gcd.fir | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 test/parser/gcd.fir

(limited to 'test/parser/gcd.fir')

diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir
new file mode 100644
index 00000000..03eb6ba9
--- /dev/null
+++ b/test/parser/gcd.fir
@@ -0,0 +1,52 @@
+; RUN: firrtl -i %s -o %s.out -X HighFIRRTL && cat %s.out | FileCheck %s
+circuit GCD : 
+  module GCD : 
+    input e : UInt<1>
+    input clk : Clock
+    input reset : UInt<1>
+    output z : UInt<16>
+    output v : UInt<1>
+    input a : UInt<16>
+    input b : UInt<16>
+    
+    reg x : UInt<16>,clk,reset
+    reg y : UInt<16>,clk,reset
+    node T_17 = gt(x, y)
+    when T_17 : 
+      node T_18 = subw(x, y)
+      x := T_18
+    else : 
+      node T_19 = subw(y, x)
+      y := T_19
+    when e : 
+      x := a
+      y := b
+    z := x
+    node T_20 = eq(y, UInt<1>(0))
+    v := T_20
+
+; CHECK: circuit GCD : 
+; CHECK:   module GCD : 
+; CHECK:     input e : UInt<1>
+; CHECK:     input clk : Clock
+; CHECK:     input reset : UInt<1>
+; CHECK:     output z : UInt<16>
+; CHECK:     output v : UInt<1>
+; CHECK:     input a : UInt<16>
+; CHECK:     input b : UInt<16>
+; CHECK:     reg x : UInt<16>, clk, reset
+; CHECK:     reg y : UInt<16>, clk, reset
+; CHECK:     node T_17 = gt(x, y)
+; CHECK:     when T_17 : 
+; CHECK:       node T_18 = subw(x, y)
+; CHECK:       x := T_18
+; CHECK:     else :
+; CHECK:       node T_19 = subw(y, x)
+; CHECK:       y := T_19
+; CHECK:     when e : 
+; CHECK:       x := a
+; CHECK:       y := b
+; CHECK:     z := x
+; CHECK:     node T_20 = eq(y, UInt<1>("h00"))
+; CHECK:     v := T_20
+
-- 
cgit v1.2.3


From 9b737de6551e7446dfd92d86cd009b4b2f95c980 Mon Sep 17 00:00:00 2001
From: Jack
Date: Wed, 14 Oct 2015 13:53:22 -0700
Subject: Moved Logger to new private object DebugUtils, changed UInt/SInt
 value printing to match stanza implementation

---
 test/parser/gcd.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/parser/gcd.fir')

diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir
index 03eb6ba9..3a9317b8 100644
--- a/test/parser/gcd.fir
+++ b/test/parser/gcd.fir
@@ -47,6 +47,6 @@ circuit GCD :
 ; CHECK:       x := a
 ; CHECK:       y := b
 ; CHECK:     z := x
-; CHECK:     node T_20 = eq(y, UInt<1>("h00"))
+; CHECK:     node T_20 = eq(y, UInt<1>("h0"))
 ; CHECK:     v := T_20
 
-- 
cgit v1.2.3