From e985d47312458459e9ebe42fe99b5a063c08e637 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sun, 31 Jan 2016 12:59:31 -0800
Subject: Changed stanza output of UInt/SInt to include widths. Made tests
 match accordingly

---
 test/parser/bundle.fir | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'test/parser/bundle.fir')

diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir
index dae02d2a..16a72a1b 100644
--- a/test/parser/bundle.fir
+++ b/test/parser/bundle.fir
@@ -24,21 +24,21 @@ circuit top :
 ; CHECK: circuit top :
 ; CHECK:    module top :
 ; CHECK:       wire z : { x : UInt, flip y : SInt}
-; CHECK:       z.x <= UInt("h1")
-; CHECK:       z.y <= SInt("h1")
+; CHECK:       z.x <= UInt<1>("h1")
+; CHECK:       z.y <= SInt<2>("h1")
 ; CHECK:       node x = z.x            
 ; CHECK:       node y = z.y            
 ; CHECK:       wire a : UInt<3>[10]    
-; CHECK:       a[0] <= UInt("h1")
-; CHECK:       a[1] <= UInt("h1")
-; CHECK:       a[2] <= UInt("h1")
-; CHECK:       a[3] <= UInt("h1")
-; CHECK:       a[4] <= UInt("h1")
-; CHECK:       a[5] <= UInt("h1")
-; CHECK:       a[6] <= UInt("h1")
-; CHECK:       a[7] <= UInt("h1")
-; CHECK:       a[8] <= UInt("h1")
-; CHECK:       a[9] <= UInt("h1")
+; CHECK:       a[0] <= UInt<1>("h1")
+; CHECK:       a[1] <= UInt<1>("h1")
+; CHECK:       a[2] <= UInt<1>("h1")
+; CHECK:       a[3] <= UInt<1>("h1")
+; CHECK:       a[4] <= UInt<1>("h1")
+; CHECK:       a[5] <= UInt<1>("h1")
+; CHECK:       a[6] <= UInt<1>("h1")
+; CHECK:       a[7] <= UInt<1>("h1")
+; CHECK:       a[8] <= UInt<1>("h1")
+; CHECK:       a[9] <= UInt<1>("h1")
 ; CHECK:       node b = a[2]           
-; CHECK:       node c = a[UInt("h3")] 
+; CHECK:       node c = a[UInt<2>("h3")] 
 
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