From f8f9de58dbba5e53193246a5fd2145dfe6537e10 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 10:41:27 -0700
Subject: Added sequential/combinational memories. Started debugging verilog
 backend. Added Long support so UInt(LARGENUMBER) works

---
 test/features/Long.fir | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 test/features/Long.fir

(limited to 'test/features')

diff --git a/test/features/Long.fir b/test/features/Long.fir
new file mode 100644
index 00000000..e03ab091
--- /dev/null
+++ b/test/features/Long.fir
@@ -0,0 +1,6 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done
+circuit Top : 
+  module Top : 
+    wire a : UInt
+    a := UInt(4261441663)
-- 
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