From d696dd01de8a1a83a376c719490f475be991f387 Mon Sep 17 00:00:00 2001 From: azidar Date: Tue, 7 Jul 2015 10:13:29 -0700 Subject: Pass most tests. The ones that do not pass are not expected to, yet --- test/features/BulkConnect.fir | 15 +++++++++++++++ test/features/SeqMem.fir | 9 +++++---- 2 files changed, 20 insertions(+), 4 deletions(-) (limited to 'test/features') diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index f78ba45b..f8840f46 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -3,7 +3,14 @@ circuit Top : module Top : wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>} + a.w := UInt(1) + a.y := UInt(1) + a.z := SInt(1) wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>} + b.w := UInt(1) + b.x := UInt(1) + b.y := UInt(1) + b.z := UInt(1) a <> b ; CHECK: a$w := b$w ; CHECK: a$x := b$x @@ -13,7 +20,15 @@ circuit Top : wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] + c[0].x.z := UInt(1) + c[1].x.z := UInt(1) + c[2].x.y := UInt(1) + c[2].x.z := UInt(1) + c[3].x.y := UInt(1) + c[3].x.z := UInt(1) wire d : { x : { y : UInt<1>}}[2] + d[0].x.y := UInt(1) + d[1].x.y := UInt(1) c <> d ; CHECK: c$0$x$y := d$0$x$y ; CHECK: c$1$x$y := d$1$x$y diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir index 998df8c9..4b346ea9 100644 --- a/test/features/SeqMem.fir +++ b/test/features/SeqMem.fir @@ -3,20 +3,21 @@ circuit Top : module Top : wire i : UInt<5> + i := UInt(1) wire i0 : UInt<5> wire j : UInt<128> i0 := UInt(10) cmem m-com : UInt<128>[32] - accessor r-com = m-com[i] - accessor w-com = m-com[i] + infer accessor r-com = m-com[i] + infer accessor w-com = m-com[i] j := r-com w-com := j smem m-seq : UInt<128>[32] - accessor r-seq = m-seq[i] - accessor w-seq = m-seq[i] + infer accessor r-seq = m-seq[i] + infer accessor w-seq = m-seq[i] j := r-seq w-seq := j -- cgit v1.2.3