From cf80ff9c83c2fedd42ec186a3e342520c89f91ab Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 May 2015 17:33:40 -0700
Subject: Added <>. Added additional checks for primops. Added new chisel3
 files.

---
 test/features/BulkConnect.fir | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 test/features/BulkConnect.fir

(limited to 'test/features')

diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
new file mode 100644
index 00000000..eab0e602
--- /dev/null
+++ b/test/features/BulkConnect.fir
@@ -0,0 +1,28 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Lower To Ground
+circuit Top : 
+  module Top : 
+    wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
+    wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
+    a <> b 
+    ; CHECK:     a_w := b_w
+    ; CHECK:     a_x := b_x
+    ; CHECK-NOT: a_y := b_y
+    ; CHECK-NOT: b_y := a_y
+    ; CHECK-NOT: a_z := b_z
+    
+
+    wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
+    wire d : { x : { y : UInt<1>}}[2]
+    c <> d
+    ; CHECK:     c_0_x_y := d_0_x_y
+    ; CHECK:     c_1_x_y := d_1_x_y
+    ; CHECK-NOT: c_2_x_y := d_2_x_y
+    ; CHECK-NOT: c_3_x_y := d_3_x_y
+    ; CHECK-NOT: c_0_x_z := d_0_x_z
+    ; CHECK-NOT: c_1_x_z := d_1_x_z
+    ; CHECK-NOT: c_2_x_z := d_2_x_z
+    ; CHECK-NOT: c_3_x_z := d_3_x_z
+
+;CHECK: Finished Lower To Ground
+;CHECK: Done!
-- 
cgit v1.2.3


From a2a48576534f87b28566504bb1e0c7faa493f463 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 May 2015 15:43:15 -0700
Subject: Added external modules. Switched lower firrtl back to wire r; r :=
 Register, instead of using nodes. Added a renaming pass for different
 backends. This will likely get deprecated, as a more robust name mangling
 scheme could be needed

---
 test/features/ExModule.fir | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 test/features/ExModule.fir

(limited to 'test/features')

diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
new file mode 100644
index 00000000..b47b14ab
--- /dev/null
+++ b/test/features/ExModule.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    output z : UInt<4>
+    inst i of BlackBox
+    i.x := UInt(1)
+    i.y := UInt(2)
+    z := i.z
+  exmodule BlackBox :
+    input x : UInt<4>
+    input y : UInt<4>
+    output z : UInt<4>
+
+;CHECK: Done!
-- 
cgit v1.2.3


From b44b49e6a6589add30b5b1d89d85f2e20432a515 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 27 May 2015 17:15:44 -0700
Subject: Added sequential memories. mem no longer exists, must declare either
 cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

---
 test/features/BulkConnect.fir | 26 +++++++++++++-------------
 test/features/SeqMem.fir      | 22 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 13 deletions(-)
 create mode 100644 test/features/SeqMem.fir

(limited to 'test/features')

diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index eab0e602..f78ba45b 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -5,24 +5,24 @@ circuit Top :
     wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
     wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
     a <> b 
-    ; CHECK:     a_w := b_w
-    ; CHECK:     a_x := b_x
-    ; CHECK-NOT: a_y := b_y
-    ; CHECK-NOT: b_y := a_y
-    ; CHECK-NOT: a_z := b_z
+    ; CHECK:     a$w := b$w
+    ; CHECK:     a$x := b$x
+    ; CHECK-NOT: a$y := b$y
+    ; CHECK-NOT: b$y := a$y
+    ; CHECK-NOT: a$z := b$z
     
 
     wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
     wire d : { x : { y : UInt<1>}}[2]
     c <> d
-    ; CHECK:     c_0_x_y := d_0_x_y
-    ; CHECK:     c_1_x_y := d_1_x_y
-    ; CHECK-NOT: c_2_x_y := d_2_x_y
-    ; CHECK-NOT: c_3_x_y := d_3_x_y
-    ; CHECK-NOT: c_0_x_z := d_0_x_z
-    ; CHECK-NOT: c_1_x_z := d_1_x_z
-    ; CHECK-NOT: c_2_x_z := d_2_x_z
-    ; CHECK-NOT: c_3_x_z := d_3_x_z
+    ; CHECK:     c$0$x$y := d$0$x$y
+    ; CHECK:     c$1$x$y := d$1$x$y
+    ; CHECK-NOT: c$2$x$y := d$2$x$y
+    ; CHECK-NOT: c$3$x$y := d$3$x$y
+    ; CHECK-NOT: c$0$x$z := d$0$x$z
+    ; CHECK-NOT: c$1$x$z := d$1$x$z
+    ; CHECK-NOT: c$2$x$z := d$2$x$z
+    ; CHECK-NOT: c$3$x$z := d$3$x$z
 
 ;CHECK: Finished Lower To Ground
 ;CHECK: Done!
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
new file mode 100644
index 00000000..998df8c9
--- /dev/null
+++ b/test/features/SeqMem.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Top : 
+  module Top : 
+    wire i : UInt<5>
+    wire i0 : UInt<5>
+    wire j : UInt<128>
+
+    i0 := UInt(10)
+
+    cmem m-com : UInt<128>[32]
+    accessor r-com = m-com[i]
+    accessor w-com = m-com[i]
+    j := r-com
+    w-com := j
+
+
+    smem m-seq : UInt<128>[32]
+    accessor r-seq = m-seq[i]
+    accessor w-seq = m-seq[i]
+    j := r-seq
+    w-seq := j
-- 
cgit v1.2.3