From 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 12 Dec 2015 14:37:41 -0800
Subject: WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but
 hit roadblock in assigning clocked ports

---
 test/features/BulkConnect.fir  | 2 +-
 test/features/InitAccessor.fir | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/features')

diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index a57ce199..1b68bbdc 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -2,7 +2,7 @@
 ;CHECK: Expand Connects
 circuit Top : 
   module Top : 
-    wire a : { w : UInt<42>}
+    wire a : { w : UInt}
     a.w <= UInt(1)
     wire b : { w : UInt<42>, x : UInt<20>}
     b.w <= UInt(1)
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
index 5a81a62e..6261ec01 100644
--- a/test/features/InitAccessor.fir
+++ b/test/features/InitAccessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Done!
 circuit Top : 
-- 
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