From fb625a03237a2ec094778d8e8c0935d5b8e2c715 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 31 Jul 2015 17:27:38 -0700
Subject: Reading from output ports no longer causes errors

---
 test/errors/gender/BulkWrong.fir | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'test/errors')

diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 13534385..632dd709 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -6,7 +6,9 @@ circuit BTB :
     input clk : Clock
     input reset : UInt<1>
     input req : {valid : UInt<1>, bits : {addr : UInt<39>}}
+    output r : UInt<1>
 
     wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
 
     req <> x
+    x.valid := r
-- 
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