From f8f9de58dbba5e53193246a5fd2145dfe6537e10 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 10:41:27 -0700
Subject: Added sequential/combinational memories. Started debugging verilog
 backend. Added Long support so UInt(LARGENUMBER) works

---
 test/errors/high-form/NegUInt.fir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/errors')

diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir
index 9050ac12..a793cdb9 100644
--- a/test/errors/high-form/NegUInt.fir
+++ b/test/errors/high-form/NegUInt.fir
@@ -1,5 +1,5 @@
-; to run: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; to check: UIntValue cannot be negative.
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: UIntValue cannot be negative.
 
 circuit Top :
   module Top :
-- 
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