From c427b31a1ef8361b643d5f7435aeb42472dfe626 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 3 Dec 2015 15:12:02 -0800
Subject: WIP. Compiles and almost done with verilog backend. Need to think
 about emitting ports (and the assignments to them)

---
 test/errors/high-form/Flip-Mem.fir | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'test/errors')

diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 38935b57..ebc3ddbf 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -5,5 +5,9 @@
 circuit Flip-Mem : 
   module Flip-Mem : 
     input clk : Clock
-    cmem mc : {x : UInt<3>, flip y : UInt<5>}[10], clk
-    smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk
+    mem mc : 
+       depth => 10
+       data-type => {x : UInt<3>, flip y : UInt<5>}
+       write-latency => 1
+       read-latency => 0
+    ;smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk
-- 
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