From c4271d9e428bba7b447ed6d18fb11729d2b61b22 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 16 Jan 2016 15:24:04 -0800
Subject: Fixed all tests so they either pass are marked as expected failures

---
 test/errors/type/NodeWithFlips.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/errors')

diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir
index 80c2b160..0b8b9e6b 100644
--- a/test/errors/type/NodeWithFlips.fir
+++ b/test/errors/type/NodeWithFlips.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Node cannot be a bundle type with flips.
+; CHECK: Node must be a ground type.
 
 circuit Top : 
   module Top : 
-- 
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