From 80846abc76ff6bed9984d2ab3aaad22de665ac4f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 4 Aug 2015 13:58:06 -0700
Subject: Added verilog keywords to uniquify them

---
 test/errors/gender/InstancePorts.fir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/errors')

diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir
index d8d1355c..55d5fd46 100644
--- a/test/errors/gender/InstancePorts.fir
+++ b/test/errors/gender/InstancePorts.fir
@@ -8,10 +8,10 @@ circuit BTB :
     output out : UInt<1>
     out := in
   module BTB : 
-    input in : UInt<1>
+    input time : UInt<1>
     output out : UInt<1>
     
     inst queue of Queue
-    queue.in := in
+    queue.in := time
     out := queue.in
 
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