From 40bf74bfdf4d07f0d7171b77ae34004eb9c1fa11 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 25 Aug 2015 15:37:53 -0700
Subject: Fixed bug in split expression that leaked connect statements out of a
 conditional assignment

---
 test/errors/init/Output.fir | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 test/errors/init/Output.fir

(limited to 'test/errors')

diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir
new file mode 100644
index 00000000..f28d1e0b
--- /dev/null
+++ b/test/errors/init/Output.fir
@@ -0,0 +1,10 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Reference y is not fully initialized.
+
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    wire y : UInt<1>
+
+    when UInt(0) : 
+      y := UInt(1)
-- 
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